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Commit | Line | Data |
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0b2182dd SY |
1 | /* |
2 | * SH RSPI driver | |
3 | * | |
93722206 | 4 | * Copyright (C) 2012, 2013 Renesas Solutions Corp. |
880c6d11 | 5 | * Copyright (C) 2014 Glider bvba |
0b2182dd SY |
6 | * |
7 | * Based on spi-sh.c: | |
8 | * Copyright (C) 2011 Renesas Solutions Corp. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <linux/module.h> | |
26 | #include <linux/kernel.h> | |
27 | #include <linux/sched.h> | |
28 | #include <linux/errno.h> | |
0b2182dd SY |
29 | #include <linux/interrupt.h> |
30 | #include <linux/platform_device.h> | |
31 | #include <linux/io.h> | |
32 | #include <linux/clk.h> | |
a3633fe7 SY |
33 | #include <linux/dmaengine.h> |
34 | #include <linux/dma-mapping.h> | |
426ef76d | 35 | #include <linux/of_device.h> |
490c9774 | 36 | #include <linux/pm_runtime.h> |
a3633fe7 | 37 | #include <linux/sh_dma.h> |
0b2182dd | 38 | #include <linux/spi/spi.h> |
a3633fe7 | 39 | #include <linux/spi/rspi.h> |
0b2182dd | 40 | |
6ab4865b GU |
41 | #define RSPI_SPCR 0x00 /* Control Register */ |
42 | #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ | |
43 | #define RSPI_SPPCR 0x02 /* Pin Control Register */ | |
44 | #define RSPI_SPSR 0x03 /* Status Register */ | |
45 | #define RSPI_SPDR 0x04 /* Data Register */ | |
46 | #define RSPI_SPSCR 0x08 /* Sequence Control Register */ | |
47 | #define RSPI_SPSSR 0x09 /* Sequence Status Register */ | |
48 | #define RSPI_SPBR 0x0a /* Bit Rate Register */ | |
49 | #define RSPI_SPDCR 0x0b /* Data Control Register */ | |
50 | #define RSPI_SPCKD 0x0c /* Clock Delay Register */ | |
51 | #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ | |
52 | #define RSPI_SPND 0x0e /* Next-Access Delay Register */ | |
862d357f | 53 | #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ |
6ab4865b GU |
54 | #define RSPI_SPCMD0 0x10 /* Command Register 0 */ |
55 | #define RSPI_SPCMD1 0x12 /* Command Register 1 */ | |
56 | #define RSPI_SPCMD2 0x14 /* Command Register 2 */ | |
57 | #define RSPI_SPCMD3 0x16 /* Command Register 3 */ | |
58 | #define RSPI_SPCMD4 0x18 /* Command Register 4 */ | |
59 | #define RSPI_SPCMD5 0x1a /* Command Register 5 */ | |
60 | #define RSPI_SPCMD6 0x1c /* Command Register 6 */ | |
61 | #define RSPI_SPCMD7 0x1e /* Command Register 7 */ | |
880c6d11 GU |
62 | #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) |
63 | #define RSPI_NUM_SPCMD 8 | |
64 | #define RSPI_RZ_NUM_SPCMD 4 | |
65 | #define QSPI_NUM_SPCMD 4 | |
862d357f GU |
66 | |
67 | /* RSPI on RZ only */ | |
6ab4865b GU |
68 | #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ |
69 | #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ | |
0b2182dd | 70 | |
862d357f | 71 | /* QSPI only */ |
fbe5072b GU |
72 | #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ |
73 | #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ | |
74 | #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ | |
75 | #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ | |
76 | #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ | |
77 | #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ | |
880c6d11 | 78 | #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) |
5ce0ba88 | 79 | |
6ab4865b GU |
80 | /* SPCR - Control Register */ |
81 | #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ | |
82 | #define SPCR_SPE 0x40 /* Function Enable */ | |
83 | #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ | |
84 | #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ | |
85 | #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ | |
86 | #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ | |
87 | /* RSPI on SH only */ | |
88 | #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ | |
89 | #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ | |
fbe5072b GU |
90 | /* QSPI on R-Car M2 only */ |
91 | #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ | |
92 | #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ | |
6ab4865b GU |
93 | |
94 | /* SSLP - Slave Select Polarity Register */ | |
95 | #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ | |
96 | #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ | |
97 | ||
98 | /* SPPCR - Pin Control Register */ | |
99 | #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ | |
100 | #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ | |
0b2182dd | 101 | #define SPPCR_SPOM 0x04 |
6ab4865b GU |
102 | #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ |
103 | #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ | |
104 | ||
fbe5072b GU |
105 | #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ |
106 | #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ | |
107 | ||
6ab4865b GU |
108 | /* SPSR - Status Register */ |
109 | #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ | |
110 | #define SPSR_TEND 0x40 /* Transmit End */ | |
111 | #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ | |
112 | #define SPSR_PERF 0x08 /* Parity Error Flag */ | |
113 | #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ | |
114 | #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ | |
862d357f | 115 | #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ |
6ab4865b GU |
116 | |
117 | /* SPSCR - Sequence Control Register */ | |
118 | #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ | |
119 | ||
120 | /* SPSSR - Sequence Status Register */ | |
121 | #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ | |
122 | #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ | |
123 | ||
124 | /* SPDCR - Data Control Register */ | |
125 | #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ | |
126 | #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ | |
127 | #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ | |
128 | #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) | |
129 | #define SPDCR_SPLWORD SPDCR_SPLW1 | |
130 | #define SPDCR_SPLBYTE SPDCR_SPLW0 | |
131 | #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ | |
862d357f | 132 | #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ |
0b2182dd SY |
133 | #define SPDCR_SLSEL1 0x08 |
134 | #define SPDCR_SLSEL0 0x04 | |
862d357f | 135 | #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ |
0b2182dd SY |
136 | #define SPDCR_SPFC1 0x02 |
137 | #define SPDCR_SPFC0 0x01 | |
862d357f | 138 | #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ |
0b2182dd | 139 | |
6ab4865b GU |
140 | /* SPCKD - Clock Delay Register */ |
141 | #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ | |
0b2182dd | 142 | |
6ab4865b GU |
143 | /* SSLND - Slave Select Negation Delay Register */ |
144 | #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ | |
0b2182dd | 145 | |
6ab4865b GU |
146 | /* SPND - Next-Access Delay Register */ |
147 | #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ | |
0b2182dd | 148 | |
6ab4865b GU |
149 | /* SPCR2 - Control Register 2 */ |
150 | #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ | |
151 | #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ | |
152 | #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ | |
153 | #define SPCR2_SPPE 0x01 /* Parity Enable */ | |
0b2182dd | 154 | |
6ab4865b GU |
155 | /* SPCMDn - Command Registers */ |
156 | #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ | |
157 | #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ | |
158 | #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ | |
159 | #define SPCMD_LSBF 0x1000 /* LSB First */ | |
160 | #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ | |
0b2182dd | 161 | #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) |
880c6d11 | 162 | #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ |
5ce0ba88 | 163 | #define SPCMD_SPB_16BIT 0x0100 |
0b2182dd SY |
164 | #define SPCMD_SPB_20BIT 0x0000 |
165 | #define SPCMD_SPB_24BIT 0x0100 | |
166 | #define SPCMD_SPB_32BIT 0x0200 | |
6ab4865b | 167 | #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ |
fbe5072b GU |
168 | #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ |
169 | #define SPCMD_SPIMOD1 0x0040 | |
170 | #define SPCMD_SPIMOD0 0x0020 | |
171 | #define SPCMD_SPIMOD_SINGLE 0 | |
172 | #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 | |
173 | #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 | |
174 | #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ | |
6ab4865b GU |
175 | #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ |
176 | #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ | |
177 | #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ | |
178 | #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ | |
179 | ||
180 | /* SPBFCR - Buffer Control Register */ | |
862d357f GU |
181 | #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ |
182 | #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ | |
6ab4865b GU |
183 | #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ |
184 | #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ | |
5ce0ba88 | 185 | |
0b2182dd SY |
186 | struct rspi_data { |
187 | void __iomem *addr; | |
188 | u32 max_speed_hz; | |
189 | struct spi_master *master; | |
0b2182dd | 190 | wait_queue_head_t wait; |
0b2182dd | 191 | struct clk *clk; |
348e5153 | 192 | u16 spcmd; |
06a7a3cf GU |
193 | u8 spsr; |
194 | u8 sppcr; | |
93722206 | 195 | int rx_irq, tx_irq; |
5ce0ba88 | 196 | const struct spi_ops *ops; |
a3633fe7 | 197 | |
a3633fe7 | 198 | unsigned dma_callbacked:1; |
74da7686 | 199 | unsigned byte_access:1; |
0b2182dd SY |
200 | }; |
201 | ||
baf588f4 | 202 | static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) |
0b2182dd SY |
203 | { |
204 | iowrite8(data, rspi->addr + offset); | |
205 | } | |
206 | ||
baf588f4 | 207 | static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) |
0b2182dd SY |
208 | { |
209 | iowrite16(data, rspi->addr + offset); | |
210 | } | |
211 | ||
baf588f4 | 212 | static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) |
5ce0ba88 HCM |
213 | { |
214 | iowrite32(data, rspi->addr + offset); | |
215 | } | |
216 | ||
baf588f4 | 217 | static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
218 | { |
219 | return ioread8(rspi->addr + offset); | |
220 | } | |
221 | ||
baf588f4 | 222 | static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) |
0b2182dd SY |
223 | { |
224 | return ioread16(rspi->addr + offset); | |
225 | } | |
226 | ||
74da7686 GU |
227 | static void rspi_write_data(const struct rspi_data *rspi, u16 data) |
228 | { | |
229 | if (rspi->byte_access) | |
230 | rspi_write8(rspi, data, RSPI_SPDR); | |
231 | else /* 16 bit */ | |
232 | rspi_write16(rspi, data, RSPI_SPDR); | |
233 | } | |
234 | ||
235 | static u16 rspi_read_data(const struct rspi_data *rspi) | |
236 | { | |
237 | if (rspi->byte_access) | |
238 | return rspi_read8(rspi, RSPI_SPDR); | |
239 | else /* 16 bit */ | |
240 | return rspi_read16(rspi, RSPI_SPDR); | |
241 | } | |
242 | ||
5ce0ba88 HCM |
243 | /* optional functions */ |
244 | struct spi_ops { | |
74da7686 | 245 | int (*set_config_register)(struct rspi_data *rspi, int access_size); |
eb557f75 GU |
246 | int (*transfer_one)(struct spi_master *master, struct spi_device *spi, |
247 | struct spi_transfer *xfer); | |
880c6d11 | 248 | u16 mode_bits; |
b42e0359 | 249 | u16 flags; |
2f777ec9 | 250 | u16 fifo_size; |
5ce0ba88 HCM |
251 | }; |
252 | ||
253 | /* | |
862d357f | 254 | * functions for RSPI on legacy SH |
5ce0ba88 | 255 | */ |
74da7686 | 256 | static int rspi_set_config_register(struct rspi_data *rspi, int access_size) |
0b2182dd | 257 | { |
5ce0ba88 HCM |
258 | int spbr; |
259 | ||
06a7a3cf GU |
260 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
261 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
0b2182dd | 262 | |
5ce0ba88 | 263 | /* Sets transfer bit rate */ |
3beb61db GU |
264 | spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), |
265 | 2 * rspi->max_speed_hz) - 1; | |
5ce0ba88 HCM |
266 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
267 | ||
74da7686 GU |
268 | /* Disable dummy transmission, set 16-bit word access, 1 frame */ |
269 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
270 | rspi->byte_access = 0; | |
0b2182dd | 271 | |
5ce0ba88 HCM |
272 | /* Sets RSPCK, SSL, next-access delay value */ |
273 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
274 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
275 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
276 | ||
277 | /* Sets parity, interrupt mask */ | |
278 | rspi_write8(rspi, 0x00, RSPI_SPCR2); | |
279 | ||
280 | /* Sets SPCMD */ | |
880c6d11 GU |
281 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); |
282 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
5ce0ba88 HCM |
283 | |
284 | /* Sets RSPI mode */ | |
285 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
286 | ||
287 | return 0; | |
0b2182dd SY |
288 | } |
289 | ||
862d357f GU |
290 | /* |
291 | * functions for RSPI on RZ | |
292 | */ | |
293 | static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) | |
294 | { | |
295 | int spbr; | |
296 | ||
06a7a3cf GU |
297 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
298 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
862d357f GU |
299 | |
300 | /* Sets transfer bit rate */ | |
3beb61db GU |
301 | spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), |
302 | 2 * rspi->max_speed_hz) - 1; | |
862d357f GU |
303 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
304 | ||
305 | /* Disable dummy transmission, set byte access */ | |
306 | rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); | |
307 | rspi->byte_access = 1; | |
308 | ||
309 | /* Sets RSPCK, SSL, next-access delay value */ | |
310 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
311 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
312 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
313 | ||
314 | /* Sets SPCMD */ | |
315 | rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); | |
316 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
317 | ||
318 | /* Sets RSPI mode */ | |
319 | rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
5ce0ba88 HCM |
324 | /* |
325 | * functions for QSPI | |
326 | */ | |
74da7686 | 327 | static int qspi_set_config_register(struct rspi_data *rspi, int access_size) |
5ce0ba88 | 328 | { |
5ce0ba88 HCM |
329 | int spbr; |
330 | ||
06a7a3cf GU |
331 | /* Sets output mode, MOSI signal, and (optionally) loopback */ |
332 | rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); | |
5ce0ba88 HCM |
333 | |
334 | /* Sets transfer bit rate */ | |
3beb61db | 335 | spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz); |
5ce0ba88 HCM |
336 | rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); |
337 | ||
74da7686 GU |
338 | /* Disable dummy transmission, set byte access */ |
339 | rspi_write8(rspi, 0, RSPI_SPDCR); | |
340 | rspi->byte_access = 1; | |
5ce0ba88 HCM |
341 | |
342 | /* Sets RSPCK, SSL, next-access delay value */ | |
343 | rspi_write8(rspi, 0x00, RSPI_SPCKD); | |
344 | rspi_write8(rspi, 0x00, RSPI_SSLND); | |
345 | rspi_write8(rspi, 0x00, RSPI_SPND); | |
346 | ||
347 | /* Data Length Setting */ | |
348 | if (access_size == 8) | |
880c6d11 | 349 | rspi->spcmd |= SPCMD_SPB_8BIT; |
5ce0ba88 | 350 | else if (access_size == 16) |
880c6d11 | 351 | rspi->spcmd |= SPCMD_SPB_16BIT; |
8e1c8096 | 352 | else |
880c6d11 | 353 | rspi->spcmd |= SPCMD_SPB_32BIT; |
5ce0ba88 | 354 | |
880c6d11 | 355 | rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; |
5ce0ba88 HCM |
356 | |
357 | /* Resets transfer data length */ | |
358 | rspi_write32(rspi, 0, QSPI_SPBMUL0); | |
359 | ||
360 | /* Resets transmit and receive buffer */ | |
361 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); | |
362 | /* Sets buffer to allow normal operation */ | |
363 | rspi_write8(rspi, 0x00, QSPI_SPBFCR); | |
364 | ||
365 | /* Sets SPCMD */ | |
880c6d11 | 366 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); |
5ce0ba88 | 367 | |
880c6d11 | 368 | /* Enables SPI function in master mode */ |
5ce0ba88 HCM |
369 | rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
374 | #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) | |
375 | ||
baf588f4 | 376 | static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) |
0b2182dd SY |
377 | { |
378 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); | |
379 | } | |
380 | ||
baf588f4 | 381 | static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) |
0b2182dd SY |
382 | { |
383 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); | |
384 | } | |
385 | ||
386 | static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, | |
387 | u8 enable_bit) | |
388 | { | |
389 | int ret; | |
390 | ||
391 | rspi->spsr = rspi_read8(rspi, RSPI_SPSR); | |
5dd1ad23 GU |
392 | if (rspi->spsr & wait_mask) |
393 | return 0; | |
394 | ||
0b2182dd SY |
395 | rspi_enable_irq(rspi, enable_bit); |
396 | ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); | |
397 | if (ret == 0 && !(rspi->spsr & wait_mask)) | |
398 | return -ETIMEDOUT; | |
399 | ||
400 | return 0; | |
401 | } | |
402 | ||
5f684c34 GU |
403 | static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi) |
404 | { | |
405 | return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); | |
406 | } | |
407 | ||
408 | static inline int rspi_wait_for_rx_full(struct rspi_data *rspi) | |
409 | { | |
410 | return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE); | |
411 | } | |
412 | ||
35301c99 GU |
413 | static int rspi_data_out(struct rspi_data *rspi, u8 data) |
414 | { | |
5f684c34 GU |
415 | int error = rspi_wait_for_tx_empty(rspi); |
416 | if (error < 0) { | |
35301c99 | 417 | dev_err(&rspi->master->dev, "transmit timeout\n"); |
5f684c34 | 418 | return error; |
35301c99 GU |
419 | } |
420 | rspi_write_data(rspi, data); | |
421 | return 0; | |
422 | } | |
423 | ||
424 | static int rspi_data_in(struct rspi_data *rspi) | |
425 | { | |
5f684c34 | 426 | int error; |
35301c99 GU |
427 | u8 data; |
428 | ||
5f684c34 GU |
429 | error = rspi_wait_for_rx_full(rspi); |
430 | if (error < 0) { | |
35301c99 | 431 | dev_err(&rspi->master->dev, "receive timeout\n"); |
5f684c34 | 432 | return error; |
35301c99 GU |
433 | } |
434 | data = rspi_read_data(rspi); | |
435 | return data; | |
436 | } | |
437 | ||
6837b8e9 GU |
438 | static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx, |
439 | unsigned int n) | |
35301c99 | 440 | { |
6837b8e9 GU |
441 | while (n-- > 0) { |
442 | if (tx) { | |
443 | int ret = rspi_data_out(rspi, *tx++); | |
444 | if (ret < 0) | |
445 | return ret; | |
446 | } | |
447 | if (rx) { | |
448 | int ret = rspi_data_in(rspi); | |
449 | if (ret < 0) | |
450 | return ret; | |
451 | *rx++ = ret; | |
452 | } | |
453 | } | |
35301c99 | 454 | |
6837b8e9 | 455 | return 0; |
35301c99 GU |
456 | } |
457 | ||
a3633fe7 SY |
458 | static void rspi_dma_complete(void *arg) |
459 | { | |
460 | struct rspi_data *rspi = arg; | |
461 | ||
462 | rspi->dma_callbacked = 1; | |
463 | wake_up_interruptible(&rspi->wait); | |
464 | } | |
465 | ||
c52fb6d6 GU |
466 | static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, |
467 | struct sg_table *rx) | |
a3633fe7 | 468 | { |
c52fb6d6 GU |
469 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; |
470 | u8 irq_mask = 0; | |
471 | unsigned int other_irq = 0; | |
472 | dma_cookie_t cookie; | |
2f777ec9 | 473 | int ret; |
a3633fe7 | 474 | |
c52fb6d6 GU |
475 | if (tx) { |
476 | desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx, | |
477 | tx->sgl, tx->nents, DMA_TO_DEVICE, | |
478 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
479 | if (!desc_tx) | |
480 | return -EIO; | |
481 | ||
482 | irq_mask |= SPCR_SPTIE; | |
483 | } | |
484 | if (rx) { | |
485 | desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx, | |
486 | rx->sgl, rx->nents, DMA_FROM_DEVICE, | |
487 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
488 | if (!desc_rx) | |
489 | return -EIO; | |
490 | ||
491 | irq_mask |= SPCR_SPRIE; | |
492 | } | |
a3633fe7 SY |
493 | |
494 | /* | |
c52fb6d6 | 495 | * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be |
a3633fe7 SY |
496 | * called. So, this driver disables the IRQ while DMA transfer. |
497 | */ | |
c52fb6d6 GU |
498 | if (tx) |
499 | disable_irq(other_irq = rspi->tx_irq); | |
500 | if (rx && rspi->rx_irq != other_irq) | |
501 | disable_irq(rspi->rx_irq); | |
a3633fe7 | 502 | |
c52fb6d6 | 503 | rspi_enable_irq(rspi, irq_mask); |
a3633fe7 SY |
504 | rspi->dma_callbacked = 0; |
505 | ||
c52fb6d6 GU |
506 | if (rx) { |
507 | desc_rx->callback = rspi_dma_complete; | |
508 | desc_rx->callback_param = rspi; | |
509 | cookie = dmaengine_submit(desc_rx); | |
510 | if (dma_submit_error(cookie)) | |
511 | return cookie; | |
512 | dma_async_issue_pending(rspi->master->dma_rx); | |
513 | } | |
514 | if (tx) { | |
515 | if (rx) { | |
516 | /* No callback */ | |
517 | desc_tx->callback = NULL; | |
518 | } else { | |
519 | desc_tx->callback = rspi_dma_complete; | |
520 | desc_tx->callback_param = rspi; | |
521 | } | |
522 | cookie = dmaengine_submit(desc_tx); | |
523 | if (dma_submit_error(cookie)) | |
524 | return cookie; | |
525 | dma_async_issue_pending(rspi->master->dma_tx); | |
526 | } | |
a3633fe7 SY |
527 | |
528 | ret = wait_event_interruptible_timeout(rspi->wait, | |
529 | rspi->dma_callbacked, HZ); | |
530 | if (ret > 0 && rspi->dma_callbacked) | |
531 | ret = 0; | |
532 | else if (!ret) | |
533 | ret = -ETIMEDOUT; | |
a3633fe7 | 534 | |
c52fb6d6 GU |
535 | rspi_disable_irq(rspi, irq_mask); |
536 | ||
537 | if (tx) | |
538 | enable_irq(rspi->tx_irq); | |
539 | if (rx && rspi->rx_irq != other_irq) | |
540 | enable_irq(rspi->rx_irq); | |
541 | ||
a3633fe7 SY |
542 | return ret; |
543 | } | |
544 | ||
baf588f4 | 545 | static void rspi_receive_init(const struct rspi_data *rspi) |
0b2182dd | 546 | { |
97b95c11 | 547 | u8 spsr; |
0b2182dd SY |
548 | |
549 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
550 | if (spsr & SPSR_SPRF) | |
74da7686 | 551 | rspi_read_data(rspi); /* dummy read */ |
0b2182dd SY |
552 | if (spsr & SPSR_OVRF) |
553 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, | |
df900e67 | 554 | RSPI_SPSR); |
a3633fe7 SY |
555 | } |
556 | ||
862d357f GU |
557 | static void rspi_rz_receive_init(const struct rspi_data *rspi) |
558 | { | |
559 | rspi_receive_init(rspi); | |
560 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); | |
561 | rspi_write8(rspi, 0, RSPI_SPBFCR); | |
562 | } | |
563 | ||
baf588f4 | 564 | static void qspi_receive_init(const struct rspi_data *rspi) |
cb52c673 | 565 | { |
97b95c11 | 566 | u8 spsr; |
cb52c673 HCM |
567 | |
568 | spsr = rspi_read8(rspi, RSPI_SPSR); | |
569 | if (spsr & SPSR_SPRF) | |
74da7686 | 570 | rspi_read_data(rspi); /* dummy read */ |
cb52c673 | 571 | rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); |
340a15e6 | 572 | rspi_write8(rspi, 0, QSPI_SPBFCR); |
cb52c673 HCM |
573 | } |
574 | ||
2f777ec9 GU |
575 | static bool __rspi_can_dma(const struct rspi_data *rspi, |
576 | const struct spi_transfer *xfer) | |
a3633fe7 | 577 | { |
2f777ec9 GU |
578 | return xfer->len > rspi->ops->fifo_size; |
579 | } | |
a3633fe7 | 580 | |
2f777ec9 GU |
581 | static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi, |
582 | struct spi_transfer *xfer) | |
583 | { | |
584 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
585 | ||
586 | return __rspi_can_dma(rspi, xfer); | |
a3633fe7 SY |
587 | } |
588 | ||
8b983e90 GU |
589 | static int rspi_common_transfer(struct rspi_data *rspi, |
590 | struct spi_transfer *xfer) | |
591 | { | |
592 | int ret; | |
593 | ||
594 | if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { | |
595 | /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ | |
596 | return rspi_dma_transfer(rspi, &xfer->tx_sg, | |
597 | xfer->rx_buf ? &xfer->rx_sg : NULL); | |
598 | } | |
599 | ||
600 | ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); | |
601 | if (ret < 0) | |
602 | return ret; | |
603 | ||
604 | /* Wait for the last transmission */ | |
605 | rspi_wait_for_tx_empty(rspi); | |
606 | ||
607 | return 0; | |
608 | } | |
609 | ||
8393fa78 GU |
610 | static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
611 | struct spi_transfer *xfer) | |
8449fd76 | 612 | { |
8393fa78 | 613 | struct rspi_data *rspi = spi_master_get_devdata(master); |
b42e0359 | 614 | u8 spcr; |
8449fd76 | 615 | |
8449fd76 | 616 | spcr = rspi_read8(rspi, RSPI_SPCR); |
6837b8e9 | 617 | if (xfer->rx_buf) { |
32c64261 | 618 | rspi_receive_init(rspi); |
8449fd76 | 619 | spcr &= ~SPCR_TXMD; |
32c64261 | 620 | } else { |
8449fd76 | 621 | spcr |= SPCR_TXMD; |
32c64261 | 622 | } |
8449fd76 GU |
623 | rspi_write8(rspi, spcr, RSPI_SPCR); |
624 | ||
8b983e90 | 625 | return rspi_common_transfer(rspi, xfer); |
8449fd76 GU |
626 | } |
627 | ||
03e627c5 GU |
628 | static int rspi_rz_transfer_one(struct spi_master *master, |
629 | struct spi_device *spi, | |
630 | struct spi_transfer *xfer) | |
862d357f | 631 | { |
03e627c5 | 632 | struct rspi_data *rspi = spi_master_get_devdata(master); |
862d357f GU |
633 | |
634 | rspi_rz_receive_init(rspi); | |
635 | ||
8b983e90 | 636 | return rspi_common_transfer(rspi, xfer); |
862d357f GU |
637 | } |
638 | ||
340a15e6 GU |
639 | static int qspi_transfer_out_in(struct rspi_data *rspi, |
640 | struct spi_transfer *xfer) | |
eb557f75 | 641 | { |
340a15e6 GU |
642 | qspi_receive_init(rspi); |
643 | ||
8b983e90 | 644 | return rspi_common_transfer(rspi, xfer); |
340a15e6 GU |
645 | } |
646 | ||
880c6d11 GU |
647 | static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) |
648 | { | |
880c6d11 GU |
649 | int ret; |
650 | ||
4f12b5e5 GU |
651 | if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) |
652 | return rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); | |
653 | ||
6837b8e9 GU |
654 | ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len); |
655 | if (ret < 0) | |
656 | return ret; | |
880c6d11 GU |
657 | |
658 | /* Wait for the last transmission */ | |
5f684c34 | 659 | rspi_wait_for_tx_empty(rspi); |
880c6d11 GU |
660 | |
661 | return 0; | |
662 | } | |
663 | ||
664 | static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) | |
665 | { | |
4f12b5e5 GU |
666 | if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) |
667 | return rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); | |
668 | ||
6837b8e9 | 669 | return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len); |
880c6d11 GU |
670 | } |
671 | ||
340a15e6 GU |
672 | static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, |
673 | struct spi_transfer *xfer) | |
674 | { | |
675 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
676 | ||
ba824d49 GU |
677 | if (spi->mode & SPI_LOOP) { |
678 | return qspi_transfer_out_in(rspi, xfer); | |
b42e0359 | 679 | } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { |
880c6d11 GU |
680 | /* Quad or Dual SPI Write */ |
681 | return qspi_transfer_out(rspi, xfer); | |
b42e0359 | 682 | } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { |
880c6d11 GU |
683 | /* Quad or Dual SPI Read */ |
684 | return qspi_transfer_in(rspi, xfer); | |
685 | } else { | |
686 | /* Single SPI Transfer */ | |
687 | return qspi_transfer_out_in(rspi, xfer); | |
688 | } | |
0b2182dd SY |
689 | } |
690 | ||
691 | static int rspi_setup(struct spi_device *spi) | |
692 | { | |
693 | struct rspi_data *rspi = spi_master_get_devdata(spi->master); | |
694 | ||
0b2182dd SY |
695 | rspi->max_speed_hz = spi->max_speed_hz; |
696 | ||
348e5153 GU |
697 | rspi->spcmd = SPCMD_SSLKP; |
698 | if (spi->mode & SPI_CPOL) | |
699 | rspi->spcmd |= SPCMD_CPOL; | |
700 | if (spi->mode & SPI_CPHA) | |
701 | rspi->spcmd |= SPCMD_CPHA; | |
702 | ||
06a7a3cf GU |
703 | /* CMOS output mode and MOSI signal from previous transfer */ |
704 | rspi->sppcr = 0; | |
705 | if (spi->mode & SPI_LOOP) | |
706 | rspi->sppcr |= SPPCR_SPLP; | |
707 | ||
5ce0ba88 | 708 | set_config_register(rspi, 8); |
0b2182dd SY |
709 | |
710 | return 0; | |
711 | } | |
712 | ||
880c6d11 GU |
713 | static u16 qspi_transfer_mode(const struct spi_transfer *xfer) |
714 | { | |
715 | if (xfer->tx_buf) | |
716 | switch (xfer->tx_nbits) { | |
717 | case SPI_NBITS_QUAD: | |
718 | return SPCMD_SPIMOD_QUAD; | |
719 | case SPI_NBITS_DUAL: | |
720 | return SPCMD_SPIMOD_DUAL; | |
721 | default: | |
722 | return 0; | |
723 | } | |
724 | if (xfer->rx_buf) | |
725 | switch (xfer->rx_nbits) { | |
726 | case SPI_NBITS_QUAD: | |
727 | return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; | |
728 | case SPI_NBITS_DUAL: | |
729 | return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; | |
730 | default: | |
731 | return 0; | |
732 | } | |
733 | ||
734 | return 0; | |
735 | } | |
736 | ||
737 | static int qspi_setup_sequencer(struct rspi_data *rspi, | |
738 | const struct spi_message *msg) | |
739 | { | |
740 | const struct spi_transfer *xfer; | |
741 | unsigned int i = 0, len = 0; | |
742 | u16 current_mode = 0xffff, mode; | |
743 | ||
744 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
745 | mode = qspi_transfer_mode(xfer); | |
746 | if (mode == current_mode) { | |
747 | len += xfer->len; | |
748 | continue; | |
749 | } | |
750 | ||
751 | /* Transfer mode change */ | |
752 | if (i) { | |
753 | /* Set transfer data length of previous transfer */ | |
754 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
755 | } | |
756 | ||
757 | if (i >= QSPI_NUM_SPCMD) { | |
758 | dev_err(&msg->spi->dev, | |
759 | "Too many different transfer modes"); | |
760 | return -EINVAL; | |
761 | } | |
762 | ||
763 | /* Program transfer mode for this transfer */ | |
764 | rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); | |
765 | current_mode = mode; | |
766 | len = xfer->len; | |
767 | i++; | |
768 | } | |
769 | if (i) { | |
770 | /* Set final transfer data length and sequence length */ | |
771 | rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); | |
772 | rspi_write8(rspi, i - 1, RSPI_SPSCR); | |
773 | } | |
774 | ||
775 | return 0; | |
776 | } | |
777 | ||
79d23495 | 778 | static int rspi_prepare_message(struct spi_master *master, |
880c6d11 | 779 | struct spi_message *msg) |
79d23495 GU |
780 | { |
781 | struct rspi_data *rspi = spi_master_get_devdata(master); | |
880c6d11 | 782 | int ret; |
0b2182dd | 783 | |
880c6d11 GU |
784 | if (msg->spi->mode & |
785 | (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { | |
786 | /* Setup sequencer for messages with multiple transfer modes */ | |
787 | ret = qspi_setup_sequencer(rspi, msg); | |
788 | if (ret < 0) | |
789 | return ret; | |
790 | } | |
791 | ||
792 | /* Enable SPI function in master mode */ | |
79d23495 | 793 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); |
0b2182dd SY |
794 | return 0; |
795 | } | |
796 | ||
79d23495 | 797 | static int rspi_unprepare_message(struct spi_master *master, |
880c6d11 | 798 | struct spi_message *msg) |
0b2182dd | 799 | { |
79d23495 GU |
800 | struct rspi_data *rspi = spi_master_get_devdata(master); |
801 | ||
880c6d11 | 802 | /* Disable SPI function */ |
79d23495 | 803 | rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); |
880c6d11 GU |
804 | |
805 | /* Reset sequencer for Single SPI Transfers */ | |
806 | rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); | |
807 | rspi_write8(rspi, 0, RSPI_SPSCR); | |
79d23495 | 808 | return 0; |
0b2182dd SY |
809 | } |
810 | ||
93722206 | 811 | static irqreturn_t rspi_irq_mux(int irq, void *_sr) |
0b2182dd | 812 | { |
c132f094 | 813 | struct rspi_data *rspi = _sr; |
97b95c11 | 814 | u8 spsr; |
0b2182dd | 815 | irqreturn_t ret = IRQ_NONE; |
97b95c11 | 816 | u8 disable_irq = 0; |
0b2182dd SY |
817 | |
818 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
819 | if (spsr & SPSR_SPRF) | |
820 | disable_irq |= SPCR_SPRIE; | |
821 | if (spsr & SPSR_SPTEF) | |
822 | disable_irq |= SPCR_SPTIE; | |
823 | ||
824 | if (disable_irq) { | |
825 | ret = IRQ_HANDLED; | |
826 | rspi_disable_irq(rspi, disable_irq); | |
827 | wake_up(&rspi->wait); | |
828 | } | |
829 | ||
830 | return ret; | |
831 | } | |
832 | ||
93722206 GU |
833 | static irqreturn_t rspi_irq_rx(int irq, void *_sr) |
834 | { | |
835 | struct rspi_data *rspi = _sr; | |
836 | u8 spsr; | |
837 | ||
838 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
839 | if (spsr & SPSR_SPRF) { | |
840 | rspi_disable_irq(rspi, SPCR_SPRIE); | |
841 | wake_up(&rspi->wait); | |
842 | return IRQ_HANDLED; | |
843 | } | |
844 | ||
845 | return 0; | |
846 | } | |
847 | ||
848 | static irqreturn_t rspi_irq_tx(int irq, void *_sr) | |
849 | { | |
850 | struct rspi_data *rspi = _sr; | |
851 | u8 spsr; | |
852 | ||
853 | rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); | |
854 | if (spsr & SPSR_SPTEF) { | |
855 | rspi_disable_irq(rspi, SPCR_SPTIE); | |
856 | wake_up(&rspi->wait); | |
857 | return IRQ_HANDLED; | |
858 | } | |
859 | ||
860 | return 0; | |
861 | } | |
862 | ||
65bf2205 GU |
863 | static struct dma_chan *rspi_request_dma_chan(struct device *dev, |
864 | enum dma_transfer_direction dir, | |
865 | unsigned int id, | |
866 | dma_addr_t port_addr) | |
a3633fe7 | 867 | { |
a3633fe7 | 868 | dma_cap_mask_t mask; |
65bf2205 | 869 | struct dma_chan *chan; |
0243c536 SY |
870 | struct dma_slave_config cfg; |
871 | int ret; | |
a3633fe7 | 872 | |
65bf2205 GU |
873 | dma_cap_zero(mask); |
874 | dma_cap_set(DMA_SLAVE, mask); | |
875 | ||
876 | chan = dma_request_channel(mask, shdma_chan_filter, | |
877 | (void *)(unsigned long)id); | |
878 | if (!chan) { | |
879 | dev_warn(dev, "dma_request_channel failed\n"); | |
880 | return NULL; | |
881 | } | |
882 | ||
883 | memset(&cfg, 0, sizeof(cfg)); | |
884 | cfg.slave_id = id; | |
885 | cfg.direction = dir; | |
886 | if (dir == DMA_MEM_TO_DEV) | |
887 | cfg.dst_addr = port_addr; | |
888 | else | |
889 | cfg.src_addr = port_addr; | |
890 | ||
891 | ret = dmaengine_slave_config(chan, &cfg); | |
892 | if (ret) { | |
893 | dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); | |
894 | dma_release_channel(chan); | |
895 | return NULL; | |
896 | } | |
897 | ||
898 | return chan; | |
899 | } | |
900 | ||
2f777ec9 | 901 | static int rspi_request_dma(struct device *dev, struct spi_master *master, |
fcdc49ae | 902 | const struct resource *res) |
65bf2205 | 903 | { |
fcdc49ae | 904 | const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev); |
65bf2205 | 905 | |
5f338d0c | 906 | if (!rspi_pd || !rspi_pd->dma_rx_id || !rspi_pd->dma_tx_id) |
0243c536 | 907 | return 0; /* The driver assumes no error. */ |
a3633fe7 | 908 | |
2f777ec9 GU |
909 | master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, |
910 | rspi_pd->dma_rx_id, | |
911 | res->start + RSPI_SPDR); | |
912 | if (!master->dma_rx) | |
5f338d0c GU |
913 | return -ENODEV; |
914 | ||
2f777ec9 GU |
915 | master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, |
916 | rspi_pd->dma_tx_id, | |
917 | res->start + RSPI_SPDR); | |
918 | if (!master->dma_tx) { | |
919 | dma_release_channel(master->dma_rx); | |
920 | master->dma_rx = NULL; | |
5f338d0c | 921 | return -ENODEV; |
a3633fe7 | 922 | } |
0243c536 | 923 | |
2f777ec9 | 924 | master->can_dma = rspi_can_dma; |
5f338d0c | 925 | dev_info(dev, "DMA available"); |
0243c536 | 926 | return 0; |
a3633fe7 SY |
927 | } |
928 | ||
fd4a319b | 929 | static void rspi_release_dma(struct rspi_data *rspi) |
a3633fe7 | 930 | { |
2f777ec9 GU |
931 | if (rspi->master->dma_tx) |
932 | dma_release_channel(rspi->master->dma_tx); | |
933 | if (rspi->master->dma_rx) | |
934 | dma_release_channel(rspi->master->dma_rx); | |
a3633fe7 SY |
935 | } |
936 | ||
fd4a319b | 937 | static int rspi_remove(struct platform_device *pdev) |
0b2182dd | 938 | { |
5ffbe2d9 | 939 | struct rspi_data *rspi = platform_get_drvdata(pdev); |
0b2182dd | 940 | |
a3633fe7 | 941 | rspi_release_dma(rspi); |
490c9774 | 942 | pm_runtime_disable(&pdev->dev); |
0b2182dd SY |
943 | |
944 | return 0; | |
945 | } | |
946 | ||
426ef76d | 947 | static const struct spi_ops rspi_ops = { |
b42e0359 GU |
948 | .set_config_register = rspi_set_config_register, |
949 | .transfer_one = rspi_transfer_one, | |
950 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, | |
951 | .flags = SPI_MASTER_MUST_TX, | |
2f777ec9 | 952 | .fifo_size = 8, |
426ef76d GU |
953 | }; |
954 | ||
955 | static const struct spi_ops rspi_rz_ops = { | |
b42e0359 GU |
956 | .set_config_register = rspi_rz_set_config_register, |
957 | .transfer_one = rspi_rz_transfer_one, | |
958 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, | |
959 | .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX, | |
2f777ec9 | 960 | .fifo_size = 8, /* 8 for TX, 32 for RX */ |
426ef76d GU |
961 | }; |
962 | ||
963 | static const struct spi_ops qspi_ops = { | |
b42e0359 GU |
964 | .set_config_register = qspi_set_config_register, |
965 | .transfer_one = qspi_transfer_one, | |
966 | .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | | |
967 | SPI_TX_DUAL | SPI_TX_QUAD | | |
968 | SPI_RX_DUAL | SPI_RX_QUAD, | |
969 | .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX, | |
2f777ec9 | 970 | .fifo_size = 32, |
426ef76d GU |
971 | }; |
972 | ||
973 | #ifdef CONFIG_OF | |
974 | static const struct of_device_id rspi_of_match[] = { | |
975 | /* RSPI on legacy SH */ | |
976 | { .compatible = "renesas,rspi", .data = &rspi_ops }, | |
977 | /* RSPI on RZ/A1H */ | |
978 | { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, | |
979 | /* QSPI on R-Car Gen2 */ | |
980 | { .compatible = "renesas,qspi", .data = &qspi_ops }, | |
981 | { /* sentinel */ } | |
982 | }; | |
983 | ||
984 | MODULE_DEVICE_TABLE(of, rspi_of_match); | |
985 | ||
986 | static int rspi_parse_dt(struct device *dev, struct spi_master *master) | |
987 | { | |
988 | u32 num_cs; | |
989 | int error; | |
990 | ||
991 | /* Parse DT properties */ | |
992 | error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); | |
993 | if (error) { | |
994 | dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); | |
995 | return error; | |
996 | } | |
997 | ||
998 | master->num_chipselect = num_cs; | |
999 | return 0; | |
1000 | } | |
1001 | #else | |
64b67def | 1002 | #define rspi_of_match NULL |
426ef76d GU |
1003 | static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) |
1004 | { | |
1005 | return -EINVAL; | |
1006 | } | |
1007 | #endif /* CONFIG_OF */ | |
1008 | ||
93722206 GU |
1009 | static int rspi_request_irq(struct device *dev, unsigned int irq, |
1010 | irq_handler_t handler, const char *suffix, | |
1011 | void *dev_id) | |
1012 | { | |
1013 | const char *base = dev_name(dev); | |
1014 | size_t len = strlen(base) + strlen(suffix) + 2; | |
1015 | char *name = devm_kzalloc(dev, len, GFP_KERNEL); | |
1016 | if (!name) | |
1017 | return -ENOMEM; | |
1018 | snprintf(name, len, "%s:%s", base, suffix); | |
1019 | return devm_request_irq(dev, irq, handler, 0, name, dev_id); | |
1020 | } | |
1021 | ||
fd4a319b | 1022 | static int rspi_probe(struct platform_device *pdev) |
0b2182dd SY |
1023 | { |
1024 | struct resource *res; | |
1025 | struct spi_master *master; | |
1026 | struct rspi_data *rspi; | |
93722206 | 1027 | int ret; |
426ef76d GU |
1028 | const struct of_device_id *of_id; |
1029 | const struct rspi_plat_data *rspi_pd; | |
5ce0ba88 | 1030 | const struct spi_ops *ops; |
0b2182dd | 1031 | |
0b2182dd SY |
1032 | master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); |
1033 | if (master == NULL) { | |
1034 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
1035 | return -ENOMEM; | |
1036 | } | |
1037 | ||
426ef76d GU |
1038 | of_id = of_match_device(rspi_of_match, &pdev->dev); |
1039 | if (of_id) { | |
1040 | ops = of_id->data; | |
1041 | ret = rspi_parse_dt(&pdev->dev, master); | |
1042 | if (ret) | |
1043 | goto error1; | |
1044 | } else { | |
1045 | ops = (struct spi_ops *)pdev->id_entry->driver_data; | |
1046 | rspi_pd = dev_get_platdata(&pdev->dev); | |
1047 | if (rspi_pd && rspi_pd->num_chipselect) | |
1048 | master->num_chipselect = rspi_pd->num_chipselect; | |
1049 | else | |
1050 | master->num_chipselect = 2; /* default */ | |
1051 | }; | |
1052 | ||
1053 | /* ops parameter check */ | |
1054 | if (!ops->set_config_register) { | |
1055 | dev_err(&pdev->dev, "there is no set_config_register\n"); | |
1056 | ret = -ENODEV; | |
1057 | goto error1; | |
1058 | } | |
1059 | ||
0b2182dd | 1060 | rspi = spi_master_get_devdata(master); |
24b5a82c | 1061 | platform_set_drvdata(pdev, rspi); |
5ce0ba88 | 1062 | rspi->ops = ops; |
0b2182dd | 1063 | rspi->master = master; |
5d79e9ac LP |
1064 | |
1065 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1066 | rspi->addr = devm_ioremap_resource(&pdev->dev, res); | |
1067 | if (IS_ERR(rspi->addr)) { | |
1068 | ret = PTR_ERR(rspi->addr); | |
0b2182dd SY |
1069 | goto error1; |
1070 | } | |
1071 | ||
29f397b7 | 1072 | rspi->clk = devm_clk_get(&pdev->dev, NULL); |
0b2182dd SY |
1073 | if (IS_ERR(rspi->clk)) { |
1074 | dev_err(&pdev->dev, "cannot get clock\n"); | |
1075 | ret = PTR_ERR(rspi->clk); | |
5d79e9ac | 1076 | goto error1; |
0b2182dd | 1077 | } |
17fe0d9a | 1078 | |
490c9774 | 1079 | pm_runtime_enable(&pdev->dev); |
0b2182dd | 1080 | |
0b2182dd SY |
1081 | init_waitqueue_head(&rspi->wait); |
1082 | ||
0b2182dd SY |
1083 | master->bus_num = pdev->id; |
1084 | master->setup = rspi_setup; | |
490c9774 | 1085 | master->auto_runtime_pm = true; |
eb557f75 | 1086 | master->transfer_one = ops->transfer_one; |
79d23495 GU |
1087 | master->prepare_message = rspi_prepare_message; |
1088 | master->unprepare_message = rspi_unprepare_message; | |
880c6d11 | 1089 | master->mode_bits = ops->mode_bits; |
b42e0359 | 1090 | master->flags = ops->flags; |
426ef76d | 1091 | master->dev.of_node = pdev->dev.of_node; |
0b2182dd | 1092 | |
93722206 GU |
1093 | ret = platform_get_irq_byname(pdev, "rx"); |
1094 | if (ret < 0) { | |
1095 | ret = platform_get_irq_byname(pdev, "mux"); | |
1096 | if (ret < 0) | |
1097 | ret = platform_get_irq(pdev, 0); | |
1098 | if (ret >= 0) | |
1099 | rspi->rx_irq = rspi->tx_irq = ret; | |
1100 | } else { | |
1101 | rspi->rx_irq = ret; | |
1102 | ret = platform_get_irq_byname(pdev, "tx"); | |
1103 | if (ret >= 0) | |
1104 | rspi->tx_irq = ret; | |
1105 | } | |
1106 | if (ret < 0) { | |
1107 | dev_err(&pdev->dev, "platform_get_irq error\n"); | |
1108 | goto error2; | |
1109 | } | |
1110 | ||
1111 | if (rspi->rx_irq == rspi->tx_irq) { | |
1112 | /* Single multiplexed interrupt */ | |
1113 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, | |
1114 | "mux", rspi); | |
1115 | } else { | |
1116 | /* Multi-interrupt mode, only SPRI and SPTI are used */ | |
1117 | ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, | |
1118 | "rx", rspi); | |
1119 | if (!ret) | |
1120 | ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, | |
1121 | rspi_irq_tx, "tx", rspi); | |
1122 | } | |
0b2182dd SY |
1123 | if (ret < 0) { |
1124 | dev_err(&pdev->dev, "request_irq error\n"); | |
fcb4ed74 | 1125 | goto error2; |
0b2182dd SY |
1126 | } |
1127 | ||
2f777ec9 | 1128 | ret = rspi_request_dma(&pdev->dev, master, res); |
27e105a6 GU |
1129 | if (ret < 0) |
1130 | dev_warn(&pdev->dev, "DMA not available, using PIO\n"); | |
a3633fe7 | 1131 | |
9e03d05e | 1132 | ret = devm_spi_register_master(&pdev->dev, master); |
0b2182dd SY |
1133 | if (ret < 0) { |
1134 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
fcb4ed74 | 1135 | goto error3; |
0b2182dd SY |
1136 | } |
1137 | ||
1138 | dev_info(&pdev->dev, "probed\n"); | |
1139 | ||
1140 | return 0; | |
1141 | ||
fcb4ed74 | 1142 | error3: |
5d79e9ac | 1143 | rspi_release_dma(rspi); |
fcb4ed74 | 1144 | error2: |
490c9774 | 1145 | pm_runtime_disable(&pdev->dev); |
0b2182dd SY |
1146 | error1: |
1147 | spi_master_put(master); | |
1148 | ||
1149 | return ret; | |
1150 | } | |
1151 | ||
5ce0ba88 HCM |
1152 | static struct platform_device_id spi_driver_ids[] = { |
1153 | { "rspi", (kernel_ulong_t)&rspi_ops }, | |
862d357f | 1154 | { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, |
5ce0ba88 HCM |
1155 | { "qspi", (kernel_ulong_t)&qspi_ops }, |
1156 | {}, | |
1157 | }; | |
1158 | ||
1159 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); | |
1160 | ||
0b2182dd SY |
1161 | static struct platform_driver rspi_driver = { |
1162 | .probe = rspi_probe, | |
fd4a319b | 1163 | .remove = rspi_remove, |
5ce0ba88 | 1164 | .id_table = spi_driver_ids, |
0b2182dd | 1165 | .driver = { |
5ce0ba88 | 1166 | .name = "renesas_spi", |
0b2182dd | 1167 | .owner = THIS_MODULE, |
426ef76d | 1168 | .of_match_table = of_match_ptr(rspi_of_match), |
0b2182dd SY |
1169 | }, |
1170 | }; | |
1171 | module_platform_driver(rspi_driver); | |
1172 | ||
1173 | MODULE_DESCRIPTION("Renesas RSPI bus driver"); | |
1174 | MODULE_LICENSE("GPL v2"); | |
1175 | MODULE_AUTHOR("Yoshihiro Shimoda"); | |
1176 | MODULE_ALIAS("platform:rspi"); |