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Commit | Line | Data |
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ca632f55 | 1 | /* |
230d42d4 JB |
2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
3 | * Jaswinder Singh <jassi.brar@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/workqueue.h> | |
c2573128 | 23 | #include <linux/interrupt.h> |
230d42d4 JB |
24 | #include <linux/delay.h> |
25 | #include <linux/clk.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/platform_device.h> | |
b97b6621 | 28 | #include <linux/pm_runtime.h> |
230d42d4 JB |
29 | #include <linux/spi/spi.h> |
30 | ||
31 | #include <mach/dma.h> | |
e6b873c9 | 32 | #include <plat/s3c64xx-spi.h> |
230d42d4 JB |
33 | |
34 | /* Registers and bit-fields */ | |
35 | ||
36 | #define S3C64XX_SPI_CH_CFG 0x00 | |
37 | #define S3C64XX_SPI_CLK_CFG 0x04 | |
38 | #define S3C64XX_SPI_MODE_CFG 0x08 | |
39 | #define S3C64XX_SPI_SLAVE_SEL 0x0C | |
40 | #define S3C64XX_SPI_INT_EN 0x10 | |
41 | #define S3C64XX_SPI_STATUS 0x14 | |
42 | #define S3C64XX_SPI_TX_DATA 0x18 | |
43 | #define S3C64XX_SPI_RX_DATA 0x1C | |
44 | #define S3C64XX_SPI_PACKET_CNT 0x20 | |
45 | #define S3C64XX_SPI_PENDING_CLR 0x24 | |
46 | #define S3C64XX_SPI_SWAP_CFG 0x28 | |
47 | #define S3C64XX_SPI_FB_CLK 0x2C | |
48 | ||
49 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ | |
50 | #define S3C64XX_SPI_CH_SW_RST (1<<5) | |
51 | #define S3C64XX_SPI_CH_SLAVE (1<<4) | |
52 | #define S3C64XX_SPI_CPOL_L (1<<3) | |
53 | #define S3C64XX_SPI_CPHA_B (1<<2) | |
54 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) | |
55 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) | |
56 | ||
57 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) | |
58 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 | |
59 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) | |
60 | #define S3C64XX_SPI_PSR_MASK 0xff | |
61 | ||
62 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) | |
63 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) | |
64 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) | |
65 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) | |
66 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) | |
67 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) | |
68 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) | |
69 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) | |
70 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) | |
71 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) | |
72 | #define S3C64XX_SPI_MODE_4BURST (1<<0) | |
73 | ||
74 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) | |
75 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) | |
76 | ||
77 | #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL) | |
78 | ||
79 | #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \ | |
80 | (c)->regs + S3C64XX_SPI_SLAVE_SEL) | |
81 | ||
82 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) | |
83 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) | |
84 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) | |
85 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) | |
86 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) | |
87 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) | |
88 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) | |
89 | ||
90 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) | |
91 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) | |
92 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) | |
93 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) | |
94 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) | |
95 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) | |
96 | ||
97 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) | |
98 | ||
99 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) | |
100 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) | |
101 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) | |
102 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) | |
103 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) | |
104 | ||
105 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) | |
106 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) | |
107 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) | |
108 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) | |
109 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) | |
110 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) | |
111 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) | |
112 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) | |
113 | ||
114 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) | |
115 | ||
116 | #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \ | |
117 | (((i)->fifo_lvl_mask + 1))) \ | |
118 | ? 1 : 0) | |
119 | ||
30757414 | 120 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0) |
230d42d4 JB |
121 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask) |
122 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask) | |
123 | ||
124 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff | |
125 | #define S3C64XX_SPI_TRAILCNT_OFF 19 | |
126 | ||
127 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT | |
128 | ||
129 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
130 | ||
131 | #define SUSPND (1<<0) | |
132 | #define SPIBUSY (1<<1) | |
133 | #define RXBUSY (1<<2) | |
134 | #define TXBUSY (1<<3) | |
135 | ||
82ab8cd7 BK |
136 | struct s3c64xx_spi_dma_data { |
137 | unsigned ch; | |
138 | enum dma_data_direction direction; | |
139 | enum dma_ch dmach; | |
140 | }; | |
141 | ||
230d42d4 JB |
142 | /** |
143 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. | |
144 | * @clk: Pointer to the spi clock. | |
b0d5d6e5 | 145 | * @src_clk: Pointer to the clock used to generate SPI signals. |
230d42d4 JB |
146 | * @master: Pointer to the SPI Protocol master. |
147 | * @workqueue: Work queue for the SPI xfer requests. | |
148 | * @cntrlr_info: Platform specific data for the controller this driver manages. | |
149 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. | |
150 | * @work: Work | |
151 | * @queue: To log SPI xfer requests. | |
152 | * @lock: Controller specific lock. | |
153 | * @state: Set of FLAGS to indicate status. | |
154 | * @rx_dmach: Controller's DMA channel for Rx. | |
155 | * @tx_dmach: Controller's DMA channel for Tx. | |
156 | * @sfr_start: BUS address of SPI controller regs. | |
157 | * @regs: Pointer to ioremap'ed controller registers. | |
c2573128 | 158 | * @irq: interrupt |
230d42d4 JB |
159 | * @xfer_completion: To indicate completion of xfer task. |
160 | * @cur_mode: Stores the active configuration of the controller. | |
161 | * @cur_bpw: Stores the active bits per word settings. | |
162 | * @cur_speed: Stores the active xfer clock speed. | |
163 | */ | |
164 | struct s3c64xx_spi_driver_data { | |
165 | void __iomem *regs; | |
166 | struct clk *clk; | |
b0d5d6e5 | 167 | struct clk *src_clk; |
230d42d4 JB |
168 | struct platform_device *pdev; |
169 | struct spi_master *master; | |
170 | struct workqueue_struct *workqueue; | |
ad7de729 | 171 | struct s3c64xx_spi_info *cntrlr_info; |
230d42d4 JB |
172 | struct spi_device *tgl_spi; |
173 | struct work_struct work; | |
174 | struct list_head queue; | |
175 | spinlock_t lock; | |
230d42d4 JB |
176 | unsigned long sfr_start; |
177 | struct completion xfer_completion; | |
178 | unsigned state; | |
179 | unsigned cur_mode, cur_bpw; | |
180 | unsigned cur_speed; | |
82ab8cd7 BK |
181 | struct s3c64xx_spi_dma_data rx_dma; |
182 | struct s3c64xx_spi_dma_data tx_dma; | |
39d3e807 | 183 | struct samsung_dma_ops *ops; |
230d42d4 JB |
184 | }; |
185 | ||
186 | static struct s3c2410_dma_client s3c64xx_spi_dma_client = { | |
187 | .name = "samsung-spi-dma", | |
188 | }; | |
189 | ||
190 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) | |
191 | { | |
ad7de729 | 192 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
193 | void __iomem *regs = sdd->regs; |
194 | unsigned long loops; | |
195 | u32 val; | |
196 | ||
197 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
198 | ||
199 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
200 | val |= S3C64XX_SPI_CH_SW_RST; | |
201 | val &= ~S3C64XX_SPI_CH_HS_EN; | |
202 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
203 | ||
204 | /* Flush TxFIFO*/ | |
205 | loops = msecs_to_loops(1); | |
206 | do { | |
207 | val = readl(regs + S3C64XX_SPI_STATUS); | |
208 | } while (TX_FIFO_LVL(val, sci) && loops--); | |
209 | ||
be7852a8 MB |
210 | if (loops == 0) |
211 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); | |
212 | ||
230d42d4 JB |
213 | /* Flush RxFIFO*/ |
214 | loops = msecs_to_loops(1); | |
215 | do { | |
216 | val = readl(regs + S3C64XX_SPI_STATUS); | |
217 | if (RX_FIFO_LVL(val, sci)) | |
218 | readl(regs + S3C64XX_SPI_RX_DATA); | |
219 | else | |
220 | break; | |
221 | } while (loops--); | |
222 | ||
be7852a8 MB |
223 | if (loops == 0) |
224 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); | |
225 | ||
230d42d4 JB |
226 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
227 | val &= ~S3C64XX_SPI_CH_SW_RST; | |
228 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
229 | ||
230 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
231 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
232 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
233 | ||
234 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
235 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); | |
236 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
237 | } | |
238 | ||
82ab8cd7 | 239 | static void s3c64xx_spi_dmacb(void *data) |
39d3e807 | 240 | { |
82ab8cd7 BK |
241 | struct s3c64xx_spi_driver_data *sdd; |
242 | struct s3c64xx_spi_dma_data *dma = data; | |
39d3e807 BK |
243 | unsigned long flags; |
244 | ||
82ab8cd7 BK |
245 | if (dma->direction == DMA_FROM_DEVICE) |
246 | sdd = container_of(data, | |
247 | struct s3c64xx_spi_driver_data, rx_dma); | |
248 | else | |
249 | sdd = container_of(data, | |
250 | struct s3c64xx_spi_driver_data, tx_dma); | |
251 | ||
39d3e807 BK |
252 | spin_lock_irqsave(&sdd->lock, flags); |
253 | ||
82ab8cd7 BK |
254 | if (dma->direction == DMA_FROM_DEVICE) { |
255 | sdd->state &= ~RXBUSY; | |
256 | if (!(sdd->state & TXBUSY)) | |
257 | complete(&sdd->xfer_completion); | |
258 | } else { | |
259 | sdd->state &= ~TXBUSY; | |
260 | if (!(sdd->state & RXBUSY)) | |
261 | complete(&sdd->xfer_completion); | |
262 | } | |
39d3e807 BK |
263 | |
264 | spin_unlock_irqrestore(&sdd->lock, flags); | |
265 | } | |
266 | ||
82ab8cd7 BK |
267 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
268 | unsigned len, dma_addr_t buf) | |
39d3e807 | 269 | { |
82ab8cd7 BK |
270 | struct s3c64xx_spi_driver_data *sdd; |
271 | struct samsung_dma_prep_info info; | |
39d3e807 | 272 | |
82ab8cd7 BK |
273 | if (dma->direction == DMA_FROM_DEVICE) |
274 | sdd = container_of((void *)dma, | |
275 | struct s3c64xx_spi_driver_data, rx_dma); | |
276 | else | |
277 | sdd = container_of((void *)dma, | |
278 | struct s3c64xx_spi_driver_data, tx_dma); | |
39d3e807 | 279 | |
82ab8cd7 BK |
280 | info.cap = DMA_SLAVE; |
281 | info.len = len; | |
282 | info.fp = s3c64xx_spi_dmacb; | |
283 | info.fp_param = dma; | |
284 | info.direction = dma->direction; | |
285 | info.buf = buf; | |
286 | ||
287 | sdd->ops->prepare(dma->ch, &info); | |
288 | sdd->ops->trigger(dma->ch); | |
289 | } | |
39d3e807 | 290 | |
82ab8cd7 BK |
291 | static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) |
292 | { | |
293 | struct samsung_dma_info info; | |
294 | ||
295 | sdd->ops = samsung_dma_get_ops(); | |
296 | ||
297 | info.cap = DMA_SLAVE; | |
298 | info.client = &s3c64xx_spi_dma_client; | |
299 | info.width = sdd->cur_bpw / 8; | |
300 | ||
301 | info.direction = sdd->rx_dma.direction; | |
302 | info.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA; | |
303 | sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &info); | |
304 | info.direction = sdd->tx_dma.direction; | |
305 | info.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA; | |
306 | sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &info); | |
307 | ||
308 | return 1; | |
39d3e807 BK |
309 | } |
310 | ||
230d42d4 JB |
311 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
312 | struct spi_device *spi, | |
313 | struct spi_transfer *xfer, int dma_mode) | |
314 | { | |
ad7de729 | 315 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
316 | void __iomem *regs = sdd->regs; |
317 | u32 modecfg, chcfg; | |
318 | ||
319 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); | |
320 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
321 | ||
322 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); | |
323 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; | |
324 | ||
325 | if (dma_mode) { | |
326 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; | |
327 | } else { | |
328 | /* Always shift in data in FIFO, even if xfer is Tx only, | |
329 | * this helps setting PCKT_CNT value for generating clocks | |
330 | * as exactly needed. | |
331 | */ | |
332 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
333 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
334 | | S3C64XX_SPI_PACKET_CNT_EN, | |
335 | regs + S3C64XX_SPI_PACKET_CNT); | |
336 | } | |
337 | ||
338 | if (xfer->tx_buf != NULL) { | |
339 | sdd->state |= TXBUSY; | |
340 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; | |
341 | if (dma_mode) { | |
342 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; | |
82ab8cd7 | 343 | prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma); |
230d42d4 | 344 | } else { |
0c92ecf1 JB |
345 | switch (sdd->cur_bpw) { |
346 | case 32: | |
347 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, | |
348 | xfer->tx_buf, xfer->len / 4); | |
349 | break; | |
350 | case 16: | |
351 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, | |
352 | xfer->tx_buf, xfer->len / 2); | |
353 | break; | |
354 | default: | |
355 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, | |
356 | xfer->tx_buf, xfer->len); | |
357 | break; | |
358 | } | |
230d42d4 JB |
359 | } |
360 | } | |
361 | ||
362 | if (xfer->rx_buf != NULL) { | |
363 | sdd->state |= RXBUSY; | |
364 | ||
365 | if (sci->high_speed && sdd->cur_speed >= 30000000UL | |
366 | && !(sdd->cur_mode & SPI_CPHA)) | |
367 | chcfg |= S3C64XX_SPI_CH_HS_EN; | |
368 | ||
369 | if (dma_mode) { | |
370 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; | |
371 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
372 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
373 | | S3C64XX_SPI_PACKET_CNT_EN, | |
374 | regs + S3C64XX_SPI_PACKET_CNT); | |
82ab8cd7 | 375 | prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma); |
230d42d4 JB |
376 | } |
377 | } | |
378 | ||
379 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); | |
380 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); | |
381 | } | |
382 | ||
383 | static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, | |
384 | struct spi_device *spi) | |
385 | { | |
386 | struct s3c64xx_spi_csinfo *cs; | |
387 | ||
388 | if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */ | |
389 | if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ | |
390 | /* Deselect the last toggled device */ | |
391 | cs = sdd->tgl_spi->controller_data; | |
fa0fcde6 JB |
392 | cs->set_level(cs->line, |
393 | spi->mode & SPI_CS_HIGH ? 0 : 1); | |
230d42d4 JB |
394 | } |
395 | sdd->tgl_spi = NULL; | |
396 | } | |
397 | ||
398 | cs = spi->controller_data; | |
fa0fcde6 | 399 | cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); |
230d42d4 JB |
400 | } |
401 | ||
402 | static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, | |
403 | struct spi_transfer *xfer, int dma_mode) | |
404 | { | |
ad7de729 | 405 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
406 | void __iomem *regs = sdd->regs; |
407 | unsigned long val; | |
408 | int ms; | |
409 | ||
410 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ | |
411 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
9d8f86b5 | 412 | ms += 10; /* some tolerance */ |
230d42d4 JB |
413 | |
414 | if (dma_mode) { | |
415 | val = msecs_to_jiffies(ms) + 10; | |
416 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); | |
417 | } else { | |
c3f139b6 | 418 | u32 status; |
230d42d4 JB |
419 | val = msecs_to_loops(ms); |
420 | do { | |
c3f139b6 JB |
421 | status = readl(regs + S3C64XX_SPI_STATUS); |
422 | } while (RX_FIFO_LVL(status, sci) < xfer->len && --val); | |
230d42d4 JB |
423 | } |
424 | ||
425 | if (!val) | |
426 | return -EIO; | |
427 | ||
428 | if (dma_mode) { | |
429 | u32 status; | |
430 | ||
431 | /* | |
432 | * DmaTx returns after simply writing data in the FIFO, | |
433 | * w/o waiting for real transmission on the bus to finish. | |
434 | * DmaRx returns only after Dma read data from FIFO which | |
435 | * needs bus transmission to finish, so we don't worry if | |
436 | * Xfer involved Rx(with or without Tx). | |
437 | */ | |
438 | if (xfer->rx_buf == NULL) { | |
439 | val = msecs_to_loops(10); | |
440 | status = readl(regs + S3C64XX_SPI_STATUS); | |
441 | while ((TX_FIFO_LVL(status, sci) | |
442 | || !S3C64XX_SPI_ST_TX_DONE(status, sci)) | |
443 | && --val) { | |
444 | cpu_relax(); | |
445 | status = readl(regs + S3C64XX_SPI_STATUS); | |
446 | } | |
447 | ||
448 | if (!val) | |
449 | return -EIO; | |
450 | } | |
451 | } else { | |
230d42d4 JB |
452 | /* If it was only Tx */ |
453 | if (xfer->rx_buf == NULL) { | |
454 | sdd->state &= ~TXBUSY; | |
455 | return 0; | |
456 | } | |
457 | ||
0c92ecf1 JB |
458 | switch (sdd->cur_bpw) { |
459 | case 32: | |
460 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, | |
461 | xfer->rx_buf, xfer->len / 4); | |
462 | break; | |
463 | case 16: | |
464 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, | |
465 | xfer->rx_buf, xfer->len / 2); | |
466 | break; | |
467 | default: | |
468 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, | |
469 | xfer->rx_buf, xfer->len); | |
470 | break; | |
471 | } | |
230d42d4 JB |
472 | sdd->state &= ~RXBUSY; |
473 | } | |
474 | ||
475 | return 0; | |
476 | } | |
477 | ||
478 | static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, | |
479 | struct spi_device *spi) | |
480 | { | |
481 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
482 | ||
483 | if (sdd->tgl_spi == spi) | |
484 | sdd->tgl_spi = NULL; | |
485 | ||
fa0fcde6 | 486 | cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); |
230d42d4 JB |
487 | } |
488 | ||
489 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) | |
490 | { | |
b42a81ca | 491 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
492 | void __iomem *regs = sdd->regs; |
493 | u32 val; | |
494 | ||
495 | /* Disable Clock */ | |
b42a81ca JB |
496 | if (sci->clk_from_cmu) { |
497 | clk_disable(sdd->src_clk); | |
498 | } else { | |
499 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
500 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; | |
501 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
502 | } | |
230d42d4 JB |
503 | |
504 | /* Set Polarity and Phase */ | |
505 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
506 | val &= ~(S3C64XX_SPI_CH_SLAVE | | |
507 | S3C64XX_SPI_CPOL_L | | |
508 | S3C64XX_SPI_CPHA_B); | |
509 | ||
510 | if (sdd->cur_mode & SPI_CPOL) | |
511 | val |= S3C64XX_SPI_CPOL_L; | |
512 | ||
513 | if (sdd->cur_mode & SPI_CPHA) | |
514 | val |= S3C64XX_SPI_CPHA_B; | |
515 | ||
516 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
517 | ||
518 | /* Set Channel & DMA Mode */ | |
519 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
520 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK | |
521 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); | |
522 | ||
523 | switch (sdd->cur_bpw) { | |
524 | case 32: | |
525 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; | |
0c92ecf1 | 526 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
230d42d4 JB |
527 | break; |
528 | case 16: | |
529 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; | |
0c92ecf1 | 530 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
230d42d4 JB |
531 | break; |
532 | default: | |
533 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; | |
0c92ecf1 | 534 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
230d42d4 JB |
535 | break; |
536 | } | |
230d42d4 JB |
537 | |
538 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
539 | ||
b42a81ca JB |
540 | if (sci->clk_from_cmu) { |
541 | /* Configure Clock */ | |
542 | /* There is half-multiplier before the SPI */ | |
543 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); | |
544 | /* Enable Clock */ | |
545 | clk_enable(sdd->src_clk); | |
546 | } else { | |
547 | /* Configure Clock */ | |
548 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
549 | val &= ~S3C64XX_SPI_PSR_MASK; | |
550 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) | |
551 | & S3C64XX_SPI_PSR_MASK); | |
552 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
553 | ||
554 | /* Enable Clock */ | |
555 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
556 | val |= S3C64XX_SPI_ENCLK_ENABLE; | |
557 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
558 | } | |
230d42d4 JB |
559 | } |
560 | ||
230d42d4 JB |
561 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
562 | ||
563 | static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, | |
564 | struct spi_message *msg) | |
565 | { | |
e02ddd44 | 566 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
567 | struct device *dev = &sdd->pdev->dev; |
568 | struct spi_transfer *xfer; | |
569 | ||
570 | if (msg->is_dma_mapped) | |
571 | return 0; | |
572 | ||
573 | /* First mark all xfer unmapped */ | |
574 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
575 | xfer->rx_dma = XFER_DMAADDR_INVALID; | |
576 | xfer->tx_dma = XFER_DMAADDR_INVALID; | |
577 | } | |
578 | ||
579 | /* Map until end or first fail */ | |
580 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
581 | ||
e02ddd44 JB |
582 | if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) |
583 | continue; | |
584 | ||
230d42d4 | 585 | if (xfer->tx_buf != NULL) { |
251ee478 JB |
586 | xfer->tx_dma = dma_map_single(dev, |
587 | (void *)xfer->tx_buf, xfer->len, | |
588 | DMA_TO_DEVICE); | |
230d42d4 JB |
589 | if (dma_mapping_error(dev, xfer->tx_dma)) { |
590 | dev_err(dev, "dma_map_single Tx failed\n"); | |
591 | xfer->tx_dma = XFER_DMAADDR_INVALID; | |
592 | return -ENOMEM; | |
593 | } | |
594 | } | |
595 | ||
596 | if (xfer->rx_buf != NULL) { | |
597 | xfer->rx_dma = dma_map_single(dev, xfer->rx_buf, | |
598 | xfer->len, DMA_FROM_DEVICE); | |
599 | if (dma_mapping_error(dev, xfer->rx_dma)) { | |
600 | dev_err(dev, "dma_map_single Rx failed\n"); | |
601 | dma_unmap_single(dev, xfer->tx_dma, | |
602 | xfer->len, DMA_TO_DEVICE); | |
603 | xfer->tx_dma = XFER_DMAADDR_INVALID; | |
604 | xfer->rx_dma = XFER_DMAADDR_INVALID; | |
605 | return -ENOMEM; | |
606 | } | |
607 | } | |
608 | } | |
609 | ||
610 | return 0; | |
611 | } | |
612 | ||
613 | static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, | |
614 | struct spi_message *msg) | |
615 | { | |
e02ddd44 | 616 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
617 | struct device *dev = &sdd->pdev->dev; |
618 | struct spi_transfer *xfer; | |
619 | ||
620 | if (msg->is_dma_mapped) | |
621 | return; | |
622 | ||
623 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
624 | ||
e02ddd44 JB |
625 | if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) |
626 | continue; | |
627 | ||
230d42d4 JB |
628 | if (xfer->rx_buf != NULL |
629 | && xfer->rx_dma != XFER_DMAADDR_INVALID) | |
630 | dma_unmap_single(dev, xfer->rx_dma, | |
631 | xfer->len, DMA_FROM_DEVICE); | |
632 | ||
633 | if (xfer->tx_buf != NULL | |
634 | && xfer->tx_dma != XFER_DMAADDR_INVALID) | |
635 | dma_unmap_single(dev, xfer->tx_dma, | |
636 | xfer->len, DMA_TO_DEVICE); | |
637 | } | |
638 | } | |
639 | ||
640 | static void handle_msg(struct s3c64xx_spi_driver_data *sdd, | |
641 | struct spi_message *msg) | |
642 | { | |
ad7de729 | 643 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
644 | struct spi_device *spi = msg->spi; |
645 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
646 | struct spi_transfer *xfer; | |
647 | int status = 0, cs_toggle = 0; | |
648 | u32 speed; | |
649 | u8 bpw; | |
650 | ||
651 | /* If Master's(controller) state differs from that needed by Slave */ | |
652 | if (sdd->cur_speed != spi->max_speed_hz | |
653 | || sdd->cur_mode != spi->mode | |
654 | || sdd->cur_bpw != spi->bits_per_word) { | |
655 | sdd->cur_bpw = spi->bits_per_word; | |
656 | sdd->cur_speed = spi->max_speed_hz; | |
657 | sdd->cur_mode = spi->mode; | |
658 | s3c64xx_spi_config(sdd); | |
659 | } | |
660 | ||
661 | /* Map all the transfers if needed */ | |
662 | if (s3c64xx_spi_map_mssg(sdd, msg)) { | |
663 | dev_err(&spi->dev, | |
664 | "Xfer: Unable to map message buffers!\n"); | |
665 | status = -ENOMEM; | |
666 | goto out; | |
667 | } | |
668 | ||
669 | /* Configure feedback delay */ | |
670 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); | |
671 | ||
672 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
673 | ||
674 | unsigned long flags; | |
675 | int use_dma; | |
676 | ||
677 | INIT_COMPLETION(sdd->xfer_completion); | |
678 | ||
679 | /* Only BPW and Speed may change across transfers */ | |
680 | bpw = xfer->bits_per_word ? : spi->bits_per_word; | |
681 | speed = xfer->speed_hz ? : spi->max_speed_hz; | |
682 | ||
0c92ecf1 JB |
683 | if (xfer->len % (bpw / 8)) { |
684 | dev_err(&spi->dev, | |
685 | "Xfer length(%u) not a multiple of word size(%u)\n", | |
686 | xfer->len, bpw / 8); | |
687 | status = -EIO; | |
688 | goto out; | |
689 | } | |
690 | ||
230d42d4 JB |
691 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
692 | sdd->cur_bpw = bpw; | |
693 | sdd->cur_speed = speed; | |
694 | s3c64xx_spi_config(sdd); | |
695 | } | |
696 | ||
697 | /* Polling method for xfers not bigger than FIFO capacity */ | |
698 | if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) | |
699 | use_dma = 0; | |
700 | else | |
701 | use_dma = 1; | |
702 | ||
703 | spin_lock_irqsave(&sdd->lock, flags); | |
704 | ||
705 | /* Pending only which is to be done */ | |
706 | sdd->state &= ~RXBUSY; | |
707 | sdd->state &= ~TXBUSY; | |
708 | ||
709 | enable_datapath(sdd, spi, xfer, use_dma); | |
710 | ||
711 | /* Slave Select */ | |
712 | enable_cs(sdd, spi); | |
713 | ||
714 | /* Start the signals */ | |
715 | S3C64XX_SPI_ACT(sdd); | |
716 | ||
717 | spin_unlock_irqrestore(&sdd->lock, flags); | |
718 | ||
719 | status = wait_for_xfer(sdd, xfer, use_dma); | |
720 | ||
721 | /* Quiese the signals */ | |
722 | S3C64XX_SPI_DEACT(sdd); | |
723 | ||
724 | if (status) { | |
8a349d4b JP |
725 | dev_err(&spi->dev, "I/O Error: " |
726 | "rx-%d tx-%d res:rx-%c tx-%c len-%d\n", | |
230d42d4 JB |
727 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, |
728 | (sdd->state & RXBUSY) ? 'f' : 'p', | |
729 | (sdd->state & TXBUSY) ? 'f' : 'p', | |
730 | xfer->len); | |
731 | ||
732 | if (use_dma) { | |
733 | if (xfer->tx_buf != NULL | |
734 | && (sdd->state & TXBUSY)) | |
82ab8cd7 | 735 | sdd->ops->stop(sdd->tx_dma.ch); |
230d42d4 JB |
736 | if (xfer->rx_buf != NULL |
737 | && (sdd->state & RXBUSY)) | |
82ab8cd7 | 738 | sdd->ops->stop(sdd->rx_dma.ch); |
230d42d4 JB |
739 | } |
740 | ||
741 | goto out; | |
742 | } | |
743 | ||
744 | if (xfer->delay_usecs) | |
745 | udelay(xfer->delay_usecs); | |
746 | ||
747 | if (xfer->cs_change) { | |
748 | /* Hint that the next mssg is gonna be | |
749 | for the same device */ | |
750 | if (list_is_last(&xfer->transfer_list, | |
751 | &msg->transfers)) | |
752 | cs_toggle = 1; | |
753 | else | |
754 | disable_cs(sdd, spi); | |
755 | } | |
756 | ||
757 | msg->actual_length += xfer->len; | |
758 | ||
759 | flush_fifo(sdd); | |
760 | } | |
761 | ||
762 | out: | |
763 | if (!cs_toggle || status) | |
764 | disable_cs(sdd, spi); | |
765 | else | |
766 | sdd->tgl_spi = spi; | |
767 | ||
768 | s3c64xx_spi_unmap_mssg(sdd, msg); | |
769 | ||
770 | msg->status = status; | |
771 | ||
772 | if (msg->complete) | |
773 | msg->complete(msg->context); | |
774 | } | |
775 | ||
230d42d4 JB |
776 | static void s3c64xx_spi_work(struct work_struct *work) |
777 | { | |
778 | struct s3c64xx_spi_driver_data *sdd = container_of(work, | |
779 | struct s3c64xx_spi_driver_data, work); | |
780 | unsigned long flags; | |
781 | ||
782 | /* Acquire DMA channels */ | |
783 | while (!acquire_dma(sdd)) | |
784 | msleep(10); | |
785 | ||
b97b6621 MB |
786 | pm_runtime_get_sync(&sdd->pdev->dev); |
787 | ||
230d42d4 JB |
788 | spin_lock_irqsave(&sdd->lock, flags); |
789 | ||
790 | while (!list_empty(&sdd->queue) | |
791 | && !(sdd->state & SUSPND)) { | |
792 | ||
793 | struct spi_message *msg; | |
794 | ||
795 | msg = container_of(sdd->queue.next, struct spi_message, queue); | |
796 | ||
797 | list_del_init(&msg->queue); | |
798 | ||
799 | /* Set Xfer busy flag */ | |
800 | sdd->state |= SPIBUSY; | |
801 | ||
802 | spin_unlock_irqrestore(&sdd->lock, flags); | |
803 | ||
804 | handle_msg(sdd, msg); | |
805 | ||
806 | spin_lock_irqsave(&sdd->lock, flags); | |
807 | ||
808 | sdd->state &= ~SPIBUSY; | |
809 | } | |
810 | ||
811 | spin_unlock_irqrestore(&sdd->lock, flags); | |
812 | ||
813 | /* Free DMA channels */ | |
82ab8cd7 BK |
814 | sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client); |
815 | sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client); | |
b97b6621 MB |
816 | |
817 | pm_runtime_put(&sdd->pdev->dev); | |
230d42d4 JB |
818 | } |
819 | ||
820 | static int s3c64xx_spi_transfer(struct spi_device *spi, | |
821 | struct spi_message *msg) | |
822 | { | |
823 | struct s3c64xx_spi_driver_data *sdd; | |
824 | unsigned long flags; | |
825 | ||
826 | sdd = spi_master_get_devdata(spi->master); | |
827 | ||
828 | spin_lock_irqsave(&sdd->lock, flags); | |
829 | ||
830 | if (sdd->state & SUSPND) { | |
831 | spin_unlock_irqrestore(&sdd->lock, flags); | |
832 | return -ESHUTDOWN; | |
833 | } | |
834 | ||
835 | msg->status = -EINPROGRESS; | |
836 | msg->actual_length = 0; | |
837 | ||
838 | list_add_tail(&msg->queue, &sdd->queue); | |
839 | ||
840 | queue_work(sdd->workqueue, &sdd->work); | |
841 | ||
842 | spin_unlock_irqrestore(&sdd->lock, flags); | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
847 | /* | |
848 | * Here we only check the validity of requested configuration | |
849 | * and save the configuration in a local data-structure. | |
850 | * The controller is actually configured only just before we | |
851 | * get a message to transfer. | |
852 | */ | |
853 | static int s3c64xx_spi_setup(struct spi_device *spi) | |
854 | { | |
855 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
856 | struct s3c64xx_spi_driver_data *sdd; | |
ad7de729 | 857 | struct s3c64xx_spi_info *sci; |
230d42d4 | 858 | struct spi_message *msg; |
230d42d4 JB |
859 | unsigned long flags; |
860 | int err = 0; | |
861 | ||
862 | if (cs == NULL || cs->set_level == NULL) { | |
863 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); | |
864 | return -ENODEV; | |
865 | } | |
866 | ||
867 | sdd = spi_master_get_devdata(spi->master); | |
868 | sci = sdd->cntrlr_info; | |
869 | ||
870 | spin_lock_irqsave(&sdd->lock, flags); | |
871 | ||
872 | list_for_each_entry(msg, &sdd->queue, queue) { | |
873 | /* Is some mssg is already queued for this device */ | |
874 | if (msg->spi == spi) { | |
875 | dev_err(&spi->dev, | |
876 | "setup: attempt while mssg in queue!\n"); | |
877 | spin_unlock_irqrestore(&sdd->lock, flags); | |
878 | return -EBUSY; | |
879 | } | |
880 | } | |
881 | ||
882 | if (sdd->state & SUSPND) { | |
883 | spin_unlock_irqrestore(&sdd->lock, flags); | |
884 | dev_err(&spi->dev, | |
885 | "setup: SPI-%d not active!\n", spi->master->bus_num); | |
886 | return -ESHUTDOWN; | |
887 | } | |
888 | ||
889 | spin_unlock_irqrestore(&sdd->lock, flags); | |
890 | ||
891 | if (spi->bits_per_word != 8 | |
892 | && spi->bits_per_word != 16 | |
893 | && spi->bits_per_word != 32) { | |
894 | dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n", | |
895 | spi->bits_per_word); | |
896 | err = -EINVAL; | |
897 | goto setup_exit; | |
898 | } | |
899 | ||
b97b6621 MB |
900 | pm_runtime_get_sync(&sdd->pdev->dev); |
901 | ||
230d42d4 | 902 | /* Check if we can provide the requested rate */ |
b42a81ca JB |
903 | if (!sci->clk_from_cmu) { |
904 | u32 psr, speed; | |
905 | ||
906 | /* Max possible */ | |
907 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); | |
908 | ||
909 | if (spi->max_speed_hz > speed) | |
910 | spi->max_speed_hz = speed; | |
911 | ||
912 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; | |
913 | psr &= S3C64XX_SPI_PSR_MASK; | |
914 | if (psr == S3C64XX_SPI_PSR_MASK) | |
915 | psr--; | |
916 | ||
917 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); | |
918 | if (spi->max_speed_hz < speed) { | |
919 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { | |
920 | psr++; | |
921 | } else { | |
922 | err = -EINVAL; | |
923 | goto setup_exit; | |
924 | } | |
925 | } | |
230d42d4 | 926 | |
b42a81ca JB |
927 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
928 | if (spi->max_speed_hz >= speed) | |
929 | spi->max_speed_hz = speed; | |
930 | else | |
230d42d4 | 931 | err = -EINVAL; |
230d42d4 JB |
932 | } |
933 | ||
b97b6621 MB |
934 | pm_runtime_put(&sdd->pdev->dev); |
935 | ||
230d42d4 JB |
936 | setup_exit: |
937 | ||
938 | /* setup() returns with device de-selected */ | |
939 | disable_cs(sdd, spi); | |
940 | ||
941 | return err; | |
942 | } | |
943 | ||
c2573128 MB |
944 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
945 | { | |
946 | struct s3c64xx_spi_driver_data *sdd = data; | |
947 | struct spi_master *spi = sdd->master; | |
948 | unsigned int val; | |
949 | ||
950 | val = readl(sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
951 | ||
952 | val &= S3C64XX_SPI_PND_RX_OVERRUN_CLR | | |
953 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | | |
954 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | | |
955 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
956 | ||
957 | writel(val, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
958 | ||
959 | if (val & S3C64XX_SPI_PND_RX_OVERRUN_CLR) | |
960 | dev_err(&spi->dev, "RX overrun\n"); | |
961 | if (val & S3C64XX_SPI_PND_RX_UNDERRUN_CLR) | |
962 | dev_err(&spi->dev, "RX underrun\n"); | |
963 | if (val & S3C64XX_SPI_PND_TX_OVERRUN_CLR) | |
964 | dev_err(&spi->dev, "TX overrun\n"); | |
965 | if (val & S3C64XX_SPI_PND_TX_UNDERRUN_CLR) | |
966 | dev_err(&spi->dev, "TX underrun\n"); | |
967 | ||
968 | return IRQ_HANDLED; | |
969 | } | |
970 | ||
230d42d4 JB |
971 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
972 | { | |
ad7de729 | 973 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
974 | void __iomem *regs = sdd->regs; |
975 | unsigned int val; | |
976 | ||
977 | sdd->cur_speed = 0; | |
978 | ||
979 | S3C64XX_SPI_DEACT(sdd); | |
980 | ||
981 | /* Disable Interrupts - we use Polling if not DMA mode */ | |
982 | writel(0, regs + S3C64XX_SPI_INT_EN); | |
983 | ||
b42a81ca JB |
984 | if (!sci->clk_from_cmu) |
985 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, | |
230d42d4 JB |
986 | regs + S3C64XX_SPI_CLK_CFG); |
987 | writel(0, regs + S3C64XX_SPI_MODE_CFG); | |
988 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
989 | ||
990 | /* Clear any irq pending bits */ | |
991 | writel(readl(regs + S3C64XX_SPI_PENDING_CLR), | |
992 | regs + S3C64XX_SPI_PENDING_CLR); | |
993 | ||
994 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); | |
995 | ||
996 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
997 | val &= ~S3C64XX_SPI_MODE_4BURST; | |
998 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
999 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
1000 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
1001 | ||
1002 | flush_fifo(sdd); | |
1003 | } | |
1004 | ||
1005 | static int __init s3c64xx_spi_probe(struct platform_device *pdev) | |
1006 | { | |
1007 | struct resource *mem_res, *dmatx_res, *dmarx_res; | |
1008 | struct s3c64xx_spi_driver_data *sdd; | |
ad7de729 | 1009 | struct s3c64xx_spi_info *sci; |
230d42d4 | 1010 | struct spi_master *master; |
c2573128 | 1011 | int ret, irq; |
a24d850b | 1012 | char clk_name[16]; |
230d42d4 JB |
1013 | |
1014 | if (pdev->id < 0) { | |
1015 | dev_err(&pdev->dev, | |
1016 | "Invalid platform device id-%d\n", pdev->id); | |
1017 | return -ENODEV; | |
1018 | } | |
1019 | ||
1020 | if (pdev->dev.platform_data == NULL) { | |
1021 | dev_err(&pdev->dev, "platform_data missing!\n"); | |
1022 | return -ENODEV; | |
1023 | } | |
1024 | ||
cc0fc0bb | 1025 | sci = pdev->dev.platform_data; |
cc0fc0bb | 1026 | |
230d42d4 JB |
1027 | /* Check for availability of necessary resource */ |
1028 | ||
1029 | dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); | |
1030 | if (dmatx_res == NULL) { | |
1031 | dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n"); | |
1032 | return -ENXIO; | |
1033 | } | |
1034 | ||
1035 | dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
1036 | if (dmarx_res == NULL) { | |
1037 | dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n"); | |
1038 | return -ENXIO; | |
1039 | } | |
1040 | ||
1041 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1042 | if (mem_res == NULL) { | |
1043 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); | |
1044 | return -ENXIO; | |
1045 | } | |
1046 | ||
c2573128 MB |
1047 | irq = platform_get_irq(pdev, 0); |
1048 | if (irq < 0) { | |
1049 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); | |
1050 | return irq; | |
1051 | } | |
1052 | ||
230d42d4 JB |
1053 | master = spi_alloc_master(&pdev->dev, |
1054 | sizeof(struct s3c64xx_spi_driver_data)); | |
1055 | if (master == NULL) { | |
1056 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
1057 | return -ENOMEM; | |
1058 | } | |
1059 | ||
230d42d4 JB |
1060 | platform_set_drvdata(pdev, master); |
1061 | ||
1062 | sdd = spi_master_get_devdata(master); | |
1063 | sdd->master = master; | |
1064 | sdd->cntrlr_info = sci; | |
1065 | sdd->pdev = pdev; | |
1066 | sdd->sfr_start = mem_res->start; | |
82ab8cd7 BK |
1067 | sdd->tx_dma.dmach = dmatx_res->start; |
1068 | sdd->tx_dma.direction = DMA_TO_DEVICE; | |
1069 | sdd->rx_dma.dmach = dmarx_res->start; | |
1070 | sdd->rx_dma.direction = DMA_FROM_DEVICE; | |
230d42d4 JB |
1071 | |
1072 | sdd->cur_bpw = 8; | |
1073 | ||
1074 | master->bus_num = pdev->id; | |
1075 | master->setup = s3c64xx_spi_setup; | |
1076 | master->transfer = s3c64xx_spi_transfer; | |
1077 | master->num_chipselect = sci->num_cs; | |
1078 | master->dma_alignment = 8; | |
1079 | /* the spi->mode bits understood by this driver: */ | |
1080 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1081 | ||
1082 | if (request_mem_region(mem_res->start, | |
1083 | resource_size(mem_res), pdev->name) == NULL) { | |
1084 | dev_err(&pdev->dev, "Req mem region failed\n"); | |
1085 | ret = -ENXIO; | |
1086 | goto err0; | |
1087 | } | |
1088 | ||
1089 | sdd->regs = ioremap(mem_res->start, resource_size(mem_res)); | |
1090 | if (sdd->regs == NULL) { | |
1091 | dev_err(&pdev->dev, "Unable to remap IO\n"); | |
1092 | ret = -ENXIO; | |
1093 | goto err1; | |
1094 | } | |
1095 | ||
1096 | if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) { | |
1097 | dev_err(&pdev->dev, "Unable to config gpio\n"); | |
1098 | ret = -EBUSY; | |
1099 | goto err2; | |
1100 | } | |
1101 | ||
1102 | /* Setup clocks */ | |
1103 | sdd->clk = clk_get(&pdev->dev, "spi"); | |
1104 | if (IS_ERR(sdd->clk)) { | |
1105 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); | |
1106 | ret = PTR_ERR(sdd->clk); | |
1107 | goto err3; | |
1108 | } | |
1109 | ||
1110 | if (clk_enable(sdd->clk)) { | |
1111 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); | |
1112 | ret = -EBUSY; | |
1113 | goto err4; | |
1114 | } | |
1115 | ||
a24d850b PV |
1116 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
1117 | sdd->src_clk = clk_get(&pdev->dev, clk_name); | |
b0d5d6e5 | 1118 | if (IS_ERR(sdd->src_clk)) { |
230d42d4 | 1119 | dev_err(&pdev->dev, |
a24d850b | 1120 | "Unable to acquire clock '%s'\n", clk_name); |
b0d5d6e5 | 1121 | ret = PTR_ERR(sdd->src_clk); |
230d42d4 JB |
1122 | goto err5; |
1123 | } | |
1124 | ||
b0d5d6e5 | 1125 | if (clk_enable(sdd->src_clk)) { |
a24d850b | 1126 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
230d42d4 JB |
1127 | ret = -EBUSY; |
1128 | goto err6; | |
1129 | } | |
1130 | ||
1131 | sdd->workqueue = create_singlethread_workqueue( | |
1132 | dev_name(master->dev.parent)); | |
1133 | if (sdd->workqueue == NULL) { | |
1134 | dev_err(&pdev->dev, "Unable to create workqueue\n"); | |
1135 | ret = -ENOMEM; | |
1136 | goto err7; | |
1137 | } | |
1138 | ||
1139 | /* Setup Deufult Mode */ | |
1140 | s3c64xx_spi_hwinit(sdd, pdev->id); | |
1141 | ||
1142 | spin_lock_init(&sdd->lock); | |
1143 | init_completion(&sdd->xfer_completion); | |
1144 | INIT_WORK(&sdd->work, s3c64xx_spi_work); | |
1145 | INIT_LIST_HEAD(&sdd->queue); | |
1146 | ||
c2573128 MB |
1147 | ret = request_irq(irq, s3c64xx_spi_irq, 0, "spi-s3c64xx", sdd); |
1148 | if (ret != 0) { | |
1149 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", | |
1150 | irq, ret); | |
1151 | goto err8; | |
1152 | } | |
1153 | ||
1154 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | | |
1155 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, | |
1156 | sdd->regs + S3C64XX_SPI_INT_EN); | |
1157 | ||
230d42d4 JB |
1158 | if (spi_register_master(master)) { |
1159 | dev_err(&pdev->dev, "cannot register SPI master\n"); | |
1160 | ret = -EBUSY; | |
c2573128 | 1161 | goto err9; |
230d42d4 JB |
1162 | } |
1163 | ||
8a349d4b JP |
1164 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " |
1165 | "with %d Slaves attached\n", | |
230d42d4 | 1166 | pdev->id, master->num_chipselect); |
8a349d4b | 1167 | dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", |
230d42d4 | 1168 | mem_res->end, mem_res->start, |
82ab8cd7 | 1169 | sdd->rx_dma.dmach, sdd->tx_dma.dmach); |
230d42d4 | 1170 | |
b97b6621 MB |
1171 | pm_runtime_enable(&pdev->dev); |
1172 | ||
230d42d4 JB |
1173 | return 0; |
1174 | ||
c2573128 MB |
1175 | err9: |
1176 | free_irq(irq, sdd); | |
230d42d4 JB |
1177 | err8: |
1178 | destroy_workqueue(sdd->workqueue); | |
1179 | err7: | |
b0d5d6e5 | 1180 | clk_disable(sdd->src_clk); |
230d42d4 | 1181 | err6: |
b0d5d6e5 | 1182 | clk_put(sdd->src_clk); |
230d42d4 JB |
1183 | err5: |
1184 | clk_disable(sdd->clk); | |
1185 | err4: | |
1186 | clk_put(sdd->clk); | |
1187 | err3: | |
1188 | err2: | |
1189 | iounmap((void *) sdd->regs); | |
1190 | err1: | |
1191 | release_mem_region(mem_res->start, resource_size(mem_res)); | |
1192 | err0: | |
1193 | platform_set_drvdata(pdev, NULL); | |
1194 | spi_master_put(master); | |
1195 | ||
1196 | return ret; | |
1197 | } | |
1198 | ||
1199 | static int s3c64xx_spi_remove(struct platform_device *pdev) | |
1200 | { | |
1201 | struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); | |
1202 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
230d42d4 JB |
1203 | struct resource *mem_res; |
1204 | unsigned long flags; | |
1205 | ||
b97b6621 MB |
1206 | pm_runtime_disable(&pdev->dev); |
1207 | ||
230d42d4 JB |
1208 | spin_lock_irqsave(&sdd->lock, flags); |
1209 | sdd->state |= SUSPND; | |
1210 | spin_unlock_irqrestore(&sdd->lock, flags); | |
1211 | ||
1212 | while (sdd->state & SPIBUSY) | |
1213 | msleep(10); | |
1214 | ||
1215 | spi_unregister_master(master); | |
1216 | ||
c2573128 MB |
1217 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
1218 | ||
1219 | free_irq(platform_get_irq(pdev, 0), sdd); | |
1220 | ||
230d42d4 JB |
1221 | destroy_workqueue(sdd->workqueue); |
1222 | ||
b0d5d6e5 JB |
1223 | clk_disable(sdd->src_clk); |
1224 | clk_put(sdd->src_clk); | |
230d42d4 JB |
1225 | |
1226 | clk_disable(sdd->clk); | |
1227 | clk_put(sdd->clk); | |
1228 | ||
1229 | iounmap((void *) sdd->regs); | |
1230 | ||
1231 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
ef6c680d JB |
1232 | if (mem_res != NULL) |
1233 | release_mem_region(mem_res->start, resource_size(mem_res)); | |
230d42d4 JB |
1234 | |
1235 | platform_set_drvdata(pdev, NULL); | |
1236 | spi_master_put(master); | |
1237 | ||
1238 | return 0; | |
1239 | } | |
1240 | ||
1241 | #ifdef CONFIG_PM | |
e25d0bf9 | 1242 | static int s3c64xx_spi_suspend(struct device *dev) |
230d42d4 | 1243 | { |
e25d0bf9 | 1244 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); |
230d42d4 | 1245 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 JB |
1246 | unsigned long flags; |
1247 | ||
1248 | spin_lock_irqsave(&sdd->lock, flags); | |
1249 | sdd->state |= SUSPND; | |
1250 | spin_unlock_irqrestore(&sdd->lock, flags); | |
1251 | ||
1252 | while (sdd->state & SPIBUSY) | |
1253 | msleep(10); | |
1254 | ||
1255 | /* Disable the clock */ | |
b0d5d6e5 | 1256 | clk_disable(sdd->src_clk); |
230d42d4 JB |
1257 | clk_disable(sdd->clk); |
1258 | ||
1259 | sdd->cur_speed = 0; /* Output Clock is stopped */ | |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
e25d0bf9 | 1264 | static int s3c64xx_spi_resume(struct device *dev) |
230d42d4 | 1265 | { |
e25d0bf9 MB |
1266 | struct platform_device *pdev = to_platform_device(dev); |
1267 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); | |
230d42d4 | 1268 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
ad7de729 | 1269 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
1270 | unsigned long flags; |
1271 | ||
1272 | sci->cfg_gpio(pdev); | |
1273 | ||
1274 | /* Enable the clock */ | |
b0d5d6e5 | 1275 | clk_enable(sdd->src_clk); |
230d42d4 JB |
1276 | clk_enable(sdd->clk); |
1277 | ||
1278 | s3c64xx_spi_hwinit(sdd, pdev->id); | |
1279 | ||
1280 | spin_lock_irqsave(&sdd->lock, flags); | |
1281 | sdd->state &= ~SUSPND; | |
1282 | spin_unlock_irqrestore(&sdd->lock, flags); | |
1283 | ||
1284 | return 0; | |
1285 | } | |
230d42d4 JB |
1286 | #endif /* CONFIG_PM */ |
1287 | ||
b97b6621 MB |
1288 | #ifdef CONFIG_PM_RUNTIME |
1289 | static int s3c64xx_spi_runtime_suspend(struct device *dev) | |
1290 | { | |
1291 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); | |
1292 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
1293 | ||
1294 | clk_disable(sdd->clk); | |
1295 | clk_disable(sdd->src_clk); | |
1296 | ||
1297 | return 0; | |
1298 | } | |
1299 | ||
1300 | static int s3c64xx_spi_runtime_resume(struct device *dev) | |
1301 | { | |
1302 | struct spi_master *master = spi_master_get(dev_get_drvdata(dev)); | |
1303 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
1304 | ||
1305 | clk_enable(sdd->src_clk); | |
1306 | clk_enable(sdd->clk); | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | #endif /* CONFIG_PM_RUNTIME */ | |
1311 | ||
e25d0bf9 MB |
1312 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
1313 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) | |
b97b6621 MB |
1314 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
1315 | s3c64xx_spi_runtime_resume, NULL) | |
e25d0bf9 MB |
1316 | }; |
1317 | ||
230d42d4 JB |
1318 | static struct platform_driver s3c64xx_spi_driver = { |
1319 | .driver = { | |
1320 | .name = "s3c64xx-spi", | |
1321 | .owner = THIS_MODULE, | |
e25d0bf9 | 1322 | .pm = &s3c64xx_spi_pm, |
230d42d4 JB |
1323 | }, |
1324 | .remove = s3c64xx_spi_remove, | |
230d42d4 JB |
1325 | }; |
1326 | MODULE_ALIAS("platform:s3c64xx-spi"); | |
1327 | ||
1328 | static int __init s3c64xx_spi_init(void) | |
1329 | { | |
1330 | return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe); | |
1331 | } | |
d2a787fc | 1332 | subsys_initcall(s3c64xx_spi_init); |
230d42d4 JB |
1333 | |
1334 | static void __exit s3c64xx_spi_exit(void) | |
1335 | { | |
1336 | platform_driver_unregister(&s3c64xx_spi_driver); | |
1337 | } | |
1338 | module_exit(s3c64xx_spi_exit); | |
1339 | ||
1340 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1341 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); | |
1342 | MODULE_LICENSE("GPL"); |