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Commit | Line | Data |
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ca632f55 | 1 | /* |
230d42d4 JB |
2 | * Copyright (C) 2009 Samsung Electronics Ltd. |
3 | * Jaswinder Singh <jassi.brar@samsung.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
230d42d4 JB |
14 | */ |
15 | ||
16 | #include <linux/init.h> | |
17 | #include <linux/module.h> | |
c2573128 | 18 | #include <linux/interrupt.h> |
230d42d4 JB |
19 | #include <linux/delay.h> |
20 | #include <linux/clk.h> | |
21 | #include <linux/dma-mapping.h> | |
78843727 | 22 | #include <linux/dmaengine.h> |
230d42d4 | 23 | #include <linux/platform_device.h> |
b97b6621 | 24 | #include <linux/pm_runtime.h> |
230d42d4 | 25 | #include <linux/spi/spi.h> |
1c20c200 | 26 | #include <linux/gpio.h> |
2b908075 TA |
27 | #include <linux/of.h> |
28 | #include <linux/of_gpio.h> | |
230d42d4 | 29 | |
436d42c6 | 30 | #include <linux/platform_data/spi-s3c64xx.h> |
230d42d4 | 31 | |
bf77cba9 | 32 | #define MAX_SPI_PORTS 6 |
7e995556 | 33 | #define S3C64XX_SPI_QUIRK_POLL (1 << 0) |
bf77cba9 | 34 | #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) |
483867ee | 35 | #define AUTOSUSPEND_TIMEOUT 2000 |
a5238e36 | 36 | |
230d42d4 JB |
37 | /* Registers and bit-fields */ |
38 | ||
39 | #define S3C64XX_SPI_CH_CFG 0x00 | |
40 | #define S3C64XX_SPI_CLK_CFG 0x04 | |
41 | #define S3C64XX_SPI_MODE_CFG 0x08 | |
42 | #define S3C64XX_SPI_SLAVE_SEL 0x0C | |
43 | #define S3C64XX_SPI_INT_EN 0x10 | |
44 | #define S3C64XX_SPI_STATUS 0x14 | |
45 | #define S3C64XX_SPI_TX_DATA 0x18 | |
46 | #define S3C64XX_SPI_RX_DATA 0x1C | |
47 | #define S3C64XX_SPI_PACKET_CNT 0x20 | |
48 | #define S3C64XX_SPI_PENDING_CLR 0x24 | |
49 | #define S3C64XX_SPI_SWAP_CFG 0x28 | |
50 | #define S3C64XX_SPI_FB_CLK 0x2C | |
51 | ||
52 | #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ | |
53 | #define S3C64XX_SPI_CH_SW_RST (1<<5) | |
54 | #define S3C64XX_SPI_CH_SLAVE (1<<4) | |
55 | #define S3C64XX_SPI_CPOL_L (1<<3) | |
56 | #define S3C64XX_SPI_CPHA_B (1<<2) | |
57 | #define S3C64XX_SPI_CH_RXCH_ON (1<<1) | |
58 | #define S3C64XX_SPI_CH_TXCH_ON (1<<0) | |
59 | ||
60 | #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) | |
61 | #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 | |
62 | #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) | |
75bf3361 | 63 | #define S3C64XX_SPI_PSR_MASK 0xff |
230d42d4 JB |
64 | |
65 | #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) | |
66 | #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) | |
67 | #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) | |
68 | #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) | |
69 | #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) | |
70 | #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) | |
71 | #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) | |
72 | #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) | |
73 | #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) | |
74 | #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) | |
75 | #define S3C64XX_SPI_MODE_4BURST (1<<0) | |
76 | ||
77 | #define S3C64XX_SPI_SLAVE_AUTO (1<<1) | |
78 | #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) | |
bf77cba9 | 79 | #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4) |
230d42d4 | 80 | |
230d42d4 JB |
81 | #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) |
82 | #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) | |
83 | #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) | |
84 | #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) | |
85 | #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) | |
86 | #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) | |
87 | #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) | |
88 | ||
89 | #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) | |
90 | #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) | |
91 | #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) | |
92 | #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) | |
93 | #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) | |
94 | #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) | |
95 | ||
96 | #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) | |
97 | ||
98 | #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) | |
99 | #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) | |
100 | #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) | |
101 | #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) | |
102 | #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) | |
103 | ||
104 | #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) | |
105 | #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) | |
106 | #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) | |
107 | #define S3C64XX_SPI_SWAP_RX_EN (1<<4) | |
108 | #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) | |
109 | #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) | |
110 | #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) | |
111 | #define S3C64XX_SPI_SWAP_TX_EN (1<<0) | |
112 | ||
113 | #define S3C64XX_SPI_FBCLK_MSK (3<<0) | |
114 | ||
a5238e36 TA |
115 | #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) |
116 | #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ | |
117 | (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) | |
118 | #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) | |
119 | #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ | |
120 | FIFO_LVL_MASK(i)) | |
230d42d4 JB |
121 | |
122 | #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff | |
123 | #define S3C64XX_SPI_TRAILCNT_OFF 19 | |
124 | ||
125 | #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT | |
126 | ||
127 | #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) | |
7e995556 | 128 | #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL) |
230d42d4 | 129 | |
230d42d4 JB |
130 | #define RXBUSY (1<<2) |
131 | #define TXBUSY (1<<3) | |
132 | ||
82ab8cd7 | 133 | struct s3c64xx_spi_dma_data { |
78843727 | 134 | struct dma_chan *ch; |
c10356b9 | 135 | enum dma_transfer_direction direction; |
82ab8cd7 BK |
136 | }; |
137 | ||
a5238e36 TA |
138 | /** |
139 | * struct s3c64xx_spi_info - SPI Controller hardware info | |
140 | * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. | |
141 | * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. | |
142 | * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. | |
143 | * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. | |
144 | * @clk_from_cmu: True, if the controller does not include a clock mux and | |
145 | * prescaler unit. | |
146 | * | |
147 | * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but | |
148 | * differ in some aspects such as the size of the fifo and spi bus clock | |
149 | * setup. Such differences are specified to the driver using this structure | |
150 | * which is provided as driver data to the driver. | |
151 | */ | |
152 | struct s3c64xx_spi_port_config { | |
153 | int fifo_lvl_mask[MAX_SPI_PORTS]; | |
154 | int rx_lvl_offset; | |
155 | int tx_st_done; | |
7e995556 | 156 | int quirks; |
a5238e36 TA |
157 | bool high_speed; |
158 | bool clk_from_cmu; | |
7990b008 | 159 | bool clk_ioclk; |
a5238e36 TA |
160 | }; |
161 | ||
230d42d4 JB |
162 | /** |
163 | * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. | |
164 | * @clk: Pointer to the spi clock. | |
b0d5d6e5 | 165 | * @src_clk: Pointer to the clock used to generate SPI signals. |
7990b008 | 166 | * @ioclk: Pointer to the i/o clock between master and slave |
230d42d4 | 167 | * @master: Pointer to the SPI Protocol master. |
230d42d4 JB |
168 | * @cntrlr_info: Platform specific data for the controller this driver manages. |
169 | * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. | |
230d42d4 JB |
170 | * @lock: Controller specific lock. |
171 | * @state: Set of FLAGS to indicate status. | |
172 | * @rx_dmach: Controller's DMA channel for Rx. | |
173 | * @tx_dmach: Controller's DMA channel for Tx. | |
174 | * @sfr_start: BUS address of SPI controller regs. | |
175 | * @regs: Pointer to ioremap'ed controller registers. | |
c2573128 | 176 | * @irq: interrupt |
230d42d4 JB |
177 | * @xfer_completion: To indicate completion of xfer task. |
178 | * @cur_mode: Stores the active configuration of the controller. | |
179 | * @cur_bpw: Stores the active bits per word settings. | |
180 | * @cur_speed: Stores the active xfer clock speed. | |
181 | */ | |
182 | struct s3c64xx_spi_driver_data { | |
183 | void __iomem *regs; | |
184 | struct clk *clk; | |
b0d5d6e5 | 185 | struct clk *src_clk; |
7990b008 | 186 | struct clk *ioclk; |
230d42d4 JB |
187 | struct platform_device *pdev; |
188 | struct spi_master *master; | |
ad7de729 | 189 | struct s3c64xx_spi_info *cntrlr_info; |
230d42d4 | 190 | struct spi_device *tgl_spi; |
230d42d4 | 191 | spinlock_t lock; |
230d42d4 JB |
192 | unsigned long sfr_start; |
193 | struct completion xfer_completion; | |
194 | unsigned state; | |
195 | unsigned cur_mode, cur_bpw; | |
196 | unsigned cur_speed; | |
82ab8cd7 BK |
197 | struct s3c64xx_spi_dma_data rx_dma; |
198 | struct s3c64xx_spi_dma_data tx_dma; | |
a5238e36 TA |
199 | struct s3c64xx_spi_port_config *port_conf; |
200 | unsigned int port_id; | |
230d42d4 JB |
201 | }; |
202 | ||
230d42d4 JB |
203 | static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) |
204 | { | |
230d42d4 JB |
205 | void __iomem *regs = sdd->regs; |
206 | unsigned long loops; | |
207 | u32 val; | |
208 | ||
209 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
210 | ||
7d859ff4 KK |
211 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
212 | val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); | |
213 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
214 | ||
230d42d4 JB |
215 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
216 | val |= S3C64XX_SPI_CH_SW_RST; | |
217 | val &= ~S3C64XX_SPI_CH_HS_EN; | |
218 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
219 | ||
220 | /* Flush TxFIFO*/ | |
221 | loops = msecs_to_loops(1); | |
222 | do { | |
223 | val = readl(regs + S3C64XX_SPI_STATUS); | |
a5238e36 | 224 | } while (TX_FIFO_LVL(val, sdd) && loops--); |
230d42d4 | 225 | |
be7852a8 MB |
226 | if (loops == 0) |
227 | dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); | |
228 | ||
230d42d4 JB |
229 | /* Flush RxFIFO*/ |
230 | loops = msecs_to_loops(1); | |
231 | do { | |
232 | val = readl(regs + S3C64XX_SPI_STATUS); | |
a5238e36 | 233 | if (RX_FIFO_LVL(val, sdd)) |
230d42d4 JB |
234 | readl(regs + S3C64XX_SPI_RX_DATA); |
235 | else | |
236 | break; | |
237 | } while (loops--); | |
238 | ||
be7852a8 MB |
239 | if (loops == 0) |
240 | dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); | |
241 | ||
230d42d4 JB |
242 | val = readl(regs + S3C64XX_SPI_CH_CFG); |
243 | val &= ~S3C64XX_SPI_CH_SW_RST; | |
244 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
245 | ||
246 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
247 | val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
248 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
230d42d4 JB |
249 | } |
250 | ||
82ab8cd7 | 251 | static void s3c64xx_spi_dmacb(void *data) |
39d3e807 | 252 | { |
82ab8cd7 BK |
253 | struct s3c64xx_spi_driver_data *sdd; |
254 | struct s3c64xx_spi_dma_data *dma = data; | |
39d3e807 BK |
255 | unsigned long flags; |
256 | ||
054ebcc4 | 257 | if (dma->direction == DMA_DEV_TO_MEM) |
82ab8cd7 BK |
258 | sdd = container_of(data, |
259 | struct s3c64xx_spi_driver_data, rx_dma); | |
260 | else | |
261 | sdd = container_of(data, | |
262 | struct s3c64xx_spi_driver_data, tx_dma); | |
263 | ||
39d3e807 BK |
264 | spin_lock_irqsave(&sdd->lock, flags); |
265 | ||
054ebcc4 | 266 | if (dma->direction == DMA_DEV_TO_MEM) { |
82ab8cd7 BK |
267 | sdd->state &= ~RXBUSY; |
268 | if (!(sdd->state & TXBUSY)) | |
269 | complete(&sdd->xfer_completion); | |
270 | } else { | |
271 | sdd->state &= ~TXBUSY; | |
272 | if (!(sdd->state & RXBUSY)) | |
273 | complete(&sdd->xfer_completion); | |
274 | } | |
39d3e807 BK |
275 | |
276 | spin_unlock_irqrestore(&sdd->lock, flags); | |
277 | } | |
278 | ||
78843727 | 279 | static void prepare_dma(struct s3c64xx_spi_dma_data *dma, |
6ad45a27 | 280 | struct sg_table *sgt) |
78843727 AB |
281 | { |
282 | struct s3c64xx_spi_driver_data *sdd; | |
283 | struct dma_slave_config config; | |
78843727 AB |
284 | struct dma_async_tx_descriptor *desc; |
285 | ||
b1a8e78d TF |
286 | memset(&config, 0, sizeof(config)); |
287 | ||
78843727 AB |
288 | if (dma->direction == DMA_DEV_TO_MEM) { |
289 | sdd = container_of((void *)dma, | |
290 | struct s3c64xx_spi_driver_data, rx_dma); | |
291 | config.direction = dma->direction; | |
292 | config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; | |
293 | config.src_addr_width = sdd->cur_bpw / 8; | |
294 | config.src_maxburst = 1; | |
295 | dmaengine_slave_config(dma->ch, &config); | |
296 | } else { | |
297 | sdd = container_of((void *)dma, | |
298 | struct s3c64xx_spi_driver_data, tx_dma); | |
299 | config.direction = dma->direction; | |
300 | config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; | |
301 | config.dst_addr_width = sdd->cur_bpw / 8; | |
302 | config.dst_maxburst = 1; | |
303 | dmaengine_slave_config(dma->ch, &config); | |
304 | } | |
305 | ||
6ad45a27 MB |
306 | desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, |
307 | dma->direction, DMA_PREP_INTERRUPT); | |
78843727 AB |
308 | |
309 | desc->callback = s3c64xx_spi_dmacb; | |
310 | desc->callback_param = dma; | |
311 | ||
312 | dmaengine_submit(desc); | |
313 | dma_async_issue_pending(dma->ch); | |
314 | } | |
315 | ||
aa4964c4 AS |
316 | static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) |
317 | { | |
318 | struct s3c64xx_spi_driver_data *sdd = | |
319 | spi_master_get_devdata(spi->master); | |
320 | ||
a92e7c3d AS |
321 | if (sdd->cntrlr_info->no_cs) |
322 | return; | |
323 | ||
aa4964c4 AS |
324 | if (enable) { |
325 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { | |
326 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
327 | } else { | |
328 | u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
329 | ||
330 | ssel |= (S3C64XX_SPI_SLAVE_AUTO | | |
331 | S3C64XX_SPI_SLAVE_NSC_CNT_2); | |
332 | writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
333 | } | |
334 | } else { | |
335 | if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) | |
47c169ee DC |
336 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, |
337 | sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
aa4964c4 AS |
338 | } |
339 | } | |
340 | ||
78843727 AB |
341 | static int s3c64xx_spi_prepare_transfer(struct spi_master *spi) |
342 | { | |
343 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
78843727 | 344 | struct device *dev = &sdd->pdev->dev; |
78843727 | 345 | |
730d9d4d AS |
346 | if (is_polling(sdd)) |
347 | return 0; | |
348 | ||
730d9d4d | 349 | /* Acquire DMA channels */ |
6f8dc9d4 | 350 | sdd->rx_dma.ch = dma_request_slave_channel(dev, "rx"); |
730d9d4d AS |
351 | if (!sdd->rx_dma.ch) { |
352 | dev_err(dev, "Failed to get RX DMA channel\n"); | |
353 | return -EBUSY; | |
fb9d044e | 354 | } |
730d9d4d | 355 | spi->dma_rx = sdd->rx_dma.ch; |
fb9d044e | 356 | |
6f8dc9d4 | 357 | sdd->tx_dma.ch = dma_request_slave_channel(dev, "tx"); |
730d9d4d AS |
358 | if (!sdd->tx_dma.ch) { |
359 | dev_err(dev, "Failed to get TX DMA channel\n"); | |
360 | dma_release_channel(sdd->rx_dma.ch); | |
361 | return -EBUSY; | |
362 | } | |
363 | spi->dma_tx = sdd->tx_dma.ch; | |
fb9d044e | 364 | |
730d9d4d | 365 | return 0; |
78843727 AB |
366 | } |
367 | ||
368 | static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi) | |
369 | { | |
370 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi); | |
371 | ||
372 | /* Free DMA channels */ | |
7e995556 G |
373 | if (!is_polling(sdd)) { |
374 | dma_release_channel(sdd->rx_dma.ch); | |
375 | dma_release_channel(sdd->tx_dma.ch); | |
376 | } | |
78843727 | 377 | |
78843727 AB |
378 | return 0; |
379 | } | |
380 | ||
3f295887 MB |
381 | static bool s3c64xx_spi_can_dma(struct spi_master *master, |
382 | struct spi_device *spi, | |
383 | struct spi_transfer *xfer) | |
384 | { | |
385 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
386 | ||
387 | return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
388 | } | |
389 | ||
230d42d4 JB |
390 | static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, |
391 | struct spi_device *spi, | |
392 | struct spi_transfer *xfer, int dma_mode) | |
393 | { | |
230d42d4 JB |
394 | void __iomem *regs = sdd->regs; |
395 | u32 modecfg, chcfg; | |
396 | ||
397 | modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); | |
398 | modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); | |
399 | ||
400 | chcfg = readl(regs + S3C64XX_SPI_CH_CFG); | |
401 | chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; | |
402 | ||
403 | if (dma_mode) { | |
404 | chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; | |
405 | } else { | |
406 | /* Always shift in data in FIFO, even if xfer is Tx only, | |
407 | * this helps setting PCKT_CNT value for generating clocks | |
408 | * as exactly needed. | |
409 | */ | |
410 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
411 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
412 | | S3C64XX_SPI_PACKET_CNT_EN, | |
413 | regs + S3C64XX_SPI_PACKET_CNT); | |
414 | } | |
415 | ||
416 | if (xfer->tx_buf != NULL) { | |
417 | sdd->state |= TXBUSY; | |
418 | chcfg |= S3C64XX_SPI_CH_TXCH_ON; | |
419 | if (dma_mode) { | |
420 | modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; | |
6ad45a27 | 421 | prepare_dma(&sdd->tx_dma, &xfer->tx_sg); |
230d42d4 | 422 | } else { |
0c92ecf1 JB |
423 | switch (sdd->cur_bpw) { |
424 | case 32: | |
425 | iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, | |
426 | xfer->tx_buf, xfer->len / 4); | |
427 | break; | |
428 | case 16: | |
429 | iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, | |
430 | xfer->tx_buf, xfer->len / 2); | |
431 | break; | |
432 | default: | |
433 | iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, | |
434 | xfer->tx_buf, xfer->len); | |
435 | break; | |
436 | } | |
230d42d4 JB |
437 | } |
438 | } | |
439 | ||
440 | if (xfer->rx_buf != NULL) { | |
441 | sdd->state |= RXBUSY; | |
442 | ||
a5238e36 | 443 | if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL |
230d42d4 JB |
444 | && !(sdd->cur_mode & SPI_CPHA)) |
445 | chcfg |= S3C64XX_SPI_CH_HS_EN; | |
446 | ||
447 | if (dma_mode) { | |
448 | modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; | |
449 | chcfg |= S3C64XX_SPI_CH_RXCH_ON; | |
450 | writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) | |
451 | | S3C64XX_SPI_PACKET_CNT_EN, | |
452 | regs + S3C64XX_SPI_PACKET_CNT); | |
6ad45a27 | 453 | prepare_dma(&sdd->rx_dma, &xfer->rx_sg); |
230d42d4 JB |
454 | } |
455 | } | |
456 | ||
457 | writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); | |
458 | writel(chcfg, regs + S3C64XX_SPI_CH_CFG); | |
459 | } | |
460 | ||
79617073 | 461 | static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, |
7e995556 G |
462 | int timeout_ms) |
463 | { | |
464 | void __iomem *regs = sdd->regs; | |
465 | unsigned long val = 1; | |
466 | u32 status; | |
467 | ||
468 | /* max fifo depth available */ | |
469 | u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1; | |
470 | ||
471 | if (timeout_ms) | |
472 | val = msecs_to_loops(timeout_ms); | |
473 | ||
474 | do { | |
475 | status = readl(regs + S3C64XX_SPI_STATUS); | |
476 | } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); | |
477 | ||
478 | /* return the actual received data length */ | |
479 | return RX_FIFO_LVL(status, sdd); | |
230d42d4 JB |
480 | } |
481 | ||
3700c6eb MB |
482 | static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd, |
483 | struct spi_transfer *xfer) | |
230d42d4 | 484 | { |
230d42d4 JB |
485 | void __iomem *regs = sdd->regs; |
486 | unsigned long val; | |
3700c6eb | 487 | u32 status; |
230d42d4 JB |
488 | int ms; |
489 | ||
490 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ | |
491 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
9d8f86b5 | 492 | ms += 10; /* some tolerance */ |
230d42d4 | 493 | |
3700c6eb MB |
494 | val = msecs_to_jiffies(ms) + 10; |
495 | val = wait_for_completion_timeout(&sdd->xfer_completion, val); | |
496 | ||
497 | /* | |
498 | * If the previous xfer was completed within timeout, then | |
499 | * proceed further else return -EIO. | |
500 | * DmaTx returns after simply writing data in the FIFO, | |
501 | * w/o waiting for real transmission on the bus to finish. | |
502 | * DmaRx returns only after Dma read data from FIFO which | |
503 | * needs bus transmission to finish, so we don't worry if | |
504 | * Xfer involved Rx(with or without Tx). | |
505 | */ | |
506 | if (val && !xfer->rx_buf) { | |
507 | val = msecs_to_loops(10); | |
508 | status = readl(regs + S3C64XX_SPI_STATUS); | |
509 | while ((TX_FIFO_LVL(status, sdd) | |
510 | || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) | |
511 | && --val) { | |
512 | cpu_relax(); | |
c3f139b6 | 513 | status = readl(regs + S3C64XX_SPI_STATUS); |
3700c6eb MB |
514 | } |
515 | ||
230d42d4 JB |
516 | } |
517 | ||
3700c6eb MB |
518 | /* If timed out while checking rx/tx status return error */ |
519 | if (!val) | |
520 | return -EIO; | |
230d42d4 | 521 | |
3700c6eb MB |
522 | return 0; |
523 | } | |
7e995556 | 524 | |
3700c6eb MB |
525 | static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd, |
526 | struct spi_transfer *xfer) | |
527 | { | |
528 | void __iomem *regs = sdd->regs; | |
529 | unsigned long val; | |
530 | u32 status; | |
531 | int loops; | |
532 | u32 cpy_len; | |
533 | u8 *buf; | |
534 | int ms; | |
230d42d4 | 535 | |
3700c6eb MB |
536 | /* millisecs to xfer 'len' bytes @ 'cur_speed' */ |
537 | ms = xfer->len * 8 * 1000 / sdd->cur_speed; | |
538 | ms += 10; /* some tolerance */ | |
7e995556 | 539 | |
3700c6eb MB |
540 | val = msecs_to_loops(ms); |
541 | do { | |
542 | status = readl(regs + S3C64XX_SPI_STATUS); | |
543 | } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); | |
7e995556 | 544 | |
3700c6eb MB |
545 | |
546 | /* If it was only Tx */ | |
547 | if (!xfer->rx_buf) { | |
548 | sdd->state &= ~TXBUSY; | |
549 | return 0; | |
230d42d4 JB |
550 | } |
551 | ||
3700c6eb MB |
552 | /* |
553 | * If the receive length is bigger than the controller fifo | |
554 | * size, calculate the loops and read the fifo as many times. | |
555 | * loops = length / max fifo size (calculated by using the | |
556 | * fifo mask). | |
557 | * For any size less than the fifo size the below code is | |
558 | * executed atleast once. | |
559 | */ | |
560 | loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1); | |
561 | buf = xfer->rx_buf; | |
562 | do { | |
563 | /* wait for data to be received in the fifo */ | |
564 | cpy_len = s3c64xx_spi_wait_for_timeout(sdd, | |
565 | (loops ? ms : 0)); | |
566 | ||
567 | switch (sdd->cur_bpw) { | |
568 | case 32: | |
569 | ioread32_rep(regs + S3C64XX_SPI_RX_DATA, | |
570 | buf, cpy_len / 4); | |
571 | break; | |
572 | case 16: | |
573 | ioread16_rep(regs + S3C64XX_SPI_RX_DATA, | |
574 | buf, cpy_len / 2); | |
575 | break; | |
576 | default: | |
577 | ioread8_rep(regs + S3C64XX_SPI_RX_DATA, | |
578 | buf, cpy_len); | |
579 | break; | |
580 | } | |
581 | ||
582 | buf = buf + cpy_len; | |
583 | } while (loops--); | |
584 | sdd->state &= ~RXBUSY; | |
585 | ||
230d42d4 JB |
586 | return 0; |
587 | } | |
588 | ||
230d42d4 JB |
589 | static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) |
590 | { | |
230d42d4 JB |
591 | void __iomem *regs = sdd->regs; |
592 | u32 val; | |
593 | ||
594 | /* Disable Clock */ | |
d9aaf1dc | 595 | if (!sdd->port_conf->clk_from_cmu) { |
b42a81ca JB |
596 | val = readl(regs + S3C64XX_SPI_CLK_CFG); |
597 | val &= ~S3C64XX_SPI_ENCLK_ENABLE; | |
598 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
599 | } | |
230d42d4 JB |
600 | |
601 | /* Set Polarity and Phase */ | |
602 | val = readl(regs + S3C64XX_SPI_CH_CFG); | |
603 | val &= ~(S3C64XX_SPI_CH_SLAVE | | |
604 | S3C64XX_SPI_CPOL_L | | |
605 | S3C64XX_SPI_CPHA_B); | |
606 | ||
607 | if (sdd->cur_mode & SPI_CPOL) | |
608 | val |= S3C64XX_SPI_CPOL_L; | |
609 | ||
610 | if (sdd->cur_mode & SPI_CPHA) | |
611 | val |= S3C64XX_SPI_CPHA_B; | |
612 | ||
613 | writel(val, regs + S3C64XX_SPI_CH_CFG); | |
614 | ||
615 | /* Set Channel & DMA Mode */ | |
616 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
617 | val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK | |
618 | | S3C64XX_SPI_MODE_CH_TSZ_MASK); | |
619 | ||
620 | switch (sdd->cur_bpw) { | |
621 | case 32: | |
622 | val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; | |
0c92ecf1 | 623 | val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; |
230d42d4 JB |
624 | break; |
625 | case 16: | |
626 | val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; | |
0c92ecf1 | 627 | val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; |
230d42d4 JB |
628 | break; |
629 | default: | |
630 | val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; | |
0c92ecf1 | 631 | val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; |
230d42d4 JB |
632 | break; |
633 | } | |
230d42d4 JB |
634 | |
635 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
636 | ||
a5238e36 | 637 | if (sdd->port_conf->clk_from_cmu) { |
0dbe70a1 | 638 | /* The src_clk clock is divided internally by 2 */ |
b42a81ca | 639 | clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); |
b42a81ca JB |
640 | } else { |
641 | /* Configure Clock */ | |
642 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
643 | val &= ~S3C64XX_SPI_PSR_MASK; | |
644 | val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) | |
645 | & S3C64XX_SPI_PSR_MASK); | |
646 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
647 | ||
648 | /* Enable Clock */ | |
649 | val = readl(regs + S3C64XX_SPI_CLK_CFG); | |
650 | val |= S3C64XX_SPI_ENCLK_ENABLE; | |
651 | writel(val, regs + S3C64XX_SPI_CLK_CFG); | |
652 | } | |
230d42d4 JB |
653 | } |
654 | ||
230d42d4 JB |
655 | #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) |
656 | ||
6bb9c0e3 MB |
657 | static int s3c64xx_spi_prepare_message(struct spi_master *master, |
658 | struct spi_message *msg) | |
230d42d4 | 659 | { |
ad2a99af | 660 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 JB |
661 | struct spi_device *spi = msg->spi; |
662 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
230d42d4 | 663 | |
230d42d4 JB |
664 | /* Configure feedback delay */ |
665 | writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); | |
666 | ||
6bb9c0e3 MB |
667 | return 0; |
668 | } | |
0c92ecf1 | 669 | |
0732a9d2 MB |
670 | static int s3c64xx_spi_transfer_one(struct spi_master *master, |
671 | struct spi_device *spi, | |
672 | struct spi_transfer *xfer) | |
6bb9c0e3 MB |
673 | { |
674 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); | |
0732a9d2 | 675 | int status; |
6bb9c0e3 MB |
676 | u32 speed; |
677 | u8 bpw; | |
0732a9d2 MB |
678 | unsigned long flags; |
679 | int use_dma; | |
230d42d4 | 680 | |
3e83c194 | 681 | reinit_completion(&sdd->xfer_completion); |
230d42d4 | 682 | |
0732a9d2 MB |
683 | /* Only BPW and Speed may change across transfers */ |
684 | bpw = xfer->bits_per_word; | |
88d4a744 | 685 | speed = xfer->speed_hz; |
230d42d4 | 686 | |
0732a9d2 MB |
687 | if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { |
688 | sdd->cur_bpw = bpw; | |
689 | sdd->cur_speed = speed; | |
11f66f09 | 690 | sdd->cur_mode = spi->mode; |
0732a9d2 MB |
691 | s3c64xx_spi_config(sdd); |
692 | } | |
230d42d4 | 693 | |
0732a9d2 MB |
694 | /* Polling method for xfers not bigger than FIFO capacity */ |
695 | use_dma = 0; | |
696 | if (!is_polling(sdd) && | |
697 | (sdd->rx_dma.ch && sdd->tx_dma.ch && | |
698 | (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1)))) | |
699 | use_dma = 1; | |
230d42d4 | 700 | |
0732a9d2 | 701 | spin_lock_irqsave(&sdd->lock, flags); |
230d42d4 | 702 | |
0732a9d2 MB |
703 | /* Pending only which is to be done */ |
704 | sdd->state &= ~RXBUSY; | |
705 | sdd->state &= ~TXBUSY; | |
230d42d4 | 706 | |
0732a9d2 | 707 | enable_datapath(sdd, spi, xfer, use_dma); |
230d42d4 | 708 | |
0732a9d2 | 709 | /* Start the signals */ |
aa4964c4 | 710 | s3c64xx_spi_set_cs(spi, true); |
230d42d4 | 711 | |
0732a9d2 | 712 | spin_unlock_irqrestore(&sdd->lock, flags); |
230d42d4 | 713 | |
3700c6eb MB |
714 | if (use_dma) |
715 | status = wait_for_dma(sdd, xfer); | |
716 | else | |
717 | status = wait_for_pio(sdd, xfer); | |
0732a9d2 MB |
718 | |
719 | if (status) { | |
720 | dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n", | |
721 | xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, | |
722 | (sdd->state & RXBUSY) ? 'f' : 'p', | |
723 | (sdd->state & TXBUSY) ? 'f' : 'p', | |
724 | xfer->len); | |
725 | ||
726 | if (use_dma) { | |
727 | if (xfer->tx_buf != NULL | |
728 | && (sdd->state & TXBUSY)) | |
1b5e1b69 | 729 | dmaengine_terminate_all(sdd->tx_dma.ch); |
0732a9d2 MB |
730 | if (xfer->rx_buf != NULL |
731 | && (sdd->state & RXBUSY)) | |
1b5e1b69 | 732 | dmaengine_terminate_all(sdd->rx_dma.ch); |
230d42d4 | 733 | } |
8c09daa1 | 734 | } else { |
230d42d4 JB |
735 | flush_fifo(sdd); |
736 | } | |
737 | ||
0732a9d2 | 738 | return status; |
230d42d4 | 739 | } |
230d42d4 | 740 | |
2b908075 | 741 | static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata( |
2b908075 TA |
742 | struct spi_device *spi) |
743 | { | |
744 | struct s3c64xx_spi_csinfo *cs; | |
4732cc63 | 745 | struct device_node *slave_np, *data_np = NULL; |
2b908075 TA |
746 | u32 fb_delay = 0; |
747 | ||
748 | slave_np = spi->dev.of_node; | |
749 | if (!slave_np) { | |
750 | dev_err(&spi->dev, "device node not found\n"); | |
751 | return ERR_PTR(-EINVAL); | |
752 | } | |
753 | ||
06455bbc | 754 | data_np = of_get_child_by_name(slave_np, "controller-data"); |
2b908075 TA |
755 | if (!data_np) { |
756 | dev_err(&spi->dev, "child node 'controller-data' not found\n"); | |
757 | return ERR_PTR(-EINVAL); | |
758 | } | |
759 | ||
760 | cs = kzalloc(sizeof(*cs), GFP_KERNEL); | |
761 | if (!cs) { | |
06455bbc | 762 | of_node_put(data_np); |
2b908075 TA |
763 | return ERR_PTR(-ENOMEM); |
764 | } | |
765 | ||
2b908075 TA |
766 | of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); |
767 | cs->fb_delay = fb_delay; | |
06455bbc | 768 | of_node_put(data_np); |
2b908075 TA |
769 | return cs; |
770 | } | |
771 | ||
230d42d4 JB |
772 | /* |
773 | * Here we only check the validity of requested configuration | |
774 | * and save the configuration in a local data-structure. | |
775 | * The controller is actually configured only just before we | |
776 | * get a message to transfer. | |
777 | */ | |
778 | static int s3c64xx_spi_setup(struct spi_device *spi) | |
779 | { | |
780 | struct s3c64xx_spi_csinfo *cs = spi->controller_data; | |
781 | struct s3c64xx_spi_driver_data *sdd; | |
ad7de729 | 782 | struct s3c64xx_spi_info *sci; |
2b908075 | 783 | int err; |
230d42d4 | 784 | |
2b908075 | 785 | sdd = spi_master_get_devdata(spi->master); |
306972ce | 786 | if (spi->dev.of_node) { |
5c725b34 | 787 | cs = s3c64xx_get_slave_ctrldata(spi); |
2b908075 | 788 | spi->controller_data = cs; |
306972ce NKC |
789 | } else if (cs) { |
790 | /* On non-DT platforms the SPI core will set spi->cs_gpio | |
791 | * to -ENOENT. The GPIO pin used to drive the chip select | |
792 | * is defined by using platform data so spi->cs_gpio value | |
793 | * has to be override to have the proper GPIO pin number. | |
794 | */ | |
795 | spi->cs_gpio = cs->line; | |
2b908075 TA |
796 | } |
797 | ||
798 | if (IS_ERR_OR_NULL(cs)) { | |
230d42d4 JB |
799 | dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); |
800 | return -ENODEV; | |
801 | } | |
802 | ||
0149871c | 803 | if (!spi_get_ctldata(spi)) { |
306972ce NKC |
804 | if (gpio_is_valid(spi->cs_gpio)) { |
805 | err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH, | |
806 | dev_name(&spi->dev)); | |
807 | if (err) { | |
808 | dev_err(&spi->dev, | |
809 | "Failed to get /CS gpio [%d]: %d\n", | |
810 | spi->cs_gpio, err); | |
811 | goto err_gpio_req; | |
812 | } | |
1c20c200 | 813 | } |
1c20c200 | 814 | |
3146beec | 815 | spi_set_ctldata(spi, cs); |
230d42d4 JB |
816 | } |
817 | ||
230d42d4 | 818 | sci = sdd->cntrlr_info; |
230d42d4 | 819 | |
b97b6621 MB |
820 | pm_runtime_get_sync(&sdd->pdev->dev); |
821 | ||
230d42d4 | 822 | /* Check if we can provide the requested rate */ |
a5238e36 | 823 | if (!sdd->port_conf->clk_from_cmu) { |
b42a81ca JB |
824 | u32 psr, speed; |
825 | ||
826 | /* Max possible */ | |
827 | speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); | |
828 | ||
829 | if (spi->max_speed_hz > speed) | |
830 | spi->max_speed_hz = speed; | |
831 | ||
832 | psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; | |
833 | psr &= S3C64XX_SPI_PSR_MASK; | |
834 | if (psr == S3C64XX_SPI_PSR_MASK) | |
835 | psr--; | |
836 | ||
837 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); | |
838 | if (spi->max_speed_hz < speed) { | |
839 | if (psr+1 < S3C64XX_SPI_PSR_MASK) { | |
840 | psr++; | |
841 | } else { | |
842 | err = -EINVAL; | |
843 | goto setup_exit; | |
844 | } | |
845 | } | |
230d42d4 | 846 | |
b42a81ca | 847 | speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); |
2b908075 | 848 | if (spi->max_speed_hz >= speed) { |
b42a81ca | 849 | spi->max_speed_hz = speed; |
2b908075 | 850 | } else { |
e1b0f0df MB |
851 | dev_err(&spi->dev, "Can't set %dHz transfer speed\n", |
852 | spi->max_speed_hz); | |
230d42d4 | 853 | err = -EINVAL; |
2b908075 TA |
854 | goto setup_exit; |
855 | } | |
230d42d4 JB |
856 | } |
857 | ||
483867ee HK |
858 | pm_runtime_mark_last_busy(&sdd->pdev->dev); |
859 | pm_runtime_put_autosuspend(&sdd->pdev->dev); | |
aa4964c4 AS |
860 | s3c64xx_spi_set_cs(spi, false); |
861 | ||
2b908075 | 862 | return 0; |
b97b6621 | 863 | |
230d42d4 | 864 | setup_exit: |
483867ee HK |
865 | pm_runtime_mark_last_busy(&sdd->pdev->dev); |
866 | pm_runtime_put_autosuspend(&sdd->pdev->dev); | |
230d42d4 | 867 | /* setup() returns with device de-selected */ |
aa4964c4 | 868 | s3c64xx_spi_set_cs(spi, false); |
230d42d4 | 869 | |
306972ce NKC |
870 | if (gpio_is_valid(spi->cs_gpio)) |
871 | gpio_free(spi->cs_gpio); | |
2b908075 TA |
872 | spi_set_ctldata(spi, NULL); |
873 | ||
874 | err_gpio_req: | |
5bee3b94 SN |
875 | if (spi->dev.of_node) |
876 | kfree(cs); | |
2b908075 | 877 | |
230d42d4 JB |
878 | return err; |
879 | } | |
880 | ||
1c20c200 TA |
881 | static void s3c64xx_spi_cleanup(struct spi_device *spi) |
882 | { | |
883 | struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); | |
884 | ||
306972ce | 885 | if (gpio_is_valid(spi->cs_gpio)) { |
dd97e268 | 886 | gpio_free(spi->cs_gpio); |
2b908075 TA |
887 | if (spi->dev.of_node) |
888 | kfree(cs); | |
306972ce NKC |
889 | else { |
890 | /* On non-DT platforms, the SPI core sets | |
891 | * spi->cs_gpio to -ENOENT and .setup() | |
892 | * overrides it with the GPIO pin value | |
893 | * passed using platform data. | |
894 | */ | |
895 | spi->cs_gpio = -ENOENT; | |
896 | } | |
2b908075 | 897 | } |
306972ce | 898 | |
1c20c200 TA |
899 | spi_set_ctldata(spi, NULL); |
900 | } | |
901 | ||
c2573128 MB |
902 | static irqreturn_t s3c64xx_spi_irq(int irq, void *data) |
903 | { | |
904 | struct s3c64xx_spi_driver_data *sdd = data; | |
905 | struct spi_master *spi = sdd->master; | |
375981f2 | 906 | unsigned int val, clr = 0; |
c2573128 | 907 | |
375981f2 | 908 | val = readl(sdd->regs + S3C64XX_SPI_STATUS); |
c2573128 | 909 | |
375981f2 G |
910 | if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { |
911 | clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; | |
c2573128 | 912 | dev_err(&spi->dev, "RX overrun\n"); |
375981f2 G |
913 | } |
914 | if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { | |
915 | clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; | |
c2573128 | 916 | dev_err(&spi->dev, "RX underrun\n"); |
375981f2 G |
917 | } |
918 | if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { | |
919 | clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; | |
c2573128 | 920 | dev_err(&spi->dev, "TX overrun\n"); |
375981f2 G |
921 | } |
922 | if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { | |
923 | clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
c2573128 | 924 | dev_err(&spi->dev, "TX underrun\n"); |
375981f2 G |
925 | } |
926 | ||
927 | /* Clear the pending irq by setting and then clearing it */ | |
928 | writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
929 | writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); | |
c2573128 MB |
930 | |
931 | return IRQ_HANDLED; | |
932 | } | |
933 | ||
230d42d4 JB |
934 | static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) |
935 | { | |
ad7de729 | 936 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
230d42d4 JB |
937 | void __iomem *regs = sdd->regs; |
938 | unsigned int val; | |
939 | ||
940 | sdd->cur_speed = 0; | |
941 | ||
a92e7c3d AS |
942 | if (sci->no_cs) |
943 | writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL); | |
944 | else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) | |
bf77cba9 | 945 | writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL); |
230d42d4 JB |
946 | |
947 | /* Disable Interrupts - we use Polling if not DMA mode */ | |
948 | writel(0, regs + S3C64XX_SPI_INT_EN); | |
949 | ||
a5238e36 | 950 | if (!sdd->port_conf->clk_from_cmu) |
b42a81ca | 951 | writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, |
230d42d4 JB |
952 | regs + S3C64XX_SPI_CLK_CFG); |
953 | writel(0, regs + S3C64XX_SPI_MODE_CFG); | |
954 | writel(0, regs + S3C64XX_SPI_PACKET_CNT); | |
955 | ||
375981f2 G |
956 | /* Clear any irq pending bits, should set and clear the bits */ |
957 | val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | | |
958 | S3C64XX_SPI_PND_RX_UNDERRUN_CLR | | |
959 | S3C64XX_SPI_PND_TX_OVERRUN_CLR | | |
960 | S3C64XX_SPI_PND_TX_UNDERRUN_CLR; | |
961 | writel(val, regs + S3C64XX_SPI_PENDING_CLR); | |
962 | writel(0, regs + S3C64XX_SPI_PENDING_CLR); | |
230d42d4 JB |
963 | |
964 | writel(0, regs + S3C64XX_SPI_SWAP_CFG); | |
965 | ||
966 | val = readl(regs + S3C64XX_SPI_MODE_CFG); | |
967 | val &= ~S3C64XX_SPI_MODE_4BURST; | |
968 | val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
969 | val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); | |
970 | writel(val, regs + S3C64XX_SPI_MODE_CFG); | |
971 | ||
972 | flush_fifo(sdd); | |
973 | } | |
974 | ||
2b908075 | 975 | #ifdef CONFIG_OF |
75bf3361 | 976 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) |
2b908075 TA |
977 | { |
978 | struct s3c64xx_spi_info *sci; | |
979 | u32 temp; | |
980 | ||
981 | sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); | |
1273eb05 | 982 | if (!sci) |
2b908075 | 983 | return ERR_PTR(-ENOMEM); |
2b908075 TA |
984 | |
985 | if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { | |
75bf3361 | 986 | dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); |
2b908075 TA |
987 | sci->src_clk_nr = 0; |
988 | } else { | |
989 | sci->src_clk_nr = temp; | |
990 | } | |
991 | ||
992 | if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { | |
75bf3361 | 993 | dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); |
2b908075 TA |
994 | sci->num_cs = 1; |
995 | } else { | |
996 | sci->num_cs = temp; | |
997 | } | |
998 | ||
40acd9b6 | 999 | sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); |
a92e7c3d | 1000 | |
2b908075 TA |
1001 | return sci; |
1002 | } | |
1003 | #else | |
1004 | static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) | |
1005 | { | |
8074cf06 | 1006 | return dev_get_platdata(dev); |
2b908075 | 1007 | } |
2b908075 TA |
1008 | #endif |
1009 | ||
1010 | static const struct of_device_id s3c64xx_spi_dt_match[]; | |
1011 | ||
a5238e36 TA |
1012 | static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( |
1013 | struct platform_device *pdev) | |
1014 | { | |
2b908075 TA |
1015 | #ifdef CONFIG_OF |
1016 | if (pdev->dev.of_node) { | |
1017 | const struct of_device_id *match; | |
1018 | match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node); | |
1019 | return (struct s3c64xx_spi_port_config *)match->data; | |
1020 | } | |
1021 | #endif | |
a5238e36 TA |
1022 | return (struct s3c64xx_spi_port_config *) |
1023 | platform_get_device_id(pdev)->driver_data; | |
1024 | } | |
1025 | ||
2deff8d6 | 1026 | static int s3c64xx_spi_probe(struct platform_device *pdev) |
230d42d4 | 1027 | { |
2b908075 | 1028 | struct resource *mem_res; |
230d42d4 | 1029 | struct s3c64xx_spi_driver_data *sdd; |
8074cf06 | 1030 | struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); |
230d42d4 | 1031 | struct spi_master *master; |
c2573128 | 1032 | int ret, irq; |
a24d850b | 1033 | char clk_name[16]; |
230d42d4 | 1034 | |
2b908075 TA |
1035 | if (!sci && pdev->dev.of_node) { |
1036 | sci = s3c64xx_spi_parse_dt(&pdev->dev); | |
1037 | if (IS_ERR(sci)) | |
1038 | return PTR_ERR(sci); | |
230d42d4 JB |
1039 | } |
1040 | ||
2b908075 | 1041 | if (!sci) { |
230d42d4 JB |
1042 | dev_err(&pdev->dev, "platform_data missing!\n"); |
1043 | return -ENODEV; | |
1044 | } | |
1045 | ||
230d42d4 JB |
1046 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1047 | if (mem_res == NULL) { | |
1048 | dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); | |
1049 | return -ENXIO; | |
1050 | } | |
1051 | ||
c2573128 MB |
1052 | irq = platform_get_irq(pdev, 0); |
1053 | if (irq < 0) { | |
1054 | dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq); | |
1055 | return irq; | |
1056 | } | |
1057 | ||
230d42d4 JB |
1058 | master = spi_alloc_master(&pdev->dev, |
1059 | sizeof(struct s3c64xx_spi_driver_data)); | |
1060 | if (master == NULL) { | |
1061 | dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); | |
1062 | return -ENOMEM; | |
1063 | } | |
1064 | ||
230d42d4 JB |
1065 | platform_set_drvdata(pdev, master); |
1066 | ||
1067 | sdd = spi_master_get_devdata(master); | |
a5238e36 | 1068 | sdd->port_conf = s3c64xx_spi_get_port_config(pdev); |
230d42d4 JB |
1069 | sdd->master = master; |
1070 | sdd->cntrlr_info = sci; | |
1071 | sdd->pdev = pdev; | |
1072 | sdd->sfr_start = mem_res->start; | |
2b908075 TA |
1073 | if (pdev->dev.of_node) { |
1074 | ret = of_alias_get_id(pdev->dev.of_node, "spi"); | |
1075 | if (ret < 0) { | |
75bf3361 JH |
1076 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", |
1077 | ret); | |
60a9a964 | 1078 | goto err_deref_master; |
2b908075 TA |
1079 | } |
1080 | sdd->port_id = ret; | |
1081 | } else { | |
1082 | sdd->port_id = pdev->id; | |
1083 | } | |
230d42d4 JB |
1084 | |
1085 | sdd->cur_bpw = 8; | |
1086 | ||
b5be04d3 PV |
1087 | sdd->tx_dma.direction = DMA_MEM_TO_DEV; |
1088 | sdd->rx_dma.direction = DMA_DEV_TO_MEM; | |
2b908075 TA |
1089 | |
1090 | master->dev.of_node = pdev->dev.of_node; | |
a5238e36 | 1091 | master->bus_num = sdd->port_id; |
230d42d4 | 1092 | master->setup = s3c64xx_spi_setup; |
1c20c200 | 1093 | master->cleanup = s3c64xx_spi_cleanup; |
ad2a99af | 1094 | master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; |
6bb9c0e3 | 1095 | master->prepare_message = s3c64xx_spi_prepare_message; |
0732a9d2 | 1096 | master->transfer_one = s3c64xx_spi_transfer_one; |
ad2a99af | 1097 | master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; |
230d42d4 JB |
1098 | master->num_chipselect = sci->num_cs; |
1099 | master->dma_alignment = 8; | |
24778be2 SW |
1100 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
1101 | SPI_BPW_MASK(8); | |
230d42d4 JB |
1102 | /* the spi->mode bits understood by this driver: */ |
1103 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
fc0f81b7 | 1104 | master->auto_runtime_pm = true; |
3f295887 MB |
1105 | if (!is_polling(sdd)) |
1106 | master->can_dma = s3c64xx_spi_can_dma; | |
230d42d4 | 1107 | |
b0ee5605 TR |
1108 | sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res); |
1109 | if (IS_ERR(sdd->regs)) { | |
1110 | ret = PTR_ERR(sdd->regs); | |
60a9a964 | 1111 | goto err_deref_master; |
230d42d4 JB |
1112 | } |
1113 | ||
00ab5392 | 1114 | if (sci->cfg_gpio && sci->cfg_gpio()) { |
230d42d4 JB |
1115 | dev_err(&pdev->dev, "Unable to config gpio\n"); |
1116 | ret = -EBUSY; | |
60a9a964 | 1117 | goto err_deref_master; |
230d42d4 JB |
1118 | } |
1119 | ||
1120 | /* Setup clocks */ | |
4eb77006 | 1121 | sdd->clk = devm_clk_get(&pdev->dev, "spi"); |
230d42d4 JB |
1122 | if (IS_ERR(sdd->clk)) { |
1123 | dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); | |
1124 | ret = PTR_ERR(sdd->clk); | |
60a9a964 | 1125 | goto err_deref_master; |
230d42d4 JB |
1126 | } |
1127 | ||
25981d82 AS |
1128 | ret = clk_prepare_enable(sdd->clk); |
1129 | if (ret) { | |
230d42d4 | 1130 | dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); |
60a9a964 | 1131 | goto err_deref_master; |
230d42d4 JB |
1132 | } |
1133 | ||
a24d850b | 1134 | sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); |
4eb77006 | 1135 | sdd->src_clk = devm_clk_get(&pdev->dev, clk_name); |
b0d5d6e5 | 1136 | if (IS_ERR(sdd->src_clk)) { |
230d42d4 | 1137 | dev_err(&pdev->dev, |
a24d850b | 1138 | "Unable to acquire clock '%s'\n", clk_name); |
b0d5d6e5 | 1139 | ret = PTR_ERR(sdd->src_clk); |
60a9a964 | 1140 | goto err_disable_clk; |
230d42d4 JB |
1141 | } |
1142 | ||
25981d82 AS |
1143 | ret = clk_prepare_enable(sdd->src_clk); |
1144 | if (ret) { | |
a24d850b | 1145 | dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); |
60a9a964 | 1146 | goto err_disable_clk; |
230d42d4 JB |
1147 | } |
1148 | ||
7990b008 AS |
1149 | if (sdd->port_conf->clk_ioclk) { |
1150 | sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk"); | |
1151 | if (IS_ERR(sdd->ioclk)) { | |
1152 | dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n"); | |
1153 | ret = PTR_ERR(sdd->ioclk); | |
1154 | goto err_disable_src_clk; | |
1155 | } | |
1156 | ||
1157 | ret = clk_prepare_enable(sdd->ioclk); | |
1158 | if (ret) { | |
1159 | dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n"); | |
1160 | goto err_disable_src_clk; | |
1161 | } | |
1162 | } | |
1163 | ||
483867ee HK |
1164 | pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); |
1165 | pm_runtime_use_autosuspend(&pdev->dev); | |
1166 | pm_runtime_set_active(&pdev->dev); | |
1167 | pm_runtime_enable(&pdev->dev); | |
1168 | pm_runtime_get_sync(&pdev->dev); | |
1169 | ||
230d42d4 | 1170 | /* Setup Deufult Mode */ |
a5238e36 | 1171 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
230d42d4 JB |
1172 | |
1173 | spin_lock_init(&sdd->lock); | |
1174 | init_completion(&sdd->xfer_completion); | |
230d42d4 | 1175 | |
4eb77006 JH |
1176 | ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, |
1177 | "spi-s3c64xx", sdd); | |
c2573128 MB |
1178 | if (ret != 0) { |
1179 | dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", | |
1180 | irq, ret); | |
60a9a964 | 1181 | goto err_pm_put; |
c2573128 MB |
1182 | } |
1183 | ||
1184 | writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | | |
1185 | S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, | |
1186 | sdd->regs + S3C64XX_SPI_INT_EN); | |
1187 | ||
91800f0e MB |
1188 | ret = devm_spi_register_master(&pdev->dev, master); |
1189 | if (ret != 0) { | |
1190 | dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret); | |
60a9a964 | 1191 | goto err_pm_put; |
230d42d4 JB |
1192 | } |
1193 | ||
75bf3361 | 1194 | dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n", |
a5238e36 | 1195 | sdd->port_id, master->num_chipselect); |
6f8dc9d4 SN |
1196 | dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", |
1197 | mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1); | |
230d42d4 | 1198 | |
483867ee HK |
1199 | pm_runtime_mark_last_busy(&pdev->dev); |
1200 | pm_runtime_put_autosuspend(&pdev->dev); | |
1201 | ||
230d42d4 JB |
1202 | return 0; |
1203 | ||
60a9a964 | 1204 | err_pm_put: |
483867ee | 1205 | pm_runtime_put_noidle(&pdev->dev); |
3c863792 HK |
1206 | pm_runtime_disable(&pdev->dev); |
1207 | pm_runtime_set_suspended(&pdev->dev); | |
483867ee | 1208 | |
7990b008 AS |
1209 | clk_disable_unprepare(sdd->ioclk); |
1210 | err_disable_src_clk: | |
9f667bff | 1211 | clk_disable_unprepare(sdd->src_clk); |
60a9a964 | 1212 | err_disable_clk: |
9f667bff | 1213 | clk_disable_unprepare(sdd->clk); |
60a9a964 | 1214 | err_deref_master: |
230d42d4 JB |
1215 | spi_master_put(master); |
1216 | ||
1217 | return ret; | |
1218 | } | |
1219 | ||
1220 | static int s3c64xx_spi_remove(struct platform_device *pdev) | |
1221 | { | |
9f135787 | 1222 | struct spi_master *master = platform_get_drvdata(pdev); |
230d42d4 | 1223 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 | 1224 | |
8ebe9d16 | 1225 | pm_runtime_get_sync(&pdev->dev); |
b97b6621 | 1226 | |
c2573128 MB |
1227 | writel(0, sdd->regs + S3C64XX_SPI_INT_EN); |
1228 | ||
7990b008 AS |
1229 | clk_disable_unprepare(sdd->ioclk); |
1230 | ||
9f667bff | 1231 | clk_disable_unprepare(sdd->src_clk); |
230d42d4 | 1232 | |
9f667bff | 1233 | clk_disable_unprepare(sdd->clk); |
230d42d4 | 1234 | |
8ebe9d16 HK |
1235 | pm_runtime_put_noidle(&pdev->dev); |
1236 | pm_runtime_disable(&pdev->dev); | |
1237 | pm_runtime_set_suspended(&pdev->dev); | |
1238 | ||
230d42d4 JB |
1239 | return 0; |
1240 | } | |
1241 | ||
997230d0 | 1242 | #ifdef CONFIG_PM_SLEEP |
e25d0bf9 | 1243 | static int s3c64xx_spi_suspend(struct device *dev) |
230d42d4 | 1244 | { |
9a2a5245 | 1245 | struct spi_master *master = dev_get_drvdata(dev); |
230d42d4 | 1246 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
230d42d4 | 1247 | |
347de6ba KK |
1248 | int ret = spi_master_suspend(master); |
1249 | if (ret) | |
1250 | return ret; | |
230d42d4 | 1251 | |
4fcd9b9e HK |
1252 | ret = pm_runtime_force_suspend(dev); |
1253 | if (ret < 0) | |
1254 | return ret; | |
230d42d4 JB |
1255 | |
1256 | sdd->cur_speed = 0; /* Output Clock is stopped */ | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
e25d0bf9 | 1261 | static int s3c64xx_spi_resume(struct device *dev) |
230d42d4 | 1262 | { |
9a2a5245 | 1263 | struct spi_master *master = dev_get_drvdata(dev); |
230d42d4 | 1264 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
ad7de729 | 1265 | struct s3c64xx_spi_info *sci = sdd->cntrlr_info; |
4fcd9b9e | 1266 | int ret; |
230d42d4 | 1267 | |
00ab5392 | 1268 | if (sci->cfg_gpio) |
2b908075 | 1269 | sci->cfg_gpio(); |
230d42d4 | 1270 | |
4fcd9b9e HK |
1271 | ret = pm_runtime_force_resume(dev); |
1272 | if (ret < 0) | |
1273 | return ret; | |
230d42d4 | 1274 | |
a5238e36 | 1275 | s3c64xx_spi_hwinit(sdd, sdd->port_id); |
230d42d4 | 1276 | |
347de6ba | 1277 | return spi_master_resume(master); |
230d42d4 | 1278 | } |
997230d0 | 1279 | #endif /* CONFIG_PM_SLEEP */ |
230d42d4 | 1280 | |
ec833050 | 1281 | #ifdef CONFIG_PM |
b97b6621 MB |
1282 | static int s3c64xx_spi_runtime_suspend(struct device *dev) |
1283 | { | |
9a2a5245 | 1284 | struct spi_master *master = dev_get_drvdata(dev); |
b97b6621 MB |
1285 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
1286 | ||
9f667bff TA |
1287 | clk_disable_unprepare(sdd->clk); |
1288 | clk_disable_unprepare(sdd->src_clk); | |
7990b008 | 1289 | clk_disable_unprepare(sdd->ioclk); |
b97b6621 MB |
1290 | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static int s3c64xx_spi_runtime_resume(struct device *dev) | |
1295 | { | |
9a2a5245 | 1296 | struct spi_master *master = dev_get_drvdata(dev); |
b97b6621 | 1297 | struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); |
8b06d5b8 | 1298 | int ret; |
b97b6621 | 1299 | |
7990b008 AS |
1300 | if (sdd->port_conf->clk_ioclk) { |
1301 | ret = clk_prepare_enable(sdd->ioclk); | |
1302 | if (ret != 0) | |
1303 | return ret; | |
1304 | } | |
1305 | ||
8b06d5b8 MB |
1306 | ret = clk_prepare_enable(sdd->src_clk); |
1307 | if (ret != 0) | |
7990b008 | 1308 | goto err_disable_ioclk; |
8b06d5b8 MB |
1309 | |
1310 | ret = clk_prepare_enable(sdd->clk); | |
7990b008 AS |
1311 | if (ret != 0) |
1312 | goto err_disable_src_clk; | |
b97b6621 MB |
1313 | |
1314 | return 0; | |
7990b008 AS |
1315 | |
1316 | err_disable_src_clk: | |
1317 | clk_disable_unprepare(sdd->src_clk); | |
1318 | err_disable_ioclk: | |
1319 | clk_disable_unprepare(sdd->ioclk); | |
1320 | ||
1321 | return ret; | |
b97b6621 | 1322 | } |
ec833050 | 1323 | #endif /* CONFIG_PM */ |
b97b6621 | 1324 | |
e25d0bf9 MB |
1325 | static const struct dev_pm_ops s3c64xx_spi_pm = { |
1326 | SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) | |
b97b6621 MB |
1327 | SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, |
1328 | s3c64xx_spi_runtime_resume, NULL) | |
e25d0bf9 MB |
1329 | }; |
1330 | ||
10ce0473 | 1331 | static struct s3c64xx_spi_port_config s3c2443_spi_port_config = { |
a5238e36 TA |
1332 | .fifo_lvl_mask = { 0x7f }, |
1333 | .rx_lvl_offset = 13, | |
1334 | .tx_st_done = 21, | |
1335 | .high_speed = true, | |
1336 | }; | |
1337 | ||
10ce0473 | 1338 | static struct s3c64xx_spi_port_config s3c6410_spi_port_config = { |
a5238e36 TA |
1339 | .fifo_lvl_mask = { 0x7f, 0x7F }, |
1340 | .rx_lvl_offset = 13, | |
1341 | .tx_st_done = 21, | |
1342 | }; | |
1343 | ||
10ce0473 | 1344 | static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { |
a5238e36 TA |
1345 | .fifo_lvl_mask = { 0x1ff, 0x7F }, |
1346 | .rx_lvl_offset = 15, | |
1347 | .tx_st_done = 25, | |
1348 | .high_speed = true, | |
1349 | }; | |
1350 | ||
10ce0473 | 1351 | static struct s3c64xx_spi_port_config exynos4_spi_port_config = { |
a5238e36 TA |
1352 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, |
1353 | .rx_lvl_offset = 15, | |
1354 | .tx_st_done = 25, | |
1355 | .high_speed = true, | |
1356 | .clk_from_cmu = true, | |
1357 | }; | |
1358 | ||
bff82038 G |
1359 | static struct s3c64xx_spi_port_config exynos5440_spi_port_config = { |
1360 | .fifo_lvl_mask = { 0x1ff }, | |
1361 | .rx_lvl_offset = 15, | |
1362 | .tx_st_done = 25, | |
1363 | .high_speed = true, | |
1364 | .clk_from_cmu = true, | |
1365 | .quirks = S3C64XX_SPI_QUIRK_POLL, | |
1366 | }; | |
1367 | ||
bf77cba9 PV |
1368 | static struct s3c64xx_spi_port_config exynos7_spi_port_config = { |
1369 | .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, | |
1370 | .rx_lvl_offset = 15, | |
1371 | .tx_st_done = 25, | |
1372 | .high_speed = true, | |
1373 | .clk_from_cmu = true, | |
1374 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, | |
1375 | }; | |
1376 | ||
7990b008 AS |
1377 | static struct s3c64xx_spi_port_config exynos5433_spi_port_config = { |
1378 | .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, | |
1379 | .rx_lvl_offset = 15, | |
1380 | .tx_st_done = 25, | |
1381 | .high_speed = true, | |
1382 | .clk_from_cmu = true, | |
1383 | .clk_ioclk = true, | |
1384 | .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, | |
1385 | }; | |
1386 | ||
23f6d39e | 1387 | static const struct platform_device_id s3c64xx_spi_driver_ids[] = { |
a5238e36 TA |
1388 | { |
1389 | .name = "s3c2443-spi", | |
1390 | .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, | |
1391 | }, { | |
1392 | .name = "s3c6410-spi", | |
1393 | .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, | |
a5238e36 TA |
1394 | }, |
1395 | { }, | |
1396 | }; | |
1397 | ||
2b908075 | 1398 | static const struct of_device_id s3c64xx_spi_dt_match[] = { |
a3b924df MK |
1399 | { .compatible = "samsung,s3c2443-spi", |
1400 | .data = (void *)&s3c2443_spi_port_config, | |
1401 | }, | |
1402 | { .compatible = "samsung,s3c6410-spi", | |
1403 | .data = (void *)&s3c6410_spi_port_config, | |
1404 | }, | |
a3b924df MK |
1405 | { .compatible = "samsung,s5pv210-spi", |
1406 | .data = (void *)&s5pv210_spi_port_config, | |
1407 | }, | |
2b908075 TA |
1408 | { .compatible = "samsung,exynos4210-spi", |
1409 | .data = (void *)&exynos4_spi_port_config, | |
1410 | }, | |
bff82038 G |
1411 | { .compatible = "samsung,exynos5440-spi", |
1412 | .data = (void *)&exynos5440_spi_port_config, | |
1413 | }, | |
bf77cba9 PV |
1414 | { .compatible = "samsung,exynos7-spi", |
1415 | .data = (void *)&exynos7_spi_port_config, | |
1416 | }, | |
7990b008 AS |
1417 | { .compatible = "samsung,exynos5433-spi", |
1418 | .data = (void *)&exynos5433_spi_port_config, | |
1419 | }, | |
2b908075 TA |
1420 | { }, |
1421 | }; | |
1422 | MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); | |
2b908075 | 1423 | |
230d42d4 JB |
1424 | static struct platform_driver s3c64xx_spi_driver = { |
1425 | .driver = { | |
1426 | .name = "s3c64xx-spi", | |
e25d0bf9 | 1427 | .pm = &s3c64xx_spi_pm, |
2b908075 | 1428 | .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), |
230d42d4 | 1429 | }, |
50c959fc | 1430 | .probe = s3c64xx_spi_probe, |
230d42d4 | 1431 | .remove = s3c64xx_spi_remove, |
a5238e36 | 1432 | .id_table = s3c64xx_spi_driver_ids, |
230d42d4 JB |
1433 | }; |
1434 | MODULE_ALIAS("platform:s3c64xx-spi"); | |
1435 | ||
50c959fc | 1436 | module_platform_driver(s3c64xx_spi_driver); |
230d42d4 JB |
1437 | |
1438 | MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); | |
1439 | MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); | |
1440 | MODULE_LICENSE("GPL"); |