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d1c8bbd7 KM |
1 | /* |
2 | * SuperH HSPI bus driver | |
3 | * | |
4 | * Copyright (C) 2011 Kuninori Morimoto | |
5 | * | |
6 | * Based on spi-sh.c: | |
7 | * Based on pxa2xx_spi.c: | |
8 | * Copyright (C) 2011 Renesas Solutions Corp. | |
9 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; version 2 of the License. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
23 | * | |
24 | */ | |
49e599b8 KM |
25 | |
26 | #include <linux/clk.h> | |
d1c8bbd7 KM |
27 | #include <linux/module.h> |
28 | #include <linux/kernel.h> | |
29 | #include <linux/timer.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/list.h> | |
d1c8bbd7 KM |
32 | #include <linux/interrupt.h> |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/pm_runtime.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/spi/spi.h> | |
37 | #include <linux/spi/sh_hspi.h> | |
38 | ||
39 | #define SPCR 0x00 | |
40 | #define SPSR 0x04 | |
41 | #define SPSCR 0x08 | |
42 | #define SPTBR 0x0C | |
43 | #define SPRBR 0x10 | |
44 | #define SPCR2 0x14 | |
45 | ||
46 | /* SPSR */ | |
47 | #define RXFL (1 << 2) | |
48 | ||
49 | #define hspi2info(h) (h->dev->platform_data) | |
50 | ||
51 | struct hspi_priv { | |
52 | void __iomem *addr; | |
53 | struct spi_master *master; | |
d1c8bbd7 | 54 | struct device *dev; |
49e599b8 | 55 | struct clk *clk; |
d1c8bbd7 KM |
56 | }; |
57 | ||
58 | /* | |
59 | * basic function | |
60 | */ | |
61 | static void hspi_write(struct hspi_priv *hspi, int reg, u32 val) | |
62 | { | |
63 | iowrite32(val, hspi->addr + reg); | |
64 | } | |
65 | ||
66 | static u32 hspi_read(struct hspi_priv *hspi, int reg) | |
67 | { | |
68 | return ioread32(hspi->addr + reg); | |
69 | } | |
70 | ||
71 | /* | |
72 | * transfer function | |
73 | */ | |
74 | static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val) | |
75 | { | |
76 | int t = 256; | |
77 | ||
78 | while (t--) { | |
79 | if ((mask & hspi_read(hspi, SPSR)) == val) | |
80 | return 0; | |
81 | ||
82 | msleep(20); | |
83 | } | |
84 | ||
85 | dev_err(hspi->dev, "timeout\n"); | |
86 | return -ETIMEDOUT; | |
87 | } | |
88 | ||
89 | static int hspi_push(struct hspi_priv *hspi, struct spi_message *msg, | |
90 | struct spi_transfer *t) | |
91 | { | |
92 | int i, ret; | |
93 | u8 *data = (u8 *)t->tx_buf; | |
94 | ||
95 | /* | |
96 | * FIXME | |
97 | * very simple, but polling transfer | |
98 | */ | |
99 | for (i = 0; i < t->len; i++) { | |
100 | /* wait remains */ | |
101 | ret = hspi_status_check_timeout(hspi, 0x1, 0x0); | |
102 | if (ret < 0) | |
103 | return ret; | |
104 | ||
105 | hspi_write(hspi, SPTBR, (u32)data[i]); | |
106 | ||
107 | /* wait recive */ | |
108 | ret = hspi_status_check_timeout(hspi, 0x4, 0x4); | |
109 | if (ret < 0) | |
110 | return ret; | |
111 | ||
112 | /* dummy read */ | |
113 | hspi_read(hspi, SPRBR); | |
114 | } | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | static int hspi_pop(struct hspi_priv *hspi, struct spi_message *msg, | |
120 | struct spi_transfer *t) | |
121 | { | |
122 | int i, ret; | |
123 | u8 *data = (u8 *)t->rx_buf; | |
124 | ||
125 | /* | |
126 | * FIXME | |
127 | * very simple, but polling receive | |
128 | */ | |
129 | for (i = 0; i < t->len; i++) { | |
130 | /* wait remains */ | |
131 | ret = hspi_status_check_timeout(hspi, 0x1, 0); | |
132 | if (ret < 0) | |
133 | return ret; | |
134 | ||
135 | /* dummy write */ | |
136 | hspi_write(hspi, SPTBR, 0x0); | |
137 | ||
138 | /* wait recive */ | |
139 | ret = hspi_status_check_timeout(hspi, 0x4, 0x4); | |
140 | if (ret < 0) | |
141 | return ret; | |
142 | ||
143 | data[i] = (u8)hspi_read(hspi, SPRBR); | |
144 | } | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
ec139b67 KM |
149 | /* |
150 | * spi master function | |
151 | */ | |
152 | static int hspi_prepare_transfer(struct spi_master *master) | |
d1c8bbd7 | 153 | { |
ec139b67 | 154 | struct hspi_priv *hspi = spi_master_get_devdata(master); |
d1c8bbd7 | 155 | |
d1c8bbd7 | 156 | pm_runtime_get_sync(hspi->dev); |
ec139b67 KM |
157 | return 0; |
158 | } | |
d1c8bbd7 | 159 | |
ec139b67 KM |
160 | static int hspi_unprepare_transfer(struct spi_master *master) |
161 | { | |
162 | struct hspi_priv *hspi = spi_master_get_devdata(master); | |
d1c8bbd7 | 163 | |
ec139b67 KM |
164 | pm_runtime_put_sync(hspi->dev); |
165 | return 0; | |
166 | } | |
d1c8bbd7 | 167 | |
49e599b8 KM |
168 | static void hspi_hw_setup(struct hspi_priv *hspi, |
169 | struct spi_message *msg, | |
170 | struct spi_transfer *t) | |
171 | { | |
172 | struct spi_device *spi = msg->spi; | |
173 | struct device *dev = hspi->dev; | |
174 | u32 target_rate; | |
175 | u32 spcr, idiv_clk; | |
176 | u32 rate, best_rate, min, tmp; | |
177 | ||
178 | target_rate = t ? t->speed_hz : 0; | |
179 | if (!target_rate) | |
180 | target_rate = spi->max_speed_hz; | |
181 | ||
182 | /* | |
183 | * find best IDIV/CLKCx settings | |
184 | */ | |
185 | min = ~0; | |
186 | best_rate = 0; | |
187 | spcr = 0; | |
188 | for (idiv_clk = 0x00; idiv_clk <= 0x3F; idiv_clk++) { | |
189 | rate = clk_get_rate(hspi->clk); | |
190 | ||
191 | /* IDIV calculation */ | |
192 | if (idiv_clk & (1 << 5)) | |
193 | rate /= 128; | |
194 | else | |
195 | rate /= 16; | |
196 | ||
197 | /* CLKCx calculation */ | |
198 | rate /= (((idiv_clk & 0x1F) + 1) * 2) ; | |
199 | ||
200 | /* save best settings */ | |
201 | tmp = abs(target_rate - rate); | |
202 | if (tmp < min) { | |
203 | min = tmp; | |
204 | spcr = idiv_clk; | |
205 | best_rate = rate; | |
206 | } | |
207 | } | |
208 | ||
209 | if (spi->mode & SPI_CPHA) | |
210 | spcr |= 1 << 7; | |
211 | if (spi->mode & SPI_CPOL) | |
212 | spcr |= 1 << 6; | |
213 | ||
214 | dev_dbg(dev, "speed %d/%d\n", target_rate, best_rate); | |
215 | ||
216 | hspi_write(hspi, SPCR, spcr); | |
217 | hspi_write(hspi, SPSR, 0x0); | |
218 | hspi_write(hspi, SPSCR, 0x1); /* master mode */ | |
219 | } | |
220 | ||
ec139b67 KM |
221 | static int hspi_transfer_one_message(struct spi_master *master, |
222 | struct spi_message *msg) | |
223 | { | |
224 | struct hspi_priv *hspi = spi_master_get_devdata(master); | |
225 | struct spi_transfer *t; | |
226 | int ret; | |
d1c8bbd7 | 227 | |
ec139b67 | 228 | dev_dbg(hspi->dev, "%s\n", __func__); |
d1c8bbd7 | 229 | |
ec139b67 KM |
230 | ret = 0; |
231 | list_for_each_entry(t, &msg->transfers, transfer_list) { | |
49e599b8 KM |
232 | hspi_hw_setup(hspi, msg, t); |
233 | ||
ec139b67 KM |
234 | if (t->tx_buf) { |
235 | ret = hspi_push(hspi, msg, t); | |
236 | if (ret < 0) | |
237 | goto error; | |
d1c8bbd7 | 238 | } |
ec139b67 KM |
239 | if (t->rx_buf) { |
240 | ret = hspi_pop(hspi, msg, t); | |
241 | if (ret < 0) | |
242 | goto error; | |
d1c8bbd7 | 243 | } |
ec139b67 | 244 | msg->actual_length += t->len; |
d1c8bbd7 | 245 | } |
ec139b67 | 246 | error: |
d1c8bbd7 | 247 | |
ec139b67 KM |
248 | msg->status = ret; |
249 | spi_finalize_current_message(master); | |
d1c8bbd7 | 250 | |
ec139b67 | 251 | return ret; |
d1c8bbd7 KM |
252 | } |
253 | ||
d1c8bbd7 KM |
254 | static int hspi_setup(struct spi_device *spi) |
255 | { | |
256 | struct hspi_priv *hspi = spi_master_get_devdata(spi->master); | |
257 | struct device *dev = hspi->dev; | |
258 | ||
259 | if (8 != spi->bits_per_word) { | |
260 | dev_err(dev, "bits_per_word should be 8\n"); | |
261 | return -EIO; | |
262 | } | |
263 | ||
264 | dev_dbg(dev, "%s setup\n", spi->modalias); | |
265 | ||
266 | return 0; | |
267 | } | |
268 | ||
269 | static void hspi_cleanup(struct spi_device *spi) | |
270 | { | |
271 | struct hspi_priv *hspi = spi_master_get_devdata(spi->master); | |
272 | struct device *dev = hspi->dev; | |
273 | ||
274 | dev_dbg(dev, "%s cleanup\n", spi->modalias); | |
275 | } | |
276 | ||
d1c8bbd7 KM |
277 | static int __devinit hspi_probe(struct platform_device *pdev) |
278 | { | |
279 | struct resource *res; | |
280 | struct spi_master *master; | |
281 | struct hspi_priv *hspi; | |
49e599b8 | 282 | struct clk *clk; |
d1c8bbd7 KM |
283 | int ret; |
284 | ||
285 | /* get base addr */ | |
286 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
287 | if (!res) { | |
288 | dev_err(&pdev->dev, "invalid resource\n"); | |
289 | return -EINVAL; | |
290 | } | |
291 | ||
292 | master = spi_alloc_master(&pdev->dev, sizeof(*hspi)); | |
293 | if (!master) { | |
294 | dev_err(&pdev->dev, "spi_alloc_master error.\n"); | |
295 | return -ENOMEM; | |
296 | } | |
297 | ||
49e599b8 KM |
298 | clk = clk_get(NULL, "shyway_clk"); |
299 | if (!clk) { | |
300 | dev_err(&pdev->dev, "shyway_clk is required\n"); | |
301 | ret = -EINVAL; | |
302 | goto error0; | |
303 | } | |
304 | ||
d1c8bbd7 KM |
305 | hspi = spi_master_get_devdata(master); |
306 | dev_set_drvdata(&pdev->dev, hspi); | |
307 | ||
308 | /* init hspi */ | |
309 | hspi->master = master; | |
310 | hspi->dev = &pdev->dev; | |
49e599b8 | 311 | hspi->clk = clk; |
d1c8bbd7 KM |
312 | hspi->addr = devm_ioremap(hspi->dev, |
313 | res->start, resource_size(res)); | |
314 | if (!hspi->addr) { | |
315 | dev_err(&pdev->dev, "ioremap error.\n"); | |
316 | ret = -ENOMEM; | |
317 | goto error1; | |
318 | } | |
d1c8bbd7 KM |
319 | |
320 | master->num_chipselect = 1; | |
321 | master->bus_num = pdev->id; | |
322 | master->setup = hspi_setup; | |
d1c8bbd7 KM |
323 | master->cleanup = hspi_cleanup; |
324 | master->mode_bits = SPI_CPOL | SPI_CPHA; | |
ec139b67 KM |
325 | master->prepare_transfer_hardware = hspi_prepare_transfer; |
326 | master->transfer_one_message = hspi_transfer_one_message; | |
327 | master->unprepare_transfer_hardware = hspi_unprepare_transfer; | |
d1c8bbd7 KM |
328 | ret = spi_register_master(master); |
329 | if (ret < 0) { | |
330 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
ec139b67 | 331 | goto error2; |
d1c8bbd7 KM |
332 | } |
333 | ||
334 | pm_runtime_enable(&pdev->dev); | |
335 | ||
336 | dev_info(&pdev->dev, "probed\n"); | |
337 | ||
338 | return 0; | |
339 | ||
d1c8bbd7 KM |
340 | error2: |
341 | devm_iounmap(hspi->dev, hspi->addr); | |
342 | error1: | |
49e599b8 KM |
343 | clk_put(clk); |
344 | error0: | |
d1c8bbd7 KM |
345 | spi_master_put(master); |
346 | ||
347 | return ret; | |
348 | } | |
349 | ||
350 | static int __devexit hspi_remove(struct platform_device *pdev) | |
351 | { | |
352 | struct hspi_priv *hspi = dev_get_drvdata(&pdev->dev); | |
353 | ||
354 | pm_runtime_disable(&pdev->dev); | |
355 | ||
49e599b8 | 356 | clk_put(hspi->clk); |
d1c8bbd7 | 357 | spi_unregister_master(hspi->master); |
d1c8bbd7 KM |
358 | devm_iounmap(hspi->dev, hspi->addr); |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
363 | static struct platform_driver hspi_driver = { | |
364 | .probe = hspi_probe, | |
365 | .remove = __devexit_p(hspi_remove), | |
366 | .driver = { | |
367 | .name = "sh-hspi", | |
368 | .owner = THIS_MODULE, | |
369 | }, | |
370 | }; | |
371 | module_platform_driver(hspi_driver); | |
372 | ||
373 | MODULE_DESCRIPTION("SuperH HSPI bus driver"); | |
374 | MODULE_LICENSE("GPL"); | |
375 | MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"); | |
376 | MODULE_ALIAS("platform:sh_spi"); |