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Commit | Line | Data |
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8051effc MD |
1 | /* |
2 | * SuperH MSIOF SPI Master Interface | |
3 | * | |
4 | * Copyright (c) 2009 Magnus Damm | |
cf9e4784 HN |
5 | * Copyright (C) 2014 Renesas Electronics Corporation |
6 | * Copyright (C) 2014-2017 Glider bvba | |
8051effc MD |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | */ | |
13 | ||
e2dbf5eb GL |
14 | #include <linux/bitmap.h> |
15 | #include <linux/clk.h> | |
16 | #include <linux/completion.h> | |
8051effc | 17 | #include <linux/delay.h> |
b0d0ce8b GU |
18 | #include <linux/dma-mapping.h> |
19 | #include <linux/dmaengine.h> | |
e2dbf5eb GL |
20 | #include <linux/err.h> |
21 | #include <linux/gpio.h> | |
8051effc | 22 | #include <linux/interrupt.h> |
e2dbf5eb GL |
23 | #include <linux/io.h> |
24 | #include <linux/kernel.h> | |
d7614de4 | 25 | #include <linux/module.h> |
cf9c86ef | 26 | #include <linux/of.h> |
50a7e23f | 27 | #include <linux/of_device.h> |
8051effc | 28 | #include <linux/platform_device.h> |
8051effc | 29 | #include <linux/pm_runtime.h> |
b0d0ce8b | 30 | #include <linux/sh_dma.h> |
8051effc | 31 | |
e2dbf5eb | 32 | #include <linux/spi/sh_msiof.h> |
8051effc | 33 | #include <linux/spi/spi.h> |
8051effc | 34 | |
8051effc MD |
35 | #include <asm/unaligned.h> |
36 | ||
50a7e23f GU |
37 | struct sh_msiof_chipdata { |
38 | u16 tx_fifo_size; | |
39 | u16 rx_fifo_size; | |
beb74bb0 | 40 | u16 master_flags; |
61a8dec5 | 41 | u16 min_div; |
50a7e23f GU |
42 | }; |
43 | ||
8051effc | 44 | struct sh_msiof_spi_priv { |
b0d0ce8b | 45 | struct spi_master *master; |
8051effc MD |
46 | void __iomem *mapbase; |
47 | struct clk *clk; | |
48 | struct platform_device *pdev; | |
49 | struct sh_msiof_spi_info *info; | |
50 | struct completion done; | |
fe78d0b7 KM |
51 | unsigned int tx_fifo_size; |
52 | unsigned int rx_fifo_size; | |
61a8dec5 | 53 | unsigned int min_div; |
b0d0ce8b GU |
54 | void *tx_dma_page; |
55 | void *rx_dma_page; | |
56 | dma_addr_t tx_dma_addr; | |
57 | dma_addr_t rx_dma_addr; | |
8950792b GU |
58 | bool native_cs_inited; |
59 | bool native_cs_high; | |
cf9e4784 | 60 | bool slave_aborted; |
8051effc MD |
61 | }; |
62 | ||
01cfef57 GU |
63 | #define TMDR1 0x00 /* Transmit Mode Register 1 */ |
64 | #define TMDR2 0x04 /* Transmit Mode Register 2 */ | |
65 | #define TMDR3 0x08 /* Transmit Mode Register 3 */ | |
66 | #define RMDR1 0x10 /* Receive Mode Register 1 */ | |
67 | #define RMDR2 0x14 /* Receive Mode Register 2 */ | |
68 | #define RMDR3 0x18 /* Receive Mode Register 3 */ | |
69 | #define TSCR 0x20 /* Transmit Clock Select Register */ | |
70 | #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ | |
71 | #define CTR 0x28 /* Control Register */ | |
72 | #define FCTR 0x30 /* FIFO Control Register */ | |
73 | #define STR 0x40 /* Status Register */ | |
74 | #define IER 0x44 /* Interrupt Enable Register */ | |
75 | #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ | |
76 | #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ | |
77 | #define TFDR 0x50 /* Transmit FIFO Data Register */ | |
78 | #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ | |
79 | #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ | |
80 | #define RFDR 0x60 /* Receive FIFO Data Register */ | |
81 | ||
82 | /* TMDR1 and RMDR1 */ | |
83 | #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */ | |
84 | #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */ | |
85 | #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */ | |
86 | #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */ | |
87 | #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ | |
88 | #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ | |
3110628d YS |
89 | #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */ |
90 | #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */ | |
6d40530e | 91 | #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */ |
01cfef57 GU |
92 | #define MDR1_FLD_SHIFT 2 |
93 | #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */ | |
94 | /* TMDR1 */ | |
95 | #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */ | |
96 | ||
97 | /* TMDR2 and RMDR2 */ | |
98 | #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ | |
99 | #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ | |
100 | #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */ | |
101 | ||
102 | /* TSCR and RSCR */ | |
103 | #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */ | |
104 | #define SCR_BRPS(i) (((i) - 1) << 8) | |
105 | #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */ | |
106 | #define SCR_BRDV_DIV_2 0x0000 | |
107 | #define SCR_BRDV_DIV_4 0x0001 | |
108 | #define SCR_BRDV_DIV_8 0x0002 | |
109 | #define SCR_BRDV_DIV_16 0x0003 | |
110 | #define SCR_BRDV_DIV_32 0x0004 | |
111 | #define SCR_BRDV_DIV_1 0x0007 | |
112 | ||
113 | /* CTR */ | |
114 | #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */ | |
115 | #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */ | |
116 | #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ | |
117 | #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */ | |
118 | #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */ | |
119 | #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ | |
120 | #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ | |
121 | #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ | |
122 | #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */ | |
123 | #define CTR_TXDIZ_LOW 0x00000000 /* 0 */ | |
124 | #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */ | |
125 | #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */ | |
126 | #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */ | |
127 | #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */ | |
128 | #define CTR_TXE 0x00000200 /* Transmit Enable */ | |
129 | #define CTR_RXE 0x00000100 /* Receive Enable */ | |
130 | ||
2e2b3687 GU |
131 | /* FCTR */ |
132 | #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */ | |
133 | #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */ | |
134 | #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */ | |
135 | #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */ | |
136 | #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */ | |
137 | #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */ | |
138 | #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */ | |
139 | #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */ | |
140 | #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */ | |
141 | #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */ | |
142 | #define FCTR_TFUA_SHIFT 20 | |
143 | #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT) | |
144 | #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */ | |
145 | #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */ | |
146 | #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */ | |
147 | #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */ | |
148 | #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */ | |
149 | #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */ | |
150 | #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */ | |
151 | #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */ | |
152 | #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */ | |
153 | #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */ | |
154 | #define FCTR_RFUA_SHIFT 4 | |
155 | #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT) | |
156 | ||
157 | /* STR */ | |
158 | #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */ | |
159 | #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */ | |
01cfef57 | 160 | #define STR_TEOF 0x00800000 /* Frame Transmission End */ |
2e2b3687 GU |
161 | #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */ |
162 | #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */ | |
163 | #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */ | |
164 | #define STR_RFFUL 0x00002000 /* Receive FIFO Full */ | |
165 | #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */ | |
01cfef57 | 166 | #define STR_REOF 0x00000080 /* Frame Reception End */ |
2e2b3687 GU |
167 | #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */ |
168 | #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */ | |
169 | #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */ | |
170 | ||
171 | /* IER */ | |
172 | #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */ | |
173 | #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */ | |
174 | #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */ | |
175 | #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */ | |
176 | #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */ | |
177 | #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */ | |
178 | #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */ | |
179 | #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */ | |
180 | #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */ | |
181 | #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */ | |
182 | #define IER_REOFE 0x00000080 /* Frame Reception End Enable */ | |
183 | #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */ | |
184 | #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */ | |
185 | #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */ | |
01cfef57 | 186 | |
8051effc | 187 | |
e2dbf5eb | 188 | static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) |
8051effc MD |
189 | { |
190 | switch (reg_offs) { | |
191 | case TSCR: | |
192 | case RSCR: | |
193 | return ioread16(p->mapbase + reg_offs); | |
194 | default: | |
195 | return ioread32(p->mapbase + reg_offs); | |
196 | } | |
197 | } | |
198 | ||
199 | static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, | |
e2dbf5eb | 200 | u32 value) |
8051effc MD |
201 | { |
202 | switch (reg_offs) { | |
203 | case TSCR: | |
204 | case RSCR: | |
205 | iowrite16(value, p->mapbase + reg_offs); | |
206 | break; | |
207 | default: | |
208 | iowrite32(value, p->mapbase + reg_offs); | |
209 | break; | |
210 | } | |
211 | } | |
212 | ||
213 | static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, | |
e2dbf5eb | 214 | u32 clr, u32 set) |
8051effc | 215 | { |
e2dbf5eb GL |
216 | u32 mask = clr | set; |
217 | u32 data; | |
8051effc MD |
218 | int k; |
219 | ||
220 | data = sh_msiof_read(p, CTR); | |
221 | data &= ~clr; | |
222 | data |= set; | |
223 | sh_msiof_write(p, CTR, data); | |
224 | ||
225 | for (k = 100; k > 0; k--) { | |
226 | if ((sh_msiof_read(p, CTR) & mask) == set) | |
227 | break; | |
228 | ||
229 | udelay(10); | |
230 | } | |
231 | ||
232 | return k > 0 ? 0 : -ETIMEDOUT; | |
233 | } | |
234 | ||
235 | static irqreturn_t sh_msiof_spi_irq(int irq, void *data) | |
236 | { | |
237 | struct sh_msiof_spi_priv *p = data; | |
238 | ||
239 | /* just disable the interrupt and wake up */ | |
240 | sh_msiof_write(p, IER, 0); | |
241 | complete(&p->done); | |
242 | ||
243 | return IRQ_HANDLED; | |
244 | } | |
245 | ||
246 | static struct { | |
247 | unsigned short div; | |
65d5665b NI |
248 | unsigned short brdv; |
249 | } const sh_msiof_spi_div_table[] = { | |
250 | { 1, SCR_BRDV_DIV_1 }, | |
251 | { 2, SCR_BRDV_DIV_2 }, | |
252 | { 4, SCR_BRDV_DIV_4 }, | |
253 | { 8, SCR_BRDV_DIV_8 }, | |
254 | { 16, SCR_BRDV_DIV_16 }, | |
255 | { 32, SCR_BRDV_DIV_32 }, | |
8051effc MD |
256 | }; |
257 | ||
258 | static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, | |
6a85fc5a | 259 | unsigned long parent_rate, u32 spi_hz) |
8051effc MD |
260 | { |
261 | unsigned long div = 1024; | |
65d5665b | 262 | u32 brps, scr; |
8051effc MD |
263 | size_t k; |
264 | ||
265 | if (!WARN_ON(!spi_hz || !parent_rate)) | |
e4d313ff | 266 | div = DIV_ROUND_UP(parent_rate, spi_hz); |
8051effc | 267 | |
61a8dec5 GU |
268 | div = max_t(unsigned long, div, p->min_div); |
269 | ||
65d5665b NI |
270 | for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) { |
271 | brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div); | |
c3ccf357 GU |
272 | /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */ |
273 | if (sh_msiof_spi_div_table[k].div == 1 && brps > 2) | |
274 | continue; | |
65d5665b | 275 | if (brps <= 32) /* max of brdv is 32 */ |
8051effc MD |
276 | break; |
277 | } | |
278 | ||
65d5665b | 279 | k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1); |
30b3f52b | 280 | brps = min_t(int, brps, 32); |
8051effc | 281 | |
65d5665b NI |
282 | scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps); |
283 | sh_msiof_write(p, TSCR, scr); | |
a6802cc0 | 284 | if (!(p->master->flags & SPI_MASTER_MUST_TX)) |
65d5665b | 285 | sh_msiof_write(p, RSCR, scr); |
8051effc MD |
286 | } |
287 | ||
3110628d YS |
288 | static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) |
289 | { | |
290 | /* | |
291 | * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl | |
292 | * b'000 : 0 | |
293 | * b'001 : 100 | |
294 | * b'010 : 200 | |
295 | * b'011 (SYNCDL only) : 300 | |
296 | * b'101 : 50 | |
297 | * b'110 : 150 | |
298 | */ | |
299 | if (dtdl_or_syncdl % 100) | |
300 | return dtdl_or_syncdl / 100 + 5; | |
301 | else | |
302 | return dtdl_or_syncdl / 100; | |
303 | } | |
304 | ||
305 | static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) | |
306 | { | |
307 | u32 val; | |
308 | ||
309 | if (!p->info) | |
310 | return 0; | |
311 | ||
312 | /* check if DTDL and SYNCDL is allowed value */ | |
313 | if (p->info->dtdl > 200 || p->info->syncdl > 300) { | |
314 | dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n"); | |
315 | return 0; | |
316 | } | |
317 | ||
318 | /* check if the sum of DTDL and SYNCDL becomes an integer value */ | |
319 | if ((p->info->dtdl + p->info->syncdl) % 100) { | |
320 | dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n"); | |
321 | return 0; | |
322 | } | |
323 | ||
324 | val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT; | |
325 | val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT; | |
326 | ||
327 | return val; | |
328 | } | |
329 | ||
8051effc | 330 | static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, |
e2dbf5eb | 331 | u32 cpol, u32 cpha, |
50a77998 | 332 | u32 tx_hi_z, u32 lsb_first, u32 cs_high) |
8051effc | 333 | { |
e2dbf5eb | 334 | u32 tmp; |
8051effc MD |
335 | int edge; |
336 | ||
337 | /* | |
e8708ef7 MP |
338 | * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG |
339 | * 0 0 10 10 1 1 | |
340 | * 0 1 10 10 0 0 | |
341 | * 1 0 11 11 0 0 | |
342 | * 1 1 11 11 1 1 | |
8051effc | 343 | */ |
01cfef57 GU |
344 | tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP; |
345 | tmp |= !cs_high << MDR1_SYNCAC_SHIFT; | |
346 | tmp |= lsb_first << MDR1_BITLSB_SHIFT; | |
3110628d | 347 | tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); |
cf9e4784 HN |
348 | if (spi_controller_is_slave(p->master)) |
349 | sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON); | |
350 | else | |
351 | sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON); | |
a6802cc0 | 352 | if (p->master->flags & SPI_MASTER_MUST_TX) { |
beb74bb0 GU |
353 | /* These bits are reserved if RX needs TX */ |
354 | tmp &= ~0x0000ffff; | |
355 | } | |
01cfef57 | 356 | sh_msiof_write(p, RMDR1, tmp); |
8051effc | 357 | |
01cfef57 GU |
358 | tmp = 0; |
359 | tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT; | |
360 | tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT; | |
8051effc | 361 | |
e2dbf5eb | 362 | edge = cpol ^ !cpha; |
8051effc | 363 | |
01cfef57 GU |
364 | tmp |= edge << CTR_TEDG_SHIFT; |
365 | tmp |= edge << CTR_REDG_SHIFT; | |
366 | tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW; | |
8051effc MD |
367 | sh_msiof_write(p, CTR, tmp); |
368 | } | |
369 | ||
370 | static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, | |
371 | const void *tx_buf, void *rx_buf, | |
e2dbf5eb | 372 | u32 bits, u32 words) |
8051effc | 373 | { |
01cfef57 | 374 | u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words); |
8051effc | 375 | |
a6802cc0 | 376 | if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX)) |
8051effc MD |
377 | sh_msiof_write(p, TMDR2, dr2); |
378 | else | |
01cfef57 | 379 | sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1); |
8051effc MD |
380 | |
381 | if (rx_buf) | |
382 | sh_msiof_write(p, RMDR2, dr2); | |
8051effc MD |
383 | } |
384 | ||
385 | static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) | |
386 | { | |
ce49664c HY |
387 | sh_msiof_write(p, STR, |
388 | sh_msiof_read(p, STR) & ~(STR_TDREQ | STR_RDREQ)); | |
8051effc MD |
389 | } |
390 | ||
391 | static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, | |
392 | const void *tx_buf, int words, int fs) | |
393 | { | |
e2dbf5eb | 394 | const u8 *buf_8 = tx_buf; |
8051effc MD |
395 | int k; |
396 | ||
397 | for (k = 0; k < words; k++) | |
398 | sh_msiof_write(p, TFDR, buf_8[k] << fs); | |
399 | } | |
400 | ||
401 | static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, | |
402 | const void *tx_buf, int words, int fs) | |
403 | { | |
e2dbf5eb | 404 | const u16 *buf_16 = tx_buf; |
8051effc MD |
405 | int k; |
406 | ||
407 | for (k = 0; k < words; k++) | |
408 | sh_msiof_write(p, TFDR, buf_16[k] << fs); | |
409 | } | |
410 | ||
411 | static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, | |
412 | const void *tx_buf, int words, int fs) | |
413 | { | |
e2dbf5eb | 414 | const u16 *buf_16 = tx_buf; |
8051effc MD |
415 | int k; |
416 | ||
417 | for (k = 0; k < words; k++) | |
418 | sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs); | |
419 | } | |
420 | ||
421 | static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, | |
422 | const void *tx_buf, int words, int fs) | |
423 | { | |
e2dbf5eb | 424 | const u32 *buf_32 = tx_buf; |
8051effc MD |
425 | int k; |
426 | ||
427 | for (k = 0; k < words; k++) | |
428 | sh_msiof_write(p, TFDR, buf_32[k] << fs); | |
429 | } | |
430 | ||
431 | static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, | |
432 | const void *tx_buf, int words, int fs) | |
433 | { | |
e2dbf5eb | 434 | const u32 *buf_32 = tx_buf; |
8051effc MD |
435 | int k; |
436 | ||
437 | for (k = 0; k < words; k++) | |
438 | sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs); | |
439 | } | |
440 | ||
9dabb3f3 GL |
441 | static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, |
442 | const void *tx_buf, int words, int fs) | |
443 | { | |
444 | const u32 *buf_32 = tx_buf; | |
445 | int k; | |
446 | ||
447 | for (k = 0; k < words; k++) | |
448 | sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs)); | |
449 | } | |
450 | ||
451 | static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, | |
452 | const void *tx_buf, int words, int fs) | |
453 | { | |
454 | const u32 *buf_32 = tx_buf; | |
455 | int k; | |
456 | ||
457 | for (k = 0; k < words; k++) | |
458 | sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs)); | |
459 | } | |
460 | ||
8051effc MD |
461 | static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, |
462 | void *rx_buf, int words, int fs) | |
463 | { | |
e2dbf5eb | 464 | u8 *buf_8 = rx_buf; |
8051effc MD |
465 | int k; |
466 | ||
467 | for (k = 0; k < words; k++) | |
468 | buf_8[k] = sh_msiof_read(p, RFDR) >> fs; | |
469 | } | |
470 | ||
471 | static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, | |
472 | void *rx_buf, int words, int fs) | |
473 | { | |
e2dbf5eb | 474 | u16 *buf_16 = rx_buf; |
8051effc MD |
475 | int k; |
476 | ||
477 | for (k = 0; k < words; k++) | |
478 | buf_16[k] = sh_msiof_read(p, RFDR) >> fs; | |
479 | } | |
480 | ||
481 | static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, | |
482 | void *rx_buf, int words, int fs) | |
483 | { | |
e2dbf5eb | 484 | u16 *buf_16 = rx_buf; |
8051effc MD |
485 | int k; |
486 | ||
487 | for (k = 0; k < words; k++) | |
488 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]); | |
489 | } | |
490 | ||
491 | static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, | |
492 | void *rx_buf, int words, int fs) | |
493 | { | |
e2dbf5eb | 494 | u32 *buf_32 = rx_buf; |
8051effc MD |
495 | int k; |
496 | ||
497 | for (k = 0; k < words; k++) | |
498 | buf_32[k] = sh_msiof_read(p, RFDR) >> fs; | |
499 | } | |
500 | ||
501 | static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, | |
502 | void *rx_buf, int words, int fs) | |
503 | { | |
e2dbf5eb | 504 | u32 *buf_32 = rx_buf; |
8051effc MD |
505 | int k; |
506 | ||
507 | for (k = 0; k < words; k++) | |
508 | put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]); | |
509 | } | |
510 | ||
9dabb3f3 GL |
511 | static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, |
512 | void *rx_buf, int words, int fs) | |
513 | { | |
514 | u32 *buf_32 = rx_buf; | |
515 | int k; | |
516 | ||
517 | for (k = 0; k < words; k++) | |
518 | buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs); | |
519 | } | |
520 | ||
521 | static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, | |
522 | void *rx_buf, int words, int fs) | |
523 | { | |
524 | u32 *buf_32 = rx_buf; | |
525 | int k; | |
526 | ||
527 | for (k = 0; k < words; k++) | |
528 | put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]); | |
529 | } | |
530 | ||
8d19534a | 531 | static int sh_msiof_spi_setup(struct spi_device *spi) |
8051effc | 532 | { |
8d19534a | 533 | struct device_node *np = spi->master->dev.of_node; |
c833ff73 | 534 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master); |
8950792b | 535 | u32 clr, set, tmp; |
01576056 | 536 | |
8d19534a GU |
537 | if (!np) { |
538 | /* | |
539 | * Use spi->controller_data for CS (same strategy as spi_gpio), | |
540 | * if any. otherwise let HW control CS | |
541 | */ | |
542 | spi->cs_gpio = (uintptr_t)spi->controller_data; | |
543 | } | |
8051effc | 544 | |
8950792b | 545 | if (spi->cs_gpio >= 0) { |
1bd6363b | 546 | gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); |
8950792b GU |
547 | return 0; |
548 | } | |
8051effc | 549 | |
8950792b GU |
550 | if (spi_controller_is_slave(p->master)) |
551 | return 0; | |
01576056 | 552 | |
8950792b GU |
553 | if (p->native_cs_inited && |
554 | (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH))) | |
555 | return 0; | |
01576056 | 556 | |
8950792b GU |
557 | /* Configure native chip select mode/polarity early */ |
558 | clr = MDR1_SYNCMD_MASK; | |
e6059969 | 559 | set = MDR1_SYNCMD_SPI; |
8950792b GU |
560 | if (spi->mode & SPI_CS_HIGH) |
561 | clr |= BIT(MDR1_SYNCAC_SHIFT); | |
562 | else | |
563 | set |= BIT(MDR1_SYNCAC_SHIFT); | |
564 | pm_runtime_get_sync(&p->pdev->dev); | |
565 | tmp = sh_msiof_read(p, TMDR1) & ~clr; | |
e6059969 GU |
566 | sh_msiof_write(p, TMDR1, tmp | set | MDR1_TRMD | TMDR1_PCON); |
567 | tmp = sh_msiof_read(p, RMDR1) & ~clr; | |
568 | sh_msiof_write(p, RMDR1, tmp | set); | |
8950792b GU |
569 | pm_runtime_put(&p->pdev->dev); |
570 | p->native_cs_high = spi->mode & SPI_CS_HIGH; | |
571 | p->native_cs_inited = true; | |
1bd6363b | 572 | return 0; |
8051effc MD |
573 | } |
574 | ||
c833ff73 GU |
575 | static int sh_msiof_prepare_message(struct spi_master *master, |
576 | struct spi_message *msg) | |
8051effc | 577 | { |
c833ff73 GU |
578 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
579 | const struct spi_device *spi = msg->spi; | |
8051effc | 580 | |
c833ff73 GU |
581 | /* Configure pins before asserting CS */ |
582 | sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL), | |
583 | !!(spi->mode & SPI_CPHA), | |
584 | !!(spi->mode & SPI_3WIRE), | |
585 | !!(spi->mode & SPI_LSB_FIRST), | |
586 | !!(spi->mode & SPI_CS_HIGH)); | |
587 | return 0; | |
8051effc MD |
588 | } |
589 | ||
76c02e71 GU |
590 | static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) |
591 | { | |
cf9e4784 HN |
592 | bool slave = spi_controller_is_slave(p->master); |
593 | int ret = 0; | |
76c02e71 GU |
594 | |
595 | /* setup clock and rx/tx signals */ | |
cf9e4784 HN |
596 | if (!slave) |
597 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE); | |
76c02e71 GU |
598 | if (rx_buf && !ret) |
599 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE); | |
600 | if (!ret) | |
601 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE); | |
602 | ||
603 | /* start by setting frame bit */ | |
cf9e4784 | 604 | if (!ret && !slave) |
76c02e71 GU |
605 | ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE); |
606 | ||
607 | return ret; | |
608 | } | |
609 | ||
610 | static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) | |
611 | { | |
cf9e4784 HN |
612 | bool slave = spi_controller_is_slave(p->master); |
613 | int ret = 0; | |
76c02e71 GU |
614 | |
615 | /* shut down frame, rx/tx and clock signals */ | |
cf9e4784 HN |
616 | if (!slave) |
617 | ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0); | |
76c02e71 GU |
618 | if (!ret) |
619 | ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0); | |
620 | if (rx_buf && !ret) | |
621 | ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0); | |
cf9e4784 | 622 | if (!ret && !slave) |
76c02e71 GU |
623 | ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0); |
624 | ||
625 | return ret; | |
626 | } | |
627 | ||
cf9e4784 HN |
628 | static int sh_msiof_slave_abort(struct spi_master *master) |
629 | { | |
630 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); | |
631 | ||
632 | p->slave_aborted = true; | |
633 | complete(&p->done); | |
634 | return 0; | |
635 | } | |
636 | ||
637 | static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p) | |
638 | { | |
639 | if (spi_controller_is_slave(p->master)) { | |
640 | if (wait_for_completion_interruptible(&p->done) || | |
641 | p->slave_aborted) { | |
642 | dev_dbg(&p->pdev->dev, "interrupted\n"); | |
643 | return -EINTR; | |
644 | } | |
645 | } else { | |
646 | if (!wait_for_completion_timeout(&p->done, HZ)) { | |
647 | dev_err(&p->pdev->dev, "timeout\n"); | |
648 | return -ETIMEDOUT; | |
649 | } | |
650 | } | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
8051effc MD |
655 | static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, |
656 | void (*tx_fifo)(struct sh_msiof_spi_priv *, | |
657 | const void *, int, int), | |
658 | void (*rx_fifo)(struct sh_msiof_spi_priv *, | |
659 | void *, int, int), | |
660 | const void *tx_buf, void *rx_buf, | |
661 | int words, int bits) | |
662 | { | |
663 | int fifo_shift; | |
664 | int ret; | |
665 | ||
666 | /* limit maximum word transfer to rx/tx fifo size */ | |
667 | if (tx_buf) | |
668 | words = min_t(int, words, p->tx_fifo_size); | |
669 | if (rx_buf) | |
670 | words = min_t(int, words, p->rx_fifo_size); | |
671 | ||
672 | /* the fifo contents need shifting */ | |
673 | fifo_shift = 32 - bits; | |
674 | ||
b0d0ce8b GU |
675 | /* default FIFO watermarks for PIO */ |
676 | sh_msiof_write(p, FCTR, 0); | |
677 | ||
8051effc MD |
678 | /* setup msiof transfer mode registers */ |
679 | sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); | |
b0d0ce8b | 680 | sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE); |
8051effc MD |
681 | |
682 | /* write tx fifo */ | |
683 | if (tx_buf) | |
684 | tx_fifo(p, tx_buf, words, fifo_shift); | |
685 | ||
16735d02 | 686 | reinit_completion(&p->done); |
cf9e4784 | 687 | p->slave_aborted = false; |
76c02e71 GU |
688 | |
689 | ret = sh_msiof_spi_start(p, rx_buf); | |
8051effc MD |
690 | if (ret) { |
691 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
75b82e23 | 692 | goto stop_ier; |
8051effc MD |
693 | } |
694 | ||
695 | /* wait for tx fifo to be emptied / rx fifo to be filled */ | |
cf9e4784 HN |
696 | ret = sh_msiof_wait_for_completion(p); |
697 | if (ret) | |
75b82e23 | 698 | goto stop_reset; |
8051effc MD |
699 | |
700 | /* read rx fifo */ | |
701 | if (rx_buf) | |
702 | rx_fifo(p, rx_buf, words, fifo_shift); | |
703 | ||
704 | /* clear status bits */ | |
705 | sh_msiof_reset_str(p); | |
706 | ||
76c02e71 | 707 | ret = sh_msiof_spi_stop(p, rx_buf); |
8051effc MD |
708 | if (ret) { |
709 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
75b82e23 | 710 | return ret; |
8051effc MD |
711 | } |
712 | ||
713 | return words; | |
714 | ||
75b82e23 GU |
715 | stop_reset: |
716 | sh_msiof_reset_str(p); | |
717 | sh_msiof_spi_stop(p, rx_buf); | |
718 | stop_ier: | |
8051effc MD |
719 | sh_msiof_write(p, IER, 0); |
720 | return ret; | |
721 | } | |
722 | ||
b0d0ce8b GU |
723 | static void sh_msiof_dma_complete(void *arg) |
724 | { | |
725 | struct sh_msiof_spi_priv *p = arg; | |
726 | ||
727 | sh_msiof_write(p, IER, 0); | |
728 | complete(&p->done); | |
729 | } | |
730 | ||
731 | static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, | |
732 | void *rx, unsigned int len) | |
733 | { | |
734 | u32 ier_bits = 0; | |
735 | struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; | |
736 | dma_cookie_t cookie; | |
737 | int ret; | |
738 | ||
3e81b592 | 739 | /* First prepare and submit the DMA request(s), as this may fail */ |
b0d0ce8b GU |
740 | if (rx) { |
741 | ier_bits |= IER_RDREQE | IER_RDMAE; | |
742 | desc_rx = dmaengine_prep_slave_single(p->master->dma_rx, | |
743 | p->rx_dma_addr, len, DMA_FROM_DEVICE, | |
744 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
a5e7c719 GU |
745 | if (!desc_rx) |
746 | return -EAGAIN; | |
b0d0ce8b | 747 | |
b0d0ce8b GU |
748 | desc_rx->callback = sh_msiof_dma_complete; |
749 | desc_rx->callback_param = p; | |
750 | cookie = dmaengine_submit(desc_rx); | |
a5e7c719 GU |
751 | if (dma_submit_error(cookie)) |
752 | return cookie; | |
b0d0ce8b GU |
753 | } |
754 | ||
755 | if (tx) { | |
3e81b592 GU |
756 | ier_bits |= IER_TDREQE | IER_TDMAE; |
757 | dma_sync_single_for_device(p->master->dma_tx->device->dev, | |
758 | p->tx_dma_addr, len, DMA_TO_DEVICE); | |
759 | desc_tx = dmaengine_prep_slave_single(p->master->dma_tx, | |
760 | p->tx_dma_addr, len, DMA_TO_DEVICE, | |
761 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
762 | if (!desc_tx) { | |
763 | ret = -EAGAIN; | |
764 | goto no_dma_tx; | |
765 | } | |
766 | ||
b0d0ce8b GU |
767 | if (rx) { |
768 | /* No callback */ | |
769 | desc_tx->callback = NULL; | |
770 | } else { | |
771 | desc_tx->callback = sh_msiof_dma_complete; | |
772 | desc_tx->callback_param = p; | |
773 | } | |
774 | cookie = dmaengine_submit(desc_tx); | |
775 | if (dma_submit_error(cookie)) { | |
776 | ret = cookie; | |
3e81b592 | 777 | goto no_dma_tx; |
b0d0ce8b | 778 | } |
b0d0ce8b GU |
779 | } |
780 | ||
3e81b592 GU |
781 | /* 1 stage FIFO watermarks for DMA */ |
782 | sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1); | |
783 | ||
784 | /* setup msiof transfer mode registers (32-bit words) */ | |
785 | sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); | |
786 | ||
787 | sh_msiof_write(p, IER, ier_bits); | |
788 | ||
789 | reinit_completion(&p->done); | |
cf9e4784 | 790 | p->slave_aborted = false; |
3e81b592 GU |
791 | |
792 | /* Now start DMA */ | |
3e81b592 | 793 | if (rx) |
7a9f957b GU |
794 | dma_async_issue_pending(p->master->dma_rx); |
795 | if (tx) | |
3e81b592 GU |
796 | dma_async_issue_pending(p->master->dma_tx); |
797 | ||
b0d0ce8b GU |
798 | ret = sh_msiof_spi_start(p, rx); |
799 | if (ret) { | |
800 | dev_err(&p->pdev->dev, "failed to start hardware\n"); | |
3e81b592 | 801 | goto stop_dma; |
b0d0ce8b GU |
802 | } |
803 | ||
ab2f094c | 804 | /* wait for tx/rx DMA completion */ |
cf9e4784 HN |
805 | ret = sh_msiof_wait_for_completion(p); |
806 | if (ret) | |
b0d0ce8b | 807 | goto stop_reset; |
b0d0ce8b | 808 | |
ab2f094c GU |
809 | if (!rx) { |
810 | reinit_completion(&p->done); | |
811 | sh_msiof_write(p, IER, IER_TEOFE); | |
812 | ||
813 | /* wait for tx fifo to be emptied */ | |
814 | ret = sh_msiof_wait_for_completion(p); | |
815 | if (ret) | |
816 | goto stop_reset; | |
817 | } | |
818 | ||
b0d0ce8b GU |
819 | /* clear status bits */ |
820 | sh_msiof_reset_str(p); | |
821 | ||
822 | ret = sh_msiof_spi_stop(p, rx); | |
823 | if (ret) { | |
824 | dev_err(&p->pdev->dev, "failed to shut down hardware\n"); | |
825 | return ret; | |
826 | } | |
827 | ||
828 | if (rx) | |
5dabcf2f GU |
829 | dma_sync_single_for_cpu(p->master->dma_rx->device->dev, |
830 | p->rx_dma_addr, len, | |
b0d0ce8b GU |
831 | DMA_FROM_DEVICE); |
832 | ||
833 | return 0; | |
834 | ||
835 | stop_reset: | |
836 | sh_msiof_reset_str(p); | |
837 | sh_msiof_spi_stop(p, rx); | |
3e81b592 | 838 | stop_dma: |
b0d0ce8b GU |
839 | if (tx) |
840 | dmaengine_terminate_all(p->master->dma_tx); | |
3e81b592 | 841 | no_dma_tx: |
b0d0ce8b GU |
842 | if (rx) |
843 | dmaengine_terminate_all(p->master->dma_rx); | |
b0d0ce8b GU |
844 | sh_msiof_write(p, IER, 0); |
845 | return ret; | |
846 | } | |
847 | ||
848 | static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) | |
849 | { | |
850 | /* src or dst can be unaligned, but not both */ | |
851 | if ((unsigned long)src & 3) { | |
852 | while (words--) { | |
853 | *dst++ = swab32(get_unaligned(src)); | |
854 | src++; | |
855 | } | |
856 | } else if ((unsigned long)dst & 3) { | |
857 | while (words--) { | |
858 | put_unaligned(swab32(*src++), dst); | |
859 | dst++; | |
860 | } | |
861 | } else { | |
862 | while (words--) | |
863 | *dst++ = swab32(*src++); | |
864 | } | |
865 | } | |
866 | ||
867 | static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) | |
868 | { | |
869 | /* src or dst can be unaligned, but not both */ | |
870 | if ((unsigned long)src & 3) { | |
871 | while (words--) { | |
872 | *dst++ = swahw32(get_unaligned(src)); | |
873 | src++; | |
874 | } | |
875 | } else if ((unsigned long)dst & 3) { | |
876 | while (words--) { | |
877 | put_unaligned(swahw32(*src++), dst); | |
878 | dst++; | |
879 | } | |
880 | } else { | |
881 | while (words--) | |
882 | *dst++ = swahw32(*src++); | |
883 | } | |
884 | } | |
885 | ||
886 | static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) | |
887 | { | |
888 | memcpy(dst, src, words * 4); | |
889 | } | |
890 | ||
1bd6363b GU |
891 | static int sh_msiof_transfer_one(struct spi_master *master, |
892 | struct spi_device *spi, | |
893 | struct spi_transfer *t) | |
8051effc | 894 | { |
1bd6363b | 895 | struct sh_msiof_spi_priv *p = spi_master_get_devdata(master); |
b0d0ce8b | 896 | void (*copy32)(u32 *, const u32 *, unsigned int); |
8051effc MD |
897 | void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); |
898 | void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); | |
0312d591 GU |
899 | const void *tx_buf = t->tx_buf; |
900 | void *rx_buf = t->rx_buf; | |
901 | unsigned int len = t->len; | |
902 | unsigned int bits = t->bits_per_word; | |
903 | unsigned int bytes_per_word; | |
904 | unsigned int words; | |
8051effc | 905 | int n; |
9dabb3f3 | 906 | bool swab; |
b0d0ce8b GU |
907 | int ret; |
908 | ||
909 | /* setup clocks (clock already enabled in chipselect()) */ | |
cf9e4784 HN |
910 | if (!spi_controller_is_slave(p->master)) |
911 | sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz); | |
b0d0ce8b GU |
912 | |
913 | while (master->dma_tx && len > 15) { | |
914 | /* | |
915 | * DMA supports 32-bit words only, hence pack 8-bit and 16-bit | |
916 | * words, with byte resp. word swapping. | |
917 | */ | |
fe78d0b7 KM |
918 | unsigned int l = 0; |
919 | ||
920 | if (tx_buf) | |
921 | l = min(len, p->tx_fifo_size * 4); | |
922 | if (rx_buf) | |
923 | l = min(len, p->rx_fifo_size * 4); | |
b0d0ce8b GU |
924 | |
925 | if (bits <= 8) { | |
926 | if (l & 3) | |
927 | break; | |
928 | copy32 = copy_bswap32; | |
929 | } else if (bits <= 16) { | |
36735783 | 930 | if (l & 3) |
b0d0ce8b GU |
931 | break; |
932 | copy32 = copy_wswap32; | |
933 | } else { | |
934 | copy32 = copy_plain32; | |
935 | } | |
936 | ||
937 | if (tx_buf) | |
938 | copy32(p->tx_dma_page, tx_buf, l / 4); | |
8051effc | 939 | |
b0d0ce8b | 940 | ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); |
279d2378 GU |
941 | if (ret == -EAGAIN) { |
942 | pr_warn_once("%s %s: DMA not available, falling back to PIO\n", | |
943 | dev_driver_string(&p->pdev->dev), | |
944 | dev_name(&p->pdev->dev)); | |
945 | break; | |
946 | } | |
b0d0ce8b GU |
947 | if (ret) |
948 | return ret; | |
949 | ||
950 | if (rx_buf) { | |
951 | copy32(rx_buf, p->rx_dma_page, l / 4); | |
952 | rx_buf += l; | |
953 | } | |
954 | if (tx_buf) | |
955 | tx_buf += l; | |
956 | ||
957 | len -= l; | |
958 | if (!len) | |
959 | return 0; | |
960 | } | |
8051effc | 961 | |
0312d591 | 962 | if (bits <= 8 && len > 15 && !(len & 3)) { |
9dabb3f3 GL |
963 | bits = 32; |
964 | swab = true; | |
965 | } else { | |
966 | swab = false; | |
967 | } | |
968 | ||
8051effc MD |
969 | /* setup bytes per word and fifo read/write functions */ |
970 | if (bits <= 8) { | |
971 | bytes_per_word = 1; | |
972 | tx_fifo = sh_msiof_spi_write_fifo_8; | |
973 | rx_fifo = sh_msiof_spi_read_fifo_8; | |
974 | } else if (bits <= 16) { | |
975 | bytes_per_word = 2; | |
0312d591 | 976 | if ((unsigned long)tx_buf & 0x01) |
8051effc MD |
977 | tx_fifo = sh_msiof_spi_write_fifo_16u; |
978 | else | |
979 | tx_fifo = sh_msiof_spi_write_fifo_16; | |
980 | ||
0312d591 | 981 | if ((unsigned long)rx_buf & 0x01) |
8051effc MD |
982 | rx_fifo = sh_msiof_spi_read_fifo_16u; |
983 | else | |
984 | rx_fifo = sh_msiof_spi_read_fifo_16; | |
9dabb3f3 GL |
985 | } else if (swab) { |
986 | bytes_per_word = 4; | |
0312d591 | 987 | if ((unsigned long)tx_buf & 0x03) |
9dabb3f3 GL |
988 | tx_fifo = sh_msiof_spi_write_fifo_s32u; |
989 | else | |
990 | tx_fifo = sh_msiof_spi_write_fifo_s32; | |
991 | ||
0312d591 | 992 | if ((unsigned long)rx_buf & 0x03) |
9dabb3f3 GL |
993 | rx_fifo = sh_msiof_spi_read_fifo_s32u; |
994 | else | |
995 | rx_fifo = sh_msiof_spi_read_fifo_s32; | |
8051effc MD |
996 | } else { |
997 | bytes_per_word = 4; | |
0312d591 | 998 | if ((unsigned long)tx_buf & 0x03) |
8051effc MD |
999 | tx_fifo = sh_msiof_spi_write_fifo_32u; |
1000 | else | |
1001 | tx_fifo = sh_msiof_spi_write_fifo_32; | |
1002 | ||
0312d591 | 1003 | if ((unsigned long)rx_buf & 0x03) |
8051effc MD |
1004 | rx_fifo = sh_msiof_spi_read_fifo_32u; |
1005 | else | |
1006 | rx_fifo = sh_msiof_spi_read_fifo_32; | |
1007 | } | |
1008 | ||
8051effc | 1009 | /* transfer in fifo sized chunks */ |
0312d591 GU |
1010 | words = len / bytes_per_word; |
1011 | ||
1012 | while (words > 0) { | |
1013 | n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, | |
8051effc MD |
1014 | words, bits); |
1015 | if (n < 0) | |
75b82e23 | 1016 | return n; |
8051effc | 1017 | |
0312d591 GU |
1018 | if (tx_buf) |
1019 | tx_buf += n * bytes_per_word; | |
1020 | if (rx_buf) | |
1021 | rx_buf += n * bytes_per_word; | |
8051effc MD |
1022 | words -= n; |
1023 | } | |
1024 | ||
8051effc MD |
1025 | return 0; |
1026 | } | |
1027 | ||
50a7e23f GU |
1028 | static const struct sh_msiof_chipdata sh_data = { |
1029 | .tx_fifo_size = 64, | |
1030 | .rx_fifo_size = 64, | |
beb74bb0 | 1031 | .master_flags = 0, |
61a8dec5 GU |
1032 | .min_div = 1, |
1033 | }; | |
1034 | ||
1035 | static const struct sh_msiof_chipdata rcar_gen2_data = { | |
1036 | .tx_fifo_size = 64, | |
1037 | .rx_fifo_size = 64, | |
1038 | .master_flags = SPI_MASTER_MUST_TX, | |
1039 | .min_div = 1, | |
beb74bb0 GU |
1040 | }; |
1041 | ||
61a8dec5 | 1042 | static const struct sh_msiof_chipdata rcar_gen3_data = { |
beb74bb0 | 1043 | .tx_fifo_size = 64, |
fe78d0b7 | 1044 | .rx_fifo_size = 64, |
beb74bb0 | 1045 | .master_flags = SPI_MASTER_MUST_TX, |
61a8dec5 | 1046 | .min_div = 2, |
50a7e23f GU |
1047 | }; |
1048 | ||
1049 | static const struct of_device_id sh_msiof_match[] = { | |
50a7e23f | 1050 | { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, |
bdacfc7b FC |
1051 | { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data }, |
1052 | { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data }, | |
61a8dec5 GU |
1053 | { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data }, |
1054 | { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data }, | |
1055 | { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data }, | |
1056 | { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data }, | |
1057 | { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data }, | |
1058 | { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data }, | |
1059 | { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data }, | |
1060 | { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data }, | |
264c3e8d | 1061 | { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */ |
50a7e23f GU |
1062 | {}, |
1063 | }; | |
1064 | MODULE_DEVICE_TABLE(of, sh_msiof_match); | |
1065 | ||
cf9c86ef BH |
1066 | #ifdef CONFIG_OF |
1067 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
1068 | { | |
1069 | struct sh_msiof_spi_info *info; | |
1070 | struct device_node *np = dev->of_node; | |
32d3b2d1 | 1071 | u32 num_cs = 1; |
cf9c86ef BH |
1072 | |
1073 | info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); | |
1e8231b7 | 1074 | if (!info) |
cf9c86ef | 1075 | return NULL; |
cf9c86ef | 1076 | |
cf9e4784 HN |
1077 | info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE |
1078 | : MSIOF_SPI_MASTER; | |
1079 | ||
cf9c86ef | 1080 | /* Parse the MSIOF properties */ |
cf9e4784 HN |
1081 | if (info->mode == MSIOF_SPI_MASTER) |
1082 | of_property_read_u32(np, "num-cs", &num_cs); | |
cf9c86ef BH |
1083 | of_property_read_u32(np, "renesas,tx-fifo-size", |
1084 | &info->tx_fifo_override); | |
1085 | of_property_read_u32(np, "renesas,rx-fifo-size", | |
1086 | &info->rx_fifo_override); | |
3110628d YS |
1087 | of_property_read_u32(np, "renesas,dtdl", &info->dtdl); |
1088 | of_property_read_u32(np, "renesas,syncdl", &info->syncdl); | |
cf9c86ef BH |
1089 | |
1090 | info->num_chipselect = num_cs; | |
1091 | ||
1092 | return info; | |
1093 | } | |
1094 | #else | |
1095 | static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) | |
1096 | { | |
1097 | return NULL; | |
1098 | } | |
1099 | #endif | |
1100 | ||
b0d0ce8b GU |
1101 | static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, |
1102 | enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) | |
1103 | { | |
1104 | dma_cap_mask_t mask; | |
1105 | struct dma_chan *chan; | |
1106 | struct dma_slave_config cfg; | |
1107 | int ret; | |
1108 | ||
1109 | dma_cap_zero(mask); | |
1110 | dma_cap_set(DMA_SLAVE, mask); | |
1111 | ||
a6be4de6 GU |
1112 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, |
1113 | (void *)(unsigned long)id, dev, | |
1114 | dir == DMA_MEM_TO_DEV ? "tx" : "rx"); | |
b0d0ce8b | 1115 | if (!chan) { |
a6be4de6 | 1116 | dev_warn(dev, "dma_request_slave_channel_compat failed\n"); |
b0d0ce8b GU |
1117 | return NULL; |
1118 | } | |
1119 | ||
1120 | memset(&cfg, 0, sizeof(cfg)); | |
b0d0ce8b | 1121 | cfg.direction = dir; |
52fba2b8 | 1122 | if (dir == DMA_MEM_TO_DEV) { |
b0d0ce8b | 1123 | cfg.dst_addr = port_addr; |
52fba2b8 GU |
1124 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
1125 | } else { | |
b0d0ce8b | 1126 | cfg.src_addr = port_addr; |
52fba2b8 GU |
1127 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; |
1128 | } | |
b0d0ce8b GU |
1129 | |
1130 | ret = dmaengine_slave_config(chan, &cfg); | |
1131 | if (ret) { | |
1132 | dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); | |
1133 | dma_release_channel(chan); | |
1134 | return NULL; | |
1135 | } | |
1136 | ||
1137 | return chan; | |
1138 | } | |
1139 | ||
1140 | static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) | |
1141 | { | |
1142 | struct platform_device *pdev = p->pdev; | |
1143 | struct device *dev = &pdev->dev; | |
1144 | const struct sh_msiof_spi_info *info = dev_get_platdata(dev); | |
a6be4de6 | 1145 | unsigned int dma_tx_id, dma_rx_id; |
b0d0ce8b GU |
1146 | const struct resource *res; |
1147 | struct spi_master *master; | |
5dabcf2f | 1148 | struct device *tx_dev, *rx_dev; |
b0d0ce8b | 1149 | |
a6be4de6 GU |
1150 | if (dev->of_node) { |
1151 | /* In the OF case we will get the slave IDs from the DT */ | |
1152 | dma_tx_id = 0; | |
1153 | dma_rx_id = 0; | |
1154 | } else if (info && info->dma_tx_id && info->dma_rx_id) { | |
1155 | dma_tx_id = info->dma_tx_id; | |
1156 | dma_rx_id = info->dma_rx_id; | |
1157 | } else { | |
1158 | /* The driver assumes no error */ | |
1159 | return 0; | |
1160 | } | |
b0d0ce8b GU |
1161 | |
1162 | /* The DMA engine uses the second register set, if present */ | |
1163 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1164 | if (!res) | |
1165 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1166 | ||
1167 | master = p->master; | |
1168 | master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, | |
a6be4de6 | 1169 | dma_tx_id, |
b0d0ce8b GU |
1170 | res->start + TFDR); |
1171 | if (!master->dma_tx) | |
1172 | return -ENODEV; | |
1173 | ||
1174 | master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, | |
a6be4de6 | 1175 | dma_rx_id, |
b0d0ce8b GU |
1176 | res->start + RFDR); |
1177 | if (!master->dma_rx) | |
1178 | goto free_tx_chan; | |
1179 | ||
1180 | p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
1181 | if (!p->tx_dma_page) | |
1182 | goto free_rx_chan; | |
1183 | ||
1184 | p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); | |
1185 | if (!p->rx_dma_page) | |
1186 | goto free_tx_page; | |
1187 | ||
5dabcf2f GU |
1188 | tx_dev = master->dma_tx->device->dev; |
1189 | p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, | |
b0d0ce8b | 1190 | DMA_TO_DEVICE); |
5dabcf2f | 1191 | if (dma_mapping_error(tx_dev, p->tx_dma_addr)) |
b0d0ce8b GU |
1192 | goto free_rx_page; |
1193 | ||
5dabcf2f GU |
1194 | rx_dev = master->dma_rx->device->dev; |
1195 | p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, | |
b0d0ce8b | 1196 | DMA_FROM_DEVICE); |
5dabcf2f | 1197 | if (dma_mapping_error(rx_dev, p->rx_dma_addr)) |
b0d0ce8b GU |
1198 | goto unmap_tx_page; |
1199 | ||
1200 | dev_info(dev, "DMA available"); | |
1201 | return 0; | |
1202 | ||
1203 | unmap_tx_page: | |
5dabcf2f | 1204 | dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); |
b0d0ce8b GU |
1205 | free_rx_page: |
1206 | free_page((unsigned long)p->rx_dma_page); | |
1207 | free_tx_page: | |
1208 | free_page((unsigned long)p->tx_dma_page); | |
1209 | free_rx_chan: | |
1210 | dma_release_channel(master->dma_rx); | |
1211 | free_tx_chan: | |
1212 | dma_release_channel(master->dma_tx); | |
1213 | master->dma_tx = NULL; | |
1214 | return -ENODEV; | |
1215 | } | |
1216 | ||
1217 | static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) | |
1218 | { | |
1219 | struct spi_master *master = p->master; | |
b0d0ce8b GU |
1220 | |
1221 | if (!master->dma_tx) | |
1222 | return; | |
1223 | ||
5dabcf2f GU |
1224 | dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr, |
1225 | PAGE_SIZE, DMA_FROM_DEVICE); | |
1226 | dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr, | |
1227 | PAGE_SIZE, DMA_TO_DEVICE); | |
b0d0ce8b GU |
1228 | free_page((unsigned long)p->rx_dma_page); |
1229 | free_page((unsigned long)p->tx_dma_page); | |
1230 | dma_release_channel(master->dma_rx); | |
1231 | dma_release_channel(master->dma_tx); | |
1232 | } | |
1233 | ||
8051effc MD |
1234 | static int sh_msiof_spi_probe(struct platform_device *pdev) |
1235 | { | |
1236 | struct resource *r; | |
1237 | struct spi_master *master; | |
a6802cc0 | 1238 | const struct sh_msiof_chipdata *chipdata; |
cf9e4784 | 1239 | struct sh_msiof_spi_info *info; |
8051effc | 1240 | struct sh_msiof_spi_priv *p; |
8051effc MD |
1241 | int i; |
1242 | int ret; | |
1243 | ||
ecb1596a GU |
1244 | chipdata = of_device_get_match_data(&pdev->dev); |
1245 | if (chipdata) { | |
cf9e4784 | 1246 | info = sh_msiof_spi_parse_dt(&pdev->dev); |
50a7e23f | 1247 | } else { |
a6802cc0 | 1248 | chipdata = (const void *)pdev->id_entry->driver_data; |
cf9e4784 | 1249 | info = dev_get_platdata(&pdev->dev); |
50a7e23f | 1250 | } |
cf9c86ef | 1251 | |
cf9e4784 | 1252 | if (!info) { |
cf9c86ef | 1253 | dev_err(&pdev->dev, "failed to obtain device info\n"); |
cf9e4784 | 1254 | return -ENXIO; |
cf9c86ef BH |
1255 | } |
1256 | ||
cf9e4784 HN |
1257 | if (info->mode == MSIOF_SPI_SLAVE) |
1258 | master = spi_alloc_slave(&pdev->dev, | |
1259 | sizeof(struct sh_msiof_spi_priv)); | |
1260 | else | |
1261 | master = spi_alloc_master(&pdev->dev, | |
1262 | sizeof(struct sh_msiof_spi_priv)); | |
1263 | if (master == NULL) | |
1264 | return -ENOMEM; | |
1265 | ||
1266 | p = spi_master_get_devdata(master); | |
1267 | ||
1268 | platform_set_drvdata(pdev, p); | |
1269 | p->master = master; | |
1270 | p->info = info; | |
61a8dec5 | 1271 | p->min_div = chipdata->min_div; |
cf9e4784 | 1272 | |
8051effc MD |
1273 | init_completion(&p->done); |
1274 | ||
b4dd05de | 1275 | p->clk = devm_clk_get(&pdev->dev, NULL); |
8051effc | 1276 | if (IS_ERR(p->clk)) { |
078b6ead | 1277 | dev_err(&pdev->dev, "cannot get clock\n"); |
8051effc MD |
1278 | ret = PTR_ERR(p->clk); |
1279 | goto err1; | |
1280 | } | |
1281 | ||
8051effc | 1282 | i = platform_get_irq(pdev, 0); |
b4dd05de | 1283 | if (i < 0) { |
3b788b1c SS |
1284 | dev_err(&pdev->dev, "cannot get IRQ\n"); |
1285 | ret = i; | |
b4dd05de | 1286 | goto err1; |
8051effc | 1287 | } |
b4dd05de LP |
1288 | |
1289 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1290 | p->mapbase = devm_ioremap_resource(&pdev->dev, r); | |
1291 | if (IS_ERR(p->mapbase)) { | |
1292 | ret = PTR_ERR(p->mapbase); | |
1293 | goto err1; | |
8051effc MD |
1294 | } |
1295 | ||
b4dd05de LP |
1296 | ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, |
1297 | dev_name(&pdev->dev), p); | |
8051effc MD |
1298 | if (ret) { |
1299 | dev_err(&pdev->dev, "unable to request irq\n"); | |
b4dd05de | 1300 | goto err1; |
8051effc MD |
1301 | } |
1302 | ||
1303 | p->pdev = pdev; | |
1304 | pm_runtime_enable(&pdev->dev); | |
1305 | ||
8051effc | 1306 | /* Platform data may override FIFO sizes */ |
a6802cc0 GU |
1307 | p->tx_fifo_size = chipdata->tx_fifo_size; |
1308 | p->rx_fifo_size = chipdata->rx_fifo_size; | |
8051effc MD |
1309 | if (p->info->tx_fifo_override) |
1310 | p->tx_fifo_size = p->info->tx_fifo_override; | |
1311 | if (p->info->rx_fifo_override) | |
1312 | p->rx_fifo_size = p->info->rx_fifo_override; | |
1313 | ||
1bd6363b | 1314 | /* init master code */ |
8051effc MD |
1315 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; |
1316 | master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; | |
a6802cc0 | 1317 | master->flags = chipdata->master_flags; |
8051effc | 1318 | master->bus_num = pdev->id; |
f7c05e83 | 1319 | master->dev.of_node = pdev->dev.of_node; |
8051effc | 1320 | master->num_chipselect = p->info->num_chipselect; |
8d19534a | 1321 | master->setup = sh_msiof_spi_setup; |
c833ff73 | 1322 | master->prepare_message = sh_msiof_prepare_message; |
cf9e4784 | 1323 | master->slave_abort = sh_msiof_slave_abort; |
2416289c | 1324 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32); |
e2a0ba54 | 1325 | master->auto_runtime_pm = true; |
1bd6363b | 1326 | master->transfer_one = sh_msiof_transfer_one; |
8051effc | 1327 | |
b0d0ce8b GU |
1328 | ret = sh_msiof_request_dma(p); |
1329 | if (ret < 0) | |
1330 | dev_warn(&pdev->dev, "DMA not available, using PIO\n"); | |
1331 | ||
1bd6363b GU |
1332 | ret = devm_spi_register_master(&pdev->dev, master); |
1333 | if (ret < 0) { | |
1334 | dev_err(&pdev->dev, "spi_register_master error.\n"); | |
1335 | goto err2; | |
1336 | } | |
8051effc | 1337 | |
1bd6363b | 1338 | return 0; |
8051effc | 1339 | |
1bd6363b | 1340 | err2: |
b0d0ce8b | 1341 | sh_msiof_release_dma(p); |
8051effc | 1342 | pm_runtime_disable(&pdev->dev); |
8051effc MD |
1343 | err1: |
1344 | spi_master_put(master); | |
8051effc MD |
1345 | return ret; |
1346 | } | |
1347 | ||
1348 | static int sh_msiof_spi_remove(struct platform_device *pdev) | |
1349 | { | |
b0d0ce8b GU |
1350 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); |
1351 | ||
1352 | sh_msiof_release_dma(p); | |
1bd6363b | 1353 | pm_runtime_disable(&pdev->dev); |
1bd6363b | 1354 | return 0; |
8051effc MD |
1355 | } |
1356 | ||
3789c852 | 1357 | static const struct platform_device_id spi_driver_ids[] = { |
50a7e23f | 1358 | { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, |
cf9c86ef BH |
1359 | {}, |
1360 | }; | |
50a7e23f | 1361 | MODULE_DEVICE_TABLE(platform, spi_driver_ids); |
cf9c86ef | 1362 | |
9e4219ff GI |
1363 | #ifdef CONFIG_PM_SLEEP |
1364 | static int sh_msiof_spi_suspend(struct device *dev) | |
1365 | { | |
1366 | struct platform_device *pdev = to_platform_device(dev); | |
1367 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
1368 | ||
1369 | return spi_master_suspend(p->master); | |
1370 | } | |
1371 | ||
1372 | static int sh_msiof_spi_resume(struct device *dev) | |
1373 | { | |
1374 | struct platform_device *pdev = to_platform_device(dev); | |
1375 | struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); | |
1376 | ||
1377 | return spi_master_resume(p->master); | |
1378 | } | |
1379 | ||
1380 | static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend, | |
1381 | sh_msiof_spi_resume); | |
1382 | #define DEV_PM_OPS &sh_msiof_spi_pm_ops | |
1383 | #else | |
1384 | #define DEV_PM_OPS NULL | |
1385 | #endif /* CONFIG_PM_SLEEP */ | |
1386 | ||
8051effc MD |
1387 | static struct platform_driver sh_msiof_spi_drv = { |
1388 | .probe = sh_msiof_spi_probe, | |
1389 | .remove = sh_msiof_spi_remove, | |
50a7e23f | 1390 | .id_table = spi_driver_ids, |
8051effc MD |
1391 | .driver = { |
1392 | .name = "spi_sh_msiof", | |
9e4219ff | 1393 | .pm = DEV_PM_OPS, |
691ee4ed | 1394 | .of_match_table = of_match_ptr(sh_msiof_match), |
8051effc MD |
1395 | }, |
1396 | }; | |
940ab889 | 1397 | module_platform_driver(sh_msiof_spi_drv); |
8051effc MD |
1398 | |
1399 | MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver"); | |
1400 | MODULE_AUTHOR("Magnus Damm"); | |
1401 | MODULE_LICENSE("GPL v2"); | |
1402 | MODULE_ALIAS("platform:spi_sh_msiof"); |