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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mattst88...
[mirror_ubuntu-zesty-kernel.git] / drivers / spi / spi-sirf.c
CommitLineData
1cc2df9d
ZS		 1/*
2 * SPI bus driver for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/clk.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/of.h>
16#include <linux/bitops.h>
17#include <linux/err.h>
18#include <linux/platform_device.h>
19#include <linux/of_gpio.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/spi_bitbang.h>
de39f5fa
BS		 22#include <linux/dmaengine.h>
23#include <linux/dma-direction.h>
24#include <linux/dma-mapping.h>
25#include <linux/sirfsoc_dma.h>
1cc2df9d
ZS		 26
27#define DRIVER_NAME "sirfsoc_spi"
28
29#define SIRFSOC_SPI_CTRL 0x0000
30#define SIRFSOC_SPI_CMD 0x0004
31#define SIRFSOC_SPI_TX_RX_EN 0x0008
32#define SIRFSOC_SPI_INT_EN 0x000C
33#define SIRFSOC_SPI_INT_STATUS 0x0010
34#define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100
35#define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104
36#define SIRFSOC_SPI_TXFIFO_CTRL 0x0108
37#define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C
38#define SIRFSOC_SPI_TXFIFO_OP 0x0110
39#define SIRFSOC_SPI_TXFIFO_STATUS 0x0114
40#define SIRFSOC_SPI_TXFIFO_DATA 0x0118
41#define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120
42#define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124
43#define SIRFSOC_SPI_RXFIFO_CTRL 0x0128
44#define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C
45#define SIRFSOC_SPI_RXFIFO_OP 0x0130
46#define SIRFSOC_SPI_RXFIFO_STATUS 0x0134
47#define SIRFSOC_SPI_RXFIFO_DATA 0x0138
48#define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144
49
50/* SPI CTRL register defines */
51#define SIRFSOC_SPI_SLV_MODE BIT(16)
52#define SIRFSOC_SPI_CMD_MODE BIT(17)
53#define SIRFSOC_SPI_CS_IO_OUT BIT(18)
54#define SIRFSOC_SPI_CS_IO_MODE BIT(19)
55#define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20)
56#define SIRFSOC_SPI_CS_IDLE_STAT BIT(21)
57#define SIRFSOC_SPI_TRAN_MSB BIT(22)
58#define SIRFSOC_SPI_DRV_POS_EDGE BIT(23)
59#define SIRFSOC_SPI_CS_HOLD_TIME BIT(24)
60#define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25)
61#define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26)
62#define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26)
63#define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26)
64#define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26)
65#define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28)
66#define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30)
67#define SIRFSOC_SPI_MUL_DAT_MODE BIT(31)
68
69/* Interrupt Enable */
70#define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0)
71#define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1)
72#define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2)
73#define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3)
74#define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4)
75#define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5)
76#define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6)
77#define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
78#define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8)
79#define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9)
80#define SIRFSOC_SPI_FRM_END_INT_EN BIT(10)
81
82#define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF
83
84/* Interrupt status */
85#define SIRFSOC_SPI_RX_DONE BIT(0)
86#define SIRFSOC_SPI_TX_DONE BIT(1)
87#define SIRFSOC_SPI_RX_OFLOW BIT(2)
88#define SIRFSOC_SPI_TX_UFLOW BIT(3)
89#define SIRFSOC_SPI_RX_FIFO_FULL BIT(6)
90#define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7)
91#define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8)
92#define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9)
93#define SIRFSOC_SPI_FRM_END BIT(10)
94
95/* TX RX enable */
96#define SIRFSOC_SPI_RX_EN BIT(0)
97#define SIRFSOC_SPI_TX_EN BIT(1)
98#define SIRFSOC_SPI_CMD_TX_EN BIT(2)
99
100#define SIRFSOC_SPI_IO_MODE_SEL BIT(0)
101#define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2)
102
103/* FIFO OPs */
104#define SIRFSOC_SPI_FIFO_RESET BIT(0)
105#define SIRFSOC_SPI_FIFO_START BIT(1)
106
107/* FIFO CTRL */
108#define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0)
109#define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0)
110#define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0)
111
112/* FIFO Status */
113#define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF
114#define SIRFSOC_SPI_FIFO_FULL BIT(8)
115#define SIRFSOC_SPI_FIFO_EMPTY BIT(9)
116
117/* 256 bytes rx/tx FIFO */
118#define SIRFSOC_SPI_FIFO_SIZE 256
119#define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024)
120
121#define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F)
122#define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10)
123#define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20)
124#define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2)
125
de39f5fa
BS		 126/*
127 * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma
128 * due to the limitation of dma controller
129 */
130
131#define ALIGNED(x) (!((u32)x & 0x3))
132#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
692fb0fe 133 ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
de39f5fa 134
1cc2df9d
ZS		 135struct sirfsoc_spi {
136 struct spi_bitbang bitbang;
de39f5fa
BS		 137 struct completion rx_done;
138 struct completion tx_done;
1cc2df9d
ZS		 139
140 void __iomem *base;
141 u32 ctrl_freq; /* SPI controller clock speed */
142 struct clk *clk;
1cc2df9d
ZS		 143
144 /* rx & tx bufs from the spi_transfer */
145 const void *tx;
146 void *rx;
147
148 /* place received word into rx buffer */
149 void (*rx_word) (struct sirfsoc_spi *);
150 /* get word from tx buffer for sending */
151 void (*tx_word) (struct sirfsoc_spi *);
152
153 /* number of words left to be tranmitted/received */
692fb0fe
QL		 154 unsigned int left_tx_word;
155 unsigned int left_rx_word;
1cc2df9d 156
de39f5fa
BS		 157 /* rx & tx DMA channels */
158 struct dma_chan *rx_chan;
159 struct dma_chan *tx_chan;
160 dma_addr_t src_start;
161 dma_addr_t dst_start;
162 void *dummypage;
163 int word_width; /* in bytes */
1cc2df9d 164
1cc2df9d
ZS		 165 int chipselect[0];
166};
167
168static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
169{
170 u32 data;
171 u8 *rx = sspi->rx;
172
173 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
174
175 if (rx) {
176 *rx++ = (u8) data;
177 sspi->rx = rx;
178 }
179
692fb0fe 180 sspi->left_rx_word--;
1cc2df9d
ZS		 181}
182
183static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
184{
185 u32 data = 0;
186 const u8 *tx = sspi->tx;
187
188 if (tx) {
189 data = *tx++;
190 sspi->tx = tx;
191 }
192
193 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
692fb0fe 194 sspi->left_tx_word--;
1cc2df9d
ZS		 195}
196
197static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
198{
199 u32 data;
200 u16 *rx = sspi->rx;
201
202 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
203
204 if (rx) {
205 *rx++ = (u16) data;
206 sspi->rx = rx;
207 }
208
692fb0fe 209 sspi->left_rx_word--;
1cc2df9d
ZS		 210}
211
212static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
213{
214 u32 data = 0;
215 const u16 *tx = sspi->tx;
216
217 if (tx) {
218 data = *tx++;
219 sspi->tx = tx;
220 }
221
222 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
692fb0fe 223 sspi->left_tx_word--;
1cc2df9d
ZS		 224}
225
226static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
227{
228 u32 data;
229 u32 *rx = sspi->rx;
230
231 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
232
233 if (rx) {
234 *rx++ = (u32) data;
235 sspi->rx = rx;
236 }
237
692fb0fe 238 sspi->left_rx_word--;
1cc2df9d
ZS		 239
240}
241
242static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
243{
244 u32 data = 0;
245 const u32 *tx = sspi->tx;
246
247 if (tx) {
248 data = *tx++;
249 sspi->tx = tx;
250 }
251
252 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
692fb0fe 253 sspi->left_tx_word--;
1cc2df9d
ZS		 254}
255
1cc2df9d
ZS		 256static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
257{
258 struct sirfsoc_spi *sspi = dev_id;
259 u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
260
261 writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
262
263 /* Error Conditions */
264 if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
265 spi_stat & SIRFSOC_SPI_TX_UFLOW) {
de39f5fa 266 complete(&sspi->rx_done);
1cc2df9d
ZS		 267 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
268 }
269
237ce466
QL		 270 if (spi_stat & (SIRFSOC_SPI_FRM_END
271 | SIRFSOC_SPI_RXFIFO_THD_REACH))
1cc2df9d
ZS		 272 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
273 & SIRFSOC_SPI_FIFO_EMPTY)) &&
692fb0fe 274 sspi->left_rx_word)
1cc2df9d
ZS		 275 sspi->rx_word(sspi);
276
237ce466
QL		 277 if (spi_stat & (SIRFSOC_SPI_FIFO_EMPTY
278 | SIRFSOC_SPI_TXFIFO_THD_REACH))
279 while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS)
280 & SIRFSOC_SPI_FIFO_FULL)) &&
692fb0fe 281 sspi->left_tx_word)
237ce466 282 sspi->tx_word(sspi);
1cc2df9d 283
237ce466 284 /* Received all words */
692fb0fe 285 if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) {
de39f5fa 286 complete(&sspi->rx_done);
237ce466
QL		 287 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
288 }
1cc2df9d
ZS		 289 return IRQ_HANDLED;
290}
291
de39f5fa
BS		 292static void spi_sirfsoc_dma_fini_callback(void *data)
293{
294 struct completion *dma_complete = data;
295
296 complete(dma_complete);
297}
298
1cc2df9d
ZS		 299static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
300{
301 struct sirfsoc_spi *sspi;
302 int timeout = t->len * 10;
303 sspi = spi_master_get_devdata(spi->master);
304
de39f5fa
BS		 305 sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage;
306 sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage;
692fb0fe 307 sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width;
16735d02
WS		 308 reinit_completion(&sspi->rx_done);
309 reinit_completion(&sspi->tx_done);
1cc2df9d
ZS		 310
311 writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
312
692fb0fe 313 if (sspi->left_tx_word == 1) {
1cc2df9d
ZS		 314 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
315 SIRFSOC_SPI_ENA_AUTO_CLR,
316 sspi->base + SIRFSOC_SPI_CTRL);
317 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
318 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
692fb0fe
QL		 319 } else if ((sspi->left_tx_word > 1) && (sspi->left_tx_word <
320 SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
1cc2df9d
ZS		 321 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
322 SIRFSOC_SPI_MUL_DAT_MODE |
323 SIRFSOC_SPI_ENA_AUTO_CLR,
324 sspi->base + SIRFSOC_SPI_CTRL);
692fb0fe
QL		 325 writel(sspi->left_tx_word - 1,
326 sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
327 writel(sspi->left_tx_word - 1,
328 sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
1cc2df9d
ZS		 329 } else {
330 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
331 sspi->base + SIRFSOC_SPI_CTRL);
332 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
333 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
334 }
335
336 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
337 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
338 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
339 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
340
de39f5fa
BS		 341 if (IS_DMA_VALID(t)) {
342 struct dma_async_tx_descriptor *rx_desc, *tx_desc;
de39f5fa
BS		 343
344 sspi->dst_start = dma_map_single(&spi->dev, sspi->rx, t->len, DMA_FROM_DEVICE);
345 rx_desc = dmaengine_prep_slave_single(sspi->rx_chan,
692fb0fe 346 sspi->dst_start, t->len, DMA_DEV_TO_MEM,
de39f5fa
BS		 347 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
348 rx_desc->callback = spi_sirfsoc_dma_fini_callback;
349 rx_desc->callback_param = &sspi->rx_done;
350
351 sspi->src_start = dma_map_single(&spi->dev, (void *)sspi->tx, t->len, DMA_TO_DEVICE);
352 tx_desc = dmaengine_prep_slave_single(sspi->tx_chan,
692fb0fe 353 sspi->src_start, t->len, DMA_MEM_TO_DEV,
de39f5fa
BS		 354 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
355 tx_desc->callback = spi_sirfsoc_dma_fini_callback;
356 tx_desc->callback_param = &sspi->tx_done;
357
358 dmaengine_submit(tx_desc);
359 dmaengine_submit(rx_desc);
360 dma_async_issue_pending(sspi->tx_chan);
361 dma_async_issue_pending(sspi->rx_chan);
362 } else {
363 /* Send the first word to trigger the whole tx/rx process */
364 sspi->tx_word(sspi);
365
366 writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
367 SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
368 SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
369 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
370 }
1cc2df9d 371
1cc2df9d
ZS		 372 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
373
de39f5fa
BS		 374 if (!IS_DMA_VALID(t)) { /* for PIO */
375 if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0)
376 dev_err(&spi->dev, "transfer timeout\n");
377 } else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) {
1cc2df9d 378 dev_err(&spi->dev, "transfer timeout\n");
de39f5fa
BS		 379 dmaengine_terminate_all(sspi->rx_chan);
380 } else
692fb0fe 381 sspi->left_rx_word = 0;
de39f5fa
BS		 382
383 /*
384 * we only wait tx-done event if transferring by DMA. for PIO,
385 * we get rx data by writing tx data, so if rx is done, tx has
386 * done earlier
387 */
388 if (IS_DMA_VALID(t)) {
389 if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
390 dev_err(&spi->dev, "transfer timeout\n");
391 dmaengine_terminate_all(sspi->tx_chan);
392 }
393 }
394
395 if (IS_DMA_VALID(t)) {
396 dma_unmap_single(&spi->dev, sspi->src_start, t->len, DMA_TO_DEVICE);
397 dma_unmap_single(&spi->dev, sspi->dst_start, t->len, DMA_FROM_DEVICE);
398 }
1cc2df9d
ZS		 399
400 /* TX, RX FIFO stop */
401 writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
402 writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
403 writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
404 writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
405
692fb0fe 406 return t->len - sspi->left_rx_word * sspi->word_width;
1cc2df9d
ZS		 407}
408
409static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
410{
411 struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
412
413 if (sspi->chipselect[spi->chip_select] == 0) {
414 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
1cc2df9d
ZS		 415 switch (value) {
416 case BITBANG_CS_ACTIVE:
417 if (spi->mode & SPI_CS_HIGH)
418 regval |= SIRFSOC_SPI_CS_IO_OUT;
419 else
420 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
421 break;
422 case BITBANG_CS_INACTIVE:
423 if (spi->mode & SPI_CS_HIGH)
424 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
425 else
426 regval |= SIRFSOC_SPI_CS_IO_OUT;
427 break;
428 }
429 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
430 } else {
431 int gpio = sspi->chipselect[spi->chip_select];
432 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
433 }
434}
435
436static int
437spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
438{
439 struct sirfsoc_spi *sspi;
440 u8 bits_per_word = 0;
441 int hz = 0;
442 u32 regval;
443 u32 txfifo_ctrl, rxfifo_ctrl;
444 u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
445
446 sspi = spi_master_get_devdata(spi->master);
447
766ed704 448 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
1cc2df9d
ZS		 449 hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
450
1cc2df9d 451 regval = (sspi->ctrl_freq / (2 * hz)) - 1;
1cc2df9d
ZS		 452 if (regval > 0xFFFF || regval < 0) {
453 dev_err(&spi->dev, "Speed %d not supported\n", hz);
454 return -EINVAL;
455 }
456
457 switch (bits_per_word) {
458 case 8:
459 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
460 sspi->rx_word = spi_sirfsoc_rx_word_u8;
461 sspi->tx_word = spi_sirfsoc_tx_word_u8;
462 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
463 SIRFSOC_SPI_FIFO_WIDTH_BYTE;
464 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
465 SIRFSOC_SPI_FIFO_WIDTH_BYTE;
de39f5fa 466 sspi->word_width = 1;
1cc2df9d
ZS		 467 break;
468 case 12:
469 case 16:
470 regval |= (bits_per_word == 12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
471 SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
472 sspi->rx_word = spi_sirfsoc_rx_word_u16;
473 sspi->tx_word = spi_sirfsoc_tx_word_u16;
474 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
475 SIRFSOC_SPI_FIFO_WIDTH_WORD;
476 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
477 SIRFSOC_SPI_FIFO_WIDTH_WORD;
de39f5fa 478 sspi->word_width = 2;
1cc2df9d
ZS		 479 break;
480 case 32:
481 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
482 sspi->rx_word = spi_sirfsoc_rx_word_u32;
483 sspi->tx_word = spi_sirfsoc_tx_word_u32;
484 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
485 SIRFSOC_SPI_FIFO_WIDTH_DWORD;
486 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
487 SIRFSOC_SPI_FIFO_WIDTH_DWORD;
de39f5fa 488 sspi->word_width = 4;
1cc2df9d 489 break;
804ae438
AB		 490 default:
491 BUG();
1cc2df9d
ZS		 492 }
493
494 if (!(spi->mode & SPI_CS_HIGH))
495 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
496 if (!(spi->mode & SPI_LSB_FIRST))
497 regval |= SIRFSOC_SPI_TRAN_MSB;
498 if (spi->mode & SPI_CPOL)
499 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
500
501 /*
502 * Data should be driven at least 1/2 cycle before the fetch edge to make
503 * sure that data gets stable at the fetch edge.
504 */
505 if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
506 (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
507 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
508 else
509 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
510
511 writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
512 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
513 SIRFSOC_SPI_FIFO_HC(2),
514 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
515 writel(SIRFSOC_SPI_FIFO_SC(2) |
516 SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
517 SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
518 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
519 writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
520 writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
521
522 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
de39f5fa
BS		 523
524 if (IS_DMA_VALID(t)) {
525 /* Enable DMA mode for RX, TX */
526 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
527 writel(SIRFSOC_SPI_RX_DMA_FLUSH, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
528 } else {
529 /* Enable IO mode for RX, TX */
530 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
531 writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
532 }
533
1cc2df9d
ZS		 534 return 0;
535}
536
537static int spi_sirfsoc_setup(struct spi_device *spi)
538{
539 struct sirfsoc_spi *sspi;
540
541 if (!spi->max_speed_hz)
542 return -EINVAL;
543
544 sspi = spi_master_get_devdata(spi->master);
545
546 if (!spi->bits_per_word)
547 spi->bits_per_word = 8;
548
549 return spi_sirfsoc_setup_transfer(spi, NULL);
550}
551
fd4a319b 552static int spi_sirfsoc_probe(struct platform_device *pdev)
1cc2df9d
ZS		 553{
554 struct sirfsoc_spi *sspi;
555 struct spi_master *master;
556 struct resource *mem_res;
557 int num_cs, cs_gpio, irq;
de39f5fa
BS		 558 u32 rx_dma_ch, tx_dma_ch;
559 dma_cap_mask_t dma_cap_mask;
1cc2df9d
ZS		 560 int i;
561 int ret;
562
563 ret = of_property_read_u32(pdev->dev.of_node,
564 "sirf,spi-num-chipselects", &num_cs);
565 if (ret < 0) {
566 dev_err(&pdev->dev, "Unable to get chip select number\n");
567 goto err_cs;
568 }
569
de39f5fa
BS		 570 ret = of_property_read_u32(pdev->dev.of_node,
571 "sirf,spi-dma-rx-channel", &rx_dma_ch);
572 if (ret < 0) {
573 dev_err(&pdev->dev, "Unable to get rx dma channel\n");
574 goto err_cs;
575 }
576
577 ret = of_property_read_u32(pdev->dev.of_node,
578 "sirf,spi-dma-tx-channel", &tx_dma_ch);
579 if (ret < 0) {
580 dev_err(&pdev->dev, "Unable to get tx dma channel\n");
581 goto err_cs;
582 }
583
1cc2df9d
ZS		 584 master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
585 if (!master) {
586 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
587 return -ENOMEM;
588 }
589 platform_set_drvdata(pdev, master);
590 sspi = spi_master_get_devdata(master);
591
1cc2df9d
ZS		 592 master->num_chipselect = num_cs;
593
594 for (i = 0; i < master->num_chipselect; i++) {
595 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
596 if (cs_gpio < 0) {
597 dev_err(&pdev->dev, "can't get cs gpio from DT\n");
598 ret = -ENODEV;
599 goto free_master;
600 }
601
602 sspi->chipselect[i] = cs_gpio;
603 if (cs_gpio == 0)
604 continue; /* use cs from spi controller */
605
606 ret = gpio_request(cs_gpio, DRIVER_NAME);
607 if (ret) {
608 while (i > 0) {
609 i--;
610 if (sspi->chipselect[i] > 0)
611 gpio_free(sspi->chipselect[i]);
612 }
613 dev_err(&pdev->dev, "fail to request cs gpios\n");
614 goto free_master;
615 }
616 }
617
2479790b 618 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b0ee5605
TR		 619 sspi->base = devm_ioremap_resource(&pdev->dev, mem_res);
620 if (IS_ERR(sspi->base)) {
621 ret = PTR_ERR(sspi->base);
1cc2df9d
ZS		 622 goto free_master;
623 }
624
625 irq = platform_get_irq(pdev, 0);
626 if (irq < 0) {
627 ret = -ENXIO;
628 goto free_master;
629 }
630 ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
631 DRIVER_NAME, sspi);
632 if (ret)
633 goto free_master;
634
94c69f76 635 sspi->bitbang.master = master;
1cc2df9d
ZS		 636 sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
637 sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
638 sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
639 sspi->bitbang.master->setup = spi_sirfsoc_setup;
640 master->bus_num = pdev->id;
94b1f0df 641 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH;
24778be2
SW		 642 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) |
643 SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
1cc2df9d
ZS		 644 sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
645
de39f5fa
BS		 646 /* request DMA channels */
647 dma_cap_zero(dma_cap_mask);
648 dma_cap_set(DMA_INTERLEAVE, dma_cap_mask);
649
650 sspi->rx_chan = dma_request_channel(dma_cap_mask, (dma_filter_fn)sirfsoc_dma_filter_id,
651 (void *)rx_dma_ch);
652 if (!sspi->rx_chan) {
653 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
6cca9e2d 654 ret = -ENODEV;
de39f5fa
BS		 655 goto free_master;
656 }
657 sspi->tx_chan = dma_request_channel(dma_cap_mask, (dma_filter_fn)sirfsoc_dma_filter_id,
658 (void *)tx_dma_ch);
659 if (!sspi->tx_chan) {
660 dev_err(&pdev->dev, "can not allocate tx dma channel\n");
6cca9e2d 661 ret = -ENODEV;
de39f5fa
BS		 662 goto free_rx_dma;
663 }
664
1cc2df9d
ZS		 665 sspi->clk = clk_get(&pdev->dev, NULL);
666 if (IS_ERR(sspi->clk)) {
de39f5fa
BS		 667 ret = PTR_ERR(sspi->clk);
668 goto free_tx_dma;
1cc2df9d 669 }
e5118cd2 670 clk_prepare_enable(sspi->clk);
1cc2df9d
ZS		 671 sspi->ctrl_freq = clk_get_rate(sspi->clk);
672
de39f5fa
BS		 673 init_completion(&sspi->rx_done);
674 init_completion(&sspi->tx_done);
1cc2df9d 675
1cc2df9d
ZS		 676 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
677 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
678 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
679 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
680 /* We are not using dummy delay between command and data */
681 writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
682
de39f5fa 683 sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL);
6cca9e2d
WY		 684 if (!sspi->dummypage) {
685 ret = -ENOMEM;
de39f5fa 686 goto free_clk;
6cca9e2d 687 }
de39f5fa 688
1cc2df9d
ZS		 689 ret = spi_bitbang_start(&sspi->bitbang);
690 if (ret)
de39f5fa 691 goto free_dummypage;
1cc2df9d
ZS		 692
693 dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
694
695 return 0;
de39f5fa
BS		 696free_dummypage:
697 kfree(sspi->dummypage);
1cc2df9d 698free_clk:
e5118cd2 699 clk_disable_unprepare(sspi->clk);
1cc2df9d 700 clk_put(sspi->clk);
de39f5fa
BS		 701free_tx_dma:
702 dma_release_channel(sspi->tx_chan);
703free_rx_dma:
704 dma_release_channel(sspi->rx_chan);
1cc2df9d
ZS		 705free_master:
706 spi_master_put(master);
707err_cs:
708 return ret;
709}
710
fd4a319b 711static int spi_sirfsoc_remove(struct platform_device *pdev)
1cc2df9d
ZS		 712{
713 struct spi_master *master;
714 struct sirfsoc_spi *sspi;
715 int i;
716
717 master = platform_get_drvdata(pdev);
718 sspi = spi_master_get_devdata(master);
719
720 spi_bitbang_stop(&sspi->bitbang);
721 for (i = 0; i < master->num_chipselect; i++) {
722 if (sspi->chipselect[i] > 0)
723 gpio_free(sspi->chipselect[i]);
724 }
de39f5fa 725 kfree(sspi->dummypage);
e5118cd2 726 clk_disable_unprepare(sspi->clk);
1cc2df9d 727 clk_put(sspi->clk);
de39f5fa
BS		 728 dma_release_channel(sspi->rx_chan);
729 dma_release_channel(sspi->tx_chan);
1cc2df9d
ZS		 730 spi_master_put(master);
731 return 0;
732}
733
734#ifdef CONFIG_PM
735static int spi_sirfsoc_suspend(struct device *dev)
736{
a1216394 737 struct spi_master *master = dev_get_drvdata(dev);
1cc2df9d
ZS		 738 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
739
740 clk_disable(sspi->clk);
741 return 0;
742}
743
744static int spi_sirfsoc_resume(struct device *dev)
745{
a1216394 746 struct spi_master *master = dev_get_drvdata(dev);
1cc2df9d
ZS		 747 struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
748
749 clk_enable(sspi->clk);
750 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
751 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
752 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
753 writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
754
755 return 0;
756}
757
758static const struct dev_pm_ops spi_sirfsoc_pm_ops = {
759 .suspend = spi_sirfsoc_suspend,
760 .resume = spi_sirfsoc_resume,
761};
762#endif
763
764static const struct of_device_id spi_sirfsoc_of_match[] = {
765 { .compatible = "sirf,prima2-spi", },
f3b8a8ec 766 { .compatible = "sirf,marco-spi", },
1cc2df9d
ZS		 767 {}
768};
3af4ed70 769MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match);
1cc2df9d
ZS		 770
771static struct platform_driver spi_sirfsoc_driver = {
772 .driver = {
773 .name = DRIVER_NAME,
774 .owner = THIS_MODULE,
775#ifdef CONFIG_PM
776 .pm = &spi_sirfsoc_pm_ops,
777#endif
778 .of_match_table = spi_sirfsoc_of_match,
779 },
780 .probe = spi_sirfsoc_probe,
fd4a319b 781 .remove = spi_sirfsoc_remove,
1cc2df9d
ZS		 782};
783module_platform_driver(spi_sirfsoc_driver);
784
785MODULE_DESCRIPTION("SiRF SoC SPI master driver");
786MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
787 "Barry Song <Baohua.Song@csr.com>");
788MODULE_LICENSE("GPL v2");
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