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1cc2df9d ZS |
1 | /* |
2 | * SPI bus driver for CSR SiRFprimaII | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/clk.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/of.h> | |
16 | #include <linux/bitops.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/of_gpio.h> | |
20 | #include <linux/spi/spi.h> | |
21 | #include <linux/spi/spi_bitbang.h> | |
de39f5fa BS |
22 | #include <linux/dmaengine.h> |
23 | #include <linux/dma-direction.h> | |
24 | #include <linux/dma-mapping.h> | |
1cc2df9d ZS |
25 | |
26 | #define DRIVER_NAME "sirfsoc_spi" | |
27 | ||
28 | #define SIRFSOC_SPI_CTRL 0x0000 | |
29 | #define SIRFSOC_SPI_CMD 0x0004 | |
30 | #define SIRFSOC_SPI_TX_RX_EN 0x0008 | |
31 | #define SIRFSOC_SPI_INT_EN 0x000C | |
32 | #define SIRFSOC_SPI_INT_STATUS 0x0010 | |
33 | #define SIRFSOC_SPI_TX_DMA_IO_CTRL 0x0100 | |
34 | #define SIRFSOC_SPI_TX_DMA_IO_LEN 0x0104 | |
35 | #define SIRFSOC_SPI_TXFIFO_CTRL 0x0108 | |
36 | #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK 0x010C | |
37 | #define SIRFSOC_SPI_TXFIFO_OP 0x0110 | |
38 | #define SIRFSOC_SPI_TXFIFO_STATUS 0x0114 | |
39 | #define SIRFSOC_SPI_TXFIFO_DATA 0x0118 | |
40 | #define SIRFSOC_SPI_RX_DMA_IO_CTRL 0x0120 | |
41 | #define SIRFSOC_SPI_RX_DMA_IO_LEN 0x0124 | |
42 | #define SIRFSOC_SPI_RXFIFO_CTRL 0x0128 | |
43 | #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK 0x012C | |
44 | #define SIRFSOC_SPI_RXFIFO_OP 0x0130 | |
45 | #define SIRFSOC_SPI_RXFIFO_STATUS 0x0134 | |
46 | #define SIRFSOC_SPI_RXFIFO_DATA 0x0138 | |
47 | #define SIRFSOC_SPI_DUMMY_DELAY_CTL 0x0144 | |
48 | ||
49 | /* SPI CTRL register defines */ | |
50 | #define SIRFSOC_SPI_SLV_MODE BIT(16) | |
51 | #define SIRFSOC_SPI_CMD_MODE BIT(17) | |
52 | #define SIRFSOC_SPI_CS_IO_OUT BIT(18) | |
53 | #define SIRFSOC_SPI_CS_IO_MODE BIT(19) | |
54 | #define SIRFSOC_SPI_CLK_IDLE_STAT BIT(20) | |
55 | #define SIRFSOC_SPI_CS_IDLE_STAT BIT(21) | |
56 | #define SIRFSOC_SPI_TRAN_MSB BIT(22) | |
57 | #define SIRFSOC_SPI_DRV_POS_EDGE BIT(23) | |
58 | #define SIRFSOC_SPI_CS_HOLD_TIME BIT(24) | |
59 | #define SIRFSOC_SPI_CLK_SAMPLE_MODE BIT(25) | |
60 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8 (0 << 26) | |
61 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12 (1 << 26) | |
62 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16 (2 << 26) | |
63 | #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32 (3 << 26) | |
64 | #define SIRFSOC_SPI_CMD_BYTE_NUM(x) ((x & 3) << 28) | |
65 | #define SIRFSOC_SPI_ENA_AUTO_CLR BIT(30) | |
66 | #define SIRFSOC_SPI_MUL_DAT_MODE BIT(31) | |
67 | ||
68 | /* Interrupt Enable */ | |
69 | #define SIRFSOC_SPI_RX_DONE_INT_EN BIT(0) | |
70 | #define SIRFSOC_SPI_TX_DONE_INT_EN BIT(1) | |
71 | #define SIRFSOC_SPI_RX_OFLOW_INT_EN BIT(2) | |
72 | #define SIRFSOC_SPI_TX_UFLOW_INT_EN BIT(3) | |
73 | #define SIRFSOC_SPI_RX_IO_DMA_INT_EN BIT(4) | |
74 | #define SIRFSOC_SPI_TX_IO_DMA_INT_EN BIT(5) | |
75 | #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN BIT(6) | |
76 | #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7) | |
77 | #define SIRFSOC_SPI_RXFIFO_THD_INT_EN BIT(8) | |
78 | #define SIRFSOC_SPI_TXFIFO_THD_INT_EN BIT(9) | |
79 | #define SIRFSOC_SPI_FRM_END_INT_EN BIT(10) | |
80 | ||
81 | #define SIRFSOC_SPI_INT_MASK_ALL 0x1FFF | |
82 | ||
83 | /* Interrupt status */ | |
84 | #define SIRFSOC_SPI_RX_DONE BIT(0) | |
85 | #define SIRFSOC_SPI_TX_DONE BIT(1) | |
86 | #define SIRFSOC_SPI_RX_OFLOW BIT(2) | |
87 | #define SIRFSOC_SPI_TX_UFLOW BIT(3) | |
88 | #define SIRFSOC_SPI_RX_FIFO_FULL BIT(6) | |
89 | #define SIRFSOC_SPI_TXFIFO_EMPTY BIT(7) | |
90 | #define SIRFSOC_SPI_RXFIFO_THD_REACH BIT(8) | |
91 | #define SIRFSOC_SPI_TXFIFO_THD_REACH BIT(9) | |
92 | #define SIRFSOC_SPI_FRM_END BIT(10) | |
93 | ||
94 | /* TX RX enable */ | |
95 | #define SIRFSOC_SPI_RX_EN BIT(0) | |
96 | #define SIRFSOC_SPI_TX_EN BIT(1) | |
97 | #define SIRFSOC_SPI_CMD_TX_EN BIT(2) | |
98 | ||
99 | #define SIRFSOC_SPI_IO_MODE_SEL BIT(0) | |
100 | #define SIRFSOC_SPI_RX_DMA_FLUSH BIT(2) | |
101 | ||
102 | /* FIFO OPs */ | |
103 | #define SIRFSOC_SPI_FIFO_RESET BIT(0) | |
104 | #define SIRFSOC_SPI_FIFO_START BIT(1) | |
105 | ||
106 | /* FIFO CTRL */ | |
107 | #define SIRFSOC_SPI_FIFO_WIDTH_BYTE (0 << 0) | |
108 | #define SIRFSOC_SPI_FIFO_WIDTH_WORD (1 << 0) | |
109 | #define SIRFSOC_SPI_FIFO_WIDTH_DWORD (2 << 0) | |
110 | ||
111 | /* FIFO Status */ | |
112 | #define SIRFSOC_SPI_FIFO_LEVEL_MASK 0xFF | |
113 | #define SIRFSOC_SPI_FIFO_FULL BIT(8) | |
114 | #define SIRFSOC_SPI_FIFO_EMPTY BIT(9) | |
115 | ||
116 | /* 256 bytes rx/tx FIFO */ | |
117 | #define SIRFSOC_SPI_FIFO_SIZE 256 | |
118 | #define SIRFSOC_SPI_DAT_FRM_LEN_MAX (64 * 1024) | |
119 | ||
120 | #define SIRFSOC_SPI_FIFO_SC(x) ((x) & 0x3F) | |
121 | #define SIRFSOC_SPI_FIFO_LC(x) (((x) & 0x3F) << 10) | |
122 | #define SIRFSOC_SPI_FIFO_HC(x) (((x) & 0x3F) << 20) | |
123 | #define SIRFSOC_SPI_FIFO_THD(x) (((x) & 0xFF) << 2) | |
124 | ||
de39f5fa BS |
125 | /* |
126 | * only if the rx/tx buffer and transfer size are 4-bytes aligned, we use dma | |
127 | * due to the limitation of dma controller | |
128 | */ | |
129 | ||
130 | #define ALIGNED(x) (!((u32)x & 0x3)) | |
131 | #define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \ | |
692fb0fe | 132 | ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE)) |
de39f5fa | 133 | |
eeb71395 QL |
134 | #define SIRFSOC_MAX_CMD_BYTES 4 |
135 | ||
1cc2df9d ZS |
136 | struct sirfsoc_spi { |
137 | struct spi_bitbang bitbang; | |
de39f5fa BS |
138 | struct completion rx_done; |
139 | struct completion tx_done; | |
1cc2df9d ZS |
140 | |
141 | void __iomem *base; | |
142 | u32 ctrl_freq; /* SPI controller clock speed */ | |
143 | struct clk *clk; | |
1cc2df9d ZS |
144 | |
145 | /* rx & tx bufs from the spi_transfer */ | |
146 | const void *tx; | |
147 | void *rx; | |
148 | ||
149 | /* place received word into rx buffer */ | |
150 | void (*rx_word) (struct sirfsoc_spi *); | |
151 | /* get word from tx buffer for sending */ | |
152 | void (*tx_word) (struct sirfsoc_spi *); | |
153 | ||
154 | /* number of words left to be tranmitted/received */ | |
692fb0fe QL |
155 | unsigned int left_tx_word; |
156 | unsigned int left_rx_word; | |
1cc2df9d | 157 | |
de39f5fa BS |
158 | /* rx & tx DMA channels */ |
159 | struct dma_chan *rx_chan; | |
160 | struct dma_chan *tx_chan; | |
161 | dma_addr_t src_start; | |
162 | dma_addr_t dst_start; | |
163 | void *dummypage; | |
164 | int word_width; /* in bytes */ | |
1cc2df9d | 165 | |
eeb71395 QL |
166 | /* |
167 | * if tx size is not more than 4 and rx size is NULL, use | |
168 | * command model | |
169 | */ | |
170 | bool tx_by_cmd; | |
171 | ||
1cc2df9d ZS |
172 | int chipselect[0]; |
173 | }; | |
174 | ||
175 | static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi) | |
176 | { | |
177 | u32 data; | |
178 | u8 *rx = sspi->rx; | |
179 | ||
180 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | |
181 | ||
182 | if (rx) { | |
183 | *rx++ = (u8) data; | |
184 | sspi->rx = rx; | |
185 | } | |
186 | ||
692fb0fe | 187 | sspi->left_rx_word--; |
1cc2df9d ZS |
188 | } |
189 | ||
190 | static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi) | |
191 | { | |
192 | u32 data = 0; | |
193 | const u8 *tx = sspi->tx; | |
194 | ||
195 | if (tx) { | |
196 | data = *tx++; | |
197 | sspi->tx = tx; | |
198 | } | |
199 | ||
200 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | |
692fb0fe | 201 | sspi->left_tx_word--; |
1cc2df9d ZS |
202 | } |
203 | ||
204 | static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi) | |
205 | { | |
206 | u32 data; | |
207 | u16 *rx = sspi->rx; | |
208 | ||
209 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | |
210 | ||
211 | if (rx) { | |
212 | *rx++ = (u16) data; | |
213 | sspi->rx = rx; | |
214 | } | |
215 | ||
692fb0fe | 216 | sspi->left_rx_word--; |
1cc2df9d ZS |
217 | } |
218 | ||
219 | static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi) | |
220 | { | |
221 | u32 data = 0; | |
222 | const u16 *tx = sspi->tx; | |
223 | ||
224 | if (tx) { | |
225 | data = *tx++; | |
226 | sspi->tx = tx; | |
227 | } | |
228 | ||
229 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | |
692fb0fe | 230 | sspi->left_tx_word--; |
1cc2df9d ZS |
231 | } |
232 | ||
233 | static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi) | |
234 | { | |
235 | u32 data; | |
236 | u32 *rx = sspi->rx; | |
237 | ||
238 | data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); | |
239 | ||
240 | if (rx) { | |
241 | *rx++ = (u32) data; | |
242 | sspi->rx = rx; | |
243 | } | |
244 | ||
692fb0fe | 245 | sspi->left_rx_word--; |
1cc2df9d ZS |
246 | |
247 | } | |
248 | ||
249 | static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi) | |
250 | { | |
251 | u32 data = 0; | |
252 | const u32 *tx = sspi->tx; | |
253 | ||
254 | if (tx) { | |
255 | data = *tx++; | |
256 | sspi->tx = tx; | |
257 | } | |
258 | ||
259 | writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); | |
692fb0fe | 260 | sspi->left_tx_word--; |
1cc2df9d ZS |
261 | } |
262 | ||
1cc2df9d ZS |
263 | static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id) |
264 | { | |
265 | struct sirfsoc_spi *sspi = dev_id; | |
266 | u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS); | |
267 | ||
268 | writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS); | |
269 | ||
eeb71395 QL |
270 | if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) { |
271 | complete(&sspi->tx_done); | |
272 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); | |
273 | return IRQ_HANDLED; | |
274 | } | |
275 | ||
1cc2df9d ZS |
276 | /* Error Conditions */ |
277 | if (spi_stat & SIRFSOC_SPI_RX_OFLOW || | |
278 | spi_stat & SIRFSOC_SPI_TX_UFLOW) { | |
de39f5fa | 279 | complete(&sspi->rx_done); |
1cc2df9d ZS |
280 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); |
281 | } | |
282 | ||
237ce466 QL |
283 | if (spi_stat & (SIRFSOC_SPI_FRM_END |
284 | | SIRFSOC_SPI_RXFIFO_THD_REACH)) | |
1cc2df9d ZS |
285 | while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS) |
286 | & SIRFSOC_SPI_FIFO_EMPTY)) && | |
692fb0fe | 287 | sspi->left_rx_word) |
1cc2df9d ZS |
288 | sspi->rx_word(sspi); |
289 | ||
818e9162 QL |
290 | if (spi_stat & (SIRFSOC_SPI_TXFIFO_EMPTY | |
291 | SIRFSOC_SPI_TXFIFO_THD_REACH)) | |
237ce466 QL |
292 | while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) |
293 | & SIRFSOC_SPI_FIFO_FULL)) && | |
692fb0fe | 294 | sspi->left_tx_word) |
237ce466 | 295 | sspi->tx_word(sspi); |
1cc2df9d | 296 | |
237ce466 | 297 | /* Received all words */ |
692fb0fe | 298 | if ((sspi->left_rx_word == 0) && (sspi->left_tx_word == 0)) { |
de39f5fa | 299 | complete(&sspi->rx_done); |
237ce466 QL |
300 | writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); |
301 | } | |
1cc2df9d ZS |
302 | return IRQ_HANDLED; |
303 | } | |
304 | ||
de39f5fa BS |
305 | static void spi_sirfsoc_dma_fini_callback(void *data) |
306 | { | |
307 | struct completion *dma_complete = data; | |
308 | ||
309 | complete(dma_complete); | |
310 | } | |
311 | ||
1cc2df9d ZS |
312 | static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t) |
313 | { | |
314 | struct sirfsoc_spi *sspi; | |
315 | int timeout = t->len * 10; | |
316 | sspi = spi_master_get_devdata(spi->master); | |
317 | ||
de39f5fa BS |
318 | sspi->tx = t->tx_buf ? t->tx_buf : sspi->dummypage; |
319 | sspi->rx = t->rx_buf ? t->rx_buf : sspi->dummypage; | |
692fb0fe | 320 | sspi->left_tx_word = sspi->left_rx_word = t->len / sspi->word_width; |
16735d02 WS |
321 | reinit_completion(&sspi->rx_done); |
322 | reinit_completion(&sspi->tx_done); | |
1cc2df9d ZS |
323 | |
324 | writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS); | |
325 | ||
eeb71395 QL |
326 | /* |
327 | * fill tx_buf into command register and wait for its completion | |
328 | */ | |
329 | if (sspi->tx_by_cmd) { | |
330 | u32 cmd; | |
331 | memcpy(&cmd, sspi->tx, t->len); | |
332 | ||
333 | if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST)) | |
334 | cmd = cpu_to_be32(cmd) >> | |
335 | ((SIRFSOC_MAX_CMD_BYTES - t->len) * 8); | |
336 | if (sspi->word_width == 2 && t->len == 4 && | |
337 | (!(spi->mode & SPI_LSB_FIRST))) | |
338 | cmd = ((cmd & 0xffff) << 16) | (cmd >> 16); | |
339 | ||
340 | writel(cmd, sspi->base + SIRFSOC_SPI_CMD); | |
341 | writel(SIRFSOC_SPI_FRM_END_INT_EN, | |
342 | sspi->base + SIRFSOC_SPI_INT_EN); | |
343 | writel(SIRFSOC_SPI_CMD_TX_EN, | |
344 | sspi->base + SIRFSOC_SPI_TX_RX_EN); | |
345 | ||
346 | if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { | |
347 | dev_err(&spi->dev, "transfer timeout\n"); | |
348 | return 0; | |
349 | } | |
350 | ||
351 | return t->len; | |
352 | } | |
353 | ||
692fb0fe | 354 | if (sspi->left_tx_word == 1) { |
1cc2df9d ZS |
355 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | |
356 | SIRFSOC_SPI_ENA_AUTO_CLR, | |
357 | sspi->base + SIRFSOC_SPI_CTRL); | |
358 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | |
359 | writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | |
692fb0fe QL |
360 | } else if ((sspi->left_tx_word > 1) && (sspi->left_tx_word < |
361 | SIRFSOC_SPI_DAT_FRM_LEN_MAX)) { | |
1cc2df9d ZS |
362 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL) | |
363 | SIRFSOC_SPI_MUL_DAT_MODE | | |
364 | SIRFSOC_SPI_ENA_AUTO_CLR, | |
365 | sspi->base + SIRFSOC_SPI_CTRL); | |
692fb0fe QL |
366 | writel(sspi->left_tx_word - 1, |
367 | sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | |
368 | writel(sspi->left_tx_word - 1, | |
369 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | |
1cc2df9d ZS |
370 | } else { |
371 | writel(readl(sspi->base + SIRFSOC_SPI_CTRL), | |
372 | sspi->base + SIRFSOC_SPI_CTRL); | |
373 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN); | |
374 | writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN); | |
375 | } | |
376 | ||
377 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
378 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
379 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
380 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
381 | ||
de39f5fa BS |
382 | if (IS_DMA_VALID(t)) { |
383 | struct dma_async_tx_descriptor *rx_desc, *tx_desc; | |
de39f5fa | 384 | |
d77ec5df | 385 | sspi->dst_start = dma_map_single(&spi->dev, |
bf83fd64 QL |
386 | sspi->rx, t->len, (t->tx_buf != t->rx_buf) ? |
387 | DMA_FROM_DEVICE : DMA_BIDIRECTIONAL); | |
de39f5fa | 388 | rx_desc = dmaengine_prep_slave_single(sspi->rx_chan, |
692fb0fe | 389 | sspi->dst_start, t->len, DMA_DEV_TO_MEM, |
de39f5fa BS |
390 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
391 | rx_desc->callback = spi_sirfsoc_dma_fini_callback; | |
392 | rx_desc->callback_param = &sspi->rx_done; | |
393 | ||
d77ec5df | 394 | sspi->src_start = dma_map_single(&spi->dev, |
bf83fd64 QL |
395 | (void *)sspi->tx, t->len, |
396 | (t->tx_buf != t->rx_buf) ? | |
397 | DMA_TO_DEVICE : DMA_BIDIRECTIONAL); | |
de39f5fa | 398 | tx_desc = dmaengine_prep_slave_single(sspi->tx_chan, |
692fb0fe | 399 | sspi->src_start, t->len, DMA_MEM_TO_DEV, |
de39f5fa BS |
400 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
401 | tx_desc->callback = spi_sirfsoc_dma_fini_callback; | |
402 | tx_desc->callback_param = &sspi->tx_done; | |
403 | ||
404 | dmaengine_submit(tx_desc); | |
405 | dmaengine_submit(rx_desc); | |
406 | dma_async_issue_pending(sspi->tx_chan); | |
407 | dma_async_issue_pending(sspi->rx_chan); | |
408 | } else { | |
409 | /* Send the first word to trigger the whole tx/rx process */ | |
410 | sspi->tx_word(sspi); | |
411 | ||
d77ec5df QL |
412 | writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | |
413 | SIRFSOC_SPI_TX_UFLOW_INT_EN | | |
414 | SIRFSOC_SPI_RXFIFO_THD_INT_EN | | |
415 | SIRFSOC_SPI_TXFIFO_THD_INT_EN | | |
416 | SIRFSOC_SPI_FRM_END_INT_EN | | |
417 | SIRFSOC_SPI_RXFIFO_FULL_INT_EN | | |
418 | SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, | |
419 | sspi->base + SIRFSOC_SPI_INT_EN); | |
de39f5fa | 420 | } |
1cc2df9d | 421 | |
d77ec5df QL |
422 | writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, |
423 | sspi->base + SIRFSOC_SPI_TX_RX_EN); | |
1cc2df9d | 424 | |
de39f5fa BS |
425 | if (!IS_DMA_VALID(t)) { /* for PIO */ |
426 | if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) | |
427 | dev_err(&spi->dev, "transfer timeout\n"); | |
428 | } else if (wait_for_completion_timeout(&sspi->rx_done, timeout) == 0) { | |
1cc2df9d | 429 | dev_err(&spi->dev, "transfer timeout\n"); |
de39f5fa BS |
430 | dmaengine_terminate_all(sspi->rx_chan); |
431 | } else | |
692fb0fe | 432 | sspi->left_rx_word = 0; |
de39f5fa BS |
433 | |
434 | /* | |
435 | * we only wait tx-done event if transferring by DMA. for PIO, | |
436 | * we get rx data by writing tx data, so if rx is done, tx has | |
437 | * done earlier | |
438 | */ | |
439 | if (IS_DMA_VALID(t)) { | |
440 | if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) { | |
441 | dev_err(&spi->dev, "transfer timeout\n"); | |
442 | dmaengine_terminate_all(sspi->tx_chan); | |
443 | } | |
444 | } | |
445 | ||
446 | if (IS_DMA_VALID(t)) { | |
d77ec5df QL |
447 | dma_unmap_single(&spi->dev, |
448 | sspi->src_start, t->len, DMA_TO_DEVICE); | |
449 | dma_unmap_single(&spi->dev, | |
450 | sspi->dst_start, t->len, DMA_FROM_DEVICE); | |
de39f5fa | 451 | } |
1cc2df9d ZS |
452 | |
453 | /* TX, RX FIFO stop */ | |
454 | writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
455 | writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
456 | writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN); | |
457 | writel(0, sspi->base + SIRFSOC_SPI_INT_EN); | |
458 | ||
692fb0fe | 459 | return t->len - sspi->left_rx_word * sspi->word_width; |
1cc2df9d ZS |
460 | } |
461 | ||
462 | static void spi_sirfsoc_chipselect(struct spi_device *spi, int value) | |
463 | { | |
464 | struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master); | |
465 | ||
466 | if (sspi->chipselect[spi->chip_select] == 0) { | |
467 | u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL); | |
1cc2df9d ZS |
468 | switch (value) { |
469 | case BITBANG_CS_ACTIVE: | |
470 | if (spi->mode & SPI_CS_HIGH) | |
471 | regval |= SIRFSOC_SPI_CS_IO_OUT; | |
472 | else | |
473 | regval &= ~SIRFSOC_SPI_CS_IO_OUT; | |
474 | break; | |
475 | case BITBANG_CS_INACTIVE: | |
476 | if (spi->mode & SPI_CS_HIGH) | |
477 | regval &= ~SIRFSOC_SPI_CS_IO_OUT; | |
478 | else | |
479 | regval |= SIRFSOC_SPI_CS_IO_OUT; | |
480 | break; | |
481 | } | |
482 | writel(regval, sspi->base + SIRFSOC_SPI_CTRL); | |
483 | } else { | |
484 | int gpio = sspi->chipselect[spi->chip_select]; | |
6ee8a2f7 QL |
485 | switch (value) { |
486 | case BITBANG_CS_ACTIVE: | |
487 | gpio_direction_output(gpio, | |
488 | spi->mode & SPI_CS_HIGH ? 1 : 0); | |
489 | break; | |
490 | case BITBANG_CS_INACTIVE: | |
491 | gpio_direction_output(gpio, | |
492 | spi->mode & SPI_CS_HIGH ? 0 : 1); | |
493 | break; | |
494 | } | |
1cc2df9d ZS |
495 | } |
496 | } | |
497 | ||
498 | static int | |
499 | spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |
500 | { | |
501 | struct sirfsoc_spi *sspi; | |
502 | u8 bits_per_word = 0; | |
503 | int hz = 0; | |
504 | u32 regval; | |
505 | u32 txfifo_ctrl, rxfifo_ctrl; | |
506 | u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4; | |
507 | ||
508 | sspi = spi_master_get_devdata(spi->master); | |
509 | ||
766ed704 | 510 | bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word; |
1cc2df9d ZS |
511 | hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz; |
512 | ||
1cc2df9d | 513 | regval = (sspi->ctrl_freq / (2 * hz)) - 1; |
1cc2df9d ZS |
514 | if (regval > 0xFFFF || regval < 0) { |
515 | dev_err(&spi->dev, "Speed %d not supported\n", hz); | |
516 | return -EINVAL; | |
517 | } | |
518 | ||
519 | switch (bits_per_word) { | |
520 | case 8: | |
521 | regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8; | |
522 | sspi->rx_word = spi_sirfsoc_rx_word_u8; | |
523 | sspi->tx_word = spi_sirfsoc_tx_word_u8; | |
1cc2df9d ZS |
524 | break; |
525 | case 12: | |
526 | case 16: | |
d77ec5df QL |
527 | regval |= (bits_per_word == 12) ? |
528 | SIRFSOC_SPI_TRAN_DAT_FORMAT_12 : | |
1cc2df9d ZS |
529 | SIRFSOC_SPI_TRAN_DAT_FORMAT_16; |
530 | sspi->rx_word = spi_sirfsoc_rx_word_u16; | |
531 | sspi->tx_word = spi_sirfsoc_tx_word_u16; | |
1cc2df9d ZS |
532 | break; |
533 | case 32: | |
534 | regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32; | |
535 | sspi->rx_word = spi_sirfsoc_rx_word_u32; | |
536 | sspi->tx_word = spi_sirfsoc_tx_word_u32; | |
1cc2df9d | 537 | break; |
804ae438 AB |
538 | default: |
539 | BUG(); | |
1cc2df9d ZS |
540 | } |
541 | ||
8c328a26 AL |
542 | sspi->word_width = DIV_ROUND_UP(bits_per_word, 8); |
543 | txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | |
544 | sspi->word_width; | |
545 | rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) | | |
546 | sspi->word_width; | |
547 | ||
1cc2df9d ZS |
548 | if (!(spi->mode & SPI_CS_HIGH)) |
549 | regval |= SIRFSOC_SPI_CS_IDLE_STAT; | |
550 | if (!(spi->mode & SPI_LSB_FIRST)) | |
551 | regval |= SIRFSOC_SPI_TRAN_MSB; | |
552 | if (spi->mode & SPI_CPOL) | |
553 | regval |= SIRFSOC_SPI_CLK_IDLE_STAT; | |
554 | ||
555 | /* | |
d77ec5df QL |
556 | * Data should be driven at least 1/2 cycle before the fetch edge |
557 | * to make sure that data gets stable at the fetch edge. | |
1cc2df9d ZS |
558 | */ |
559 | if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) || | |
560 | (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA))) | |
561 | regval &= ~SIRFSOC_SPI_DRV_POS_EDGE; | |
562 | else | |
563 | regval |= SIRFSOC_SPI_DRV_POS_EDGE; | |
564 | ||
565 | writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) | | |
566 | SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | | |
567 | SIRFSOC_SPI_FIFO_HC(2), | |
568 | sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK); | |
569 | writel(SIRFSOC_SPI_FIFO_SC(2) | | |
570 | SIRFSOC_SPI_FIFO_LC(fifo_size / 2) | | |
571 | SIRFSOC_SPI_FIFO_HC(fifo_size - 2), | |
572 | sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK); | |
573 | writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL); | |
574 | writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL); | |
575 | ||
eeb71395 QL |
576 | if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) { |
577 | regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) | | |
578 | SIRFSOC_SPI_CMD_MODE); | |
579 | sspi->tx_by_cmd = true; | |
580 | } else { | |
581 | regval &= ~SIRFSOC_SPI_CMD_MODE; | |
582 | sspi->tx_by_cmd = false; | |
583 | } | |
625227a4 QL |
584 | /* |
585 | * set spi controller in RISC chipselect mode, we are controlling CS by | |
586 | * software BITBANG_CS_ACTIVE and BITBANG_CS_INACTIVE. | |
587 | */ | |
588 | regval |= SIRFSOC_SPI_CS_IO_MODE; | |
1cc2df9d | 589 | writel(regval, sspi->base + SIRFSOC_SPI_CTRL); |
de39f5fa BS |
590 | |
591 | if (IS_DMA_VALID(t)) { | |
592 | /* Enable DMA mode for RX, TX */ | |
593 | writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); | |
d77ec5df QL |
594 | writel(SIRFSOC_SPI_RX_DMA_FLUSH, |
595 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); | |
de39f5fa BS |
596 | } else { |
597 | /* Enable IO mode for RX, TX */ | |
d77ec5df QL |
598 | writel(SIRFSOC_SPI_IO_MODE_SEL, |
599 | sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL); | |
600 | writel(SIRFSOC_SPI_IO_MODE_SEL, | |
601 | sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL); | |
de39f5fa BS |
602 | } |
603 | ||
1cc2df9d ZS |
604 | return 0; |
605 | } | |
606 | ||
607 | static int spi_sirfsoc_setup(struct spi_device *spi) | |
608 | { | |
1cc2df9d ZS |
609 | if (!spi->max_speed_hz) |
610 | return -EINVAL; | |
611 | ||
1cc2df9d ZS |
612 | return spi_sirfsoc_setup_transfer(spi, NULL); |
613 | } | |
614 | ||
fd4a319b | 615 | static int spi_sirfsoc_probe(struct platform_device *pdev) |
1cc2df9d ZS |
616 | { |
617 | struct sirfsoc_spi *sspi; | |
618 | struct spi_master *master; | |
619 | struct resource *mem_res; | |
620 | int num_cs, cs_gpio, irq; | |
621 | int i; | |
622 | int ret; | |
623 | ||
624 | ret = of_property_read_u32(pdev->dev.of_node, | |
625 | "sirf,spi-num-chipselects", &num_cs); | |
626 | if (ret < 0) { | |
627 | dev_err(&pdev->dev, "Unable to get chip select number\n"); | |
628 | goto err_cs; | |
629 | } | |
630 | ||
d77ec5df QL |
631 | master = spi_alloc_master(&pdev->dev, |
632 | sizeof(*sspi) + sizeof(int) * num_cs); | |
1cc2df9d ZS |
633 | if (!master) { |
634 | dev_err(&pdev->dev, "Unable to allocate SPI master\n"); | |
635 | return -ENOMEM; | |
636 | } | |
637 | platform_set_drvdata(pdev, master); | |
638 | sspi = spi_master_get_devdata(master); | |
639 | ||
1cc2df9d ZS |
640 | master->num_chipselect = num_cs; |
641 | ||
642 | for (i = 0; i < master->num_chipselect; i++) { | |
643 | cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i); | |
644 | if (cs_gpio < 0) { | |
645 | dev_err(&pdev->dev, "can't get cs gpio from DT\n"); | |
646 | ret = -ENODEV; | |
647 | goto free_master; | |
648 | } | |
649 | ||
650 | sspi->chipselect[i] = cs_gpio; | |
651 | if (cs_gpio == 0) | |
652 | continue; /* use cs from spi controller */ | |
653 | ||
654 | ret = gpio_request(cs_gpio, DRIVER_NAME); | |
655 | if (ret) { | |
656 | while (i > 0) { | |
657 | i--; | |
658 | if (sspi->chipselect[i] > 0) | |
659 | gpio_free(sspi->chipselect[i]); | |
660 | } | |
661 | dev_err(&pdev->dev, "fail to request cs gpios\n"); | |
662 | goto free_master; | |
663 | } | |
664 | } | |
665 | ||
2479790b | 666 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
b0ee5605 TR |
667 | sspi->base = devm_ioremap_resource(&pdev->dev, mem_res); |
668 | if (IS_ERR(sspi->base)) { | |
669 | ret = PTR_ERR(sspi->base); | |
1cc2df9d ZS |
670 | goto free_master; |
671 | } | |
672 | ||
673 | irq = platform_get_irq(pdev, 0); | |
674 | if (irq < 0) { | |
675 | ret = -ENXIO; | |
676 | goto free_master; | |
677 | } | |
678 | ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0, | |
679 | DRIVER_NAME, sspi); | |
680 | if (ret) | |
681 | goto free_master; | |
682 | ||
94c69f76 | 683 | sspi->bitbang.master = master; |
1cc2df9d ZS |
684 | sspi->bitbang.chipselect = spi_sirfsoc_chipselect; |
685 | sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer; | |
686 | sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer; | |
687 | sspi->bitbang.master->setup = spi_sirfsoc_setup; | |
688 | master->bus_num = pdev->id; | |
94b1f0df | 689 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH; |
24778be2 SW |
690 | master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(12) | |
691 | SPI_BPW_MASK(16) | SPI_BPW_MASK(32); | |
1cc2df9d ZS |
692 | sspi->bitbang.master->dev.of_node = pdev->dev.of_node; |
693 | ||
de39f5fa | 694 | /* request DMA channels */ |
dd7243d6 | 695 | sspi->rx_chan = dma_request_slave_channel(&pdev->dev, "rx"); |
de39f5fa BS |
696 | if (!sspi->rx_chan) { |
697 | dev_err(&pdev->dev, "can not allocate rx dma channel\n"); | |
6cca9e2d | 698 | ret = -ENODEV; |
de39f5fa BS |
699 | goto free_master; |
700 | } | |
dd7243d6 | 701 | sspi->tx_chan = dma_request_slave_channel(&pdev->dev, "tx"); |
de39f5fa BS |
702 | if (!sspi->tx_chan) { |
703 | dev_err(&pdev->dev, "can not allocate tx dma channel\n"); | |
6cca9e2d | 704 | ret = -ENODEV; |
de39f5fa BS |
705 | goto free_rx_dma; |
706 | } | |
707 | ||
1cc2df9d ZS |
708 | sspi->clk = clk_get(&pdev->dev, NULL); |
709 | if (IS_ERR(sspi->clk)) { | |
de39f5fa BS |
710 | ret = PTR_ERR(sspi->clk); |
711 | goto free_tx_dma; | |
1cc2df9d | 712 | } |
e5118cd2 | 713 | clk_prepare_enable(sspi->clk); |
1cc2df9d ZS |
714 | sspi->ctrl_freq = clk_get_rate(sspi->clk); |
715 | ||
de39f5fa BS |
716 | init_completion(&sspi->rx_done); |
717 | init_completion(&sspi->tx_done); | |
1cc2df9d | 718 | |
1cc2df9d ZS |
719 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); |
720 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
721 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
722 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
723 | /* We are not using dummy delay between command and data */ | |
724 | writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL); | |
725 | ||
de39f5fa | 726 | sspi->dummypage = kmalloc(2 * PAGE_SIZE, GFP_KERNEL); |
6cca9e2d WY |
727 | if (!sspi->dummypage) { |
728 | ret = -ENOMEM; | |
de39f5fa | 729 | goto free_clk; |
6cca9e2d | 730 | } |
de39f5fa | 731 | |
1cc2df9d ZS |
732 | ret = spi_bitbang_start(&sspi->bitbang); |
733 | if (ret) | |
de39f5fa | 734 | goto free_dummypage; |
1cc2df9d ZS |
735 | |
736 | dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num); | |
737 | ||
738 | return 0; | |
de39f5fa BS |
739 | free_dummypage: |
740 | kfree(sspi->dummypage); | |
1cc2df9d | 741 | free_clk: |
e5118cd2 | 742 | clk_disable_unprepare(sspi->clk); |
1cc2df9d | 743 | clk_put(sspi->clk); |
de39f5fa BS |
744 | free_tx_dma: |
745 | dma_release_channel(sspi->tx_chan); | |
746 | free_rx_dma: | |
747 | dma_release_channel(sspi->rx_chan); | |
1cc2df9d ZS |
748 | free_master: |
749 | spi_master_put(master); | |
750 | err_cs: | |
751 | return ret; | |
752 | } | |
753 | ||
fd4a319b | 754 | static int spi_sirfsoc_remove(struct platform_device *pdev) |
1cc2df9d ZS |
755 | { |
756 | struct spi_master *master; | |
757 | struct sirfsoc_spi *sspi; | |
758 | int i; | |
759 | ||
760 | master = platform_get_drvdata(pdev); | |
761 | sspi = spi_master_get_devdata(master); | |
762 | ||
763 | spi_bitbang_stop(&sspi->bitbang); | |
764 | for (i = 0; i < master->num_chipselect; i++) { | |
765 | if (sspi->chipselect[i] > 0) | |
766 | gpio_free(sspi->chipselect[i]); | |
767 | } | |
de39f5fa | 768 | kfree(sspi->dummypage); |
e5118cd2 | 769 | clk_disable_unprepare(sspi->clk); |
1cc2df9d | 770 | clk_put(sspi->clk); |
de39f5fa BS |
771 | dma_release_channel(sspi->rx_chan); |
772 | dma_release_channel(sspi->tx_chan); | |
1cc2df9d ZS |
773 | spi_master_put(master); |
774 | return 0; | |
775 | } | |
776 | ||
facffed2 | 777 | #ifdef CONFIG_PM_SLEEP |
1cc2df9d ZS |
778 | static int spi_sirfsoc_suspend(struct device *dev) |
779 | { | |
a1216394 | 780 | struct spi_master *master = dev_get_drvdata(dev); |
1cc2df9d | 781 | struct sirfsoc_spi *sspi = spi_master_get_devdata(master); |
a82ba3a3 AL |
782 | int ret; |
783 | ||
784 | ret = spi_master_suspend(master); | |
785 | if (ret) | |
786 | return ret; | |
1cc2df9d ZS |
787 | |
788 | clk_disable(sspi->clk); | |
789 | return 0; | |
790 | } | |
791 | ||
792 | static int spi_sirfsoc_resume(struct device *dev) | |
793 | { | |
a1216394 | 794 | struct spi_master *master = dev_get_drvdata(dev); |
1cc2df9d ZS |
795 | struct sirfsoc_spi *sspi = spi_master_get_devdata(master); |
796 | ||
797 | clk_enable(sspi->clk); | |
798 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
799 | writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
800 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP); | |
801 | writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP); | |
802 | ||
a82ba3a3 | 803 | return spi_master_resume(master); |
1cc2df9d | 804 | } |
facffed2 | 805 | #endif |
1cc2df9d | 806 | |
71aa2e32 JH |
807 | static SIMPLE_DEV_PM_OPS(spi_sirfsoc_pm_ops, spi_sirfsoc_suspend, |
808 | spi_sirfsoc_resume); | |
1cc2df9d ZS |
809 | |
810 | static const struct of_device_id spi_sirfsoc_of_match[] = { | |
811 | { .compatible = "sirf,prima2-spi", }, | |
f3b8a8ec | 812 | { .compatible = "sirf,marco-spi", }, |
1cc2df9d ZS |
813 | {} |
814 | }; | |
3af4ed70 | 815 | MODULE_DEVICE_TABLE(of, spi_sirfsoc_of_match); |
1cc2df9d ZS |
816 | |
817 | static struct platform_driver spi_sirfsoc_driver = { | |
818 | .driver = { | |
819 | .name = DRIVER_NAME, | |
820 | .owner = THIS_MODULE, | |
1cc2df9d | 821 | .pm = &spi_sirfsoc_pm_ops, |
1cc2df9d ZS |
822 | .of_match_table = spi_sirfsoc_of_match, |
823 | }, | |
824 | .probe = spi_sirfsoc_probe, | |
fd4a319b | 825 | .remove = spi_sirfsoc_remove, |
1cc2df9d ZS |
826 | }; |
827 | module_platform_driver(spi_sirfsoc_driver); | |
1cc2df9d | 828 | MODULE_DESCRIPTION("SiRF SoC SPI master driver"); |
d77ec5df QL |
829 | MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>"); |
830 | MODULE_AUTHOR("Barry Song <Baohua.Song@csr.com>"); | |
1cc2df9d | 831 | MODULE_LICENSE("GPL v2"); |