[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-sprd-adi.c

/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#include <linux/hwspinlock.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/sizes.h>

/* Registers definitions for ADI controller */
#define REG_ADI_CTRL0			0x4
#define REG_ADI_CHN_PRIL		0x8
#define REG_ADI_CHN_PRIH		0xc
#define REG_ADI_INT_EN			0x10
#define REG_ADI_INT_RAW			0x14
#define REG_ADI_INT_MASK		0x18
#define REG_ADI_INT_CLR			0x1c
#define REG_ADI_GSSI_CFG0		0x20
#define REG_ADI_GSSI_CFG1		0x24
#define REG_ADI_RD_CMD			0x28
#define REG_ADI_RD_DATA			0x2c
#define REG_ADI_ARM_FIFO_STS		0x30
#define REG_ADI_STS			0x34
#define REG_ADI_EVT_FIFO_STS		0x38
#define REG_ADI_ARM_CMD_STS		0x3c
#define REG_ADI_CHN_EN			0x40
#define REG_ADI_CHN_ADDR(id)		(0x44 + (id - 2) * 4)
#define REG_ADI_CHN_EN1			0x20c

/* Bits definitions for register REG_ADI_GSSI_CFG0 */
#define BIT_CLK_ALL_ON			BIT(30)

/* Bits definitions for register REG_ADI_RD_DATA */
#define BIT_RD_CMD_BUSY			BIT(31)
#define RD_ADDR_SHIFT			16
#define RD_VALUE_MASK			GENMASK(15, 0)
#define RD_ADDR_MASK			GENMASK(30, 16)

/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
#define BIT_FIFO_FULL			BIT(11)
#define BIT_FIFO_EMPTY			BIT(10)

/*
 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
 * The slave devices address offset is always 0x8000 and size is 4K.
 */
#define ADI_SLAVE_ADDR_SIZE		SZ_4K
#define ADI_SLAVE_OFFSET		0x8000

/* Timeout (ms) for the trylock of hardware spinlocks */
#define ADI_HWSPINLOCK_TIMEOUT		5000
/*
 * ADI controller has 50 channels including 2 software channels
 * and 48 hardware channels.
 */
#define ADI_HW_CHNS			50

#define ADI_FIFO_DRAIN_TIMEOUT		1000
#define ADI_READ_TIMEOUT		2000
#define REG_ADDR_LOW_MASK		GENMASK(11, 0)

struct sprd_adi {
	struct spi_controller	*ctlr;
	struct device		*dev;
	void __iomem		*base;
	struct hwspinlock	*hwlock;
	unsigned long		slave_vbase;
	unsigned long		slave_pbase;
};

static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
{
	if (paddr < sadi->slave_pbase || paddr >
	    (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
		dev_err(sadi->dev,
			"slave physical address is incorrect, addr = 0x%x\n",
			paddr);
		return -EINVAL;
	}

	return 0;
}

static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
{
	return (paddr - sadi->slave_pbase + sadi->slave_vbase);
}

static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
{
	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	u32 sts;

	do {
		sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
		if (sts & BIT_FIFO_EMPTY)
			break;

		cpu_relax();
	} while (--timeout);

	if (timeout == 0) {
		dev_err(sadi->dev, "drain write fifo timeout\n");
		return -EBUSY;
	}

	return 0;
}

static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
{
	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
}

static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
{
	int read_timeout = ADI_READ_TIMEOUT;
	u32 val, rd_addr;

	/*
	 * Set the physical register address need to read into RD_CMD register,
	 * then ADI controller will start to transfer automatically.
	 */
	writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);

	/*
	 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
	 * simultaneously when writing read command to register, and the
	 * BIT_RD_CMD_BUSY will be cleared after the read operation is
	 * completed.
	 */
	do {
		val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
		if (!(val & BIT_RD_CMD_BUSY))
			break;

		cpu_relax();
	} while (--read_timeout);

	if (read_timeout == 0) {
		dev_err(sadi->dev, "ADI read timeout\n");
		return -EBUSY;
	}

	/*
	 * The return value includes data and read register address, from bit 0
	 * to bit 15 are data, and from bit 16 to bit 30 are read register
	 * address. Then we can check the returned register address to validate
	 * data.
	 */
	rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;

	if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
		dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
			reg_paddr, val);
		return -EIO;
	}

	*read_val = val & RD_VALUE_MASK;
	return 0;
}

static int sprd_adi_write(struct sprd_adi *sadi, unsigned long reg, u32 val)
{
	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	int ret;

	ret = sprd_adi_drain_fifo(sadi);
	if (ret < 0)
		return ret;

	/*
	 * we should wait for write fifo is empty before writing data to PMIC
	 * registers.
	 */
	do {
		if (!sprd_adi_fifo_is_full(sadi)) {
			writel_relaxed(val, (void __iomem *)reg);
			break;
		}

		cpu_relax();
	} while (--timeout);

	if (timeout == 0) {
		dev_err(sadi->dev, "write fifo is full\n");
		return -EBUSY;
	}

	return 0;
}

static int sprd_adi_transfer_one(struct spi_controller *ctlr,
				 struct spi_device *spi_dev,
				 struct spi_transfer *t)
{
	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
	unsigned long flags, virt_reg;
	u32 phy_reg, val;
	int ret;

	if (t->rx_buf) {
		phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;

		ret = sprd_adi_check_paddr(sadi, phy_reg);
		if (ret)
			return ret;

		ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
						  ADI_HWSPINLOCK_TIMEOUT,
						  &flags);
		if (ret) {
			dev_err(sadi->dev, "get the hw lock failed\n");
			return ret;
		}

		ret = sprd_adi_read(sadi, phy_reg, &val);
		hwspin_unlock_irqrestore(sadi->hwlock, &flags);
		if (ret)
			return ret;

		*(u32 *)t->rx_buf = val;
	} else if (t->tx_buf) {
		u32 *p = (u32 *)t->tx_buf;

		/*
		 * Get the physical register address need to write and convert
		 * the physical address to virtual address. Since we need
		 * virtual register address to write.
		 */
		phy_reg = *p++ + sadi->slave_pbase;
		ret = sprd_adi_check_paddr(sadi, phy_reg);
		if (ret)
			return ret;

		virt_reg = sprd_adi_to_vaddr(sadi, phy_reg);
		val = *p;

		ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
						  ADI_HWSPINLOCK_TIMEOUT,
						  &flags);
		if (ret) {
			dev_err(sadi->dev, "get the hw lock failed\n");
			return ret;
		}

		ret = sprd_adi_write(sadi, virt_reg, val);
		hwspin_unlock_irqrestore(sadi->hwlock, &flags);
		if (ret)
			return ret;
	} else {
		dev_err(sadi->dev, "no buffer for transfer\n");
		return -EINVAL;
	}

	return 0;
}

static void sprd_adi_hw_init(struct sprd_adi *sadi)
{
	struct device_node *np = sadi->dev->of_node;
	int i, size, chn_cnt;
	const __be32 *list;
	u32 tmp;

	/* Address bits select default 12 bits */
	writel_relaxed(0, sadi->base + REG_ADI_CTRL0);

	/* Set all channels as default priority */
	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);

	/* Set clock auto gate mode */
	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
	tmp &= ~BIT_CLK_ALL_ON;
	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);

	/* Set hardware channels setting */
	list = of_get_property(np, "sprd,hw-channels", &size);
	if (!list || !size) {
		dev_info(sadi->dev, "no hw channels setting in node\n");
		return;
	}

	chn_cnt = size / 8;
	for (i = 0; i < chn_cnt; i++) {
		u32 value;
		u32 chn_id = be32_to_cpu(*list++);
		u32 chn_config = be32_to_cpu(*list++);

		/* Channel 0 and 1 are software channels */
		if (chn_id < 2)
			continue;

		writel_relaxed(chn_config, sadi->base +
			       REG_ADI_CHN_ADDR(chn_id));

		if (chn_id < 32) {
			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
			value |= BIT(chn_id);
			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
		} else if (chn_id < ADI_HW_CHNS) {
			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
			value |= BIT(chn_id - 32);
			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
		}
	}
}

static int sprd_adi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spi_controller *ctlr;
	struct sprd_adi *sadi;
	struct resource *res;
	u32 num_chipselect;
	int ret;

	if (!np) {
		dev_err(&pdev->dev, "can not find the adi bus node\n");
		return -ENODEV;
	}

	pdev->id = of_alias_get_id(np, "spi");
	num_chipselect = of_get_child_count(np);

	ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
	if (!ctlr)
		return -ENOMEM;

	dev_set_drvdata(&pdev->dev, ctlr);
	sadi = spi_controller_get_devdata(ctlr);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sadi->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(sadi->base)) {
		ret = PTR_ERR(sadi->base);
		goto put_ctlr;
	}

	sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
	sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
	sadi->ctlr = ctlr;
	sadi->dev = &pdev->dev;
	ret = of_hwspin_lock_get_id(np, 0);
	if (ret < 0) {
		dev_err(&pdev->dev, "can not get the hardware spinlock\n");
		goto put_ctlr;
	}

	sadi->hwlock = hwspin_lock_request_specific(ret);
	if (!sadi->hwlock) {
		ret = -ENXIO;
		goto put_ctlr;
	}

	sprd_adi_hw_init(sadi);

	ctlr->dev.of_node = pdev->dev.of_node;
	ctlr->bus_num = pdev->id;
	ctlr->num_chipselect = num_chipselect;
	ctlr->flags = SPI_MASTER_HALF_DUPLEX;
	ctlr->bits_per_word_mask = 0;
	ctlr->transfer_one = sprd_adi_transfer_one;

	ret = devm_spi_register_controller(&pdev->dev, ctlr);
	if (ret) {
		dev_err(&pdev->dev, "failed to register SPI controller\n");
		goto free_hwlock;
	}

	return 0;

free_hwlock:
	hwspin_lock_free(sadi->hwlock);
put_ctlr:
	spi_controller_put(ctlr);
	return ret;
}

static int sprd_adi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);

	hwspin_lock_free(sadi->hwlock);
	return 0;
}

static const struct of_device_id sprd_adi_of_match[] = {
	{
		.compatible = "sprd,sc9860-adi",
	},
	{ },
};
MODULE_DEVICE_TABLE(of, sprd_adi_of_match);

static struct platform_driver sprd_adi_driver = {
	.driver = {
		.name = "sprd-adi",
		.of_match_table = sprd_adi_of_match,
	},
	.probe = sprd_adi_probe,
	.remove = sprd_adi_remove,
};
module_platform_driver(sprd_adi_driver);

MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
7e2903cb BW	1	/*
	2	* Copyright (C) 2017 Spreadtrum Communications Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
	7	#include <linux/hwspinlock.h>
	8	#include <linux/init.h>
	9	#include <linux/io.h>
	10	#include <linux/kernel.h>
	11	#include <linux/module.h>
	12	#include <linux/of.h>
	13	#include <linux/of_device.h>
	14	#include <linux/platform_device.h>
	15	#include <linux/spi/spi.h>
	16	#include <linux/sizes.h>
	17
	18	/* Registers definitions for ADI controller */
	19	#define REG_ADI_CTRL0 0x4
	20	#define REG_ADI_CHN_PRIL 0x8
	21	#define REG_ADI_CHN_PRIH 0xc
	22	#define REG_ADI_INT_EN 0x10
	23	#define REG_ADI_INT_RAW 0x14
	24	#define REG_ADI_INT_MASK 0x18
	25	#define REG_ADI_INT_CLR 0x1c
	26	#define REG_ADI_GSSI_CFG0 0x20
	27	#define REG_ADI_GSSI_CFG1 0x24
	28	#define REG_ADI_RD_CMD 0x28
	29	#define REG_ADI_RD_DATA 0x2c
	30	#define REG_ADI_ARM_FIFO_STS 0x30
	31	#define REG_ADI_STS 0x34
	32	#define REG_ADI_EVT_FIFO_STS 0x38
	33	#define REG_ADI_ARM_CMD_STS 0x3c
	34	#define REG_ADI_CHN_EN 0x40
	35	#define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
	36	#define REG_ADI_CHN_EN1 0x20c
	37
	38	/* Bits definitions for register REG_ADI_GSSI_CFG0 */
	39	#define BIT_CLK_ALL_ON BIT(30)
	40
	41	/* Bits definitions for register REG_ADI_RD_DATA */
	42	#define BIT_RD_CMD_BUSY BIT(31)
	43	#define RD_ADDR_SHIFT 16
	44	#define RD_VALUE_MASK GENMASK(15, 0)
	45	#define RD_ADDR_MASK GENMASK(30, 16)
	46
	47	/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
	48	#define BIT_FIFO_FULL BIT(11)
	49	#define BIT_FIFO_EMPTY BIT(10)
	50
	51	/*
	52	* ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
	53	* The slave devices address offset is always 0x8000 and size is 4K.
	54	*/
	55	#define ADI_SLAVE_ADDR_SIZE SZ_4K
	56	#define ADI_SLAVE_OFFSET 0x8000
	57
	58	/* Timeout (ms) for the trylock of hardware spinlocks */
	59	#define ADI_HWSPINLOCK_TIMEOUT 5000
	60	/*
	61	* ADI controller has 50 channels including 2 software channels
	62	* and 48 hardware channels.
	63	*/
	64	#define ADI_HW_CHNS 50
65
66	#define ADI_FIFO_DRAIN_TIMEOUT 1000
67	#define ADI_READ_TIMEOUT 2000
68	#define REG_ADDR_LOW_MASK GENMASK(11, 0)
69
70	struct sprd_adi {
71	struct spi_controller *ctlr;
72	struct device *dev;
73	void __iomem *base;
74	struct hwspinlock *hwlock;
75	unsigned long slave_vbase;
76	unsigned long slave_pbase;
77	};
78
79	static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
80	{
81	if (paddr < sadi->slave_pbase \|\| paddr >
82	(sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
83	dev_err(sadi->dev,
84	"slave physical address is incorrect, addr = 0x%x\n",
85	paddr);
86	return -EINVAL;
87	}
88
89	return 0;
90	}
91
92	static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
93	{
94	return (paddr - sadi->slave_pbase + sadi->slave_vbase);
95	}
96
97	static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
98	{
99	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
100	u32 sts;
101
102	do {
103	sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
104	if (sts & BIT_FIFO_EMPTY)
105	break;
106
107	cpu_relax();
108	} while (--timeout);
109
110	if (timeout == 0) {
111	dev_err(sadi->dev, "drain write fifo timeout\n");
112	return -EBUSY;
113	}
114
115	return 0;
116	}
117
118	static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
119	{
120	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
121	}
122
123	static int sprd_adi_read(struct sprd_adi sadi, u32 reg_paddr, u32 read_val)
124	{
125	int read_timeout = ADI_READ_TIMEOUT;
126	u32 val, rd_addr;
127
128	/*
129	* Set the physical register address need to read into RD_CMD register,
130	* then ADI controller will start to transfer automatically.
131	*/
132	writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
133
134	/*
135	* Wait read operation complete, the BIT_RD_CMD_BUSY will be set
136	* simultaneously when writing read command to register, and the
137	* BIT_RD_CMD_BUSY will be cleared after the read operation is
138	* completed.
139	*/
140	do {
141	val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
142	if (!(val & BIT_RD_CMD_BUSY))
143	break;
144
145	cpu_relax();
146	} while (--read_timeout);
147
148	if (read_timeout == 0) {
149	dev_err(sadi->dev, "ADI read timeout\n");
150	return -EBUSY;
151	}
152
153	/*
154	* The return value includes data and read register address, from bit 0
155	* to bit 15 are data, and from bit 16 to bit 30 are read register
156	* address. Then we can check the returned register address to validate
157	* data.
158	*/
159	rd_addr = (val & RD_ADDR_MASK ) >> RD_ADDR_SHIFT;
160
161	if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
162	dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
163	reg_paddr, val);
164	return -EIO;
165	}
166
167	*read_val = val & RD_VALUE_MASK;
168	return 0;
169	}
170
171	static int sprd_adi_write(struct sprd_adi *sadi, unsigned long reg, u32 val)
172	{
173	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
174	int ret;
175
176	ret = sprd_adi_drain_fifo(sadi);
177	if (ret < 0)
178	return ret;
179
180	/*
181	* we should wait for write fifo is empty before writing data to PMIC
182	* registers.
183	*/
184	do {
185	if (!sprd_adi_fifo_is_full(sadi)) {
186	writel_relaxed(val, (void __iomem *)reg);
187	break;
188	}
189
190	cpu_relax();
191	} while (--timeout);
192
193	if (timeout == 0) {
194	dev_err(sadi->dev, "write fifo is full\n");
195	return -EBUSY;
196	}
197
198	return 0;
199	}
200
201	static int sprd_adi_transfer_one(struct spi_controller *ctlr,
202	struct spi_device *spi_dev,
203	struct spi_transfer *t)
204	{
205	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
206	unsigned long flags, virt_reg;
207	u32 phy_reg, val;
208	int ret;
209
210	if (t->rx_buf) {
211	phy_reg = (u32 )t->rx_buf + sadi->slave_pbase;
212
213	ret = sprd_adi_check_paddr(sadi, phy_reg);
214	if (ret)
215	return ret;
216
217	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
218	ADI_HWSPINLOCK_TIMEOUT,
219	&flags);
220	if (ret) {
221	dev_err(sadi->dev, "get the hw lock failed\n");
222	return ret;
223	}
224
225	ret = sprd_adi_read(sadi, phy_reg, &val);
226	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
227	if (ret)
228	return ret;
229
230	(u32 )t->rx_buf = val;
231	} else if (t->tx_buf) {
232	u32 p = (u32 )t->tx_buf;
233
234	/*
235	* Get the physical register address need to write and convert
236	* the physical address to virtual address. Since we need
237	* virtual register address to write.
238	*/
239	phy_reg = *p++ + sadi->slave_pbase;
240	ret = sprd_adi_check_paddr(sadi, phy_reg);
241	if (ret)
242	return ret;
243
244	virt_reg = sprd_adi_to_vaddr(sadi, phy_reg);
245	val = *p;
246
247	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
248	ADI_HWSPINLOCK_TIMEOUT,
249	&flags);
250	if (ret) {
251	dev_err(sadi->dev, "get the hw lock failed\n");
252	return ret;
253	}
254
255	ret = sprd_adi_write(sadi, virt_reg, val);
256	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
257	if (ret)
258	return ret;
259	} else {
260	dev_err(sadi->dev, "no buffer for transfer\n");
261	return -EINVAL;
262	}
263
264	return 0;
265	}
266
267	static void sprd_adi_hw_init(struct sprd_adi *sadi)
268	{
269	struct device_node *np = sadi->dev->of_node;
270	int i, size, chn_cnt;
271	const __be32 *list;
272	u32 tmp;
273
274	/* Address bits select default 12 bits */
275	writel_relaxed(0, sadi->base + REG_ADI_CTRL0);
276
277	/* Set all channels as default priority */
278	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
279	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
280
281	/* Set clock auto gate mode */
282	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
283	tmp &= ~BIT_CLK_ALL_ON;
284	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
285
286	/* Set hardware channels setting */
287	list = of_get_property(np, "sprd,hw-channels", &size);
b0d6e097	288	if (!list \|\| !size) {
7e2903cb BW	289	dev_info(sadi->dev, "no hw channels setting in node\n");
	290	return;
	291	}
	292
	293	chn_cnt = size / 8;
	294	for (i = 0; i < chn_cnt; i++) {
	295	u32 value;
	296	u32 chn_id = be32_to_cpu(*list++);
	297	u32 chn_config = be32_to_cpu(*list++);
	298
	299	/* Channel 0 and 1 are software channels */
	300	if (chn_id < 2)
	301	continue;
	302
	303	writel_relaxed(chn_config, sadi->base +
	304	REG_ADI_CHN_ADDR(chn_id));
	305
54e2fc28	306	if (chn_id < 32) {
7e2903cb BW	307	value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
	308	value \|= BIT(chn_id);
	309	writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
	310	} else if (chn_id < ADI_HW_CHNS) {
	311	value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
	312	value \|= BIT(chn_id - 32);
	313	writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
	314	}
	315	}
	316	}
	317
	318	static int sprd_adi_probe(struct platform_device *pdev)
	319	{
	320	struct device_node *np = pdev->dev.of_node;
	321	struct spi_controller *ctlr;
	322	struct sprd_adi *sadi;
	323	struct resource *res;
	324	u32 num_chipselect;
	325	int ret;
	326
	327	if (!np) {
	328	dev_err(&pdev->dev, "can not find the adi bus node\n");
	329	return -ENODEV;
	330	}
	331
	332	pdev->id = of_alias_get_id(np, "spi");
	333	num_chipselect = of_get_child_count(np);
	334
	335	ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
	336	if (!ctlr)
	337	return -ENOMEM;
	338
	339	dev_set_drvdata(&pdev->dev, ctlr);
	340	sadi = spi_controller_get_devdata(ctlr);
	341
	342	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	343	sadi->base = devm_ioremap_resource(&pdev->dev, res);
04063a01 DC	344	if (IS_ERR(sadi->base)) {
04063a01 DC	345	ret = PTR_ERR(sadi->base);
7e2903cb BW	346	goto put_ctlr;
	347	}
	348
	349	sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
	350	sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
	351	sadi->ctlr = ctlr;
	352	sadi->dev = &pdev->dev;
	353	ret = of_hwspin_lock_get_id(np, 0);
	354	if (ret < 0) {
	355	dev_err(&pdev->dev, "can not get the hardware spinlock\n");
	356	goto put_ctlr;
	357	}
	358
	359	sadi->hwlock = hwspin_lock_request_specific(ret);
	360	if (!sadi->hwlock) {
	361	ret = -ENXIO;
	362	goto put_ctlr;
	363	}
	364
	365	sprd_adi_hw_init(sadi);
	366
	367	ctlr->dev.of_node = pdev->dev.of_node;
	368	ctlr->bus_num = pdev->id;
	369	ctlr->num_chipselect = num_chipselect;
	370	ctlr->flags = SPI_MASTER_HALF_DUPLEX;
	371	ctlr->bits_per_word_mask = 0;
	372	ctlr->transfer_one = sprd_adi_transfer_one;
	373
	374	ret = devm_spi_register_controller(&pdev->dev, ctlr);
	375	if (ret) {
	376	dev_err(&pdev->dev, "failed to register SPI controller\n");
	377	goto free_hwlock;
	378	}
	379
	380	return 0;
	381
	382	free_hwlock:
	383	hwspin_lock_free(sadi->hwlock);
	384	put_ctlr:
	385	spi_controller_put(ctlr);
	386	return ret;
	387	}
	388
	389	static int sprd_adi_remove(struct platform_device *pdev)
	390	{
	391	struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
	392	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
	393
	394	hwspin_lock_free(sadi->hwlock);
	395	return 0;
	396	}
	397
	398	static const struct of_device_id sprd_adi_of_match[] = {
	399	{
	400	.compatible = "sprd,sc9860-adi",
	401	},
	402	{ },
	403	};
	404	MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
	405
	406	static struct platform_driver sprd_adi_driver = {
	407	.driver = {
	408	.name = "sprd-adi",
7e2903cb BW	409	.of_match_table = sprd_adi_of_match,
	410	},
	411	.probe = sprd_adi_probe,
	412	.remove = sprd_adi_remove,
	413	};
	414	module_platform_driver(sprd_adi_driver);
	415
	416	MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
	417	MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
	418	MODULE_LICENSE("GPL v2");