[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-sprd-adi.c

/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#include <linux/delay.h>
#include <linux/hwspinlock.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/spi/spi.h>
#include <linux/sizes.h>

/* Registers definitions for ADI controller */
#define REG_ADI_CTRL0			0x4
#define REG_ADI_CHN_PRIL		0x8
#define REG_ADI_CHN_PRIH		0xc
#define REG_ADI_INT_EN			0x10
#define REG_ADI_INT_RAW			0x14
#define REG_ADI_INT_MASK		0x18
#define REG_ADI_INT_CLR			0x1c
#define REG_ADI_GSSI_CFG0		0x20
#define REG_ADI_GSSI_CFG1		0x24
#define REG_ADI_RD_CMD			0x28
#define REG_ADI_RD_DATA			0x2c
#define REG_ADI_ARM_FIFO_STS		0x30
#define REG_ADI_STS			0x34
#define REG_ADI_EVT_FIFO_STS		0x38
#define REG_ADI_ARM_CMD_STS		0x3c
#define REG_ADI_CHN_EN			0x40
#define REG_ADI_CHN_ADDR(id)		(0x44 + (id - 2) * 4)
#define REG_ADI_CHN_EN1			0x20c

/* Bits definitions for register REG_ADI_GSSI_CFG0 */
#define BIT_CLK_ALL_ON			BIT(30)

/* Bits definitions for register REG_ADI_RD_DATA */
#define BIT_RD_CMD_BUSY			BIT(31)
#define RD_ADDR_SHIFT			16
#define RD_VALUE_MASK			GENMASK(15, 0)
#define RD_ADDR_MASK			GENMASK(30, 16)

/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
#define BIT_FIFO_FULL			BIT(11)
#define BIT_FIFO_EMPTY			BIT(10)

/*
 * ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
 * The slave devices address offset is always 0x8000 and size is 4K.
 */
#define ADI_SLAVE_ADDR_SIZE		SZ_4K
#define ADI_SLAVE_OFFSET		0x8000

/* Timeout (ms) for the trylock of hardware spinlocks */
#define ADI_HWSPINLOCK_TIMEOUT		5000
/*
 * ADI controller has 50 channels including 2 software channels
 * and 48 hardware channels.
 */
#define ADI_HW_CHNS			50

#define ADI_FIFO_DRAIN_TIMEOUT		1000
#define ADI_READ_TIMEOUT		2000
#define REG_ADDR_LOW_MASK		GENMASK(11, 0)

/* Registers definitions for PMIC watchdog controller */
#define REG_WDG_LOAD_LOW		0x80
#define REG_WDG_LOAD_HIGH		0x84
#define REG_WDG_CTRL			0x88
#define REG_WDG_LOCK			0xa0

/* Bits definitions for register REG_WDG_CTRL */
#define BIT_WDG_RUN			BIT(1)
#define BIT_WDG_NEW			BIT(2)
#define BIT_WDG_RST			BIT(3)

/* Registers definitions for PMIC */
#define PMIC_RST_STATUS			0xee8
#define PMIC_MODULE_EN			0xc08
#define PMIC_CLK_EN			0xc18
#define BIT_WDG_EN			BIT(2)

/* Definition of PMIC reset status register */
#define HWRST_STATUS_SECURITY		0x02
#define HWRST_STATUS_RECOVERY		0x20
#define HWRST_STATUS_NORMAL		0x40
#define HWRST_STATUS_ALARM		0x50
#define HWRST_STATUS_SLEEP		0x60
#define HWRST_STATUS_FASTBOOT		0x30
#define HWRST_STATUS_SPECIAL		0x70
#define HWRST_STATUS_PANIC		0x80
#define HWRST_STATUS_CFTREBOOT		0x90
#define HWRST_STATUS_AUTODLOADER	0xa0
#define HWRST_STATUS_IQMODE		0xb0
#define HWRST_STATUS_SPRDISK		0xc0
#define HWRST_STATUS_FACTORYTEST	0xe0
#define HWRST_STATUS_WATCHDOG		0xf0

/* Use default timeout 50 ms that converts to watchdog values */
#define WDG_LOAD_VAL			((50 * 1000) / 32768)
#define WDG_LOAD_MASK			GENMASK(15, 0)
#define WDG_UNLOCK_KEY			0xe551

struct sprd_adi {
	struct spi_controller	*ctlr;
	struct device		*dev;
	void __iomem		*base;
	struct hwspinlock	*hwlock;
	unsigned long		slave_vbase;
	unsigned long		slave_pbase;
	struct notifier_block	restart_handler;
};

static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
{
	if (paddr < sadi->slave_pbase || paddr >
	    (sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
		dev_err(sadi->dev,
			"slave physical address is incorrect, addr = 0x%x\n",
			paddr);
		return -EINVAL;
	}

	return 0;
}

static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
{
	return (paddr - sadi->slave_pbase + sadi->slave_vbase);
}

static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
{
	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	u32 sts;

	do {
		sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
		if (sts & BIT_FIFO_EMPTY)
			break;

		cpu_relax();
	} while (--timeout);

	if (timeout == 0) {
		dev_err(sadi->dev, "drain write fifo timeout\n");
		return -EBUSY;
	}

	return 0;
}

static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
{
	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
}

static int sprd_adi_read(struct sprd_adi *sadi, u32 reg_paddr, u32 *read_val)
{
	int read_timeout = ADI_READ_TIMEOUT;
	unsigned long flags;
	u32 val, rd_addr;
	int ret = 0;

	if (sadi->hwlock) {
		ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
						  ADI_HWSPINLOCK_TIMEOUT,
						  &flags);
		if (ret) {
			dev_err(sadi->dev, "get the hw lock failed\n");
			return ret;
		}
	}

	/*
	 * Set the physical register address need to read into RD_CMD register,
	 * then ADI controller will start to transfer automatically.
	 */
	writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);

	/*
	 * Wait read operation complete, the BIT_RD_CMD_BUSY will be set
	 * simultaneously when writing read command to register, and the
	 * BIT_RD_CMD_BUSY will be cleared after the read operation is
	 * completed.
	 */
	do {
		val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
		if (!(val & BIT_RD_CMD_BUSY))
			break;

		cpu_relax();
	} while (--read_timeout);

	if (read_timeout == 0) {
		dev_err(sadi->dev, "ADI read timeout\n");
		ret = -EBUSY;
		goto out;
	}

	/*
	 * The return value includes data and read register address, from bit 0
	 * to bit 15 are data, and from bit 16 to bit 30 are read register
	 * address. Then we can check the returned register address to validate
	 * data.
	 */
	rd_addr = (val & RD_ADDR_MASK) >> RD_ADDR_SHIFT;

	if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
		dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
			reg_paddr, val);
		ret = -EIO;
		goto out;
	}

	*read_val = val & RD_VALUE_MASK;

out:
	if (sadi->hwlock)
		hwspin_unlock_irqrestore(sadi->hwlock, &flags);
	return ret;
}

static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
{
	unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	unsigned long flags;
	int ret;

	if (sadi->hwlock) {
		ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
						  ADI_HWSPINLOCK_TIMEOUT,
						  &flags);
		if (ret) {
			dev_err(sadi->dev, "get the hw lock failed\n");
			return ret;
		}
	}

	ret = sprd_adi_drain_fifo(sadi);
	if (ret < 0)
		goto out;

	/*
	 * we should wait for write fifo is empty before writing data to PMIC
	 * registers.
	 */
	do {
		if (!sprd_adi_fifo_is_full(sadi)) {
			writel_relaxed(val, (void __iomem *)reg);
			break;
		}

		cpu_relax();
	} while (--timeout);

	if (timeout == 0) {
		dev_err(sadi->dev, "write fifo is full\n");
		ret = -EBUSY;
	}

out:
	if (sadi->hwlock)
		hwspin_unlock_irqrestore(sadi->hwlock, &flags);
	return ret;
}

static int sprd_adi_transfer_one(struct spi_controller *ctlr,
				 struct spi_device *spi_dev,
				 struct spi_transfer *t)
{
	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
	u32 phy_reg, val;
	int ret;

	if (t->rx_buf) {
		phy_reg = *(u32 *)t->rx_buf + sadi->slave_pbase;

		ret = sprd_adi_check_paddr(sadi, phy_reg);
		if (ret)
			return ret;

		ret = sprd_adi_read(sadi, phy_reg, &val);
		if (ret)
			return ret;

		*(u32 *)t->rx_buf = val;
	} else if (t->tx_buf) {
		u32 *p = (u32 *)t->tx_buf;

		/*
		 * Get the physical register address need to write and convert
		 * the physical address to virtual address. Since we need
		 * virtual register address to write.
		 */
		phy_reg = *p++ + sadi->slave_pbase;
		ret = sprd_adi_check_paddr(sadi, phy_reg);
		if (ret)
			return ret;

		val = *p;
		ret = sprd_adi_write(sadi, phy_reg, val);
		if (ret)
			return ret;
	} else {
		dev_err(sadi->dev, "no buffer for transfer\n");
		return -EINVAL;
	}

	return 0;
}

static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
{
#if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
	u32 val;

	/* Set default watchdog reboot mode */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
	val |= HWRST_STATUS_WATCHDOG;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
#endif
}

static int sprd_adi_restart_handler(struct notifier_block *this,
				    unsigned long mode, void *cmd)
{
	struct sprd_adi *sadi = container_of(this, struct sprd_adi,
					     restart_handler);
	u32 val, reboot_mode = 0;

	if (!cmd)
		reboot_mode = HWRST_STATUS_NORMAL;
	else if (!strncmp(cmd, "recovery", 8))
		reboot_mode = HWRST_STATUS_RECOVERY;
	else if (!strncmp(cmd, "alarm", 5))
		reboot_mode = HWRST_STATUS_ALARM;
	else if (!strncmp(cmd, "fastsleep", 9))
		reboot_mode = HWRST_STATUS_SLEEP;
	else if (!strncmp(cmd, "bootloader", 10))
		reboot_mode = HWRST_STATUS_FASTBOOT;
	else if (!strncmp(cmd, "panic", 5))
		reboot_mode = HWRST_STATUS_PANIC;
	else if (!strncmp(cmd, "special", 7))
		reboot_mode = HWRST_STATUS_SPECIAL;
	else if (!strncmp(cmd, "cftreboot", 9))
		reboot_mode = HWRST_STATUS_CFTREBOOT;
	else if (!strncmp(cmd, "autodloader", 11))
		reboot_mode = HWRST_STATUS_AUTODLOADER;
	else if (!strncmp(cmd, "iqmode", 6))
		reboot_mode = HWRST_STATUS_IQMODE;
	else if (!strncmp(cmd, "sprdisk", 7))
		reboot_mode = HWRST_STATUS_SPRDISK;
	else if (!strncmp(cmd, "tospanic", 8))
		reboot_mode = HWRST_STATUS_SECURITY;
	else if (!strncmp(cmd, "factorytest", 11))
		reboot_mode = HWRST_STATUS_FACTORYTEST;
	else
		reboot_mode = HWRST_STATUS_NORMAL;

	/* Record the reboot mode */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
	val &= ~HWRST_STATUS_WATCHDOG;
	val |= reboot_mode;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);

	/* Enable the interface clock of the watchdog */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
	val |= BIT_WDG_EN;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);

	/* Enable the work clock of the watchdog */
	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
	val |= BIT_WDG_EN;
	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);

	/* Unlock the watchdog */
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);

	sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
	val |= BIT_WDG_NEW;
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);

	/* Load the watchdog timeout value, 50ms is always enough. */
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
		       WDG_LOAD_VAL & WDG_LOAD_MASK);

	/* Start the watchdog to reset system */
	sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
	val |= BIT_WDG_RUN | BIT_WDG_RST;
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);

	/* Lock the watchdog */
	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, ~WDG_UNLOCK_KEY);

	mdelay(1000);

	dev_emerg(sadi->dev, "Unable to restart system\n");
	return NOTIFY_DONE;
}

static void sprd_adi_hw_init(struct sprd_adi *sadi)
{
	struct device_node *np = sadi->dev->of_node;
	int i, size, chn_cnt;
	const __be32 *list;
	u32 tmp;

	/* Set all channels as default priority */
	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);

	/* Set clock auto gate mode */
	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
	tmp &= ~BIT_CLK_ALL_ON;
	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);

	/* Set hardware channels setting */
	list = of_get_property(np, "sprd,hw-channels", &size);
	if (!list || !size) {
		dev_info(sadi->dev, "no hw channels setting in node\n");
		return;
	}

	chn_cnt = size / 8;
	for (i = 0; i < chn_cnt; i++) {
		u32 value;
		u32 chn_id = be32_to_cpu(*list++);
		u32 chn_config = be32_to_cpu(*list++);

		/* Channel 0 and 1 are software channels */
		if (chn_id < 2)
			continue;

		writel_relaxed(chn_config, sadi->base +
			       REG_ADI_CHN_ADDR(chn_id));

		if (chn_id < 32) {
			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
			value |= BIT(chn_id);
			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
		} else if (chn_id < ADI_HW_CHNS) {
			value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
			value |= BIT(chn_id - 32);
			writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
		}
	}
}

static int sprd_adi_probe(struct platform_device *pdev)
{
	struct device_node *np = pdev->dev.of_node;
	struct spi_controller *ctlr;
	struct sprd_adi *sadi;
	struct resource *res;
	u32 num_chipselect;
	int ret;

	if (!np) {
		dev_err(&pdev->dev, "can not find the adi bus node\n");
		return -ENODEV;
	}

	pdev->id = of_alias_get_id(np, "spi");
	num_chipselect = of_get_child_count(np);

	ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
	if (!ctlr)
		return -ENOMEM;

	dev_set_drvdata(&pdev->dev, ctlr);
	sadi = spi_controller_get_devdata(ctlr);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sadi->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(sadi->base)) {
		ret = PTR_ERR(sadi->base);
		goto put_ctlr;
	}

	sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
	sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
	sadi->ctlr = ctlr;
	sadi->dev = &pdev->dev;
	ret = of_hwspin_lock_get_id(np, 0);
	if (ret > 0 || (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
		sadi->hwlock =
			devm_hwspin_lock_request_specific(&pdev->dev, ret);
		if (!sadi->hwlock) {
			ret = -ENXIO;
			goto put_ctlr;
		}
	} else {
		switch (ret) {
		case -ENOENT:
			dev_info(&pdev->dev, "no hardware spinlock supplied\n");
			break;
		default:
			dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n");
			goto put_ctlr;
		}
	}

	sprd_adi_hw_init(sadi);
	sprd_adi_set_wdt_rst_mode(sadi);

	ctlr->dev.of_node = pdev->dev.of_node;
	ctlr->bus_num = pdev->id;
	ctlr->num_chipselect = num_chipselect;
	ctlr->flags = SPI_MASTER_HALF_DUPLEX;
	ctlr->bits_per_word_mask = 0;
	ctlr->transfer_one = sprd_adi_transfer_one;

	ret = devm_spi_register_controller(&pdev->dev, ctlr);
	if (ret) {
		dev_err(&pdev->dev, "failed to register SPI controller\n");
		goto put_ctlr;
	}

	sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
	sadi->restart_handler.priority = 128;
	ret = register_restart_handler(&sadi->restart_handler);
	if (ret) {
		dev_err(&pdev->dev, "can not register restart handler\n");
		goto put_ctlr;
	}

	return 0;

put_ctlr:
	spi_controller_put(ctlr);
	return ret;
}

static int sprd_adi_remove(struct platform_device *pdev)
{
	struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);

	unregister_restart_handler(&sadi->restart_handler);
	return 0;
}

static const struct of_device_id sprd_adi_of_match[] = {
	{
		.compatible = "sprd,sc9860-adi",
	},
	{ },
};
MODULE_DEVICE_TABLE(of, sprd_adi_of_match);

static struct platform_driver sprd_adi_driver = {
	.driver = {
		.name = "sprd-adi",
		.of_match_table = sprd_adi_of_match,
	},
	.probe = sprd_adi_probe,
	.remove = sprd_adi_remove,
};
module_platform_driver(sprd_adi_driver);

MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
7e2903cb BW	1	/*
	2	* Copyright (C) 2017 Spreadtrum Communications Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
ac177501	7	#include <linux/delay.h>
7e2903cb BW	8	#include <linux/hwspinlock.h>
	9	#include <linux/init.h>
	10	#include <linux/io.h>
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/of.h>
	14	#include <linux/of_device.h>
	15	#include <linux/platform_device.h>
ac177501	16	#include <linux/reboot.h>
7e2903cb BW	17	#include <linux/spi/spi.h>
	18	#include <linux/sizes.h>
	19
	20	/* Registers definitions for ADI controller */
	21	#define REG_ADI_CTRL0 0x4
	22	#define REG_ADI_CHN_PRIL 0x8
	23	#define REG_ADI_CHN_PRIH 0xc
	24	#define REG_ADI_INT_EN 0x10
	25	#define REG_ADI_INT_RAW 0x14
	26	#define REG_ADI_INT_MASK 0x18
	27	#define REG_ADI_INT_CLR 0x1c
	28	#define REG_ADI_GSSI_CFG0 0x20
	29	#define REG_ADI_GSSI_CFG1 0x24
	30	#define REG_ADI_RD_CMD 0x28
	31	#define REG_ADI_RD_DATA 0x2c
	32	#define REG_ADI_ARM_FIFO_STS 0x30
	33	#define REG_ADI_STS 0x34
	34	#define REG_ADI_EVT_FIFO_STS 0x38
	35	#define REG_ADI_ARM_CMD_STS 0x3c
	36	#define REG_ADI_CHN_EN 0x40
	37	#define REG_ADI_CHN_ADDR(id) (0x44 + (id - 2) * 4)
	38	#define REG_ADI_CHN_EN1 0x20c
	39
	40	/* Bits definitions for register REG_ADI_GSSI_CFG0 */
	41	#define BIT_CLK_ALL_ON BIT(30)
	42
	43	/* Bits definitions for register REG_ADI_RD_DATA */
	44	#define BIT_RD_CMD_BUSY BIT(31)
	45	#define RD_ADDR_SHIFT 16
	46	#define RD_VALUE_MASK GENMASK(15, 0)
	47	#define RD_ADDR_MASK GENMASK(30, 16)
	48
	49	/* Bits definitions for register REG_ADI_ARM_FIFO_STS */
	50	#define BIT_FIFO_FULL BIT(11)
	51	#define BIT_FIFO_EMPTY BIT(10)
	52
	53	/*
	54	* ADI slave devices include RTC, ADC, regulator, charger, thermal and so on.
	55	* The slave devices address offset is always 0x8000 and size is 4K.
	56	*/
	57	#define ADI_SLAVE_ADDR_SIZE SZ_4K
	58	#define ADI_SLAVE_OFFSET 0x8000
	59
	60	/* Timeout (ms) for the trylock of hardware spinlocks */
	61	#define ADI_HWSPINLOCK_TIMEOUT 5000
	62	/*
	63	* ADI controller has 50 channels including 2 software channels
	64	* and 48 hardware channels.
	65	*/
	66	#define ADI_HW_CHNS 50
	67
	68	#define ADI_FIFO_DRAIN_TIMEOUT 1000
	69	#define ADI_READ_TIMEOUT 2000
	70	#define REG_ADDR_LOW_MASK GENMASK(11, 0)
	71
ac177501 BW	72	/* Registers definitions for PMIC watchdog controller */
	73	#define REG_WDG_LOAD_LOW 0x80
	74	#define REG_WDG_LOAD_HIGH 0x84
	75	#define REG_WDG_CTRL 0x88
	76	#define REG_WDG_LOCK 0xa0
	77
	78	/* Bits definitions for register REG_WDG_CTRL */
	79	#define BIT_WDG_RUN BIT(1)
1d00a67c	80	#define BIT_WDG_NEW BIT(2)
ac177501 BW	81	#define BIT_WDG_RST BIT(3)
	82
	83	/* Registers definitions for PMIC */
	84	#define PMIC_RST_STATUS 0xee8
	85	#define PMIC_MODULE_EN 0xc08
	86	#define PMIC_CLK_EN 0xc18
	87	#define BIT_WDG_EN BIT(2)
	88
	89	/* Definition of PMIC reset status register */
cc6b3431	90	#define HWRST_STATUS_SECURITY 0x02
ac177501 BW	91	#define HWRST_STATUS_RECOVERY 0x20
	92	#define HWRST_STATUS_NORMAL 0x40
	93	#define HWRST_STATUS_ALARM 0x50
	94	#define HWRST_STATUS_SLEEP 0x60
	95	#define HWRST_STATUS_FASTBOOT 0x30
	96	#define HWRST_STATUS_SPECIAL 0x70
	97	#define HWRST_STATUS_PANIC 0x80
	98	#define HWRST_STATUS_CFTREBOOT 0x90
	99	#define HWRST_STATUS_AUTODLOADER 0xa0
	100	#define HWRST_STATUS_IQMODE 0xb0
	101	#define HWRST_STATUS_SPRDISK 0xc0
9d9aa1cc	102	#define HWRST_STATUS_FACTORYTEST 0xe0
e6d722ca	103	#define HWRST_STATUS_WATCHDOG 0xf0
ac177501 BW	104
	105	/* Use default timeout 50 ms that converts to watchdog values */
	106	#define WDG_LOAD_VAL ((50 * 1000) / 32768)
	107	#define WDG_LOAD_MASK GENMASK(15, 0)
	108	#define WDG_UNLOCK_KEY 0xe551
	109
7e2903cb BW	110	struct sprd_adi {
	111	struct spi_controller *ctlr;
	112	struct device *dev;
	113	void __iomem *base;
	114	struct hwspinlock *hwlock;
	115	unsigned long slave_vbase;
	116	unsigned long slave_pbase;
ac177501	117	struct notifier_block restart_handler;
7e2903cb BW	118	};
	119
	120	static int sprd_adi_check_paddr(struct sprd_adi *sadi, u32 paddr)
	121	{
	122	if (paddr < sadi->slave_pbase \|\| paddr >
	123	(sadi->slave_pbase + ADI_SLAVE_ADDR_SIZE)) {
	124	dev_err(sadi->dev,
	125	"slave physical address is incorrect, addr = 0x%x\n",
	126	paddr);
	127	return -EINVAL;
	128	}
	129
	130	return 0;
	131	}
	132
	133	static unsigned long sprd_adi_to_vaddr(struct sprd_adi *sadi, u32 paddr)
	134	{
	135	return (paddr - sadi->slave_pbase + sadi->slave_vbase);
	136	}
	137
	138	static int sprd_adi_drain_fifo(struct sprd_adi *sadi)
	139	{
	140	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
	141	u32 sts;
	142
	143	do {
	144	sts = readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS);
	145	if (sts & BIT_FIFO_EMPTY)
	146	break;
	147
	148	cpu_relax();
	149	} while (--timeout);
	150
	151	if (timeout == 0) {
	152	dev_err(sadi->dev, "drain write fifo timeout\n");
	153	return -EBUSY;
	154	}
	155
	156	return 0;
	157	}
	158
	159	static int sprd_adi_fifo_is_full(struct sprd_adi *sadi)
	160	{
	161	return readl_relaxed(sadi->base + REG_ADI_ARM_FIFO_STS) & BIT_FIFO_FULL;
	162	}
	163
	164	static int sprd_adi_read(struct sprd_adi sadi, u32 reg_paddr, u32 read_val)
	165	{
	166	int read_timeout = ADI_READ_TIMEOUT;
a61aa683	167	unsigned long flags;
7e2903cb	168	u32 val, rd_addr;
f9adf61e BW	169	int ret = 0;
	170
	171	if (sadi->hwlock) {
	172	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
	173	ADI_HWSPINLOCK_TIMEOUT,
	174	&flags);
	175	if (ret) {
	176	dev_err(sadi->dev, "get the hw lock failed\n");
	177	return ret;
	178	}
a61aa683	179	}
7e2903cb BW	180
	181	/*
	182	* Set the physical register address need to read into RD_CMD register,
	183	* then ADI controller will start to transfer automatically.
	184	*/
	185	writel_relaxed(reg_paddr, sadi->base + REG_ADI_RD_CMD);
	186
	187	/*
	188	* Wait read operation complete, the BIT_RD_CMD_BUSY will be set
	189	* simultaneously when writing read command to register, and the
	190	* BIT_RD_CMD_BUSY will be cleared after the read operation is
	191	* completed.
	192	*/
	193	do {
	194	val = readl_relaxed(sadi->base + REG_ADI_RD_DATA);
	195	if (!(val & BIT_RD_CMD_BUSY))
	196	break;
	197
	198	cpu_relax();
	199	} while (--read_timeout);
	200
	201	if (read_timeout == 0) {
	202	dev_err(sadi->dev, "ADI read timeout\n");
a61aa683 BW	203	ret = -EBUSY;
a61aa683 BW	204	goto out;
7e2903cb BW	205	}
	206
	207	/*
	208	* The return value includes data and read register address, from bit 0
	209	* to bit 15 are data, and from bit 16 to bit 30 are read register
	210	* address. Then we can check the returned register address to validate
	211	* data.
	212	*/
e13a870f	213	rd_addr = (val & RD_ADDR_MASK) >> RD_ADDR_SHIFT;
7e2903cb BW	214
	215	if (rd_addr != (reg_paddr & REG_ADDR_LOW_MASK)) {
	216	dev_err(sadi->dev, "read error, reg addr = 0x%x, val = 0x%x\n",
	217	reg_paddr, val);
a61aa683 BW	218	ret = -EIO;
a61aa683 BW	219	goto out;
7e2903cb BW	220	}
	221
	222	*read_val = val & RD_VALUE_MASK;
a61aa683 BW	223
a61aa683 BW	224	out:
f9adf61e BW	225	if (sadi->hwlock)
f9adf61e BW	226	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
a61aa683	227	return ret;
7e2903cb BW	228	}
7e2903cb BW	229
a61aa683	230	static int sprd_adi_write(struct sprd_adi *sadi, u32 reg_paddr, u32 val)
7e2903cb	231	{
a61aa683	232	unsigned long reg = sprd_adi_to_vaddr(sadi, reg_paddr);
7e2903cb	233	u32 timeout = ADI_FIFO_DRAIN_TIMEOUT;
a61aa683	234	unsigned long flags;
7e2903cb BW	235	int ret;
7e2903cb BW	236
f9adf61e BW	237	if (sadi->hwlock) {
	238	ret = hwspin_lock_timeout_irqsave(sadi->hwlock,
	239	ADI_HWSPINLOCK_TIMEOUT,
	240	&flags);
	241	if (ret) {
	242	dev_err(sadi->dev, "get the hw lock failed\n");
	243	return ret;
	244	}
a61aa683 BW	245	}
a61aa683 BW	246
7e2903cb BW	247	ret = sprd_adi_drain_fifo(sadi);
7e2903cb BW	248	if (ret < 0)
a61aa683	249	goto out;
7e2903cb BW	250
	251	/*
	252	* we should wait for write fifo is empty before writing data to PMIC
	253	* registers.
	254	*/
	255	do {
	256	if (!sprd_adi_fifo_is_full(sadi)) {
	257	writel_relaxed(val, (void __iomem *)reg);
	258	break;
	259	}
	260
	261	cpu_relax();
	262	} while (--timeout);
	263
	264	if (timeout == 0) {
	265	dev_err(sadi->dev, "write fifo is full\n");
a61aa683	266	ret = -EBUSY;
7e2903cb BW	267	}
7e2903cb BW	268
a61aa683	269	out:
f9adf61e BW	270	if (sadi->hwlock)
f9adf61e BW	271	hwspin_unlock_irqrestore(sadi->hwlock, &flags);
a61aa683	272	return ret;
7e2903cb BW	273	}
	274
	275	static int sprd_adi_transfer_one(struct spi_controller *ctlr,
	276	struct spi_device *spi_dev,
	277	struct spi_transfer *t)
	278	{
	279	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
7e2903cb BW	280	u32 phy_reg, val;
	281	int ret;
	282
	283	if (t->rx_buf) {
	284	phy_reg = (u32 )t->rx_buf + sadi->slave_pbase;
	285
	286	ret = sprd_adi_check_paddr(sadi, phy_reg);
	287	if (ret)
	288	return ret;
	289
7e2903cb	290	ret = sprd_adi_read(sadi, phy_reg, &val);
7e2903cb BW	291	if (ret)
	292	return ret;
	293
	294	(u32 )t->rx_buf = val;
	295	} else if (t->tx_buf) {
	296	u32 p = (u32 )t->tx_buf;
	297
	298	/*
	299	* Get the physical register address need to write and convert
	300	* the physical address to virtual address. Since we need
	301	* virtual register address to write.
	302	*/
	303	phy_reg = *p++ + sadi->slave_pbase;
	304	ret = sprd_adi_check_paddr(sadi, phy_reg);
	305	if (ret)
	306	return ret;
	307
7e2903cb	308	val = *p;
a61aa683	309	ret = sprd_adi_write(sadi, phy_reg, val);
7e2903cb BW	310	if (ret)
	311	return ret;
	312	} else {
	313	dev_err(sadi->dev, "no buffer for transfer\n");
	314	return -EINVAL;
	315	}
	316
	317	return 0;
	318	}
	319
e6d722ca SZ	320	static void sprd_adi_set_wdt_rst_mode(struct sprd_adi *sadi)
e6d722ca SZ	321	{
bb4bf8d2	322	#if IS_ENABLED(CONFIG_SPRD_WATCHDOG)
e6d722ca SZ	323	u32 val;
	324
	325	/* Set default watchdog reboot mode */
	326	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
	327	val \|= HWRST_STATUS_WATCHDOG;
	328	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
	329	#endif
	330	}
	331
ac177501 BW	332	static int sprd_adi_restart_handler(struct notifier_block *this,
	333	unsigned long mode, void *cmd)
	334	{
	335	struct sprd_adi *sadi = container_of(this, struct sprd_adi,
	336	restart_handler);
	337	u32 val, reboot_mode = 0;
	338
	339	if (!cmd)
	340	reboot_mode = HWRST_STATUS_NORMAL;
	341	else if (!strncmp(cmd, "recovery", 8))
	342	reboot_mode = HWRST_STATUS_RECOVERY;
	343	else if (!strncmp(cmd, "alarm", 5))
	344	reboot_mode = HWRST_STATUS_ALARM;
	345	else if (!strncmp(cmd, "fastsleep", 9))
	346	reboot_mode = HWRST_STATUS_SLEEP;
	347	else if (!strncmp(cmd, "bootloader", 10))
	348	reboot_mode = HWRST_STATUS_FASTBOOT;
	349	else if (!strncmp(cmd, "panic", 5))
	350	reboot_mode = HWRST_STATUS_PANIC;
	351	else if (!strncmp(cmd, "special", 7))
	352	reboot_mode = HWRST_STATUS_SPECIAL;
	353	else if (!strncmp(cmd, "cftreboot", 9))
	354	reboot_mode = HWRST_STATUS_CFTREBOOT;
	355	else if (!strncmp(cmd, "autodloader", 11))
	356	reboot_mode = HWRST_STATUS_AUTODLOADER;
	357	else if (!strncmp(cmd, "iqmode", 6))
	358	reboot_mode = HWRST_STATUS_IQMODE;
	359	else if (!strncmp(cmd, "sprdisk", 7))
	360	reboot_mode = HWRST_STATUS_SPRDISK;
cc6b3431 CW	361	else if (!strncmp(cmd, "tospanic", 8))
cc6b3431 CW	362	reboot_mode = HWRST_STATUS_SECURITY;
9d9aa1cc SZ	363	else if (!strncmp(cmd, "factorytest", 11))
9d9aa1cc SZ	364	reboot_mode = HWRST_STATUS_FACTORYTEST;
ac177501 BW	365	else
	366	reboot_mode = HWRST_STATUS_NORMAL;
	367
	368	/* Record the reboot mode */
	369	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_RST_STATUS, &val);
e6d722ca	370	val &= ~HWRST_STATUS_WATCHDOG;
ac177501 BW	371	val \|= reboot_mode;
	372	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_RST_STATUS, val);
	373
	374	/* Enable the interface clock of the watchdog */
	375	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_MODULE_EN, &val);
	376	val \|= BIT_WDG_EN;
	377	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_MODULE_EN, val);
	378
	379	/* Enable the work clock of the watchdog */
	380	sprd_adi_read(sadi, sadi->slave_pbase + PMIC_CLK_EN, &val);
	381	val \|= BIT_WDG_EN;
	382	sprd_adi_write(sadi, sadi->slave_pbase + PMIC_CLK_EN, val);
	383
	384	/* Unlock the watchdog */
	385	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, WDG_UNLOCK_KEY);
	386
1d00a67c LX	387	sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
	388	val \|= BIT_WDG_NEW;
	389	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
	390
ac177501	391	/* Load the watchdog timeout value, 50ms is always enough. */
8bdd79da	392	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_HIGH, 0);
ac177501 BW	393	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOAD_LOW,
ac177501 BW	394	WDG_LOAD_VAL & WDG_LOAD_MASK);
ac177501 BW	395
	396	/* Start the watchdog to reset system */
	397	sprd_adi_read(sadi, sadi->slave_pbase + REG_WDG_CTRL, &val);
	398	val \|= BIT_WDG_RUN \| BIT_WDG_RST;
	399	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_CTRL, val);
	400
91ea1d70 LX	401	/* Lock the watchdog */
	402	sprd_adi_write(sadi, sadi->slave_pbase + REG_WDG_LOCK, ~WDG_UNLOCK_KEY);
	403
ac177501 BW	404	mdelay(1000);
	405
	406	dev_emerg(sadi->dev, "Unable to restart system\n");
	407	return NOTIFY_DONE;
	408	}
	409
7e2903cb BW	410	static void sprd_adi_hw_init(struct sprd_adi *sadi)
	411	{
	412	struct device_node *np = sadi->dev->of_node;
	413	int i, size, chn_cnt;
	414	const __be32 *list;
	415	u32 tmp;
	416
7e2903cb BW	417	/* Set all channels as default priority */
	418	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIL);
	419	writel_relaxed(0, sadi->base + REG_ADI_CHN_PRIH);
	420
	421	/* Set clock auto gate mode */
	422	tmp = readl_relaxed(sadi->base + REG_ADI_GSSI_CFG0);
	423	tmp &= ~BIT_CLK_ALL_ON;
	424	writel_relaxed(tmp, sadi->base + REG_ADI_GSSI_CFG0);
	425
	426	/* Set hardware channels setting */
	427	list = of_get_property(np, "sprd,hw-channels", &size);
b0d6e097	428	if (!list \|\| !size) {
7e2903cb BW	429	dev_info(sadi->dev, "no hw channels setting in node\n");
	430	return;
	431	}
	432
	433	chn_cnt = size / 8;
	434	for (i = 0; i < chn_cnt; i++) {
	435	u32 value;
	436	u32 chn_id = be32_to_cpu(*list++);
	437	u32 chn_config = be32_to_cpu(*list++);
	438
	439	/* Channel 0 and 1 are software channels */
	440	if (chn_id < 2)
	441	continue;
	442
	443	writel_relaxed(chn_config, sadi->base +
	444	REG_ADI_CHN_ADDR(chn_id));
	445
54e2fc28	446	if (chn_id < 32) {
7e2903cb BW	447	value = readl_relaxed(sadi->base + REG_ADI_CHN_EN);
	448	value \|= BIT(chn_id);
	449	writel_relaxed(value, sadi->base + REG_ADI_CHN_EN);
	450	} else if (chn_id < ADI_HW_CHNS) {
	451	value = readl_relaxed(sadi->base + REG_ADI_CHN_EN1);
	452	value \|= BIT(chn_id - 32);
	453	writel_relaxed(value, sadi->base + REG_ADI_CHN_EN1);
	454	}
	455	}
	456	}
	457
	458	static int sprd_adi_probe(struct platform_device *pdev)
	459	{
	460	struct device_node *np = pdev->dev.of_node;
	461	struct spi_controller *ctlr;
	462	struct sprd_adi *sadi;
	463	struct resource *res;
	464	u32 num_chipselect;
	465	int ret;
	466
	467	if (!np) {
	468	dev_err(&pdev->dev, "can not find the adi bus node\n");
	469	return -ENODEV;
	470	}
	471
	472	pdev->id = of_alias_get_id(np, "spi");
	473	num_chipselect = of_get_child_count(np);
	474
	475	ctlr = spi_alloc_master(&pdev->dev, sizeof(struct sprd_adi));
	476	if (!ctlr)
	477	return -ENOMEM;
	478
	479	dev_set_drvdata(&pdev->dev, ctlr);
	480	sadi = spi_controller_get_devdata(ctlr);
	481
	482	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	483	sadi->base = devm_ioremap_resource(&pdev->dev, res);
04063a01 DC	484	if (IS_ERR(sadi->base)) {
04063a01 DC	485	ret = PTR_ERR(sadi->base);
7e2903cb BW	486	goto put_ctlr;
	487	}
	488
	489	sadi->slave_vbase = (unsigned long)sadi->base + ADI_SLAVE_OFFSET;
	490	sadi->slave_pbase = res->start + ADI_SLAVE_OFFSET;
	491	sadi->ctlr = ctlr;
	492	sadi->dev = &pdev->dev;
f9adf61e BW	493	ret = of_hwspin_lock_get_id(np, 0);
	494	if (ret > 0 \|\| (IS_ENABLED(CONFIG_HWSPINLOCK) && ret == 0)) {
	495	sadi->hwlock =
	496	devm_hwspin_lock_request_specific(&pdev->dev, ret);
	497	if (!sadi->hwlock) {
	498	ret = -ENXIO;
	499	goto put_ctlr;
	500	}
	501	} else {
	502	switch (ret) {
	503	case -ENOENT:
	504	dev_info(&pdev->dev, "no hardware spinlock supplied\n");
	505	break;
	506	default:
9d99e558	507	dev_err_probe(&pdev->dev, ret, "failed to find hwlock id\n");
f9adf61e BW	508	goto put_ctlr;
f9adf61e BW	509	}
7e2903cb BW	510	}
	511
	512	sprd_adi_hw_init(sadi);
e6d722ca	513	sprd_adi_set_wdt_rst_mode(sadi);
7e2903cb BW	514
	515	ctlr->dev.of_node = pdev->dev.of_node;
	516	ctlr->bus_num = pdev->id;
	517	ctlr->num_chipselect = num_chipselect;
	518	ctlr->flags = SPI_MASTER_HALF_DUPLEX;
	519	ctlr->bits_per_word_mask = 0;
	520	ctlr->transfer_one = sprd_adi_transfer_one;
	521
	522	ret = devm_spi_register_controller(&pdev->dev, ctlr);
	523	if (ret) {
	524	dev_err(&pdev->dev, "failed to register SPI controller\n");
c8d04989	525	goto put_ctlr;
7e2903cb BW	526	}
7e2903cb BW	527
ac177501 BW	528	sadi->restart_handler.notifier_call = sprd_adi_restart_handler;
	529	sadi->restart_handler.priority = 128;
	530	ret = register_restart_handler(&sadi->restart_handler);
	531	if (ret) {
	532	dev_err(&pdev->dev, "can not register restart handler\n");
c8d04989	533	goto put_ctlr;
ac177501 BW	534	}
ac177501 BW	535
7e2903cb BW	536	return 0;
7e2903cb BW	537
7e2903cb BW	538	put_ctlr:
	539	spi_controller_put(ctlr);
	540	return ret;
	541	}
	542
	543	static int sprd_adi_remove(struct platform_device *pdev)
	544	{
	545	struct spi_controller *ctlr = dev_get_drvdata(&pdev->dev);
	546	struct sprd_adi *sadi = spi_controller_get_devdata(ctlr);
	547
ac177501	548	unregister_restart_handler(&sadi->restart_handler);
7e2903cb BW	549	return 0;
	550	}
	551
	552	static const struct of_device_id sprd_adi_of_match[] = {
	553	{
	554	.compatible = "sprd,sc9860-adi",
	555	},
	556	{ },
	557	};
	558	MODULE_DEVICE_TABLE(of, sprd_adi_of_match);
	559
	560	static struct platform_driver sprd_adi_driver = {
	561	.driver = {
	562	.name = "sprd-adi",
7e2903cb BW	563	.of_match_table = sprd_adi_of_match,
	564	},
	565	.probe = sprd_adi_probe,
	566	.remove = sprd_adi_remove,
	567	};
	568	module_platform_driver(sprd_adi_driver);
	569
	570	MODULE_DESCRIPTION("Spreadtrum ADI Controller Driver");
	571	MODULE_AUTHOR("Baolin Wang <Baolin.Wang@spreadtrum.com>");
	572	MODULE_LICENSE("GPL v2");