[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-stm32-qspi.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 */
#include <linux/bitfield.h>
#include <linux/clk.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
#include <linux/sizes.h>
#include <linux/spi/spi-mem.h>

#define QSPI_CR			0x00
#define CR_EN			BIT(0)
#define CR_ABORT		BIT(1)
#define CR_DMAEN		BIT(2)
#define CR_TCEN			BIT(3)
#define CR_SSHIFT		BIT(4)
#define CR_DFM			BIT(6)
#define CR_FSEL			BIT(7)
#define CR_FTHRES_MASK		GENMASK(12, 8)
#define CR_TEIE			BIT(16)
#define CR_TCIE			BIT(17)
#define CR_FTIE			BIT(18)
#define CR_SMIE			BIT(19)
#define CR_TOIE			BIT(20)
#define CR_PRESC_MASK		GENMASK(31, 24)

#define QSPI_DCR		0x04
#define DCR_FSIZE_MASK		GENMASK(20, 16)

#define QSPI_SR			0x08
#define SR_TEF			BIT(0)
#define SR_TCF			BIT(1)
#define SR_FTF			BIT(2)
#define SR_SMF			BIT(3)
#define SR_TOF			BIT(4)
#define SR_BUSY			BIT(5)
#define SR_FLEVEL_MASK		GENMASK(13, 8)

#define QSPI_FCR		0x0c
#define FCR_CTEF		BIT(0)
#define FCR_CTCF		BIT(1)

#define QSPI_DLR		0x10

#define QSPI_CCR		0x14
#define CCR_INST_MASK		GENMASK(7, 0)
#define CCR_IMODE_MASK		GENMASK(9, 8)
#define CCR_ADMODE_MASK		GENMASK(11, 10)
#define CCR_ADSIZE_MASK		GENMASK(13, 12)
#define CCR_DCYC_MASK		GENMASK(22, 18)
#define CCR_DMODE_MASK		GENMASK(25, 24)
#define CCR_FMODE_MASK		GENMASK(27, 26)
#define CCR_FMODE_INDW		(0U << 26)
#define CCR_FMODE_INDR		(1U << 26)
#define CCR_FMODE_APM		(2U << 26)
#define CCR_FMODE_MM		(3U << 26)
#define CCR_BUSWIDTH_0		0x0
#define CCR_BUSWIDTH_1		0x1
#define CCR_BUSWIDTH_2		0x2
#define CCR_BUSWIDTH_4		0x3

#define QSPI_AR			0x18
#define QSPI_ABR		0x1c
#define QSPI_DR			0x20
#define QSPI_PSMKR		0x24
#define QSPI_PSMAR		0x28
#define QSPI_PIR		0x2c
#define QSPI_LPTR		0x30

#define STM32_QSPI_MAX_MMAP_SZ	SZ_256M
#define STM32_QSPI_MAX_NORCHIP	2

#define STM32_FIFO_TIMEOUT_US 30000
#define STM32_BUSY_TIMEOUT_US 100000
#define STM32_ABT_TIMEOUT_US 100000

struct stm32_qspi_flash {
	struct stm32_qspi *qspi;
	u32 cs;
	u32 presc;
};

struct stm32_qspi {
	struct device *dev;
	void __iomem *io_base;
	void __iomem *mm_base;
	resource_size_t mm_size;
	struct clk *clk;
	u32 clk_rate;
	struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
	struct completion data_completion;
	u32 fmode;

	u32 cr_reg;
	u32 dcr_reg;

	/*
	 * to protect device configuration, could be different between
	 * 2 flash access (bk1, bk2)
	 */
	struct mutex lock;
};

static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
{
	struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id;
	u32 cr, sr;

	sr = readl_relaxed(qspi->io_base + QSPI_SR);

	if (sr & (SR_TEF | SR_TCF)) {
		/* disable irq */
		cr = readl_relaxed(qspi->io_base + QSPI_CR);
		cr &= ~CR_TCIE & ~CR_TEIE;
		writel_relaxed(cr, qspi->io_base + QSPI_CR);
		complete(&qspi->data_completion);
	}

	return IRQ_HANDLED;
}

static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
{
	*val = readb_relaxed(addr);
}

static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr)
{
	writeb_relaxed(*val, addr);
}

static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
			      const struct spi_mem_op *op)
{
	void (*tx_fifo)(u8 *val, void __iomem *addr);
	u32 len = op->data.nbytes, sr;
	u8 *buf;
	int ret;

	if (op->data.dir == SPI_MEM_DATA_IN) {
		tx_fifo = stm32_qspi_read_fifo;
		buf = op->data.buf.in;

	} else {
		tx_fifo = stm32_qspi_write_fifo;
		buf = (u8 *)op->data.buf.out;
	}

	while (len--) {
		ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
							sr, (sr & SR_FTF), 1,
							STM32_FIFO_TIMEOUT_US);
		if (ret) {
			dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
				len, sr);
			return ret;
		}
		tx_fifo(buf++, qspi->io_base + QSPI_DR);
	}

	return 0;
}

static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
			    const struct spi_mem_op *op)
{
	memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
		      op->data.nbytes);
	return 0;
}

static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op)
{
	if (!op->data.nbytes)
		return 0;

	if (qspi->fmode == CCR_FMODE_MM)
		return stm32_qspi_tx_mm(qspi, op);

	return stm32_qspi_tx_poll(qspi, op);
}

static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
{
	u32 sr;

	return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
						 !(sr & SR_BUSY), 1,
						 STM32_BUSY_TIMEOUT_US);
}

static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
			       const struct spi_mem_op *op)
{
	u32 cr, sr;
	int err = 0;

	if (!op->data.nbytes)
		return stm32_qspi_wait_nobusy(qspi);

	if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
		goto out;

	reinit_completion(&qspi->data_completion);
	cr = readl_relaxed(qspi->io_base + QSPI_CR);
	writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR);

	if (!wait_for_completion_interruptible_timeout(&qspi->data_completion,
						msecs_to_jiffies(1000))) {
		err = -ETIMEDOUT;
	} else {
		sr = readl_relaxed(qspi->io_base + QSPI_SR);
		if (sr & SR_TEF)
			err = -EIO;
	}

out:
	/* clear flags */
	writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR);

	return err;
}

static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
{
	if (buswidth == 4)
		return CCR_BUSWIDTH_4;

	return buswidth;
}

static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op)
{
	struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
	struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
	u32 ccr, cr, addr_max;
	int timeout, err = 0;

	dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
		op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
		op->dummy.buswidth, op->data.buswidth,
		op->addr.val, op->data.nbytes);

	err = stm32_qspi_wait_nobusy(qspi);
	if (err)
		goto abort;

	addr_max = op->addr.val + op->data.nbytes + 1;

	if (op->data.dir == SPI_MEM_DATA_IN) {
		if (addr_max < qspi->mm_size &&
		    op->addr.buswidth)
			qspi->fmode = CCR_FMODE_MM;
		else
			qspi->fmode = CCR_FMODE_INDR;
	} else {
		qspi->fmode = CCR_FMODE_INDW;
	}

	cr = readl_relaxed(qspi->io_base + QSPI_CR);
	cr &= ~CR_PRESC_MASK & ~CR_FSEL;
	cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc);
	cr |= FIELD_PREP(CR_FSEL, flash->cs);
	writel_relaxed(cr, qspi->io_base + QSPI_CR);

	if (op->data.nbytes)
		writel_relaxed(op->data.nbytes - 1,
			       qspi->io_base + QSPI_DLR);
	else
		qspi->fmode = CCR_FMODE_INDW;

	ccr = qspi->fmode;
	ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
	ccr |= FIELD_PREP(CCR_IMODE_MASK,
			  stm32_qspi_get_mode(qspi, op->cmd.buswidth));

	if (op->addr.nbytes) {
		ccr |= FIELD_PREP(CCR_ADMODE_MASK,
				  stm32_qspi_get_mode(qspi, op->addr.buswidth));
		ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
	}

	if (op->dummy.buswidth && op->dummy.nbytes)
		ccr |= FIELD_PREP(CCR_DCYC_MASK,
				  op->dummy.nbytes * 8 / op->dummy.buswidth);

	if (op->data.nbytes) {
		ccr |= FIELD_PREP(CCR_DMODE_MASK,
				  stm32_qspi_get_mode(qspi, op->data.buswidth));
	}

	writel_relaxed(ccr, qspi->io_base + QSPI_CCR);

	if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
		writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);

	err = stm32_qspi_tx(qspi, op);

	/*
	 * Abort in:
	 * -error case
	 * -read memory map: prefetching must be stopped if we read the last
	 *  byte of device (device size - fifo size). like device size is not
	 *  knows, the prefetching is always stop.
	 */
	if (err || qspi->fmode == CCR_FMODE_MM)
		goto abort;

	/* wait end of tx in indirect mode */
	err = stm32_qspi_wait_cmd(qspi, op);
	if (err)
		goto abort;

	return 0;

abort:
	cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT;
	writel_relaxed(cr, qspi->io_base + QSPI_CR);

	/* wait clear of abort bit by hw */
	timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
						    cr, !(cr & CR_ABORT), 1,
						    STM32_ABT_TIMEOUT_US);

	writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);

	if (err || timeout)
		dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
			__func__, err, timeout);

	return err;
}

static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
	struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
	int ret;

	mutex_lock(&qspi->lock);
	ret = stm32_qspi_send(mem, op);
	mutex_unlock(&qspi->lock);

	return ret;
}

static int stm32_qspi_setup(struct spi_device *spi)
{
	struct spi_controller *ctrl = spi->master;
	struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
	struct stm32_qspi_flash *flash;
	u32 presc;

	if (ctrl->busy)
		return -EBUSY;

	if (!spi->max_speed_hz)
		return -EINVAL;

	presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;

	flash = &qspi->flash[spi->chip_select];
	flash->qspi = qspi;
	flash->cs = spi->chip_select;
	flash->presc = presc;

	mutex_lock(&qspi->lock);
	qspi->cr_reg = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN;
	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);

	/* set dcr fsize to max address */
	qspi->dcr_reg = DCR_FSIZE_MASK;
	writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
	mutex_unlock(&qspi->lock);

	return 0;
}

/*
 * no special host constraint, so use default spi_mem_default_supports_op
 * to check supported mode.
 */
static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
	.exec_op = stm32_qspi_exec_op,
};

static void stm32_qspi_release(struct stm32_qspi *qspi)
{
	/* disable qspi */
	writel_relaxed(0, qspi->io_base + QSPI_CR);
	mutex_destroy(&qspi->lock);
	clk_disable_unprepare(qspi->clk);
}

static int stm32_qspi_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct spi_controller *ctrl;
	struct reset_control *rstc;
	struct stm32_qspi *qspi;
	struct resource *res;
	int ret, irq;

	ctrl = spi_alloc_master(dev, sizeof(*qspi));
	if (!ctrl)
		return -ENOMEM;

	qspi = spi_controller_get_devdata(ctrl);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
	qspi->io_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(qspi->io_base))
		return PTR_ERR(qspi->io_base);

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
	qspi->mm_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(qspi->mm_base))
		return PTR_ERR(qspi->mm_base);

	qspi->mm_size = resource_size(res);
	if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ)
		return -EINVAL;

	irq = platform_get_irq(pdev, 0);
	ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
			       dev_name(dev), qspi);
	if (ret) {
		dev_err(dev, "failed to request irq\n");
		return ret;
	}

	init_completion(&qspi->data_completion);

	qspi->clk = devm_clk_get(dev, NULL);
	if (IS_ERR(qspi->clk))
		return PTR_ERR(qspi->clk);

	qspi->clk_rate = clk_get_rate(qspi->clk);
	if (!qspi->clk_rate)
		return -EINVAL;

	ret = clk_prepare_enable(qspi->clk);
	if (ret) {
		dev_err(dev, "can not enable the clock\n");
		return ret;
	}

	rstc = devm_reset_control_get_exclusive(dev, NULL);
	if (!IS_ERR(rstc)) {
		reset_control_assert(rstc);
		udelay(2);
		reset_control_deassert(rstc);
	}

	qspi->dev = dev;
	platform_set_drvdata(pdev, qspi);
	mutex_init(&qspi->lock);

	ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
		| SPI_TX_DUAL | SPI_TX_QUAD;
	ctrl->setup = stm32_qspi_setup;
	ctrl->bus_num = -1;
	ctrl->mem_ops = &stm32_qspi_mem_ops;
	ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
	ctrl->dev.of_node = dev->of_node;

	ret = devm_spi_register_master(dev, ctrl);
	if (ret)
		goto err_spi_register;

	return 0;

err_spi_register:
	stm32_qspi_release(qspi);

	return ret;
}

static int stm32_qspi_remove(struct platform_device *pdev)
{
	struct stm32_qspi *qspi = platform_get_drvdata(pdev);

	stm32_qspi_release(qspi);
	return 0;
}

static int __maybe_unused stm32_qspi_suspend(struct device *dev)
{
	struct stm32_qspi *qspi = dev_get_drvdata(dev);

	clk_disable_unprepare(qspi->clk);
	pinctrl_pm_select_sleep_state(dev);

	return 0;
}

static int __maybe_unused stm32_qspi_resume(struct device *dev)
{
	struct stm32_qspi *qspi = dev_get_drvdata(dev);

	pinctrl_pm_select_default_state(dev);
	clk_prepare_enable(qspi->clk);

	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
	writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);

	return 0;
}

static SIMPLE_DEV_PM_OPS(stm32_qspi_pm_ops, stm32_qspi_suspend, stm32_qspi_resume);

static const struct of_device_id stm32_qspi_match[] = {
	{.compatible = "st,stm32f469-qspi"},
	{}
};
MODULE_DEVICE_TABLE(of, stm32_qspi_match);

static struct platform_driver stm32_qspi_driver = {
	.probe	= stm32_qspi_probe,
	.remove	= stm32_qspi_remove,
	.driver	= {
		.name = "stm32-qspi",
		.of_match_table = stm32_qspi_match,
		.pm = &stm32_qspi_pm_ops,
	},
};
module_platform_driver(stm32_qspi_driver);

MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
c530cd1d LB	1	// SPDX-License-Identifier: GPL-2.0
	2	/*
	3	* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
	4	* Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
	5	*/
	6	#include <linux/bitfield.h>
	7	#include <linux/clk.h>
	8	#include <linux/errno.h>
	9	#include <linux/io.h>
	10	#include <linux/iopoll.h>
	11	#include <linux/interrupt.h>
	12	#include <linux/module.h>
	13	#include <linux/mutex.h>
	14	#include <linux/of.h>
	15	#include <linux/of_device.h>
2e541b64	16	#include <linux/pinctrl/consumer.h>
c530cd1d LB	17	#include <linux/platform_device.h>
	18	#include <linux/reset.h>
	19	#include <linux/sizes.h>
	20	#include <linux/spi/spi-mem.h>
	21
	22	#define QSPI_CR 0x00
	23	#define CR_EN BIT(0)
	24	#define CR_ABORT BIT(1)
	25	#define CR_DMAEN BIT(2)
	26	#define CR_TCEN BIT(3)
	27	#define CR_SSHIFT BIT(4)
	28	#define CR_DFM BIT(6)
	29	#define CR_FSEL BIT(7)
	30	#define CR_FTHRES_MASK GENMASK(12, 8)
	31	#define CR_TEIE BIT(16)
	32	#define CR_TCIE BIT(17)
	33	#define CR_FTIE BIT(18)
	34	#define CR_SMIE BIT(19)
	35	#define CR_TOIE BIT(20)
	36	#define CR_PRESC_MASK GENMASK(31, 24)
	37
	38	#define QSPI_DCR 0x04
	39	#define DCR_FSIZE_MASK GENMASK(20, 16)
	40
	41	#define QSPI_SR 0x08
	42	#define SR_TEF BIT(0)
	43	#define SR_TCF BIT(1)
	44	#define SR_FTF BIT(2)
	45	#define SR_SMF BIT(3)
	46	#define SR_TOF BIT(4)
	47	#define SR_BUSY BIT(5)
	48	#define SR_FLEVEL_MASK GENMASK(13, 8)
	49
	50	#define QSPI_FCR 0x0c
	51	#define FCR_CTEF BIT(0)
	52	#define FCR_CTCF BIT(1)
	53
	54	#define QSPI_DLR 0x10
	55
	56	#define QSPI_CCR 0x14
	57	#define CCR_INST_MASK GENMASK(7, 0)
	58	#define CCR_IMODE_MASK GENMASK(9, 8)
	59	#define CCR_ADMODE_MASK GENMASK(11, 10)
	60	#define CCR_ADSIZE_MASK GENMASK(13, 12)
	61	#define CCR_DCYC_MASK GENMASK(22, 18)
	62	#define CCR_DMODE_MASK GENMASK(25, 24)
	63	#define CCR_FMODE_MASK GENMASK(27, 26)
	64	#define CCR_FMODE_INDW (0U << 26)
	65	#define CCR_FMODE_INDR (1U << 26)
	66	#define CCR_FMODE_APM (2U << 26)
	67	#define CCR_FMODE_MM (3U << 26)
	68	#define CCR_BUSWIDTH_0 0x0
	69	#define CCR_BUSWIDTH_1 0x1
	70	#define CCR_BUSWIDTH_2 0x2
	71	#define CCR_BUSWIDTH_4 0x3
	72
	73	#define QSPI_AR 0x18
	74	#define QSPI_ABR 0x1c
	75	#define QSPI_DR 0x20
	76	#define QSPI_PSMKR 0x24
	77	#define QSPI_PSMAR 0x28
	78	#define QSPI_PIR 0x2c
	79	#define QSPI_LPTR 0x30
c530cd1d LB	80
	81	#define STM32_QSPI_MAX_MMAP_SZ SZ_256M
	82	#define STM32_QSPI_MAX_NORCHIP 2
	83
	84	#define STM32_FIFO_TIMEOUT_US 30000
	85	#define STM32_BUSY_TIMEOUT_US 100000
	86	#define STM32_ABT_TIMEOUT_US 100000
	87
	88	struct stm32_qspi_flash {
	89	struct stm32_qspi *qspi;
	90	u32 cs;
	91	u32 presc;
	92	};
	93
	94	struct stm32_qspi {
	95	struct device *dev;
	96	void __iomem *io_base;
	97	void __iomem *mm_base;
	98	resource_size_t mm_size;
	99	struct clk *clk;
	100	u32 clk_rate;
	101	struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP];
	102	struct completion data_completion;
	103	u32 fmode;
	104
2e541b64 LB	105	u32 cr_reg;
	106	u32 dcr_reg;
	107
c530cd1d LB	108	/*
	109	* to protect device configuration, could be different between
	110	* 2 flash access (bk1, bk2)
	111	*/
	112	struct mutex lock;
	113	};
	114
	115	static irqreturn_t stm32_qspi_irq(int irq, void *dev_id)
	116	{
	117	struct stm32_qspi qspi = (struct stm32_qspi )dev_id;
	118	u32 cr, sr;
	119
	120	sr = readl_relaxed(qspi->io_base + QSPI_SR);
	121
	122	if (sr & (SR_TEF \| SR_TCF)) {
	123	/* disable irq */
	124	cr = readl_relaxed(qspi->io_base + QSPI_CR);
	125	cr &= ~CR_TCIE & ~CR_TEIE;
	126	writel_relaxed(cr, qspi->io_base + QSPI_CR);
	127	complete(&qspi->data_completion);
	128	}
	129
	130	return IRQ_HANDLED;
	131	}
	132
	133	static void stm32_qspi_read_fifo(u8 val, void __iomem addr)
	134	{
	135	*val = readb_relaxed(addr);
	136	}
	137
	138	static void stm32_qspi_write_fifo(u8 val, void __iomem addr)
	139	{
	140	writeb_relaxed(*val, addr);
	141	}
	142
	143	static int stm32_qspi_tx_poll(struct stm32_qspi *qspi,
	144	const struct spi_mem_op *op)
	145	{
	146	void (tx_fifo)(u8 val, void __iomem *addr);
	147	u32 len = op->data.nbytes, sr;
	148	u8 *buf;
	149	int ret;
	150
	151	if (op->data.dir == SPI_MEM_DATA_IN) {
	152	tx_fifo = stm32_qspi_read_fifo;
	153	buf = op->data.buf.in;
	154
	155	} else {
	156	tx_fifo = stm32_qspi_write_fifo;
	157	buf = (u8 *)op->data.buf.out;
	158	}
	159
	160	while (len--) {
	161	ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR,
	162	sr, (sr & SR_FTF), 1,
	163	STM32_FIFO_TIMEOUT_US);
	164	if (ret) {
	165	dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n",
	166	len, sr);
	167	return ret;
	168	}
	169	tx_fifo(buf++, qspi->io_base + QSPI_DR);
	170	}
	171
172	return 0;
173	}
174
175	static int stm32_qspi_tx_mm(struct stm32_qspi *qspi,
176	const struct spi_mem_op *op)
177	{
178	memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val,
179	op->data.nbytes);
180	return 0;
181	}
182
183	static int stm32_qspi_tx(struct stm32_qspi qspi, const struct spi_mem_op op)
184	{
185	if (!op->data.nbytes)
186	return 0;
187
188	if (qspi->fmode == CCR_FMODE_MM)
189	return stm32_qspi_tx_mm(qspi, op);
190
191	return stm32_qspi_tx_poll(qspi, op);
192	}
193
194	static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi)
195	{
196	u32 sr;
197
198	return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr,
199	!(sr & SR_BUSY), 1,
200	STM32_BUSY_TIMEOUT_US);
201	}
202
203	static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi,
204	const struct spi_mem_op *op)
205	{
206	u32 cr, sr;
207	int err = 0;
208
209	if (!op->data.nbytes)
210	return stm32_qspi_wait_nobusy(qspi);
211
212	if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF)
213	goto out;
214
215	reinit_completion(&qspi->data_completion);
216	cr = readl_relaxed(qspi->io_base + QSPI_CR);
217	writel_relaxed(cr \| CR_TCIE \| CR_TEIE, qspi->io_base + QSPI_CR);
218
219	if (!wait_for_completion_interruptible_timeout(&qspi->data_completion,
220	msecs_to_jiffies(1000))) {
221	err = -ETIMEDOUT;
222	} else {
223	sr = readl_relaxed(qspi->io_base + QSPI_SR);
224	if (sr & SR_TEF)
225	err = -EIO;
226	}
227
228	out:
229	/* clear flags */
230	writel_relaxed(FCR_CTCF \| FCR_CTEF, qspi->io_base + QSPI_FCR);
231
232	return err;
233	}
234
235	static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth)
236	{
237	if (buswidth == 4)
238	return CCR_BUSWIDTH_4;
239
240	return buswidth;
241	}
242
243	static int stm32_qspi_send(struct spi_mem mem, const struct spi_mem_op op)
244	{
245	struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
246	struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select];
247	u32 ccr, cr, addr_max;
248	int timeout, err = 0;
249
250	dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n",
251	op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
252	op->dummy.buswidth, op->data.buswidth,
253	op->addr.val, op->data.nbytes);
254
255	err = stm32_qspi_wait_nobusy(qspi);
256	if (err)
257	goto abort;
258
259	addr_max = op->addr.val + op->data.nbytes + 1;
260
261	if (op->data.dir == SPI_MEM_DATA_IN) {
262	if (addr_max < qspi->mm_size &&
263	op->addr.buswidth)
264	qspi->fmode = CCR_FMODE_MM;
265	else
266	qspi->fmode = CCR_FMODE_INDR;
267	} else {
268	qspi->fmode = CCR_FMODE_INDW;
269	}
270
271	cr = readl_relaxed(qspi->io_base + QSPI_CR);
272	cr &= ~CR_PRESC_MASK & ~CR_FSEL;
273	cr \|= FIELD_PREP(CR_PRESC_MASK, flash->presc);
274	cr \|= FIELD_PREP(CR_FSEL, flash->cs);
275	writel_relaxed(cr, qspi->io_base + QSPI_CR);
276
277	if (op->data.nbytes)
278	writel_relaxed(op->data.nbytes - 1,
279	qspi->io_base + QSPI_DLR);
280	else
281	qspi->fmode = CCR_FMODE_INDW;
282
283	ccr = qspi->fmode;
284	ccr \|= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode);
285	ccr \|= FIELD_PREP(CCR_IMODE_MASK,
286	stm32_qspi_get_mode(qspi, op->cmd.buswidth));
287
288	if (op->addr.nbytes) {
289	ccr \|= FIELD_PREP(CCR_ADMODE_MASK,
290	stm32_qspi_get_mode(qspi, op->addr.buswidth));
291	ccr \|= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1);
292	}
293
294	if (op->dummy.buswidth && op->dummy.nbytes)
295	ccr \|= FIELD_PREP(CCR_DCYC_MASK,
296	op->dummy.nbytes * 8 / op->dummy.buswidth);
297
298	if (op->data.nbytes) {
299	ccr \|= FIELD_PREP(CCR_DMODE_MASK,
300	stm32_qspi_get_mode(qspi, op->data.buswidth));
301	}
302
303	writel_relaxed(ccr, qspi->io_base + QSPI_CCR);
304
305	if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM)
306	writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR);
307
308	err = stm32_qspi_tx(qspi, op);
309
310	/*
311	* Abort in:
312	* -error case
313	* -read memory map: prefetching must be stopped if we read the last
314	* byte of device (device size - fifo size). like device size is not
315	* knows, the prefetching is always stop.
316	*/
317	if (err \|\| qspi->fmode == CCR_FMODE_MM)
318	goto abort;
319
320	/* wait end of tx in indirect mode */
321	err = stm32_qspi_wait_cmd(qspi, op);
322	if (err)
323	goto abort;
324
325	return 0;
326
327	abort:
328	cr = readl_relaxed(qspi->io_base + QSPI_CR) \| CR_ABORT;
329	writel_relaxed(cr, qspi->io_base + QSPI_CR);
330
331	/* wait clear of abort bit by hw */
332	timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR,
333	cr, !(cr & CR_ABORT), 1,
334	STM32_ABT_TIMEOUT_US);
335
336	writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR);
337
338	if (err \|\| timeout)
339	dev_err(qspi->dev, "%s err:%d abort timeout:%d\n",
340	__func__, err, timeout);
341
342	return err;
343	}
344
345	static int stm32_qspi_exec_op(struct spi_mem mem, const struct spi_mem_op op)
346	{
347	struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master);
348	int ret;
349
350	mutex_lock(&qspi->lock);
351	ret = stm32_qspi_send(mem, op);
352	mutex_unlock(&qspi->lock);
353
354	return ret;
355	}
356
357	static int stm32_qspi_setup(struct spi_device *spi)
358	{
359	struct spi_controller *ctrl = spi->master;
360	struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl);
361	struct stm32_qspi_flash *flash;
2e541b64	362	u32 presc;
c530cd1d LB	363
	364	if (ctrl->busy)
	365	return -EBUSY;
	366
	367	if (!spi->max_speed_hz)
	368	return -EINVAL;
	369
	370	presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1;
	371
	372	flash = &qspi->flash[spi->chip_select];
	373	flash->qspi = qspi;
	374	flash->cs = spi->chip_select;
	375	flash->presc = presc;
	376
	377	mutex_lock(&qspi->lock);
2e541b64 LB	378	qspi->cr_reg = FIELD_PREP(CR_FTHRES_MASK, 3) \| CR_SSHIFT \| CR_EN;
2e541b64 LB	379	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
c530cd1d LB	380
c530cd1d LB	381	/* set dcr fsize to max address */
2e541b64 LB	382	qspi->dcr_reg = DCR_FSIZE_MASK;
2e541b64 LB	383	writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
c530cd1d LB	384	mutex_unlock(&qspi->lock);
	385
	386	return 0;
	387	}
	388
	389	/*
	390	* no special host constraint, so use default spi_mem_default_supports_op
	391	* to check supported mode.
	392	*/
	393	static const struct spi_controller_mem_ops stm32_qspi_mem_ops = {
	394	.exec_op = stm32_qspi_exec_op,
	395	};
	396
	397	static void stm32_qspi_release(struct stm32_qspi *qspi)
	398	{
	399	/* disable qspi */
	400	writel_relaxed(0, qspi->io_base + QSPI_CR);
	401	mutex_destroy(&qspi->lock);
	402	clk_disable_unprepare(qspi->clk);
	403	}
	404
	405	static int stm32_qspi_probe(struct platform_device *pdev)
	406	{
	407	struct device *dev = &pdev->dev;
	408	struct spi_controller *ctrl;
	409	struct reset_control *rstc;
	410	struct stm32_qspi *qspi;
	411	struct resource *res;
	412	int ret, irq;
	413
	414	ctrl = spi_alloc_master(dev, sizeof(*qspi));
	415	if (!ctrl)
	416	return -ENOMEM;
	417
	418	qspi = spi_controller_get_devdata(ctrl);
	419
	420	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi");
	421	qspi->io_base = devm_ioremap_resource(dev, res);
	422	if (IS_ERR(qspi->io_base))
	423	return PTR_ERR(qspi->io_base);
	424
	425	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm");
	426	qspi->mm_base = devm_ioremap_resource(dev, res);
	427	if (IS_ERR(qspi->mm_base))
	428	return PTR_ERR(qspi->mm_base);
	429
	430	qspi->mm_size = resource_size(res);
	431	if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ)
	432	return -EINVAL;
	433
	434	irq = platform_get_irq(pdev, 0);
	435	ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0,
	436	dev_name(dev), qspi);
	437	if (ret) {
	438	dev_err(dev, "failed to request irq\n");
	439	return ret;
	440	}
	441
	442	init_completion(&qspi->data_completion);
	443
	444	qspi->clk = devm_clk_get(dev, NULL);
	445	if (IS_ERR(qspi->clk))
	446	return PTR_ERR(qspi->clk);
	447
448	qspi->clk_rate = clk_get_rate(qspi->clk);
449	if (!qspi->clk_rate)
450	return -EINVAL;
451
452	ret = clk_prepare_enable(qspi->clk);
453	if (ret) {
454	dev_err(dev, "can not enable the clock\n");
455	return ret;
456	}
457
458	rstc = devm_reset_control_get_exclusive(dev, NULL);
459	if (!IS_ERR(rstc)) {
460	reset_control_assert(rstc);
461	udelay(2);
462	reset_control_deassert(rstc);
463	}
464
465	qspi->dev = dev;
466	platform_set_drvdata(pdev, qspi);
467	mutex_init(&qspi->lock);
468
469	ctrl->mode_bits = SPI_RX_DUAL \| SPI_RX_QUAD
470	\| SPI_TX_DUAL \| SPI_TX_QUAD;
471	ctrl->setup = stm32_qspi_setup;
472	ctrl->bus_num = -1;
473	ctrl->mem_ops = &stm32_qspi_mem_ops;
474	ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP;
475	ctrl->dev.of_node = dev->of_node;
476
477	ret = devm_spi_register_master(dev, ctrl);
478	if (ret)
479	goto err_spi_register;
480
481	return 0;
482
483	err_spi_register:
484	stm32_qspi_release(qspi);
485
486	return ret;
487	}
488
489	static int stm32_qspi_remove(struct platform_device *pdev)
490	{
491	struct stm32_qspi *qspi = platform_get_drvdata(pdev);
492
493	stm32_qspi_release(qspi);
494	return 0;
495	}
496
2e541b64 LB	497	static int __maybe_unused stm32_qspi_suspend(struct device *dev)
	498	{
	499	struct stm32_qspi *qspi = dev_get_drvdata(dev);
	500
	501	clk_disable_unprepare(qspi->clk);
	502	pinctrl_pm_select_sleep_state(dev);
	503
	504	return 0;
	505	}
	506
	507	static int __maybe_unused stm32_qspi_resume(struct device *dev)
	508	{
	509	struct stm32_qspi *qspi = dev_get_drvdata(dev);
	510
	511	pinctrl_pm_select_default_state(dev);
	512	clk_prepare_enable(qspi->clk);
	513
	514	writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR);
	515	writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR);
	516
	517	return 0;
	518	}
	519
43a8d240	520	static SIMPLE_DEV_PM_OPS(stm32_qspi_pm_ops, stm32_qspi_suspend, stm32_qspi_resume);
2e541b64	521
c530cd1d LB	522	static const struct of_device_id stm32_qspi_match[] = {
	523	{.compatible = "st,stm32f469-qspi"},
	524	{}
	525	};
	526	MODULE_DEVICE_TABLE(of, stm32_qspi_match);
	527
	528	static struct platform_driver stm32_qspi_driver = {
	529	.probe = stm32_qspi_probe,
	530	.remove = stm32_qspi_remove,
	531	.driver = {
	532	.name = "stm32-qspi",
	533	.of_match_table = stm32_qspi_match,
2e541b64	534	.pm = &stm32_qspi_pm_ops,
c530cd1d LB	535	},
	536	};
	537	module_platform_driver(stm32_qspi_driver);
	538
	539	MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
	540	MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver");
	541	MODULE_LICENSE("GPL v2");