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c530cd1d LB |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Copyright (C) STMicroelectronics 2018 - All Rights Reserved | |
4 | * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. | |
5 | */ | |
6 | #include <linux/bitfield.h> | |
7 | #include <linux/clk.h> | |
8 | #include <linux/errno.h> | |
9 | #include <linux/io.h> | |
10 | #include <linux/iopoll.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/module.h> | |
13 | #include <linux/mutex.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_device.h> | |
2e541b64 | 16 | #include <linux/pinctrl/consumer.h> |
c530cd1d LB |
17 | #include <linux/platform_device.h> |
18 | #include <linux/reset.h> | |
19 | #include <linux/sizes.h> | |
20 | #include <linux/spi/spi-mem.h> | |
21 | ||
22 | #define QSPI_CR 0x00 | |
23 | #define CR_EN BIT(0) | |
24 | #define CR_ABORT BIT(1) | |
25 | #define CR_DMAEN BIT(2) | |
26 | #define CR_TCEN BIT(3) | |
27 | #define CR_SSHIFT BIT(4) | |
28 | #define CR_DFM BIT(6) | |
29 | #define CR_FSEL BIT(7) | |
30 | #define CR_FTHRES_MASK GENMASK(12, 8) | |
31 | #define CR_TEIE BIT(16) | |
32 | #define CR_TCIE BIT(17) | |
33 | #define CR_FTIE BIT(18) | |
34 | #define CR_SMIE BIT(19) | |
35 | #define CR_TOIE BIT(20) | |
36 | #define CR_PRESC_MASK GENMASK(31, 24) | |
37 | ||
38 | #define QSPI_DCR 0x04 | |
39 | #define DCR_FSIZE_MASK GENMASK(20, 16) | |
40 | ||
41 | #define QSPI_SR 0x08 | |
42 | #define SR_TEF BIT(0) | |
43 | #define SR_TCF BIT(1) | |
44 | #define SR_FTF BIT(2) | |
45 | #define SR_SMF BIT(3) | |
46 | #define SR_TOF BIT(4) | |
47 | #define SR_BUSY BIT(5) | |
48 | #define SR_FLEVEL_MASK GENMASK(13, 8) | |
49 | ||
50 | #define QSPI_FCR 0x0c | |
51 | #define FCR_CTEF BIT(0) | |
52 | #define FCR_CTCF BIT(1) | |
53 | ||
54 | #define QSPI_DLR 0x10 | |
55 | ||
56 | #define QSPI_CCR 0x14 | |
57 | #define CCR_INST_MASK GENMASK(7, 0) | |
58 | #define CCR_IMODE_MASK GENMASK(9, 8) | |
59 | #define CCR_ADMODE_MASK GENMASK(11, 10) | |
60 | #define CCR_ADSIZE_MASK GENMASK(13, 12) | |
61 | #define CCR_DCYC_MASK GENMASK(22, 18) | |
62 | #define CCR_DMODE_MASK GENMASK(25, 24) | |
63 | #define CCR_FMODE_MASK GENMASK(27, 26) | |
64 | #define CCR_FMODE_INDW (0U << 26) | |
65 | #define CCR_FMODE_INDR (1U << 26) | |
66 | #define CCR_FMODE_APM (2U << 26) | |
67 | #define CCR_FMODE_MM (3U << 26) | |
68 | #define CCR_BUSWIDTH_0 0x0 | |
69 | #define CCR_BUSWIDTH_1 0x1 | |
70 | #define CCR_BUSWIDTH_2 0x2 | |
71 | #define CCR_BUSWIDTH_4 0x3 | |
72 | ||
73 | #define QSPI_AR 0x18 | |
74 | #define QSPI_ABR 0x1c | |
75 | #define QSPI_DR 0x20 | |
76 | #define QSPI_PSMKR 0x24 | |
77 | #define QSPI_PSMAR 0x28 | |
78 | #define QSPI_PIR 0x2c | |
79 | #define QSPI_LPTR 0x30 | |
c530cd1d LB |
80 | |
81 | #define STM32_QSPI_MAX_MMAP_SZ SZ_256M | |
82 | #define STM32_QSPI_MAX_NORCHIP 2 | |
83 | ||
84 | #define STM32_FIFO_TIMEOUT_US 30000 | |
85 | #define STM32_BUSY_TIMEOUT_US 100000 | |
86 | #define STM32_ABT_TIMEOUT_US 100000 | |
87 | ||
88 | struct stm32_qspi_flash { | |
89 | struct stm32_qspi *qspi; | |
90 | u32 cs; | |
91 | u32 presc; | |
92 | }; | |
93 | ||
94 | struct stm32_qspi { | |
95 | struct device *dev; | |
a88eceb1 | 96 | struct spi_controller *ctrl; |
c530cd1d LB |
97 | void __iomem *io_base; |
98 | void __iomem *mm_base; | |
99 | resource_size_t mm_size; | |
100 | struct clk *clk; | |
101 | u32 clk_rate; | |
102 | struct stm32_qspi_flash flash[STM32_QSPI_MAX_NORCHIP]; | |
103 | struct completion data_completion; | |
104 | u32 fmode; | |
105 | ||
2e541b64 LB |
106 | u32 cr_reg; |
107 | u32 dcr_reg; | |
108 | ||
c530cd1d LB |
109 | /* |
110 | * to protect device configuration, could be different between | |
111 | * 2 flash access (bk1, bk2) | |
112 | */ | |
113 | struct mutex lock; | |
114 | }; | |
115 | ||
116 | static irqreturn_t stm32_qspi_irq(int irq, void *dev_id) | |
117 | { | |
118 | struct stm32_qspi *qspi = (struct stm32_qspi *)dev_id; | |
119 | u32 cr, sr; | |
120 | ||
121 | sr = readl_relaxed(qspi->io_base + QSPI_SR); | |
122 | ||
123 | if (sr & (SR_TEF | SR_TCF)) { | |
124 | /* disable irq */ | |
125 | cr = readl_relaxed(qspi->io_base + QSPI_CR); | |
126 | cr &= ~CR_TCIE & ~CR_TEIE; | |
127 | writel_relaxed(cr, qspi->io_base + QSPI_CR); | |
128 | complete(&qspi->data_completion); | |
129 | } | |
130 | ||
131 | return IRQ_HANDLED; | |
132 | } | |
133 | ||
134 | static void stm32_qspi_read_fifo(u8 *val, void __iomem *addr) | |
135 | { | |
136 | *val = readb_relaxed(addr); | |
137 | } | |
138 | ||
139 | static void stm32_qspi_write_fifo(u8 *val, void __iomem *addr) | |
140 | { | |
141 | writeb_relaxed(*val, addr); | |
142 | } | |
143 | ||
144 | static int stm32_qspi_tx_poll(struct stm32_qspi *qspi, | |
145 | const struct spi_mem_op *op) | |
146 | { | |
147 | void (*tx_fifo)(u8 *val, void __iomem *addr); | |
148 | u32 len = op->data.nbytes, sr; | |
149 | u8 *buf; | |
150 | int ret; | |
151 | ||
152 | if (op->data.dir == SPI_MEM_DATA_IN) { | |
153 | tx_fifo = stm32_qspi_read_fifo; | |
154 | buf = op->data.buf.in; | |
155 | ||
156 | } else { | |
157 | tx_fifo = stm32_qspi_write_fifo; | |
158 | buf = (u8 *)op->data.buf.out; | |
159 | } | |
160 | ||
161 | while (len--) { | |
162 | ret = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, | |
163 | sr, (sr & SR_FTF), 1, | |
164 | STM32_FIFO_TIMEOUT_US); | |
165 | if (ret) { | |
166 | dev_err(qspi->dev, "fifo timeout (len:%d stat:%#x)\n", | |
167 | len, sr); | |
168 | return ret; | |
169 | } | |
170 | tx_fifo(buf++, qspi->io_base + QSPI_DR); | |
171 | } | |
172 | ||
173 | return 0; | |
174 | } | |
175 | ||
176 | static int stm32_qspi_tx_mm(struct stm32_qspi *qspi, | |
177 | const struct spi_mem_op *op) | |
178 | { | |
179 | memcpy_fromio(op->data.buf.in, qspi->mm_base + op->addr.val, | |
180 | op->data.nbytes); | |
181 | return 0; | |
182 | } | |
183 | ||
184 | static int stm32_qspi_tx(struct stm32_qspi *qspi, const struct spi_mem_op *op) | |
185 | { | |
186 | if (!op->data.nbytes) | |
187 | return 0; | |
188 | ||
189 | if (qspi->fmode == CCR_FMODE_MM) | |
190 | return stm32_qspi_tx_mm(qspi, op); | |
191 | ||
192 | return stm32_qspi_tx_poll(qspi, op); | |
193 | } | |
194 | ||
195 | static int stm32_qspi_wait_nobusy(struct stm32_qspi *qspi) | |
196 | { | |
197 | u32 sr; | |
198 | ||
199 | return readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_SR, sr, | |
200 | !(sr & SR_BUSY), 1, | |
201 | STM32_BUSY_TIMEOUT_US); | |
202 | } | |
203 | ||
204 | static int stm32_qspi_wait_cmd(struct stm32_qspi *qspi, | |
205 | const struct spi_mem_op *op) | |
206 | { | |
207 | u32 cr, sr; | |
208 | int err = 0; | |
209 | ||
210 | if (!op->data.nbytes) | |
211 | return stm32_qspi_wait_nobusy(qspi); | |
212 | ||
213 | if (readl_relaxed(qspi->io_base + QSPI_SR) & SR_TCF) | |
214 | goto out; | |
215 | ||
216 | reinit_completion(&qspi->data_completion); | |
217 | cr = readl_relaxed(qspi->io_base + QSPI_CR); | |
218 | writel_relaxed(cr | CR_TCIE | CR_TEIE, qspi->io_base + QSPI_CR); | |
219 | ||
220 | if (!wait_for_completion_interruptible_timeout(&qspi->data_completion, | |
221 | msecs_to_jiffies(1000))) { | |
222 | err = -ETIMEDOUT; | |
223 | } else { | |
224 | sr = readl_relaxed(qspi->io_base + QSPI_SR); | |
225 | if (sr & SR_TEF) | |
226 | err = -EIO; | |
227 | } | |
228 | ||
229 | out: | |
230 | /* clear flags */ | |
231 | writel_relaxed(FCR_CTCF | FCR_CTEF, qspi->io_base + QSPI_FCR); | |
232 | ||
233 | return err; | |
234 | } | |
235 | ||
236 | static int stm32_qspi_get_mode(struct stm32_qspi *qspi, u8 buswidth) | |
237 | { | |
238 | if (buswidth == 4) | |
239 | return CCR_BUSWIDTH_4; | |
240 | ||
241 | return buswidth; | |
242 | } | |
243 | ||
244 | static int stm32_qspi_send(struct spi_mem *mem, const struct spi_mem_op *op) | |
245 | { | |
246 | struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master); | |
247 | struct stm32_qspi_flash *flash = &qspi->flash[mem->spi->chip_select]; | |
248 | u32 ccr, cr, addr_max; | |
249 | int timeout, err = 0; | |
250 | ||
251 | dev_dbg(qspi->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx len:%#x\n", | |
252 | op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, | |
253 | op->dummy.buswidth, op->data.buswidth, | |
254 | op->addr.val, op->data.nbytes); | |
255 | ||
256 | err = stm32_qspi_wait_nobusy(qspi); | |
257 | if (err) | |
258 | goto abort; | |
259 | ||
260 | addr_max = op->addr.val + op->data.nbytes + 1; | |
261 | ||
262 | if (op->data.dir == SPI_MEM_DATA_IN) { | |
263 | if (addr_max < qspi->mm_size && | |
264 | op->addr.buswidth) | |
265 | qspi->fmode = CCR_FMODE_MM; | |
266 | else | |
267 | qspi->fmode = CCR_FMODE_INDR; | |
268 | } else { | |
269 | qspi->fmode = CCR_FMODE_INDW; | |
270 | } | |
271 | ||
272 | cr = readl_relaxed(qspi->io_base + QSPI_CR); | |
273 | cr &= ~CR_PRESC_MASK & ~CR_FSEL; | |
274 | cr |= FIELD_PREP(CR_PRESC_MASK, flash->presc); | |
275 | cr |= FIELD_PREP(CR_FSEL, flash->cs); | |
276 | writel_relaxed(cr, qspi->io_base + QSPI_CR); | |
277 | ||
278 | if (op->data.nbytes) | |
279 | writel_relaxed(op->data.nbytes - 1, | |
280 | qspi->io_base + QSPI_DLR); | |
281 | else | |
282 | qspi->fmode = CCR_FMODE_INDW; | |
283 | ||
284 | ccr = qspi->fmode; | |
285 | ccr |= FIELD_PREP(CCR_INST_MASK, op->cmd.opcode); | |
286 | ccr |= FIELD_PREP(CCR_IMODE_MASK, | |
287 | stm32_qspi_get_mode(qspi, op->cmd.buswidth)); | |
288 | ||
289 | if (op->addr.nbytes) { | |
290 | ccr |= FIELD_PREP(CCR_ADMODE_MASK, | |
291 | stm32_qspi_get_mode(qspi, op->addr.buswidth)); | |
292 | ccr |= FIELD_PREP(CCR_ADSIZE_MASK, op->addr.nbytes - 1); | |
293 | } | |
294 | ||
295 | if (op->dummy.buswidth && op->dummy.nbytes) | |
296 | ccr |= FIELD_PREP(CCR_DCYC_MASK, | |
297 | op->dummy.nbytes * 8 / op->dummy.buswidth); | |
298 | ||
299 | if (op->data.nbytes) { | |
300 | ccr |= FIELD_PREP(CCR_DMODE_MASK, | |
301 | stm32_qspi_get_mode(qspi, op->data.buswidth)); | |
302 | } | |
303 | ||
304 | writel_relaxed(ccr, qspi->io_base + QSPI_CCR); | |
305 | ||
306 | if (op->addr.nbytes && qspi->fmode != CCR_FMODE_MM) | |
307 | writel_relaxed(op->addr.val, qspi->io_base + QSPI_AR); | |
308 | ||
309 | err = stm32_qspi_tx(qspi, op); | |
310 | ||
311 | /* | |
312 | * Abort in: | |
313 | * -error case | |
314 | * -read memory map: prefetching must be stopped if we read the last | |
315 | * byte of device (device size - fifo size). like device size is not | |
316 | * knows, the prefetching is always stop. | |
317 | */ | |
318 | if (err || qspi->fmode == CCR_FMODE_MM) | |
319 | goto abort; | |
320 | ||
321 | /* wait end of tx in indirect mode */ | |
322 | err = stm32_qspi_wait_cmd(qspi, op); | |
323 | if (err) | |
324 | goto abort; | |
325 | ||
326 | return 0; | |
327 | ||
328 | abort: | |
329 | cr = readl_relaxed(qspi->io_base + QSPI_CR) | CR_ABORT; | |
330 | writel_relaxed(cr, qspi->io_base + QSPI_CR); | |
331 | ||
332 | /* wait clear of abort bit by hw */ | |
333 | timeout = readl_relaxed_poll_timeout_atomic(qspi->io_base + QSPI_CR, | |
334 | cr, !(cr & CR_ABORT), 1, | |
335 | STM32_ABT_TIMEOUT_US); | |
336 | ||
337 | writel_relaxed(FCR_CTCF, qspi->io_base + QSPI_FCR); | |
338 | ||
339 | if (err || timeout) | |
340 | dev_err(qspi->dev, "%s err:%d abort timeout:%d\n", | |
341 | __func__, err, timeout); | |
342 | ||
343 | return err; | |
344 | } | |
345 | ||
346 | static int stm32_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) | |
347 | { | |
348 | struct stm32_qspi *qspi = spi_controller_get_devdata(mem->spi->master); | |
349 | int ret; | |
350 | ||
351 | mutex_lock(&qspi->lock); | |
352 | ret = stm32_qspi_send(mem, op); | |
353 | mutex_unlock(&qspi->lock); | |
354 | ||
355 | return ret; | |
356 | } | |
357 | ||
358 | static int stm32_qspi_setup(struct spi_device *spi) | |
359 | { | |
360 | struct spi_controller *ctrl = spi->master; | |
361 | struct stm32_qspi *qspi = spi_controller_get_devdata(ctrl); | |
362 | struct stm32_qspi_flash *flash; | |
2e541b64 | 363 | u32 presc; |
c530cd1d LB |
364 | |
365 | if (ctrl->busy) | |
366 | return -EBUSY; | |
367 | ||
368 | if (!spi->max_speed_hz) | |
369 | return -EINVAL; | |
370 | ||
371 | presc = DIV_ROUND_UP(qspi->clk_rate, spi->max_speed_hz) - 1; | |
372 | ||
373 | flash = &qspi->flash[spi->chip_select]; | |
374 | flash->qspi = qspi; | |
375 | flash->cs = spi->chip_select; | |
376 | flash->presc = presc; | |
377 | ||
378 | mutex_lock(&qspi->lock); | |
2e541b64 LB |
379 | qspi->cr_reg = FIELD_PREP(CR_FTHRES_MASK, 3) | CR_SSHIFT | CR_EN; |
380 | writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); | |
c530cd1d LB |
381 | |
382 | /* set dcr fsize to max address */ | |
2e541b64 LB |
383 | qspi->dcr_reg = DCR_FSIZE_MASK; |
384 | writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); | |
c530cd1d LB |
385 | mutex_unlock(&qspi->lock); |
386 | ||
387 | return 0; | |
388 | } | |
389 | ||
390 | /* | |
391 | * no special host constraint, so use default spi_mem_default_supports_op | |
392 | * to check supported mode. | |
393 | */ | |
394 | static const struct spi_controller_mem_ops stm32_qspi_mem_ops = { | |
395 | .exec_op = stm32_qspi_exec_op, | |
396 | }; | |
397 | ||
398 | static void stm32_qspi_release(struct stm32_qspi *qspi) | |
399 | { | |
400 | /* disable qspi */ | |
401 | writel_relaxed(0, qspi->io_base + QSPI_CR); | |
402 | mutex_destroy(&qspi->lock); | |
403 | clk_disable_unprepare(qspi->clk); | |
a88eceb1 | 404 | spi_master_put(qspi->ctrl); |
c530cd1d LB |
405 | } |
406 | ||
407 | static int stm32_qspi_probe(struct platform_device *pdev) | |
408 | { | |
409 | struct device *dev = &pdev->dev; | |
410 | struct spi_controller *ctrl; | |
411 | struct reset_control *rstc; | |
412 | struct stm32_qspi *qspi; | |
413 | struct resource *res; | |
414 | int ret, irq; | |
415 | ||
416 | ctrl = spi_alloc_master(dev, sizeof(*qspi)); | |
417 | if (!ctrl) | |
418 | return -ENOMEM; | |
419 | ||
420 | qspi = spi_controller_get_devdata(ctrl); | |
a88eceb1 | 421 | qspi->ctrl = ctrl; |
c530cd1d LB |
422 | |
423 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi"); | |
424 | qspi->io_base = devm_ioremap_resource(dev, res); | |
a88eceb1 LB |
425 | if (IS_ERR(qspi->io_base)) { |
426 | ret = PTR_ERR(qspi->io_base); | |
427 | goto err; | |
428 | } | |
c530cd1d LB |
429 | |
430 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mm"); | |
431 | qspi->mm_base = devm_ioremap_resource(dev, res); | |
a88eceb1 LB |
432 | if (IS_ERR(qspi->mm_base)) { |
433 | ret = PTR_ERR(qspi->mm_base); | |
434 | goto err; | |
435 | } | |
c530cd1d LB |
436 | |
437 | qspi->mm_size = resource_size(res); | |
a88eceb1 LB |
438 | if (qspi->mm_size > STM32_QSPI_MAX_MMAP_SZ) { |
439 | ret = -EINVAL; | |
440 | goto err; | |
441 | } | |
c530cd1d LB |
442 | |
443 | irq = platform_get_irq(pdev, 0); | |
444 | ret = devm_request_irq(dev, irq, stm32_qspi_irq, 0, | |
445 | dev_name(dev), qspi); | |
446 | if (ret) { | |
447 | dev_err(dev, "failed to request irq\n"); | |
a88eceb1 | 448 | goto err; |
c530cd1d LB |
449 | } |
450 | ||
451 | init_completion(&qspi->data_completion); | |
452 | ||
453 | qspi->clk = devm_clk_get(dev, NULL); | |
a88eceb1 LB |
454 | if (IS_ERR(qspi->clk)) { |
455 | ret = PTR_ERR(qspi->clk); | |
456 | goto err; | |
457 | } | |
c530cd1d LB |
458 | |
459 | qspi->clk_rate = clk_get_rate(qspi->clk); | |
a88eceb1 LB |
460 | if (!qspi->clk_rate) { |
461 | ret = -EINVAL; | |
462 | goto err; | |
463 | } | |
c530cd1d LB |
464 | |
465 | ret = clk_prepare_enable(qspi->clk); | |
466 | if (ret) { | |
467 | dev_err(dev, "can not enable the clock\n"); | |
a88eceb1 | 468 | goto err; |
c530cd1d LB |
469 | } |
470 | ||
471 | rstc = devm_reset_control_get_exclusive(dev, NULL); | |
472 | if (!IS_ERR(rstc)) { | |
473 | reset_control_assert(rstc); | |
474 | udelay(2); | |
475 | reset_control_deassert(rstc); | |
476 | } | |
477 | ||
478 | qspi->dev = dev; | |
479 | platform_set_drvdata(pdev, qspi); | |
480 | mutex_init(&qspi->lock); | |
481 | ||
482 | ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | |
483 | | SPI_TX_DUAL | SPI_TX_QUAD; | |
484 | ctrl->setup = stm32_qspi_setup; | |
485 | ctrl->bus_num = -1; | |
486 | ctrl->mem_ops = &stm32_qspi_mem_ops; | |
487 | ctrl->num_chipselect = STM32_QSPI_MAX_NORCHIP; | |
488 | ctrl->dev.of_node = dev->of_node; | |
489 | ||
490 | ret = devm_spi_register_master(dev, ctrl); | |
a88eceb1 LB |
491 | if (!ret) |
492 | return 0; | |
c530cd1d | 493 | |
a88eceb1 | 494 | err: |
c530cd1d | 495 | stm32_qspi_release(qspi); |
c530cd1d LB |
496 | return ret; |
497 | } | |
498 | ||
499 | static int stm32_qspi_remove(struct platform_device *pdev) | |
500 | { | |
501 | struct stm32_qspi *qspi = platform_get_drvdata(pdev); | |
502 | ||
503 | stm32_qspi_release(qspi); | |
504 | return 0; | |
505 | } | |
506 | ||
2e541b64 LB |
507 | static int __maybe_unused stm32_qspi_suspend(struct device *dev) |
508 | { | |
509 | struct stm32_qspi *qspi = dev_get_drvdata(dev); | |
510 | ||
511 | clk_disable_unprepare(qspi->clk); | |
512 | pinctrl_pm_select_sleep_state(dev); | |
513 | ||
514 | return 0; | |
515 | } | |
516 | ||
517 | static int __maybe_unused stm32_qspi_resume(struct device *dev) | |
518 | { | |
519 | struct stm32_qspi *qspi = dev_get_drvdata(dev); | |
520 | ||
521 | pinctrl_pm_select_default_state(dev); | |
522 | clk_prepare_enable(qspi->clk); | |
523 | ||
524 | writel_relaxed(qspi->cr_reg, qspi->io_base + QSPI_CR); | |
525 | writel_relaxed(qspi->dcr_reg, qspi->io_base + QSPI_DCR); | |
526 | ||
527 | return 0; | |
528 | } | |
529 | ||
43a8d240 | 530 | static SIMPLE_DEV_PM_OPS(stm32_qspi_pm_ops, stm32_qspi_suspend, stm32_qspi_resume); |
2e541b64 | 531 | |
c530cd1d LB |
532 | static const struct of_device_id stm32_qspi_match[] = { |
533 | {.compatible = "st,stm32f469-qspi"}, | |
534 | {} | |
535 | }; | |
536 | MODULE_DEVICE_TABLE(of, stm32_qspi_match); | |
537 | ||
538 | static struct platform_driver stm32_qspi_driver = { | |
539 | .probe = stm32_qspi_probe, | |
540 | .remove = stm32_qspi_remove, | |
541 | .driver = { | |
542 | .name = "stm32-qspi", | |
543 | .of_match_table = stm32_qspi_match, | |
2e541b64 | 544 | .pm = &stm32_qspi_pm_ops, |
c530cd1d LB |
545 | }, |
546 | }; | |
547 | module_platform_driver(stm32_qspi_driver); | |
548 | ||
549 | MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>"); | |
550 | MODULE_DESCRIPTION("STMicroelectronics STM32 quad spi driver"); | |
551 | MODULE_LICENSE("GPL v2"); |