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d57a984f CG |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // | |
3 | // STMicroelectronics STM32 SPI Controller driver (master mode only) | |
4 | // | |
5 | // Copyright (C) 2017, STMicroelectronics - All Rights Reserved | |
6 | // Author(s): Amelie Delaunay <amelie.delaunay@st.com> for STMicroelectronics. | |
7 | ||
dcbe0d84 AD |
8 | #include <linux/debugfs.h> |
9 | #include <linux/clk.h> | |
10 | #include <linux/delay.h> | |
11 | #include <linux/dmaengine.h> | |
dcbe0d84 AD |
12 | #include <linux/interrupt.h> |
13 | #include <linux/iopoll.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/of_platform.h> | |
db96bf97 | 16 | #include <linux/pinctrl/consumer.h> |
038ac869 | 17 | #include <linux/pm_runtime.h> |
dcbe0d84 AD |
18 | #include <linux/reset.h> |
19 | #include <linux/spi/spi.h> | |
20 | ||
21 | #define DRIVER_NAME "spi_stm32" | |
22 | ||
00505edf CG |
23 | /* STM32F4 SPI registers */ |
24 | #define STM32F4_SPI_CR1 0x00 | |
25 | #define STM32F4_SPI_CR2 0x04 | |
26 | #define STM32F4_SPI_SR 0x08 | |
27 | #define STM32F4_SPI_DR 0x0C | |
28 | #define STM32F4_SPI_I2SCFGR 0x1C | |
29 | ||
30 | /* STM32F4_SPI_CR1 bit fields */ | |
31 | #define STM32F4_SPI_CR1_CPHA BIT(0) | |
32 | #define STM32F4_SPI_CR1_CPOL BIT(1) | |
33 | #define STM32F4_SPI_CR1_MSTR BIT(2) | |
34 | #define STM32F4_SPI_CR1_BR_SHIFT 3 | |
35 | #define STM32F4_SPI_CR1_BR GENMASK(5, 3) | |
36 | #define STM32F4_SPI_CR1_SPE BIT(6) | |
37 | #define STM32F4_SPI_CR1_LSBFRST BIT(7) | |
38 | #define STM32F4_SPI_CR1_SSI BIT(8) | |
39 | #define STM32F4_SPI_CR1_SSM BIT(9) | |
40 | #define STM32F4_SPI_CR1_RXONLY BIT(10) | |
41 | #define STM32F4_SPI_CR1_DFF BIT(11) | |
42 | #define STM32F4_SPI_CR1_CRCNEXT BIT(12) | |
43 | #define STM32F4_SPI_CR1_CRCEN BIT(13) | |
44 | #define STM32F4_SPI_CR1_BIDIOE BIT(14) | |
45 | #define STM32F4_SPI_CR1_BIDIMODE BIT(15) | |
46 | #define STM32F4_SPI_CR1_BR_MIN 0 | |
47 | #define STM32F4_SPI_CR1_BR_MAX (GENMASK(5, 3) >> 3) | |
48 | ||
49 | /* STM32F4_SPI_CR2 bit fields */ | |
50 | #define STM32F4_SPI_CR2_RXDMAEN BIT(0) | |
51 | #define STM32F4_SPI_CR2_TXDMAEN BIT(1) | |
52 | #define STM32F4_SPI_CR2_SSOE BIT(2) | |
53 | #define STM32F4_SPI_CR2_FRF BIT(4) | |
54 | #define STM32F4_SPI_CR2_ERRIE BIT(5) | |
55 | #define STM32F4_SPI_CR2_RXNEIE BIT(6) | |
56 | #define STM32F4_SPI_CR2_TXEIE BIT(7) | |
57 | ||
58 | /* STM32F4_SPI_SR bit fields */ | |
59 | #define STM32F4_SPI_SR_RXNE BIT(0) | |
60 | #define STM32F4_SPI_SR_TXE BIT(1) | |
61 | #define STM32F4_SPI_SR_CHSIDE BIT(2) | |
62 | #define STM32F4_SPI_SR_UDR BIT(3) | |
63 | #define STM32F4_SPI_SR_CRCERR BIT(4) | |
64 | #define STM32F4_SPI_SR_MODF BIT(5) | |
65 | #define STM32F4_SPI_SR_OVR BIT(6) | |
66 | #define STM32F4_SPI_SR_BSY BIT(7) | |
67 | #define STM32F4_SPI_SR_FRE BIT(8) | |
68 | ||
69 | /* STM32F4_SPI_I2SCFGR bit fields */ | |
70 | #define STM32F4_SPI_I2SCFGR_I2SMOD BIT(11) | |
71 | ||
72 | /* STM32F4 SPI Baud Rate min/max divisor */ | |
73 | #define STM32F4_SPI_BR_DIV_MIN (2 << STM32F4_SPI_CR1_BR_MIN) | |
74 | #define STM32F4_SPI_BR_DIV_MAX (2 << STM32F4_SPI_CR1_BR_MAX) | |
75 | ||
86026630 CG |
76 | /* STM32H7 SPI registers */ |
77 | #define STM32H7_SPI_CR1 0x00 | |
78 | #define STM32H7_SPI_CR2 0x04 | |
79 | #define STM32H7_SPI_CFG1 0x08 | |
80 | #define STM32H7_SPI_CFG2 0x0C | |
81 | #define STM32H7_SPI_IER 0x10 | |
82 | #define STM32H7_SPI_SR 0x14 | |
83 | #define STM32H7_SPI_IFCR 0x18 | |
84 | #define STM32H7_SPI_TXDR 0x20 | |
85 | #define STM32H7_SPI_RXDR 0x30 | |
86 | #define STM32H7_SPI_I2SCFGR 0x50 | |
87 | ||
88 | /* STM32H7_SPI_CR1 bit fields */ | |
89 | #define STM32H7_SPI_CR1_SPE BIT(0) | |
90 | #define STM32H7_SPI_CR1_MASRX BIT(8) | |
91 | #define STM32H7_SPI_CR1_CSTART BIT(9) | |
92 | #define STM32H7_SPI_CR1_CSUSP BIT(10) | |
93 | #define STM32H7_SPI_CR1_HDDIR BIT(11) | |
94 | #define STM32H7_SPI_CR1_SSI BIT(12) | |
95 | ||
96 | /* STM32H7_SPI_CR2 bit fields */ | |
97 | #define STM32H7_SPI_CR2_TSIZE_SHIFT 0 | |
98 | #define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0) | |
99 | ||
100 | /* STM32H7_SPI_CFG1 bit fields */ | |
101 | #define STM32H7_SPI_CFG1_DSIZE_SHIFT 0 | |
102 | #define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0) | |
103 | #define STM32H7_SPI_CFG1_FTHLV_SHIFT 5 | |
104 | #define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5) | |
105 | #define STM32H7_SPI_CFG1_RXDMAEN BIT(14) | |
106 | #define STM32H7_SPI_CFG1_TXDMAEN BIT(15) | |
107 | #define STM32H7_SPI_CFG1_MBR_SHIFT 28 | |
108 | #define STM32H7_SPI_CFG1_MBR GENMASK(30, 28) | |
109 | #define STM32H7_SPI_CFG1_MBR_MIN 0 | |
110 | #define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28) | |
111 | ||
112 | /* STM32H7_SPI_CFG2 bit fields */ | |
113 | #define STM32H7_SPI_CFG2_MIDI_SHIFT 4 | |
114 | #define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4) | |
115 | #define STM32H7_SPI_CFG2_COMM_SHIFT 17 | |
116 | #define STM32H7_SPI_CFG2_COMM GENMASK(18, 17) | |
117 | #define STM32H7_SPI_CFG2_SP_SHIFT 19 | |
118 | #define STM32H7_SPI_CFG2_SP GENMASK(21, 19) | |
119 | #define STM32H7_SPI_CFG2_MASTER BIT(22) | |
120 | #define STM32H7_SPI_CFG2_LSBFRST BIT(23) | |
121 | #define STM32H7_SPI_CFG2_CPHA BIT(24) | |
122 | #define STM32H7_SPI_CFG2_CPOL BIT(25) | |
123 | #define STM32H7_SPI_CFG2_SSM BIT(26) | |
124 | #define STM32H7_SPI_CFG2_AFCNTR BIT(31) | |
125 | ||
126 | /* STM32H7_SPI_IER bit fields */ | |
127 | #define STM32H7_SPI_IER_RXPIE BIT(0) | |
128 | #define STM32H7_SPI_IER_TXPIE BIT(1) | |
129 | #define STM32H7_SPI_IER_DXPIE BIT(2) | |
130 | #define STM32H7_SPI_IER_EOTIE BIT(3) | |
131 | #define STM32H7_SPI_IER_TXTFIE BIT(4) | |
132 | #define STM32H7_SPI_IER_OVRIE BIT(6) | |
133 | #define STM32H7_SPI_IER_MODFIE BIT(9) | |
134 | #define STM32H7_SPI_IER_ALL GENMASK(10, 0) | |
135 | ||
136 | /* STM32H7_SPI_SR bit fields */ | |
137 | #define STM32H7_SPI_SR_RXP BIT(0) | |
138 | #define STM32H7_SPI_SR_TXP BIT(1) | |
139 | #define STM32H7_SPI_SR_EOT BIT(3) | |
140 | #define STM32H7_SPI_SR_OVR BIT(6) | |
141 | #define STM32H7_SPI_SR_MODF BIT(9) | |
142 | #define STM32H7_SPI_SR_SUSP BIT(11) | |
143 | #define STM32H7_SPI_SR_RXPLVL_SHIFT 13 | |
144 | #define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13) | |
145 | #define STM32H7_SPI_SR_RXWNE BIT(15) | |
146 | ||
147 | /* STM32H7_SPI_IFCR bit fields */ | |
148 | #define STM32H7_SPI_IFCR_ALL GENMASK(11, 3) | |
149 | ||
150 | /* STM32H7_SPI_I2SCFGR bit fields */ | |
151 | #define STM32H7_SPI_I2SCFGR_I2SMOD BIT(0) | |
152 | ||
153 | /* STM32H7 SPI Master Baud Rate min/max divisor */ | |
154 | #define STM32H7_SPI_MBR_DIV_MIN (2 << STM32H7_SPI_CFG1_MBR_MIN) | |
155 | #define STM32H7_SPI_MBR_DIV_MAX (2 << STM32H7_SPI_CFG1_MBR_MAX) | |
dcbe0d84 | 156 | |
9d5fce16 CG |
157 | /* STM32H7 SPI Communication mode */ |
158 | #define STM32H7_SPI_FULL_DUPLEX 0 | |
159 | #define STM32H7_SPI_SIMPLEX_TX 1 | |
160 | #define STM32H7_SPI_SIMPLEX_RX 2 | |
161 | #define STM32H7_SPI_HALF_DUPLEX 3 | |
162 | ||
163 | /* SPI Communication type */ | |
dcbe0d84 AD |
164 | #define SPI_FULL_DUPLEX 0 |
165 | #define SPI_SIMPLEX_TX 1 | |
166 | #define SPI_SIMPLEX_RX 2 | |
9d5fce16 CG |
167 | #define SPI_3WIRE_TX 3 |
168 | #define SPI_3WIRE_RX 4 | |
dcbe0d84 AD |
169 | |
170 | #define SPI_1HZ_NS 1000000000 | |
171 | ||
00505edf CG |
172 | /* |
173 | * use PIO for small transfers, avoiding DMA setup/teardown overhead for drivers | |
174 | * without fifo buffers. | |
175 | */ | |
176 | #define SPI_DMA_MIN_BYTES 16 | |
177 | ||
55166853 | 178 | /** |
1c52be8b | 179 | * struct stm32_spi_reg - stm32 SPI register & bitfield desc |
55166853 CG |
180 | * @reg: register offset |
181 | * @mask: bitfield mask | |
182 | * @shift: left shift | |
183 | */ | |
184 | struct stm32_spi_reg { | |
185 | int reg; | |
186 | int mask; | |
187 | int shift; | |
188 | }; | |
189 | ||
190 | /** | |
1c52be8b AV |
191 | * struct stm32_spi_regspec - stm32 registers definition, compatible dependent data |
192 | * @en: enable register and SPI enable bit | |
193 | * @dma_rx_en: SPI DMA RX enable register end SPI DMA RX enable bit | |
194 | * @dma_tx_en: SPI DMA TX enable register end SPI DMA TX enable bit | |
195 | * @cpol: clock polarity register and polarity bit | |
196 | * @cpha: clock phase register and phase bit | |
197 | * @lsb_first: LSB transmitted first register and bit | |
198 | * @br: baud rate register and bitfields | |
199 | * @rx: SPI RX data register | |
200 | * @tx: SPI TX data register | |
55166853 CG |
201 | */ |
202 | struct stm32_spi_regspec { | |
203 | const struct stm32_spi_reg en; | |
204 | const struct stm32_spi_reg dma_rx_en; | |
205 | const struct stm32_spi_reg dma_tx_en; | |
206 | const struct stm32_spi_reg cpol; | |
207 | const struct stm32_spi_reg cpha; | |
208 | const struct stm32_spi_reg lsb_first; | |
209 | const struct stm32_spi_reg br; | |
210 | const struct stm32_spi_reg rx; | |
211 | const struct stm32_spi_reg tx; | |
212 | }; | |
213 | ||
214 | struct stm32_spi; | |
215 | ||
216 | /** | |
1c52be8b | 217 | * struct stm32_spi_cfg - stm32 compatible configuration data |
55166853 CG |
218 | * @regs: registers descriptions |
219 | * @get_fifo_size: routine to get fifo size | |
220 | * @get_bpw_mask: routine to get bits per word mask | |
221 | * @disable: routine to disable controller | |
222 | * @config: routine to configure controller as SPI Master | |
223 | * @set_bpw: routine to configure registers to for bits per word | |
224 | * @set_mode: routine to configure registers to desired mode | |
225 | * @set_data_idleness: optional routine to configure registers to desired idle | |
226 | * time between frames (if driver has this functionality) | |
1c52be8b | 227 | * @set_number_of_data: optional routine to configure registers to desired |
55166853 CG |
228 | * number of data (if driver has this functionality) |
229 | * @can_dma: routine to determine if the transfer is eligible for DMA use | |
230 | * @transfer_one_dma_start: routine to start transfer a single spi_transfer | |
231 | * using DMA | |
1c52be8b AV |
232 | * @dma_rx_cb: routine to call after DMA RX channel operation is complete |
233 | * @dma_tx_cb: routine to call after DMA TX channel operation is complete | |
55166853 CG |
234 | * @transfer_one_irq: routine to configure interrupts for driver |
235 | * @irq_handler_event: Interrupt handler for SPI controller events | |
236 | * @irq_handler_thread: thread of interrupt handler for SPI controller | |
237 | * @baud_rate_div_min: minimum baud rate divisor | |
238 | * @baud_rate_div_max: maximum baud rate divisor | |
239 | * @has_fifo: boolean to know if fifo is used for driver | |
240 | * @has_startbit: boolean to know if start bit is used to start transfer | |
241 | */ | |
242 | struct stm32_spi_cfg { | |
243 | const struct stm32_spi_regspec *regs; | |
244 | int (*get_fifo_size)(struct stm32_spi *spi); | |
245 | int (*get_bpw_mask)(struct stm32_spi *spi); | |
246 | void (*disable)(struct stm32_spi *spi); | |
247 | int (*config)(struct stm32_spi *spi); | |
248 | void (*set_bpw)(struct stm32_spi *spi); | |
249 | int (*set_mode)(struct stm32_spi *spi, unsigned int comm_type); | |
250 | void (*set_data_idleness)(struct stm32_spi *spi, u32 length); | |
251 | int (*set_number_of_data)(struct stm32_spi *spi, u32 length); | |
252 | void (*transfer_one_dma_start)(struct stm32_spi *spi); | |
253 | void (*dma_rx_cb)(void *data); | |
254 | void (*dma_tx_cb)(void *data); | |
255 | int (*transfer_one_irq)(struct stm32_spi *spi); | |
256 | irqreturn_t (*irq_handler_event)(int irq, void *dev_id); | |
257 | irqreturn_t (*irq_handler_thread)(int irq, void *dev_id); | |
258 | unsigned int baud_rate_div_min; | |
259 | unsigned int baud_rate_div_max; | |
260 | bool has_fifo; | |
261 | }; | |
262 | ||
dcbe0d84 AD |
263 | /** |
264 | * struct stm32_spi - private data of the SPI controller | |
265 | * @dev: driver model representation of the controller | |
266 | * @master: controller master interface | |
55166853 | 267 | * @cfg: compatible configuration data |
dcbe0d84 AD |
268 | * @base: virtual memory area |
269 | * @clk: hw kernel clock feeding the SPI clock generator | |
270 | * @clk_rate: rate of the hw kernel clock feeding the SPI clock generator | |
271 | * @rst: SPI controller reset line | |
272 | * @lock: prevent I/O concurrent access | |
273 | * @irq: SPI controller interrupt line | |
274 | * @fifo_size: size of the embedded fifo in bytes | |
275 | * @cur_midi: master inter-data idleness in ns | |
276 | * @cur_speed: speed configured in Hz | |
277 | * @cur_bpw: number of bits in a single SPI data frame | |
278 | * @cur_fthlv: fifo threshold level (data frames in a single data packet) | |
279 | * @cur_comm: SPI communication mode | |
280 | * @cur_xferlen: current transfer length in bytes | |
281 | * @cur_usedma: boolean to know if dma is used in current transfer | |
282 | * @tx_buf: data to be written, or NULL | |
283 | * @rx_buf: data to be read, or NULL | |
284 | * @tx_len: number of data to be written in bytes | |
285 | * @rx_len: number of data to be read in bytes | |
286 | * @dma_tx: dma channel for TX transfer | |
287 | * @dma_rx: dma channel for RX transfer | |
288 | * @phys_addr: SPI registers physical base address | |
289 | */ | |
290 | struct stm32_spi { | |
291 | struct device *dev; | |
292 | struct spi_master *master; | |
55166853 | 293 | const struct stm32_spi_cfg *cfg; |
dcbe0d84 AD |
294 | void __iomem *base; |
295 | struct clk *clk; | |
296 | u32 clk_rate; | |
297 | struct reset_control *rst; | |
298 | spinlock_t lock; /* prevent I/O concurrent access */ | |
299 | int irq; | |
300 | unsigned int fifo_size; | |
301 | ||
302 | unsigned int cur_midi; | |
303 | unsigned int cur_speed; | |
304 | unsigned int cur_bpw; | |
305 | unsigned int cur_fthlv; | |
306 | unsigned int cur_comm; | |
307 | unsigned int cur_xferlen; | |
308 | bool cur_usedma; | |
309 | ||
310 | const void *tx_buf; | |
311 | void *rx_buf; | |
312 | int tx_len; | |
313 | int rx_len; | |
314 | struct dma_chan *dma_tx; | |
315 | struct dma_chan *dma_rx; | |
316 | dma_addr_t phys_addr; | |
317 | }; | |
318 | ||
00505edf CG |
319 | static const struct stm32_spi_regspec stm32f4_spi_regspec = { |
320 | .en = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE }, | |
321 | ||
322 | .dma_rx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_RXDMAEN }, | |
323 | .dma_tx_en = { STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN }, | |
324 | ||
325 | .cpol = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPOL }, | |
326 | .cpha = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_CPHA }, | |
327 | .lsb_first = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_LSBFRST }, | |
328 | .br = { STM32F4_SPI_CR1, STM32F4_SPI_CR1_BR, STM32F4_SPI_CR1_BR_SHIFT }, | |
329 | ||
330 | .rx = { STM32F4_SPI_DR }, | |
331 | .tx = { STM32F4_SPI_DR }, | |
332 | }; | |
333 | ||
55166853 CG |
334 | static const struct stm32_spi_regspec stm32h7_spi_regspec = { |
335 | /* SPI data transfer is enabled but spi_ker_ck is idle. | |
336 | * CFG1 and CFG2 registers are write protected when SPE is enabled. | |
337 | */ | |
338 | .en = { STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE }, | |
339 | ||
340 | .dma_rx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_RXDMAEN }, | |
341 | .dma_tx_en = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN }, | |
342 | ||
343 | .cpol = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPOL }, | |
344 | .cpha = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_CPHA }, | |
345 | .lsb_first = { STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_LSBFRST }, | |
346 | .br = { STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_MBR, | |
347 | STM32H7_SPI_CFG1_MBR_SHIFT }, | |
348 | ||
349 | .rx = { STM32H7_SPI_RXDR }, | |
350 | .tx = { STM32H7_SPI_TXDR }, | |
351 | }; | |
352 | ||
dcbe0d84 AD |
353 | static inline void stm32_spi_set_bits(struct stm32_spi *spi, |
354 | u32 offset, u32 bits) | |
355 | { | |
356 | writel_relaxed(readl_relaxed(spi->base + offset) | bits, | |
357 | spi->base + offset); | |
358 | } | |
359 | ||
360 | static inline void stm32_spi_clr_bits(struct stm32_spi *spi, | |
361 | u32 offset, u32 bits) | |
362 | { | |
363 | writel_relaxed(readl_relaxed(spi->base + offset) & ~bits, | |
364 | spi->base + offset); | |
365 | } | |
366 | ||
367 | /** | |
55166853 | 368 | * stm32h7_spi_get_fifo_size - Return fifo size |
dcbe0d84 AD |
369 | * @spi: pointer to the spi controller data structure |
370 | */ | |
55166853 | 371 | static int stm32h7_spi_get_fifo_size(struct stm32_spi *spi) |
dcbe0d84 AD |
372 | { |
373 | unsigned long flags; | |
374 | u32 count = 0; | |
375 | ||
376 | spin_lock_irqsave(&spi->lock, flags); | |
377 | ||
86026630 | 378 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 | 379 | |
86026630 CG |
380 | while (readl_relaxed(spi->base + STM32H7_SPI_SR) & STM32H7_SPI_SR_TXP) |
381 | writeb_relaxed(++count, spi->base + STM32H7_SPI_TXDR); | |
dcbe0d84 | 382 | |
86026630 | 383 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 AD |
384 | |
385 | spin_unlock_irqrestore(&spi->lock, flags); | |
386 | ||
387 | dev_dbg(spi->dev, "%d x 8-bit fifo size\n", count); | |
388 | ||
389 | return count; | |
390 | } | |
391 | ||
00505edf CG |
392 | /** |
393 | * stm32f4_spi_get_bpw_mask - Return bits per word mask | |
394 | * @spi: pointer to the spi controller data structure | |
395 | */ | |
396 | static int stm32f4_spi_get_bpw_mask(struct stm32_spi *spi) | |
397 | { | |
398 | dev_dbg(spi->dev, "8-bit or 16-bit data frame supported\n"); | |
399 | return SPI_BPW_MASK(8) | SPI_BPW_MASK(16); | |
400 | } | |
401 | ||
dcbe0d84 | 402 | /** |
55166853 | 403 | * stm32h7_spi_get_bpw_mask - Return bits per word mask |
dcbe0d84 AD |
404 | * @spi: pointer to the spi controller data structure |
405 | */ | |
55166853 | 406 | static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi) |
dcbe0d84 AD |
407 | { |
408 | unsigned long flags; | |
409 | u32 cfg1, max_bpw; | |
410 | ||
411 | spin_lock_irqsave(&spi->lock, flags); | |
412 | ||
413 | /* | |
414 | * The most significant bit at DSIZE bit field is reserved when the | |
415 | * maximum data size of periperal instances is limited to 16-bit | |
416 | */ | |
86026630 | 417 | stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE); |
dcbe0d84 | 418 | |
86026630 CG |
419 | cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1); |
420 | max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >> | |
421 | STM32H7_SPI_CFG1_DSIZE_SHIFT; | |
dcbe0d84 AD |
422 | max_bpw += 1; |
423 | ||
424 | spin_unlock_irqrestore(&spi->lock, flags); | |
425 | ||
426 | dev_dbg(spi->dev, "%d-bit maximum data frame\n", max_bpw); | |
427 | ||
428 | return SPI_BPW_RANGE_MASK(4, max_bpw); | |
429 | } | |
430 | ||
431 | /** | |
9d5fce16 | 432 | * stm32_spi_prepare_mbr - Determine baud rate divisor value |
dcbe0d84 AD |
433 | * @spi: pointer to the spi controller data structure |
434 | * @speed_hz: requested speed | |
9d5fce16 CG |
435 | * @min_div: minimum baud rate divisor |
436 | * @max_div: maximum baud rate divisor | |
dcbe0d84 | 437 | * |
9d5fce16 | 438 | * Return baud rate divisor value in case of success or -EINVAL |
dcbe0d84 | 439 | */ |
9d5fce16 CG |
440 | static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32 speed_hz, |
441 | u32 min_div, u32 max_div) | |
dcbe0d84 AD |
442 | { |
443 | u32 div, mbrdiv; | |
444 | ||
9cc61973 AD |
445 | /* Ensure spi->clk_rate is even */ |
446 | div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz); | |
dcbe0d84 AD |
447 | |
448 | /* | |
449 | * SPI framework set xfer->speed_hz to master->max_speed_hz if | |
450 | * xfer->speed_hz is greater than master->max_speed_hz, and it returns | |
451 | * an error when xfer->speed_hz is lower than master->min_speed_hz, so | |
452 | * no need to check it there. | |
453 | * However, we need to ensure the following calculations. | |
454 | */ | |
9d5fce16 | 455 | if ((div < min_div) || (div > max_div)) |
dcbe0d84 AD |
456 | return -EINVAL; |
457 | ||
458 | /* Determine the first power of 2 greater than or equal to div */ | |
128ebb89 AD |
459 | if (div & (div - 1)) |
460 | mbrdiv = fls(div); | |
461 | else | |
462 | mbrdiv = fls(div) - 1; | |
dcbe0d84 AD |
463 | |
464 | spi->cur_speed = spi->clk_rate / (1 << mbrdiv); | |
465 | ||
466 | return mbrdiv - 1; | |
467 | } | |
468 | ||
469 | /** | |
55166853 | 470 | * stm32h7_spi_prepare_fthlv - Determine FIFO threshold level |
dcbe0d84 | 471 | * @spi: pointer to the spi controller data structure |
3373e900 | 472 | * @xfer_len: length of the message to be transferred |
dcbe0d84 | 473 | */ |
3373e900 | 474 | static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len) |
dcbe0d84 | 475 | { |
3373e900 | 476 | u32 fthlv, half_fifo, packet; |
dcbe0d84 AD |
477 | |
478 | /* data packet should not exceed 1/2 of fifo space */ | |
479 | half_fifo = (spi->fifo_size / 2); | |
480 | ||
3373e900 AD |
481 | /* data_packet should not exceed transfer length */ |
482 | if (half_fifo > xfer_len) | |
483 | packet = xfer_len; | |
484 | else | |
485 | packet = half_fifo; | |
486 | ||
128ebb89 | 487 | if (spi->cur_bpw <= 8) |
3373e900 | 488 | fthlv = packet; |
128ebb89 | 489 | else if (spi->cur_bpw <= 16) |
3373e900 | 490 | fthlv = packet / 2; |
128ebb89 | 491 | else |
3373e900 | 492 | fthlv = packet / 4; |
dcbe0d84 AD |
493 | |
494 | /* align packet size with data registers access */ | |
495 | if (spi->cur_bpw > 8) | |
496 | fthlv -= (fthlv % 2); /* multiple of 2 */ | |
497 | else | |
498 | fthlv -= (fthlv % 4); /* multiple of 4 */ | |
499 | ||
3373e900 AD |
500 | if (!fthlv) |
501 | fthlv = 1; | |
502 | ||
dcbe0d84 AD |
503 | return fthlv; |
504 | } | |
505 | ||
00505edf CG |
506 | /** |
507 | * stm32f4_spi_write_tx - Write bytes to Transmit Data Register | |
508 | * @spi: pointer to the spi controller data structure | |
509 | * | |
510 | * Read from tx_buf depends on remaining bytes to avoid to read beyond | |
511 | * tx_buf end. | |
512 | */ | |
513 | static void stm32f4_spi_write_tx(struct stm32_spi *spi) | |
514 | { | |
515 | if ((spi->tx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & | |
516 | STM32F4_SPI_SR_TXE)) { | |
517 | u32 offs = spi->cur_xferlen - spi->tx_len; | |
518 | ||
519 | if (spi->cur_bpw == 16) { | |
520 | const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); | |
521 | ||
522 | writew_relaxed(*tx_buf16, spi->base + STM32F4_SPI_DR); | |
523 | spi->tx_len -= sizeof(u16); | |
524 | } else { | |
525 | const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); | |
526 | ||
527 | writeb_relaxed(*tx_buf8, spi->base + STM32F4_SPI_DR); | |
528 | spi->tx_len -= sizeof(u8); | |
529 | } | |
530 | } | |
531 | ||
532 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); | |
533 | } | |
534 | ||
dcbe0d84 | 535 | /** |
55166853 | 536 | * stm32h7_spi_write_txfifo - Write bytes in Transmit Data Register |
dcbe0d84 AD |
537 | * @spi: pointer to the spi controller data structure |
538 | * | |
539 | * Read from tx_buf depends on remaining bytes to avoid to read beyond | |
540 | * tx_buf end. | |
541 | */ | |
55166853 | 542 | static void stm32h7_spi_write_txfifo(struct stm32_spi *spi) |
dcbe0d84 AD |
543 | { |
544 | while ((spi->tx_len > 0) && | |
86026630 CG |
545 | (readl_relaxed(spi->base + STM32H7_SPI_SR) & |
546 | STM32H7_SPI_SR_TXP)) { | |
dcbe0d84 AD |
547 | u32 offs = spi->cur_xferlen - spi->tx_len; |
548 | ||
549 | if (spi->tx_len >= sizeof(u32)) { | |
550 | const u32 *tx_buf32 = (const u32 *)(spi->tx_buf + offs); | |
551 | ||
86026630 | 552 | writel_relaxed(*tx_buf32, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
553 | spi->tx_len -= sizeof(u32); |
554 | } else if (spi->tx_len >= sizeof(u16)) { | |
555 | const u16 *tx_buf16 = (const u16 *)(spi->tx_buf + offs); | |
556 | ||
86026630 | 557 | writew_relaxed(*tx_buf16, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
558 | spi->tx_len -= sizeof(u16); |
559 | } else { | |
560 | const u8 *tx_buf8 = (const u8 *)(spi->tx_buf + offs); | |
561 | ||
86026630 | 562 | writeb_relaxed(*tx_buf8, spi->base + STM32H7_SPI_TXDR); |
dcbe0d84 AD |
563 | spi->tx_len -= sizeof(u8); |
564 | } | |
565 | } | |
566 | ||
567 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->tx_len); | |
568 | } | |
569 | ||
00505edf CG |
570 | /** |
571 | * stm32f4_spi_read_rx - Read bytes from Receive Data Register | |
572 | * @spi: pointer to the spi controller data structure | |
573 | * | |
574 | * Write in rx_buf depends on remaining bytes to avoid to write beyond | |
575 | * rx_buf end. | |
576 | */ | |
577 | static void stm32f4_spi_read_rx(struct stm32_spi *spi) | |
578 | { | |
579 | if ((spi->rx_len > 0) && (readl_relaxed(spi->base + STM32F4_SPI_SR) & | |
580 | STM32F4_SPI_SR_RXNE)) { | |
581 | u32 offs = spi->cur_xferlen - spi->rx_len; | |
582 | ||
583 | if (spi->cur_bpw == 16) { | |
584 | u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); | |
585 | ||
586 | *rx_buf16 = readw_relaxed(spi->base + STM32F4_SPI_DR); | |
587 | spi->rx_len -= sizeof(u16); | |
588 | } else { | |
589 | u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); | |
590 | ||
591 | *rx_buf8 = readb_relaxed(spi->base + STM32F4_SPI_DR); | |
592 | spi->rx_len -= sizeof(u8); | |
593 | } | |
594 | } | |
595 | ||
596 | dev_dbg(spi->dev, "%s: %d bytes left\n", __func__, spi->rx_len); | |
597 | } | |
598 | ||
dcbe0d84 | 599 | /** |
55166853 | 600 | * stm32h7_spi_read_rxfifo - Read bytes in Receive Data Register |
dcbe0d84 | 601 | * @spi: pointer to the spi controller data structure |
1c52be8b | 602 | * @flush: boolean indicating that FIFO should be flushed |
dcbe0d84 AD |
603 | * |
604 | * Write in rx_buf depends on remaining bytes to avoid to write beyond | |
605 | * rx_buf end. | |
606 | */ | |
55166853 | 607 | static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush) |
dcbe0d84 | 608 | { |
86026630 CG |
609 | u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
610 | u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> | |
611 | STM32H7_SPI_SR_RXPLVL_SHIFT; | |
dcbe0d84 AD |
612 | |
613 | while ((spi->rx_len > 0) && | |
86026630 CG |
614 | ((sr & STM32H7_SPI_SR_RXP) || |
615 | (flush && ((sr & STM32H7_SPI_SR_RXWNE) || (rxplvl > 0))))) { | |
dcbe0d84 AD |
616 | u32 offs = spi->cur_xferlen - spi->rx_len; |
617 | ||
618 | if ((spi->rx_len >= sizeof(u32)) || | |
86026630 | 619 | (flush && (sr & STM32H7_SPI_SR_RXWNE))) { |
dcbe0d84 AD |
620 | u32 *rx_buf32 = (u32 *)(spi->rx_buf + offs); |
621 | ||
86026630 | 622 | *rx_buf32 = readl_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
623 | spi->rx_len -= sizeof(u32); |
624 | } else if ((spi->rx_len >= sizeof(u16)) || | |
625 | (flush && (rxplvl >= 2 || spi->cur_bpw > 8))) { | |
626 | u16 *rx_buf16 = (u16 *)(spi->rx_buf + offs); | |
627 | ||
86026630 | 628 | *rx_buf16 = readw_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
629 | spi->rx_len -= sizeof(u16); |
630 | } else { | |
631 | u8 *rx_buf8 = (u8 *)(spi->rx_buf + offs); | |
632 | ||
86026630 | 633 | *rx_buf8 = readb_relaxed(spi->base + STM32H7_SPI_RXDR); |
dcbe0d84 AD |
634 | spi->rx_len -= sizeof(u8); |
635 | } | |
636 | ||
86026630 CG |
637 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
638 | rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >> | |
639 | STM32H7_SPI_SR_RXPLVL_SHIFT; | |
dcbe0d84 AD |
640 | } |
641 | ||
642 | dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__, | |
643 | flush ? "(flush)" : "", spi->rx_len); | |
644 | } | |
645 | ||
646 | /** | |
647 | * stm32_spi_enable - Enable SPI controller | |
648 | * @spi: pointer to the spi controller data structure | |
dcbe0d84 AD |
649 | */ |
650 | static void stm32_spi_enable(struct stm32_spi *spi) | |
651 | { | |
652 | dev_dbg(spi->dev, "enable controller\n"); | |
653 | ||
55166853 CG |
654 | stm32_spi_set_bits(spi, spi->cfg->regs->en.reg, |
655 | spi->cfg->regs->en.mask); | |
dcbe0d84 AD |
656 | } |
657 | ||
00505edf CG |
658 | /** |
659 | * stm32f4_spi_disable - Disable SPI controller | |
660 | * @spi: pointer to the spi controller data structure | |
661 | */ | |
662 | static void stm32f4_spi_disable(struct stm32_spi *spi) | |
663 | { | |
664 | unsigned long flags; | |
665 | u32 sr; | |
666 | ||
667 | dev_dbg(spi->dev, "disable controller\n"); | |
668 | ||
669 | spin_lock_irqsave(&spi->lock, flags); | |
670 | ||
671 | if (!(readl_relaxed(spi->base + STM32F4_SPI_CR1) & | |
672 | STM32F4_SPI_CR1_SPE)) { | |
673 | spin_unlock_irqrestore(&spi->lock, flags); | |
674 | return; | |
675 | } | |
676 | ||
677 | /* Disable interrupts */ | |
678 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXEIE | | |
679 | STM32F4_SPI_CR2_RXNEIE | | |
680 | STM32F4_SPI_CR2_ERRIE); | |
681 | ||
682 | /* Wait until BSY = 0 */ | |
683 | if (readl_relaxed_poll_timeout_atomic(spi->base + STM32F4_SPI_SR, | |
684 | sr, !(sr & STM32F4_SPI_SR_BSY), | |
685 | 10, 100000) < 0) { | |
686 | dev_warn(spi->dev, "disabling condition timeout\n"); | |
687 | } | |
688 | ||
689 | if (spi->cur_usedma && spi->dma_tx) | |
690 | dmaengine_terminate_all(spi->dma_tx); | |
691 | if (spi->cur_usedma && spi->dma_rx) | |
692 | dmaengine_terminate_all(spi->dma_rx); | |
693 | ||
694 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SPE); | |
695 | ||
696 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_TXDMAEN | | |
697 | STM32F4_SPI_CR2_RXDMAEN); | |
698 | ||
699 | /* Sequence to clear OVR flag */ | |
700 | readl_relaxed(spi->base + STM32F4_SPI_DR); | |
701 | readl_relaxed(spi->base + STM32F4_SPI_SR); | |
702 | ||
703 | spin_unlock_irqrestore(&spi->lock, flags); | |
704 | } | |
705 | ||
dcbe0d84 | 706 | /** |
55166853 | 707 | * stm32h7_spi_disable - Disable SPI controller |
dcbe0d84 AD |
708 | * @spi: pointer to the spi controller data structure |
709 | * | |
710 | * RX-Fifo is flushed when SPI controller is disabled. To prevent any data | |
55166853 | 711 | * loss, use stm32h7_spi_read_rxfifo(flush) to read the remaining bytes in |
dcbe0d84 | 712 | * RX-Fifo. |
55166853 CG |
713 | * Normally, if TSIZE has been configured, we should relax the hardware at the |
714 | * reception of the EOT interrupt. But in case of error, EOT will not be | |
715 | * raised. So the subsystem unprepare_message call allows us to properly | |
716 | * complete the transfer from an hardware point of view. | |
dcbe0d84 | 717 | */ |
55166853 | 718 | static void stm32h7_spi_disable(struct stm32_spi *spi) |
dcbe0d84 AD |
719 | { |
720 | unsigned long flags; | |
721 | u32 cr1, sr; | |
722 | ||
723 | dev_dbg(spi->dev, "disable controller\n"); | |
724 | ||
725 | spin_lock_irqsave(&spi->lock, flags); | |
726 | ||
86026630 | 727 | cr1 = readl_relaxed(spi->base + STM32H7_SPI_CR1); |
dcbe0d84 | 728 | |
86026630 | 729 | if (!(cr1 & STM32H7_SPI_CR1_SPE)) { |
dcbe0d84 AD |
730 | spin_unlock_irqrestore(&spi->lock, flags); |
731 | return; | |
732 | } | |
733 | ||
734 | /* Wait on EOT or suspend the flow */ | |
86026630 CG |
735 | if (readl_relaxed_poll_timeout_atomic(spi->base + STM32H7_SPI_SR, |
736 | sr, !(sr & STM32H7_SPI_SR_EOT), | |
dcbe0d84 | 737 | 10, 100000) < 0) { |
86026630 CG |
738 | if (cr1 & STM32H7_SPI_CR1_CSTART) { |
739 | writel_relaxed(cr1 | STM32H7_SPI_CR1_CSUSP, | |
740 | spi->base + STM32H7_SPI_CR1); | |
dcbe0d84 | 741 | if (readl_relaxed_poll_timeout_atomic( |
86026630 CG |
742 | spi->base + STM32H7_SPI_SR, |
743 | sr, !(sr & STM32H7_SPI_SR_SUSP), | |
dcbe0d84 AD |
744 | 10, 100000) < 0) |
745 | dev_warn(spi->dev, | |
746 | "Suspend request timeout\n"); | |
747 | } | |
748 | } | |
749 | ||
750 | if (!spi->cur_usedma && spi->rx_buf && (spi->rx_len > 0)) | |
55166853 | 751 | stm32h7_spi_read_rxfifo(spi, true); |
dcbe0d84 | 752 | |
2cbee7f8 | 753 | if (spi->cur_usedma && spi->dma_tx) |
dcbe0d84 | 754 | dmaengine_terminate_all(spi->dma_tx); |
2cbee7f8 | 755 | if (spi->cur_usedma && spi->dma_rx) |
dcbe0d84 AD |
756 | dmaengine_terminate_all(spi->dma_rx); |
757 | ||
86026630 | 758 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SPE); |
dcbe0d84 | 759 | |
86026630 CG |
760 | stm32_spi_clr_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_TXDMAEN | |
761 | STM32H7_SPI_CFG1_RXDMAEN); | |
dcbe0d84 AD |
762 | |
763 | /* Disable interrupts and clear status flags */ | |
86026630 CG |
764 | writel_relaxed(0, spi->base + STM32H7_SPI_IER); |
765 | writel_relaxed(STM32H7_SPI_IFCR_ALL, spi->base + STM32H7_SPI_IFCR); | |
dcbe0d84 AD |
766 | |
767 | spin_unlock_irqrestore(&spi->lock, flags); | |
768 | } | |
769 | ||
770 | /** | |
771 | * stm32_spi_can_dma - Determine if the transfer is eligible for DMA use | |
1c52be8b AV |
772 | * @master: controller master interface |
773 | * @spi_dev: pointer to the spi device | |
774 | * @transfer: pointer to spi transfer | |
dcbe0d84 | 775 | * |
00505edf CG |
776 | * If driver has fifo and the current transfer size is greater than fifo size, |
777 | * use DMA. Otherwise use DMA for transfer longer than defined DMA min bytes. | |
dcbe0d84 AD |
778 | */ |
779 | static bool stm32_spi_can_dma(struct spi_master *master, | |
780 | struct spi_device *spi_dev, | |
781 | struct spi_transfer *transfer) | |
782 | { | |
00505edf | 783 | unsigned int dma_size; |
dcbe0d84 AD |
784 | struct stm32_spi *spi = spi_master_get_devdata(master); |
785 | ||
00505edf CG |
786 | if (spi->cfg->has_fifo) |
787 | dma_size = spi->fifo_size; | |
788 | else | |
789 | dma_size = SPI_DMA_MIN_BYTES; | |
790 | ||
dcbe0d84 | 791 | dev_dbg(spi->dev, "%s: %s\n", __func__, |
00505edf | 792 | (transfer->len > dma_size) ? "true" : "false"); |
dcbe0d84 | 793 | |
00505edf CG |
794 | return (transfer->len > dma_size); |
795 | } | |
796 | ||
797 | /** | |
798 | * stm32f4_spi_irq_event - Interrupt handler for SPI controller events | |
799 | * @irq: interrupt line | |
800 | * @dev_id: SPI controller master interface | |
801 | */ | |
802 | static irqreturn_t stm32f4_spi_irq_event(int irq, void *dev_id) | |
803 | { | |
804 | struct spi_master *master = dev_id; | |
805 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
806 | u32 sr, mask = 0; | |
00505edf CG |
807 | bool end = false; |
808 | ||
e2368933 | 809 | spin_lock(&spi->lock); |
00505edf CG |
810 | |
811 | sr = readl_relaxed(spi->base + STM32F4_SPI_SR); | |
812 | /* | |
813 | * BSY flag is not handled in interrupt but it is normal behavior when | |
814 | * this flag is set. | |
815 | */ | |
816 | sr &= ~STM32F4_SPI_SR_BSY; | |
817 | ||
818 | if (!spi->cur_usedma && (spi->cur_comm == SPI_SIMPLEX_TX || | |
819 | spi->cur_comm == SPI_3WIRE_TX)) { | |
820 | /* OVR flag shouldn't be handled for TX only mode */ | |
821 | sr &= ~STM32F4_SPI_SR_OVR | STM32F4_SPI_SR_RXNE; | |
822 | mask |= STM32F4_SPI_SR_TXE; | |
823 | } | |
824 | ||
61367d0b | 825 | if (!spi->cur_usedma && (spi->cur_comm == SPI_FULL_DUPLEX || |
826 | spi->cur_comm == SPI_SIMPLEX_RX || | |
827 | spi->cur_comm == SPI_3WIRE_RX)) { | |
00505edf CG |
828 | /* TXE flag is set and is handled when RXNE flag occurs */ |
829 | sr &= ~STM32F4_SPI_SR_TXE; | |
830 | mask |= STM32F4_SPI_SR_RXNE | STM32F4_SPI_SR_OVR; | |
831 | } | |
832 | ||
833 | if (!(sr & mask)) { | |
834 | dev_dbg(spi->dev, "spurious IT (sr=0x%08x)\n", sr); | |
e2368933 | 835 | spin_unlock(&spi->lock); |
00505edf CG |
836 | return IRQ_NONE; |
837 | } | |
838 | ||
839 | if (sr & STM32F4_SPI_SR_OVR) { | |
840 | dev_warn(spi->dev, "Overrun: received value discarded\n"); | |
841 | ||
842 | /* Sequence to clear OVR flag */ | |
843 | readl_relaxed(spi->base + STM32F4_SPI_DR); | |
844 | readl_relaxed(spi->base + STM32F4_SPI_SR); | |
845 | ||
846 | /* | |
847 | * If overrun is detected, it means that something went wrong, | |
848 | * so stop the current transfer. Transfer can wait for next | |
849 | * RXNE but DR is already read and end never happens. | |
850 | */ | |
851 | end = true; | |
852 | goto end_irq; | |
853 | } | |
854 | ||
855 | if (sr & STM32F4_SPI_SR_TXE) { | |
856 | if (spi->tx_buf) | |
857 | stm32f4_spi_write_tx(spi); | |
858 | if (spi->tx_len == 0) | |
859 | end = true; | |
860 | } | |
861 | ||
862 | if (sr & STM32F4_SPI_SR_RXNE) { | |
863 | stm32f4_spi_read_rx(spi); | |
864 | if (spi->rx_len == 0) | |
865 | end = true; | |
61367d0b | 866 | else if (spi->tx_buf)/* Load data for discontinuous mode */ |
00505edf CG |
867 | stm32f4_spi_write_tx(spi); |
868 | } | |
869 | ||
870 | end_irq: | |
871 | if (end) { | |
872 | /* Immediately disable interrupts to do not generate new one */ | |
873 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR2, | |
874 | STM32F4_SPI_CR2_TXEIE | | |
875 | STM32F4_SPI_CR2_RXNEIE | | |
876 | STM32F4_SPI_CR2_ERRIE); | |
e2368933 | 877 | spin_unlock(&spi->lock); |
00505edf CG |
878 | return IRQ_WAKE_THREAD; |
879 | } | |
880 | ||
e2368933 | 881 | spin_unlock(&spi->lock); |
00505edf CG |
882 | return IRQ_HANDLED; |
883 | } | |
884 | ||
885 | /** | |
886 | * stm32f4_spi_irq_thread - Thread of interrupt handler for SPI controller | |
887 | * @irq: interrupt line | |
888 | * @dev_id: SPI controller master interface | |
889 | */ | |
890 | static irqreturn_t stm32f4_spi_irq_thread(int irq, void *dev_id) | |
891 | { | |
892 | struct spi_master *master = dev_id; | |
893 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
894 | ||
895 | spi_finalize_current_transfer(master); | |
896 | stm32f4_spi_disable(spi); | |
897 | ||
898 | return IRQ_HANDLED; | |
dcbe0d84 AD |
899 | } |
900 | ||
901 | /** | |
55166853 | 902 | * stm32h7_spi_irq_thread - Thread of interrupt handler for SPI controller |
dcbe0d84 AD |
903 | * @irq: interrupt line |
904 | * @dev_id: SPI controller master interface | |
905 | */ | |
55166853 | 906 | static irqreturn_t stm32h7_spi_irq_thread(int irq, void *dev_id) |
dcbe0d84 AD |
907 | { |
908 | struct spi_master *master = dev_id; | |
909 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
910 | u32 sr, ier, mask; | |
911 | unsigned long flags; | |
912 | bool end = false; | |
913 | ||
914 | spin_lock_irqsave(&spi->lock, flags); | |
915 | ||
86026630 CG |
916 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
917 | ier = readl_relaxed(spi->base + STM32H7_SPI_IER); | |
dcbe0d84 AD |
918 | |
919 | mask = ier; | |
920 | /* EOTIE is triggered on EOT, SUSP and TXC events. */ | |
86026630 | 921 | mask |= STM32H7_SPI_SR_SUSP; |
dcbe0d84 AD |
922 | /* |
923 | * When TXTF is set, DXPIE and TXPIE are cleared. So in case of | |
924 | * Full-Duplex, need to poll RXP event to know if there are remaining | |
925 | * data, before disabling SPI. | |
926 | */ | |
128ebb89 | 927 | if (spi->rx_buf && !spi->cur_usedma) |
86026630 | 928 | mask |= STM32H7_SPI_SR_RXP; |
dcbe0d84 AD |
929 | |
930 | if (!(sr & mask)) { | |
931 | dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n", | |
932 | sr, ier); | |
933 | spin_unlock_irqrestore(&spi->lock, flags); | |
934 | return IRQ_NONE; | |
935 | } | |
936 | ||
86026630 | 937 | if (sr & STM32H7_SPI_SR_SUSP) { |
ea8be08c MV |
938 | static DEFINE_RATELIMIT_STATE(rs, |
939 | DEFAULT_RATELIMIT_INTERVAL * 10, | |
940 | 1); | |
941 | if (__ratelimit(&rs)) | |
942 | dev_dbg_ratelimited(spi->dev, "Communication suspended\n"); | |
dcbe0d84 | 943 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) |
55166853 | 944 | stm32h7_spi_read_rxfifo(spi, false); |
c67ad368 AD |
945 | /* |
946 | * If communication is suspended while using DMA, it means | |
947 | * that something went wrong, so stop the current transfer | |
948 | */ | |
949 | if (spi->cur_usedma) | |
950 | end = true; | |
dcbe0d84 AD |
951 | } |
952 | ||
86026630 | 953 | if (sr & STM32H7_SPI_SR_MODF) { |
dcbe0d84 AD |
954 | dev_warn(spi->dev, "Mode fault: transfer aborted\n"); |
955 | end = true; | |
956 | } | |
957 | ||
86026630 | 958 | if (sr & STM32H7_SPI_SR_OVR) { |
dcbe0d84 AD |
959 | dev_warn(spi->dev, "Overrun: received value discarded\n"); |
960 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) | |
55166853 | 961 | stm32h7_spi_read_rxfifo(spi, false); |
c67ad368 AD |
962 | /* |
963 | * If overrun is detected while using DMA, it means that | |
964 | * something went wrong, so stop the current transfer | |
965 | */ | |
966 | if (spi->cur_usedma) | |
967 | end = true; | |
dcbe0d84 AD |
968 | } |
969 | ||
86026630 | 970 | if (sr & STM32H7_SPI_SR_EOT) { |
dcbe0d84 | 971 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) |
55166853 | 972 | stm32h7_spi_read_rxfifo(spi, true); |
dcbe0d84 AD |
973 | end = true; |
974 | } | |
975 | ||
86026630 | 976 | if (sr & STM32H7_SPI_SR_TXP) |
dcbe0d84 | 977 | if (!spi->cur_usedma && (spi->tx_buf && (spi->tx_len > 0))) |
55166853 | 978 | stm32h7_spi_write_txfifo(spi); |
dcbe0d84 | 979 | |
86026630 | 980 | if (sr & STM32H7_SPI_SR_RXP) |
dcbe0d84 | 981 | if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0))) |
55166853 | 982 | stm32h7_spi_read_rxfifo(spi, false); |
dcbe0d84 | 983 | |
ae1ba50f | 984 | writel_relaxed(sr & mask, spi->base + STM32H7_SPI_IFCR); |
dcbe0d84 AD |
985 | |
986 | spin_unlock_irqrestore(&spi->lock, flags); | |
987 | ||
988 | if (end) { | |
55166853 | 989 | stm32h7_spi_disable(spi); |
135dd873 | 990 | spi_finalize_current_transfer(master); |
dcbe0d84 AD |
991 | } |
992 | ||
993 | return IRQ_HANDLED; | |
994 | } | |
995 | ||
dcbe0d84 AD |
996 | /** |
997 | * stm32_spi_prepare_msg - set up the controller to transfer a single message | |
1c52be8b AV |
998 | * @master: controller master interface |
999 | * @msg: pointer to spi message | |
dcbe0d84 AD |
1000 | */ |
1001 | static int stm32_spi_prepare_msg(struct spi_master *master, | |
1002 | struct spi_message *msg) | |
1003 | { | |
1004 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1005 | struct spi_device *spi_dev = msg->spi; | |
1006 | struct device_node *np = spi_dev->dev.of_node; | |
1007 | unsigned long flags; | |
55166853 | 1008 | u32 clrb = 0, setb = 0; |
dcbe0d84 AD |
1009 | |
1010 | /* SPI slave device may need time between data frames */ | |
1011 | spi->cur_midi = 0; | |
042c1c60 | 1012 | if (np && !of_property_read_u32(np, "st,spi-midi-ns", &spi->cur_midi)) |
dcbe0d84 AD |
1013 | dev_dbg(spi->dev, "%dns inter-data idleness\n", spi->cur_midi); |
1014 | ||
1015 | if (spi_dev->mode & SPI_CPOL) | |
55166853 | 1016 | setb |= spi->cfg->regs->cpol.mask; |
dcbe0d84 | 1017 | else |
55166853 | 1018 | clrb |= spi->cfg->regs->cpol.mask; |
dcbe0d84 AD |
1019 | |
1020 | if (spi_dev->mode & SPI_CPHA) | |
55166853 | 1021 | setb |= spi->cfg->regs->cpha.mask; |
dcbe0d84 | 1022 | else |
55166853 | 1023 | clrb |= spi->cfg->regs->cpha.mask; |
dcbe0d84 AD |
1024 | |
1025 | if (spi_dev->mode & SPI_LSB_FIRST) | |
55166853 | 1026 | setb |= spi->cfg->regs->lsb_first.mask; |
dcbe0d84 | 1027 | else |
55166853 | 1028 | clrb |= spi->cfg->regs->lsb_first.mask; |
dcbe0d84 AD |
1029 | |
1030 | dev_dbg(spi->dev, "cpol=%d cpha=%d lsb_first=%d cs_high=%d\n", | |
1031 | spi_dev->mode & SPI_CPOL, | |
1032 | spi_dev->mode & SPI_CPHA, | |
1033 | spi_dev->mode & SPI_LSB_FIRST, | |
1034 | spi_dev->mode & SPI_CS_HIGH); | |
1035 | ||
1036 | spin_lock_irqsave(&spi->lock, flags); | |
1037 | ||
55166853 CG |
1038 | /* CPOL, CPHA and LSB FIRST bits have common register */ |
1039 | if (clrb || setb) | |
dcbe0d84 | 1040 | writel_relaxed( |
55166853 CG |
1041 | (readl_relaxed(spi->base + spi->cfg->regs->cpol.reg) & |
1042 | ~clrb) | setb, | |
1043 | spi->base + spi->cfg->regs->cpol.reg); | |
dcbe0d84 AD |
1044 | |
1045 | spin_unlock_irqrestore(&spi->lock, flags); | |
1046 | ||
1047 | return 0; | |
1048 | } | |
1049 | ||
00505edf CG |
1050 | /** |
1051 | * stm32f4_spi_dma_tx_cb - dma callback | |
1c52be8b | 1052 | * @data: pointer to the spi controller data structure |
00505edf CG |
1053 | * |
1054 | * DMA callback is called when the transfer is complete for DMA TX channel. | |
1055 | */ | |
1056 | static void stm32f4_spi_dma_tx_cb(void *data) | |
1057 | { | |
1058 | struct stm32_spi *spi = data; | |
1059 | ||
1060 | if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { | |
1061 | spi_finalize_current_transfer(spi->master); | |
1062 | stm32f4_spi_disable(spi); | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | /** | |
1067 | * stm32f4_spi_dma_rx_cb - dma callback | |
1c52be8b | 1068 | * @data: pointer to the spi controller data structure |
00505edf CG |
1069 | * |
1070 | * DMA callback is called when the transfer is complete for DMA RX channel. | |
1071 | */ | |
1072 | static void stm32f4_spi_dma_rx_cb(void *data) | |
1073 | { | |
1074 | struct stm32_spi *spi = data; | |
1075 | ||
1076 | spi_finalize_current_transfer(spi->master); | |
1077 | stm32f4_spi_disable(spi); | |
1078 | } | |
1079 | ||
dcbe0d84 | 1080 | /** |
55166853 | 1081 | * stm32h7_spi_dma_cb - dma callback |
1c52be8b | 1082 | * @data: pointer to the spi controller data structure |
dcbe0d84 AD |
1083 | * |
1084 | * DMA callback is called when the transfer is complete or when an error | |
1085 | * occurs. If the transfer is complete, EOT flag is raised. | |
1086 | */ | |
55166853 | 1087 | static void stm32h7_spi_dma_cb(void *data) |
dcbe0d84 AD |
1088 | { |
1089 | struct stm32_spi *spi = data; | |
1090 | unsigned long flags; | |
1091 | u32 sr; | |
1092 | ||
1093 | spin_lock_irqsave(&spi->lock, flags); | |
1094 | ||
86026630 | 1095 | sr = readl_relaxed(spi->base + STM32H7_SPI_SR); |
dcbe0d84 AD |
1096 | |
1097 | spin_unlock_irqrestore(&spi->lock, flags); | |
1098 | ||
86026630 | 1099 | if (!(sr & STM32H7_SPI_SR_EOT)) |
c67ad368 | 1100 | dev_warn(spi->dev, "DMA error (sr=0x%08x)\n", sr); |
dcbe0d84 | 1101 | |
c67ad368 | 1102 | /* Now wait for EOT, or SUSP or OVR in case of error */ |
dcbe0d84 AD |
1103 | } |
1104 | ||
1105 | /** | |
1106 | * stm32_spi_dma_config - configure dma slave channel depending on current | |
1107 | * transfer bits_per_word. | |
1c52be8b AV |
1108 | * @spi: pointer to the spi controller data structure |
1109 | * @dma_conf: pointer to the dma_slave_config structure | |
1110 | * @dir: direction of the dma transfer | |
dcbe0d84 AD |
1111 | */ |
1112 | static void stm32_spi_dma_config(struct stm32_spi *spi, | |
1113 | struct dma_slave_config *dma_conf, | |
1114 | enum dma_transfer_direction dir) | |
1115 | { | |
1116 | enum dma_slave_buswidth buswidth; | |
1117 | u32 maxburst; | |
1118 | ||
128ebb89 AD |
1119 | if (spi->cur_bpw <= 8) |
1120 | buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1121 | else if (spi->cur_bpw <= 16) | |
1122 | buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1123 | else | |
1124 | buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
dcbe0d84 | 1125 | |
00505edf CG |
1126 | if (spi->cfg->has_fifo) { |
1127 | /* Valid for DMA Half or Full Fifo threshold */ | |
1128 | if (spi->cur_fthlv == 2) | |
1129 | maxburst = 1; | |
1130 | else | |
1131 | maxburst = spi->cur_fthlv; | |
1132 | } else { | |
128ebb89 | 1133 | maxburst = 1; |
00505edf | 1134 | } |
dcbe0d84 AD |
1135 | |
1136 | memset(dma_conf, 0, sizeof(struct dma_slave_config)); | |
1137 | dma_conf->direction = dir; | |
1138 | if (dma_conf->direction == DMA_DEV_TO_MEM) { /* RX */ | |
55166853 | 1139 | dma_conf->src_addr = spi->phys_addr + spi->cfg->regs->rx.reg; |
dcbe0d84 AD |
1140 | dma_conf->src_addr_width = buswidth; |
1141 | dma_conf->src_maxburst = maxburst; | |
1142 | ||
1143 | dev_dbg(spi->dev, "Rx DMA config buswidth=%d, maxburst=%d\n", | |
1144 | buswidth, maxburst); | |
1145 | } else if (dma_conf->direction == DMA_MEM_TO_DEV) { /* TX */ | |
55166853 | 1146 | dma_conf->dst_addr = spi->phys_addr + spi->cfg->regs->tx.reg; |
dcbe0d84 AD |
1147 | dma_conf->dst_addr_width = buswidth; |
1148 | dma_conf->dst_maxburst = maxburst; | |
1149 | ||
1150 | dev_dbg(spi->dev, "Tx DMA config buswidth=%d, maxburst=%d\n", | |
1151 | buswidth, maxburst); | |
1152 | } | |
1153 | } | |
1154 | ||
00505edf CG |
1155 | /** |
1156 | * stm32f4_spi_transfer_one_irq - transfer a single spi_transfer using | |
1157 | * interrupts | |
1c52be8b | 1158 | * @spi: pointer to the spi controller data structure |
00505edf CG |
1159 | * |
1160 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1161 | * in progress. | |
1162 | */ | |
1163 | static int stm32f4_spi_transfer_one_irq(struct stm32_spi *spi) | |
1164 | { | |
1165 | unsigned long flags; | |
1166 | u32 cr2 = 0; | |
1167 | ||
1168 | /* Enable the interrupts relative to the current communication mode */ | |
1169 | if (spi->cur_comm == SPI_SIMPLEX_TX || spi->cur_comm == SPI_3WIRE_TX) { | |
1170 | cr2 |= STM32F4_SPI_CR2_TXEIE; | |
61367d0b | 1171 | } else if (spi->cur_comm == SPI_FULL_DUPLEX || |
1172 | spi->cur_comm == SPI_SIMPLEX_RX || | |
1173 | spi->cur_comm == SPI_3WIRE_RX) { | |
00505edf CG |
1174 | /* In transmit-only mode, the OVR flag is set in the SR register |
1175 | * since the received data are never read. Therefore set OVR | |
1176 | * interrupt only when rx buffer is available. | |
1177 | */ | |
1178 | cr2 |= STM32F4_SPI_CR2_RXNEIE | STM32F4_SPI_CR2_ERRIE; | |
1179 | } else { | |
1180 | return -EINVAL; | |
1181 | } | |
1182 | ||
1183 | spin_lock_irqsave(&spi->lock, flags); | |
1184 | ||
1185 | stm32_spi_set_bits(spi, STM32F4_SPI_CR2, cr2); | |
1186 | ||
1187 | stm32_spi_enable(spi); | |
1188 | ||
1189 | /* starting data transfer when buffer is loaded */ | |
1190 | if (spi->tx_buf) | |
1191 | stm32f4_spi_write_tx(spi); | |
1192 | ||
1193 | spin_unlock_irqrestore(&spi->lock, flags); | |
1194 | ||
1195 | return 1; | |
1196 | } | |
1197 | ||
dcbe0d84 | 1198 | /** |
55166853 CG |
1199 | * stm32h7_spi_transfer_one_irq - transfer a single spi_transfer using |
1200 | * interrupts | |
1c52be8b | 1201 | * @spi: pointer to the spi controller data structure |
dcbe0d84 AD |
1202 | * |
1203 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1204 | * in progress. | |
1205 | */ | |
55166853 | 1206 | static int stm32h7_spi_transfer_one_irq(struct stm32_spi *spi) |
dcbe0d84 AD |
1207 | { |
1208 | unsigned long flags; | |
1209 | u32 ier = 0; | |
1210 | ||
1211 | /* Enable the interrupts relative to the current communication mode */ | |
1212 | if (spi->tx_buf && spi->rx_buf) /* Full Duplex */ | |
86026630 | 1213 | ier |= STM32H7_SPI_IER_DXPIE; |
dcbe0d84 | 1214 | else if (spi->tx_buf) /* Half-Duplex TX dir or Simplex TX */ |
86026630 | 1215 | ier |= STM32H7_SPI_IER_TXPIE; |
dcbe0d84 | 1216 | else if (spi->rx_buf) /* Half-Duplex RX dir or Simplex RX */ |
86026630 | 1217 | ier |= STM32H7_SPI_IER_RXPIE; |
dcbe0d84 AD |
1218 | |
1219 | /* Enable the interrupts relative to the end of transfer */ | |
86026630 CG |
1220 | ier |= STM32H7_SPI_IER_EOTIE | STM32H7_SPI_IER_TXTFIE | |
1221 | STM32H7_SPI_IER_OVRIE | STM32H7_SPI_IER_MODFIE; | |
dcbe0d84 AD |
1222 | |
1223 | spin_lock_irqsave(&spi->lock, flags); | |
1224 | ||
1225 | stm32_spi_enable(spi); | |
1226 | ||
1227 | /* Be sure to have data in fifo before starting data transfer */ | |
1228 | if (spi->tx_buf) | |
55166853 | 1229 | stm32h7_spi_write_txfifo(spi); |
dcbe0d84 | 1230 | |
86026630 | 1231 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); |
dcbe0d84 | 1232 | |
86026630 | 1233 | writel_relaxed(ier, spi->base + STM32H7_SPI_IER); |
dcbe0d84 AD |
1234 | |
1235 | spin_unlock_irqrestore(&spi->lock, flags); | |
1236 | ||
1237 | return 1; | |
1238 | } | |
1239 | ||
00505edf CG |
1240 | /** |
1241 | * stm32f4_spi_transfer_one_dma_start - Set SPI driver registers to start | |
1242 | * transfer using DMA | |
1c52be8b | 1243 | * @spi: pointer to the spi controller data structure |
00505edf CG |
1244 | */ |
1245 | static void stm32f4_spi_transfer_one_dma_start(struct stm32_spi *spi) | |
1246 | { | |
1247 | /* In DMA mode end of transfer is handled by DMA TX or RX callback. */ | |
1248 | if (spi->cur_comm == SPI_SIMPLEX_RX || spi->cur_comm == SPI_3WIRE_RX || | |
1249 | spi->cur_comm == SPI_FULL_DUPLEX) { | |
1250 | /* | |
1251 | * In transmit-only mode, the OVR flag is set in the SR register | |
1252 | * since the received data are never read. Therefore set OVR | |
1253 | * interrupt only when rx buffer is available. | |
1254 | */ | |
1255 | stm32_spi_set_bits(spi, STM32F4_SPI_CR2, STM32F4_SPI_CR2_ERRIE); | |
1256 | } | |
1257 | ||
1258 | stm32_spi_enable(spi); | |
1259 | } | |
1260 | ||
f8bb12f2 | 1261 | /** |
55166853 CG |
1262 | * stm32h7_spi_transfer_one_dma_start - Set SPI driver registers to start |
1263 | * transfer using DMA | |
1c52be8b | 1264 | * @spi: pointer to the spi controller data structure |
f8bb12f2 | 1265 | */ |
55166853 | 1266 | static void stm32h7_spi_transfer_one_dma_start(struct stm32_spi *spi) |
f8bb12f2 CG |
1267 | { |
1268 | /* Enable the interrupts relative to the end of transfer */ | |
1269 | stm32_spi_set_bits(spi, STM32H7_SPI_IER, STM32H7_SPI_IER_EOTIE | | |
1270 | STM32H7_SPI_IER_TXTFIE | | |
1271 | STM32H7_SPI_IER_OVRIE | | |
1272 | STM32H7_SPI_IER_MODFIE); | |
1273 | ||
1274 | stm32_spi_enable(spi); | |
1275 | ||
1276 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_CSTART); | |
1277 | } | |
1278 | ||
dcbe0d84 AD |
1279 | /** |
1280 | * stm32_spi_transfer_one_dma - transfer a single spi_transfer using DMA | |
1c52be8b AV |
1281 | * @spi: pointer to the spi controller data structure |
1282 | * @xfer: pointer to the spi_transfer structure | |
dcbe0d84 AD |
1283 | * |
1284 | * It must returns 0 if the transfer is finished or 1 if the transfer is still | |
1285 | * in progress. | |
1286 | */ | |
1287 | static int stm32_spi_transfer_one_dma(struct stm32_spi *spi, | |
1288 | struct spi_transfer *xfer) | |
1289 | { | |
1290 | struct dma_slave_config tx_dma_conf, rx_dma_conf; | |
1291 | struct dma_async_tx_descriptor *tx_dma_desc, *rx_dma_desc; | |
1292 | unsigned long flags; | |
dcbe0d84 AD |
1293 | |
1294 | spin_lock_irqsave(&spi->lock, flags); | |
1295 | ||
1296 | rx_dma_desc = NULL; | |
2cbee7f8 | 1297 | if (spi->rx_buf && spi->dma_rx) { |
dcbe0d84 AD |
1298 | stm32_spi_dma_config(spi, &rx_dma_conf, DMA_DEV_TO_MEM); |
1299 | dmaengine_slave_config(spi->dma_rx, &rx_dma_conf); | |
1300 | ||
1301 | /* Enable Rx DMA request */ | |
55166853 CG |
1302 | stm32_spi_set_bits(spi, spi->cfg->regs->dma_rx_en.reg, |
1303 | spi->cfg->regs->dma_rx_en.mask); | |
dcbe0d84 AD |
1304 | |
1305 | rx_dma_desc = dmaengine_prep_slave_sg( | |
1306 | spi->dma_rx, xfer->rx_sg.sgl, | |
1307 | xfer->rx_sg.nents, | |
1308 | rx_dma_conf.direction, | |
1309 | DMA_PREP_INTERRUPT); | |
dcbe0d84 AD |
1310 | } |
1311 | ||
1312 | tx_dma_desc = NULL; | |
2cbee7f8 | 1313 | if (spi->tx_buf && spi->dma_tx) { |
dcbe0d84 AD |
1314 | stm32_spi_dma_config(spi, &tx_dma_conf, DMA_MEM_TO_DEV); |
1315 | dmaengine_slave_config(spi->dma_tx, &tx_dma_conf); | |
1316 | ||
1317 | tx_dma_desc = dmaengine_prep_slave_sg( | |
1318 | spi->dma_tx, xfer->tx_sg.sgl, | |
1319 | xfer->tx_sg.nents, | |
1320 | tx_dma_conf.direction, | |
1321 | DMA_PREP_INTERRUPT); | |
dcbe0d84 AD |
1322 | } |
1323 | ||
2cbee7f8 CG |
1324 | if ((spi->tx_buf && spi->dma_tx && !tx_dma_desc) || |
1325 | (spi->rx_buf && spi->dma_rx && !rx_dma_desc)) | |
1326 | goto dma_desc_error; | |
1327 | ||
1328 | if (spi->cur_comm == SPI_FULL_DUPLEX && (!tx_dma_desc || !rx_dma_desc)) | |
dcbe0d84 AD |
1329 | goto dma_desc_error; |
1330 | ||
1331 | if (rx_dma_desc) { | |
55166853 | 1332 | rx_dma_desc->callback = spi->cfg->dma_rx_cb; |
7b821a64 AD |
1333 | rx_dma_desc->callback_param = spi; |
1334 | ||
dcbe0d84 AD |
1335 | if (dma_submit_error(dmaengine_submit(rx_dma_desc))) { |
1336 | dev_err(spi->dev, "Rx DMA submit failed\n"); | |
1337 | goto dma_desc_error; | |
1338 | } | |
1339 | /* Enable Rx DMA channel */ | |
1340 | dma_async_issue_pending(spi->dma_rx); | |
1341 | } | |
1342 | ||
1343 | if (tx_dma_desc) { | |
9d5fce16 CG |
1344 | if (spi->cur_comm == SPI_SIMPLEX_TX || |
1345 | spi->cur_comm == SPI_3WIRE_TX) { | |
55166853 | 1346 | tx_dma_desc->callback = spi->cfg->dma_tx_cb; |
7b821a64 AD |
1347 | tx_dma_desc->callback_param = spi; |
1348 | } | |
1349 | ||
dcbe0d84 AD |
1350 | if (dma_submit_error(dmaengine_submit(tx_dma_desc))) { |
1351 | dev_err(spi->dev, "Tx DMA submit failed\n"); | |
1352 | goto dma_submit_error; | |
1353 | } | |
1354 | /* Enable Tx DMA channel */ | |
1355 | dma_async_issue_pending(spi->dma_tx); | |
1356 | ||
1357 | /* Enable Tx DMA request */ | |
55166853 CG |
1358 | stm32_spi_set_bits(spi, spi->cfg->regs->dma_tx_en.reg, |
1359 | spi->cfg->regs->dma_tx_en.mask); | |
dcbe0d84 AD |
1360 | } |
1361 | ||
55166853 | 1362 | spi->cfg->transfer_one_dma_start(spi); |
dcbe0d84 AD |
1363 | |
1364 | spin_unlock_irqrestore(&spi->lock, flags); | |
1365 | ||
1366 | return 1; | |
1367 | ||
1368 | dma_submit_error: | |
2cbee7f8 | 1369 | if (spi->dma_rx) |
dcbe0d84 AD |
1370 | dmaengine_terminate_all(spi->dma_rx); |
1371 | ||
1372 | dma_desc_error: | |
55166853 CG |
1373 | stm32_spi_clr_bits(spi, spi->cfg->regs->dma_rx_en.reg, |
1374 | spi->cfg->regs->dma_rx_en.mask); | |
dcbe0d84 AD |
1375 | |
1376 | spin_unlock_irqrestore(&spi->lock, flags); | |
1377 | ||
1378 | dev_info(spi->dev, "DMA issue: fall back to irq transfer\n"); | |
1379 | ||
2cbee7f8 | 1380 | spi->cur_usedma = false; |
55166853 | 1381 | return spi->cfg->transfer_one_irq(spi); |
dcbe0d84 AD |
1382 | } |
1383 | ||
00505edf CG |
1384 | /** |
1385 | * stm32f4_spi_set_bpw - Configure bits per word | |
1386 | * @spi: pointer to the spi controller data structure | |
1387 | */ | |
1388 | static void stm32f4_spi_set_bpw(struct stm32_spi *spi) | |
1389 | { | |
1390 | if (spi->cur_bpw == 16) | |
1391 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); | |
1392 | else | |
1393 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_DFF); | |
1394 | } | |
1395 | ||
dcbe0d84 | 1396 | /** |
55166853 | 1397 | * stm32h7_spi_set_bpw - configure bits per word |
9d5fce16 | 1398 | * @spi: pointer to the spi controller data structure |
dcbe0d84 | 1399 | */ |
55166853 | 1400 | static void stm32h7_spi_set_bpw(struct stm32_spi *spi) |
dcbe0d84 | 1401 | { |
9d5fce16 CG |
1402 | u32 bpw, fthlv; |
1403 | u32 cfg1_clrb = 0, cfg1_setb = 0; | |
dcbe0d84 | 1404 | |
9d5fce16 | 1405 | bpw = spi->cur_bpw - 1; |
dcbe0d84 | 1406 | |
9d5fce16 CG |
1407 | cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE; |
1408 | cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) & | |
1409 | STM32H7_SPI_CFG1_DSIZE; | |
dcbe0d84 | 1410 | |
3373e900 | 1411 | spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen); |
9d5fce16 | 1412 | fthlv = spi->cur_fthlv - 1; |
dcbe0d84 | 1413 | |
9d5fce16 CG |
1414 | cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV; |
1415 | cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) & | |
1416 | STM32H7_SPI_CFG1_FTHLV; | |
dcbe0d84 | 1417 | |
9d5fce16 CG |
1418 | writel_relaxed( |
1419 | (readl_relaxed(spi->base + STM32H7_SPI_CFG1) & | |
1420 | ~cfg1_clrb) | cfg1_setb, | |
1421 | spi->base + STM32H7_SPI_CFG1); | |
1422 | } | |
dcbe0d84 | 1423 | |
9d5fce16 CG |
1424 | /** |
1425 | * stm32_spi_set_mbr - Configure baud rate divisor in master mode | |
1426 | * @spi: pointer to the spi controller data structure | |
1427 | * @mbrdiv: baud rate divisor value | |
1428 | */ | |
1429 | static void stm32_spi_set_mbr(struct stm32_spi *spi, u32 mbrdiv) | |
1430 | { | |
55166853 | 1431 | u32 clrb = 0, setb = 0; |
dcbe0d84 | 1432 | |
55166853 CG |
1433 | clrb |= spi->cfg->regs->br.mask; |
1434 | setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) & | |
1435 | spi->cfg->regs->br.mask; | |
dcbe0d84 | 1436 | |
55166853 CG |
1437 | writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) & |
1438 | ~clrb) | setb, | |
1439 | spi->base + spi->cfg->regs->br.reg); | |
9d5fce16 | 1440 | } |
dcbe0d84 | 1441 | |
9d5fce16 CG |
1442 | /** |
1443 | * stm32_spi_communication_type - return transfer communication type | |
1444 | * @spi_dev: pointer to the spi device | |
1c52be8b | 1445 | * @transfer: pointer to spi transfer |
9d5fce16 CG |
1446 | */ |
1447 | static unsigned int stm32_spi_communication_type(struct spi_device *spi_dev, | |
1448 | struct spi_transfer *transfer) | |
1449 | { | |
1450 | unsigned int type = SPI_FULL_DUPLEX; | |
dcbe0d84 | 1451 | |
dcbe0d84 AD |
1452 | if (spi_dev->mode & SPI_3WIRE) { /* MISO/MOSI signals shared */ |
1453 | /* | |
1454 | * SPI_3WIRE and xfer->tx_buf != NULL and xfer->rx_buf != NULL | |
9d5fce16 | 1455 | * is forbidden and unvalidated by SPI subsystem so depending |
dcbe0d84 AD |
1456 | * on the valid buffer, we can determine the direction of the |
1457 | * transfer. | |
1458 | */ | |
dcbe0d84 | 1459 | if (!transfer->tx_buf) |
9d5fce16 CG |
1460 | type = SPI_3WIRE_RX; |
1461 | else | |
1462 | type = SPI_3WIRE_TX; | |
dcbe0d84 AD |
1463 | } else { |
1464 | if (!transfer->tx_buf) | |
9d5fce16 | 1465 | type = SPI_SIMPLEX_RX; |
dcbe0d84 | 1466 | else if (!transfer->rx_buf) |
9d5fce16 | 1467 | type = SPI_SIMPLEX_TX; |
dcbe0d84 | 1468 | } |
dcbe0d84 | 1469 | |
9d5fce16 CG |
1470 | return type; |
1471 | } | |
1472 | ||
00505edf CG |
1473 | /** |
1474 | * stm32f4_spi_set_mode - configure communication mode | |
1475 | * @spi: pointer to the spi controller data structure | |
1476 | * @comm_type: type of communication to configure | |
1477 | */ | |
1478 | static int stm32f4_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) | |
1479 | { | |
1480 | if (comm_type == SPI_3WIRE_TX || comm_type == SPI_SIMPLEX_TX) { | |
1481 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, | |
1482 | STM32F4_SPI_CR1_BIDIMODE | | |
1483 | STM32F4_SPI_CR1_BIDIOE); | |
61367d0b | 1484 | } else if (comm_type == SPI_FULL_DUPLEX || |
1485 | comm_type == SPI_SIMPLEX_RX) { | |
00505edf CG |
1486 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, |
1487 | STM32F4_SPI_CR1_BIDIMODE | | |
1488 | STM32F4_SPI_CR1_BIDIOE); | |
61367d0b | 1489 | } else if (comm_type == SPI_3WIRE_RX) { |
1490 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, | |
1491 | STM32F4_SPI_CR1_BIDIMODE); | |
1492 | stm32_spi_clr_bits(spi, STM32F4_SPI_CR1, | |
1493 | STM32F4_SPI_CR1_BIDIOE); | |
00505edf CG |
1494 | } else { |
1495 | return -EINVAL; | |
1496 | } | |
1497 | ||
1498 | return 0; | |
1499 | } | |
1500 | ||
9d5fce16 | 1501 | /** |
55166853 | 1502 | * stm32h7_spi_set_mode - configure communication mode |
9d5fce16 CG |
1503 | * @spi: pointer to the spi controller data structure |
1504 | * @comm_type: type of communication to configure | |
1505 | */ | |
55166853 | 1506 | static int stm32h7_spi_set_mode(struct stm32_spi *spi, unsigned int comm_type) |
9d5fce16 CG |
1507 | { |
1508 | u32 mode; | |
1509 | u32 cfg2_clrb = 0, cfg2_setb = 0; | |
1510 | ||
1511 | if (comm_type == SPI_3WIRE_RX) { | |
1512 | mode = STM32H7_SPI_HALF_DUPLEX; | |
1513 | stm32_spi_clr_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); | |
1514 | } else if (comm_type == SPI_3WIRE_TX) { | |
1515 | mode = STM32H7_SPI_HALF_DUPLEX; | |
1516 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_HDDIR); | |
1517 | } else if (comm_type == SPI_SIMPLEX_RX) { | |
1518 | mode = STM32H7_SPI_SIMPLEX_RX; | |
1519 | } else if (comm_type == SPI_SIMPLEX_TX) { | |
1520 | mode = STM32H7_SPI_SIMPLEX_TX; | |
1521 | } else { | |
1522 | mode = STM32H7_SPI_FULL_DUPLEX; | |
dcbe0d84 AD |
1523 | } |
1524 | ||
9d5fce16 CG |
1525 | cfg2_clrb |= STM32H7_SPI_CFG2_COMM; |
1526 | cfg2_setb |= (mode << STM32H7_SPI_CFG2_COMM_SHIFT) & | |
1527 | STM32H7_SPI_CFG2_COMM; | |
1528 | ||
1529 | writel_relaxed( | |
1530 | (readl_relaxed(spi->base + STM32H7_SPI_CFG2) & | |
1531 | ~cfg2_clrb) | cfg2_setb, | |
1532 | spi->base + STM32H7_SPI_CFG2); | |
1533 | ||
1534 | return 0; | |
1535 | } | |
1536 | ||
1537 | /** | |
55166853 CG |
1538 | * stm32h7_spi_data_idleness - configure minimum time delay inserted between two |
1539 | * consecutive data frames in master mode | |
9d5fce16 CG |
1540 | * @spi: pointer to the spi controller data structure |
1541 | * @len: transfer len | |
1542 | */ | |
55166853 | 1543 | static void stm32h7_spi_data_idleness(struct stm32_spi *spi, u32 len) |
9d5fce16 CG |
1544 | { |
1545 | u32 cfg2_clrb = 0, cfg2_setb = 0; | |
1546 | ||
86026630 | 1547 | cfg2_clrb |= STM32H7_SPI_CFG2_MIDI; |
9d5fce16 | 1548 | if ((len > 1) && (spi->cur_midi > 0)) { |
dcbe0d84 AD |
1549 | u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed); |
1550 | u32 midi = min((u32)DIV_ROUND_UP(spi->cur_midi, sck_period_ns), | |
86026630 CG |
1551 | (u32)STM32H7_SPI_CFG2_MIDI >> |
1552 | STM32H7_SPI_CFG2_MIDI_SHIFT); | |
dcbe0d84 AD |
1553 | |
1554 | dev_dbg(spi->dev, "period=%dns, midi=%d(=%dns)\n", | |
1555 | sck_period_ns, midi, midi * sck_period_ns); | |
86026630 CG |
1556 | cfg2_setb |= (midi << STM32H7_SPI_CFG2_MIDI_SHIFT) & |
1557 | STM32H7_SPI_CFG2_MIDI; | |
dcbe0d84 AD |
1558 | } |
1559 | ||
9d5fce16 CG |
1560 | writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CFG2) & |
1561 | ~cfg2_clrb) | cfg2_setb, | |
1562 | spi->base + STM32H7_SPI_CFG2); | |
1563 | } | |
1564 | ||
1565 | /** | |
55166853 | 1566 | * stm32h7_spi_number_of_data - configure number of data at current transfer |
9d5fce16 | 1567 | * @spi: pointer to the spi controller data structure |
1c52be8b | 1568 | * @nb_words: transfer length (in words) |
9d5fce16 | 1569 | */ |
55166853 | 1570 | static int stm32h7_spi_number_of_data(struct stm32_spi *spi, u32 nb_words) |
9d5fce16 CG |
1571 | { |
1572 | u32 cr2_clrb = 0, cr2_setb = 0; | |
1573 | ||
1574 | if (nb_words <= (STM32H7_SPI_CR2_TSIZE >> | |
1575 | STM32H7_SPI_CR2_TSIZE_SHIFT)) { | |
1576 | cr2_clrb |= STM32H7_SPI_CR2_TSIZE; | |
1577 | cr2_setb = nb_words << STM32H7_SPI_CR2_TSIZE_SHIFT; | |
1578 | writel_relaxed((readl_relaxed(spi->base + STM32H7_SPI_CR2) & | |
1579 | ~cr2_clrb) | cr2_setb, | |
1580 | spi->base + STM32H7_SPI_CR2); | |
1581 | } else { | |
1582 | return -EMSGSIZE; | |
1583 | } | |
1584 | ||
1585 | return 0; | |
1586 | } | |
1587 | ||
1588 | /** | |
1589 | * stm32_spi_transfer_one_setup - common setup to transfer a single | |
1590 | * spi_transfer either using DMA or | |
1591 | * interrupts. | |
1c52be8b AV |
1592 | * @spi: pointer to the spi controller data structure |
1593 | * @spi_dev: pointer to the spi device | |
1594 | * @transfer: pointer to spi transfer | |
9d5fce16 CG |
1595 | */ |
1596 | static int stm32_spi_transfer_one_setup(struct stm32_spi *spi, | |
1597 | struct spi_device *spi_dev, | |
1598 | struct spi_transfer *transfer) | |
1599 | { | |
1600 | unsigned long flags; | |
1601 | unsigned int comm_type; | |
1602 | int nb_words, ret = 0; | |
60ccb351 | 1603 | int mbr; |
9d5fce16 CG |
1604 | |
1605 | spin_lock_irqsave(&spi->lock, flags); | |
1606 | ||
3373e900 AD |
1607 | spi->cur_xferlen = transfer->len; |
1608 | ||
60ccb351 AV |
1609 | spi->cur_bpw = transfer->bits_per_word; |
1610 | spi->cfg->set_bpw(spi); | |
9d5fce16 | 1611 | |
60ccb351 AV |
1612 | /* Update spi->cur_speed with real clock speed */ |
1613 | mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz, | |
1614 | spi->cfg->baud_rate_div_min, | |
1615 | spi->cfg->baud_rate_div_max); | |
1616 | if (mbr < 0) { | |
1617 | ret = mbr; | |
1618 | goto out; | |
9d5fce16 CG |
1619 | } |
1620 | ||
60ccb351 AV |
1621 | transfer->speed_hz = spi->cur_speed; |
1622 | stm32_spi_set_mbr(spi, mbr); | |
9d5fce16 | 1623 | |
60ccb351 AV |
1624 | comm_type = stm32_spi_communication_type(spi_dev, transfer); |
1625 | ret = spi->cfg->set_mode(spi, comm_type); | |
1626 | if (ret < 0) | |
1627 | goto out; | |
9d5fce16 | 1628 | |
60ccb351 | 1629 | spi->cur_comm = comm_type; |
9d5fce16 | 1630 | |
55166853 CG |
1631 | if (spi->cfg->set_data_idleness) |
1632 | spi->cfg->set_data_idleness(spi, transfer->len); | |
dcbe0d84 | 1633 | |
128ebb89 AD |
1634 | if (spi->cur_bpw <= 8) |
1635 | nb_words = transfer->len; | |
1636 | else if (spi->cur_bpw <= 16) | |
1637 | nb_words = DIV_ROUND_UP(transfer->len * 8, 16); | |
1638 | else | |
1639 | nb_words = DIV_ROUND_UP(transfer->len * 8, 32); | |
dcbe0d84 | 1640 | |
55166853 CG |
1641 | if (spi->cfg->set_number_of_data) { |
1642 | ret = spi->cfg->set_number_of_data(spi, nb_words); | |
1643 | if (ret < 0) | |
1644 | goto out; | |
1645 | } | |
dcbe0d84 | 1646 | |
dcbe0d84 AD |
1647 | dev_dbg(spi->dev, "transfer communication mode set to %d\n", |
1648 | spi->cur_comm); | |
1649 | dev_dbg(spi->dev, | |
1650 | "data frame of %d-bit, data packet of %d data frames\n", | |
1651 | spi->cur_bpw, spi->cur_fthlv); | |
1652 | dev_dbg(spi->dev, "speed set to %dHz\n", spi->cur_speed); | |
1653 | dev_dbg(spi->dev, "transfer of %d bytes (%d data frames)\n", | |
1654 | spi->cur_xferlen, nb_words); | |
1655 | dev_dbg(spi->dev, "dma %s\n", | |
1656 | (spi->cur_usedma) ? "enabled" : "disabled"); | |
1657 | ||
1658 | out: | |
1659 | spin_unlock_irqrestore(&spi->lock, flags); | |
1660 | ||
1661 | return ret; | |
1662 | } | |
1663 | ||
1664 | /** | |
1665 | * stm32_spi_transfer_one - transfer a single spi_transfer | |
1c52be8b AV |
1666 | * @master: controller master interface |
1667 | * @spi_dev: pointer to the spi device | |
1668 | * @transfer: pointer to spi transfer | |
dcbe0d84 AD |
1669 | * |
1670 | * It must return 0 if the transfer is finished or 1 if the transfer is still | |
1671 | * in progress. | |
1672 | */ | |
1673 | static int stm32_spi_transfer_one(struct spi_master *master, | |
1674 | struct spi_device *spi_dev, | |
1675 | struct spi_transfer *transfer) | |
1676 | { | |
1677 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1678 | int ret; | |
1679 | ||
1680 | spi->tx_buf = transfer->tx_buf; | |
1681 | spi->rx_buf = transfer->rx_buf; | |
1682 | spi->tx_len = spi->tx_buf ? transfer->len : 0; | |
1683 | spi->rx_len = spi->rx_buf ? transfer->len : 0; | |
1684 | ||
c67ad368 | 1685 | spi->cur_usedma = (master->can_dma && |
2cbee7f8 | 1686 | master->can_dma(master, spi_dev, transfer)); |
dcbe0d84 AD |
1687 | |
1688 | ret = stm32_spi_transfer_one_setup(spi, spi_dev, transfer); | |
1689 | if (ret) { | |
1690 | dev_err(spi->dev, "SPI transfer setup failed\n"); | |
1691 | return ret; | |
1692 | } | |
1693 | ||
1694 | if (spi->cur_usedma) | |
1695 | return stm32_spi_transfer_one_dma(spi, transfer); | |
1696 | else | |
55166853 | 1697 | return spi->cfg->transfer_one_irq(spi); |
dcbe0d84 AD |
1698 | } |
1699 | ||
1700 | /** | |
1701 | * stm32_spi_unprepare_msg - relax the hardware | |
1c52be8b AV |
1702 | * @master: controller master interface |
1703 | * @msg: pointer to the spi message | |
dcbe0d84 AD |
1704 | */ |
1705 | static int stm32_spi_unprepare_msg(struct spi_master *master, | |
1706 | struct spi_message *msg) | |
1707 | { | |
1708 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1709 | ||
55166853 | 1710 | spi->cfg->disable(spi); |
dcbe0d84 AD |
1711 | |
1712 | return 0; | |
1713 | } | |
1714 | ||
00505edf CG |
1715 | /** |
1716 | * stm32f4_spi_config - Configure SPI controller as SPI master | |
1c52be8b | 1717 | * @spi: pointer to the spi controller data structure |
00505edf CG |
1718 | */ |
1719 | static int stm32f4_spi_config(struct stm32_spi *spi) | |
1720 | { | |
1721 | unsigned long flags; | |
1722 | ||
1723 | spin_lock_irqsave(&spi->lock, flags); | |
1724 | ||
1725 | /* Ensure I2SMOD bit is kept cleared */ | |
1726 | stm32_spi_clr_bits(spi, STM32F4_SPI_I2SCFGR, | |
1727 | STM32F4_SPI_I2SCFGR_I2SMOD); | |
1728 | ||
1729 | /* | |
1730 | * - SS input value high | |
1731 | * - transmitter half duplex direction | |
1732 | * - Set the master mode (default Motorola mode) | |
1733 | * - Consider 1 master/n slaves configuration and | |
1734 | * SS input value is determined by the SSI bit | |
1735 | */ | |
1736 | stm32_spi_set_bits(spi, STM32F4_SPI_CR1, STM32F4_SPI_CR1_SSI | | |
1737 | STM32F4_SPI_CR1_BIDIOE | | |
1738 | STM32F4_SPI_CR1_MSTR | | |
1739 | STM32F4_SPI_CR1_SSM); | |
1740 | ||
1741 | spin_unlock_irqrestore(&spi->lock, flags); | |
1742 | ||
1743 | return 0; | |
1744 | } | |
1745 | ||
dcbe0d84 | 1746 | /** |
55166853 | 1747 | * stm32h7_spi_config - Configure SPI controller as SPI master |
1c52be8b | 1748 | * @spi: pointer to the spi controller data structure |
dcbe0d84 | 1749 | */ |
55166853 | 1750 | static int stm32h7_spi_config(struct stm32_spi *spi) |
dcbe0d84 AD |
1751 | { |
1752 | unsigned long flags; | |
1753 | ||
1754 | spin_lock_irqsave(&spi->lock, flags); | |
1755 | ||
1756 | /* Ensure I2SMOD bit is kept cleared */ | |
86026630 CG |
1757 | stm32_spi_clr_bits(spi, STM32H7_SPI_I2SCFGR, |
1758 | STM32H7_SPI_I2SCFGR_I2SMOD); | |
dcbe0d84 AD |
1759 | |
1760 | /* | |
1761 | * - SS input value high | |
1762 | * - transmitter half duplex direction | |
1763 | * - automatic communication suspend when RX-Fifo is full | |
1764 | */ | |
86026630 CG |
1765 | stm32_spi_set_bits(spi, STM32H7_SPI_CR1, STM32H7_SPI_CR1_SSI | |
1766 | STM32H7_SPI_CR1_HDDIR | | |
1767 | STM32H7_SPI_CR1_MASRX); | |
dcbe0d84 AD |
1768 | |
1769 | /* | |
1770 | * - Set the master mode (default Motorola mode) | |
1771 | * - Consider 1 master/n slaves configuration and | |
1772 | * SS input value is determined by the SSI bit | |
1773 | * - keep control of all associated GPIOs | |
1774 | */ | |
86026630 CG |
1775 | stm32_spi_set_bits(spi, STM32H7_SPI_CFG2, STM32H7_SPI_CFG2_MASTER | |
1776 | STM32H7_SPI_CFG2_SSM | | |
1777 | STM32H7_SPI_CFG2_AFCNTR); | |
dcbe0d84 AD |
1778 | |
1779 | spin_unlock_irqrestore(&spi->lock, flags); | |
1780 | ||
1781 | return 0; | |
1782 | } | |
1783 | ||
00505edf CG |
1784 | static const struct stm32_spi_cfg stm32f4_spi_cfg = { |
1785 | .regs = &stm32f4_spi_regspec, | |
1786 | .get_bpw_mask = stm32f4_spi_get_bpw_mask, | |
1787 | .disable = stm32f4_spi_disable, | |
1788 | .config = stm32f4_spi_config, | |
1789 | .set_bpw = stm32f4_spi_set_bpw, | |
1790 | .set_mode = stm32f4_spi_set_mode, | |
1791 | .transfer_one_dma_start = stm32f4_spi_transfer_one_dma_start, | |
1792 | .dma_tx_cb = stm32f4_spi_dma_tx_cb, | |
1793 | .dma_rx_cb = stm32f4_spi_dma_rx_cb, | |
1794 | .transfer_one_irq = stm32f4_spi_transfer_one_irq, | |
1795 | .irq_handler_event = stm32f4_spi_irq_event, | |
1796 | .irq_handler_thread = stm32f4_spi_irq_thread, | |
1797 | .baud_rate_div_min = STM32F4_SPI_BR_DIV_MIN, | |
1798 | .baud_rate_div_max = STM32F4_SPI_BR_DIV_MAX, | |
1799 | .has_fifo = false, | |
1800 | }; | |
1801 | ||
55166853 CG |
1802 | static const struct stm32_spi_cfg stm32h7_spi_cfg = { |
1803 | .regs = &stm32h7_spi_regspec, | |
1804 | .get_fifo_size = stm32h7_spi_get_fifo_size, | |
1805 | .get_bpw_mask = stm32h7_spi_get_bpw_mask, | |
1806 | .disable = stm32h7_spi_disable, | |
1807 | .config = stm32h7_spi_config, | |
1808 | .set_bpw = stm32h7_spi_set_bpw, | |
1809 | .set_mode = stm32h7_spi_set_mode, | |
1810 | .set_data_idleness = stm32h7_spi_data_idleness, | |
1811 | .set_number_of_data = stm32h7_spi_number_of_data, | |
1812 | .transfer_one_dma_start = stm32h7_spi_transfer_one_dma_start, | |
1813 | .dma_rx_cb = stm32h7_spi_dma_cb, | |
1814 | .dma_tx_cb = stm32h7_spi_dma_cb, | |
1815 | .transfer_one_irq = stm32h7_spi_transfer_one_irq, | |
1816 | .irq_handler_thread = stm32h7_spi_irq_thread, | |
1817 | .baud_rate_div_min = STM32H7_SPI_MBR_DIV_MIN, | |
1818 | .baud_rate_div_max = STM32H7_SPI_MBR_DIV_MAX, | |
1819 | .has_fifo = true, | |
1820 | }; | |
1821 | ||
dcbe0d84 | 1822 | static const struct of_device_id stm32_spi_of_match[] = { |
55166853 | 1823 | { .compatible = "st,stm32h7-spi", .data = (void *)&stm32h7_spi_cfg }, |
00505edf | 1824 | { .compatible = "st,stm32f4-spi", .data = (void *)&stm32f4_spi_cfg }, |
dcbe0d84 AD |
1825 | {}, |
1826 | }; | |
1827 | MODULE_DEVICE_TABLE(of, stm32_spi_of_match); | |
1828 | ||
1829 | static int stm32_spi_probe(struct platform_device *pdev) | |
1830 | { | |
1831 | struct spi_master *master; | |
1832 | struct stm32_spi *spi; | |
1833 | struct resource *res; | |
8a6553ec | 1834 | int ret; |
dcbe0d84 AD |
1835 | |
1836 | master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi)); | |
1837 | if (!master) { | |
1838 | dev_err(&pdev->dev, "spi master allocation failed\n"); | |
1839 | return -ENOMEM; | |
1840 | } | |
1841 | platform_set_drvdata(pdev, master); | |
1842 | ||
1843 | spi = spi_master_get_devdata(master); | |
1844 | spi->dev = &pdev->dev; | |
1845 | spi->master = master; | |
1846 | spin_lock_init(&spi->lock); | |
1847 | ||
55166853 CG |
1848 | spi->cfg = (const struct stm32_spi_cfg *) |
1849 | of_match_device(pdev->dev.driver->of_match_table, | |
1850 | &pdev->dev)->data; | |
1851 | ||
dcbe0d84 AD |
1852 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1853 | spi->base = devm_ioremap_resource(&pdev->dev, res); | |
1854 | if (IS_ERR(spi->base)) { | |
1855 | ret = PTR_ERR(spi->base); | |
1856 | goto err_master_put; | |
1857 | } | |
55166853 | 1858 | |
dcbe0d84 AD |
1859 | spi->phys_addr = (dma_addr_t)res->start; |
1860 | ||
1861 | spi->irq = platform_get_irq(pdev, 0); | |
1862 | if (spi->irq <= 0) { | |
a05cec2d | 1863 | ret = dev_err_probe(&pdev->dev, spi->irq, "failed to get irq\n"); |
dcbe0d84 AD |
1864 | goto err_master_put; |
1865 | } | |
55166853 CG |
1866 | ret = devm_request_threaded_irq(&pdev->dev, spi->irq, |
1867 | spi->cfg->irq_handler_event, | |
1868 | spi->cfg->irq_handler_thread, | |
1869 | IRQF_ONESHOT, pdev->name, master); | |
dcbe0d84 AD |
1870 | if (ret) { |
1871 | dev_err(&pdev->dev, "irq%d request failed: %d\n", spi->irq, | |
1872 | ret); | |
1873 | goto err_master_put; | |
1874 | } | |
1875 | ||
d4c9134a | 1876 | spi->clk = devm_clk_get(&pdev->dev, NULL); |
dcbe0d84 AD |
1877 | if (IS_ERR(spi->clk)) { |
1878 | ret = PTR_ERR(spi->clk); | |
1879 | dev_err(&pdev->dev, "clk get failed: %d\n", ret); | |
1880 | goto err_master_put; | |
1881 | } | |
1882 | ||
1883 | ret = clk_prepare_enable(spi->clk); | |
1884 | if (ret) { | |
1885 | dev_err(&pdev->dev, "clk enable failed: %d\n", ret); | |
1886 | goto err_master_put; | |
1887 | } | |
1888 | spi->clk_rate = clk_get_rate(spi->clk); | |
1889 | if (!spi->clk_rate) { | |
1890 | dev_err(&pdev->dev, "clk rate = 0\n"); | |
1891 | ret = -EINVAL; | |
3dbb3eef | 1892 | goto err_clk_disable; |
dcbe0d84 AD |
1893 | } |
1894 | ||
d5e9a4a4 | 1895 | spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); |
dcbe0d84 AD |
1896 | if (!IS_ERR(spi->rst)) { |
1897 | reset_control_assert(spi->rst); | |
1898 | udelay(2); | |
1899 | reset_control_deassert(spi->rst); | |
1900 | } | |
1901 | ||
55166853 CG |
1902 | if (spi->cfg->has_fifo) |
1903 | spi->fifo_size = spi->cfg->get_fifo_size(spi); | |
dcbe0d84 | 1904 | |
55166853 | 1905 | ret = spi->cfg->config(spi); |
dcbe0d84 AD |
1906 | if (ret) { |
1907 | dev_err(&pdev->dev, "controller configuration failed: %d\n", | |
1908 | ret); | |
1909 | goto err_clk_disable; | |
1910 | } | |
1911 | ||
1912 | master->dev.of_node = pdev->dev.of_node; | |
1913 | master->auto_runtime_pm = true; | |
1914 | master->bus_num = pdev->id; | |
d6cea11b | 1915 | master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST | |
6962b055 | 1916 | SPI_3WIRE; |
55166853 CG |
1917 | master->bits_per_word_mask = spi->cfg->get_bpw_mask(spi); |
1918 | master->max_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_min; | |
1919 | master->min_speed_hz = spi->clk_rate / spi->cfg->baud_rate_div_max; | |
8a6553ec | 1920 | master->use_gpio_descriptors = true; |
dcbe0d84 AD |
1921 | master->prepare_message = stm32_spi_prepare_msg; |
1922 | master->transfer_one = stm32_spi_transfer_one; | |
1923 | master->unprepare_message = stm32_spi_unprepare_msg; | |
61367d0b | 1924 | master->flags = SPI_MASTER_MUST_TX; |
dcbe0d84 | 1925 | |
0a454258 PU |
1926 | spi->dma_tx = dma_request_chan(spi->dev, "tx"); |
1927 | if (IS_ERR(spi->dma_tx)) { | |
1928 | ret = PTR_ERR(spi->dma_tx); | |
1929 | spi->dma_tx = NULL; | |
1930 | if (ret == -EPROBE_DEFER) | |
1931 | goto err_clk_disable; | |
1932 | ||
dcbe0d84 | 1933 | dev_warn(&pdev->dev, "failed to request tx dma channel\n"); |
0a454258 | 1934 | } else { |
dcbe0d84 | 1935 | master->dma_tx = spi->dma_tx; |
0a454258 PU |
1936 | } |
1937 | ||
1938 | spi->dma_rx = dma_request_chan(spi->dev, "rx"); | |
1939 | if (IS_ERR(spi->dma_rx)) { | |
1940 | ret = PTR_ERR(spi->dma_rx); | |
1941 | spi->dma_rx = NULL; | |
1942 | if (ret == -EPROBE_DEFER) | |
1943 | goto err_dma_release; | |
dcbe0d84 | 1944 | |
dcbe0d84 | 1945 | dev_warn(&pdev->dev, "failed to request rx dma channel\n"); |
0a454258 | 1946 | } else { |
dcbe0d84 | 1947 | master->dma_rx = spi->dma_rx; |
0a454258 | 1948 | } |
dcbe0d84 AD |
1949 | |
1950 | if (spi->dma_tx || spi->dma_rx) | |
1951 | master->can_dma = stm32_spi_can_dma; | |
1952 | ||
038ac869 AD |
1953 | pm_runtime_set_active(&pdev->dev); |
1954 | pm_runtime_enable(&pdev->dev); | |
1955 | ||
dcbe0d84 AD |
1956 | ret = devm_spi_register_master(&pdev->dev, master); |
1957 | if (ret) { | |
1958 | dev_err(&pdev->dev, "spi master registration failed: %d\n", | |
1959 | ret); | |
0a454258 | 1960 | goto err_pm_disable; |
dcbe0d84 AD |
1961 | } |
1962 | ||
8a6553ec | 1963 | if (!master->cs_gpiods) { |
dcbe0d84 AD |
1964 | dev_err(&pdev->dev, "no CS gpios available\n"); |
1965 | ret = -EINVAL; | |
0a454258 | 1966 | goto err_pm_disable; |
dcbe0d84 AD |
1967 | } |
1968 | ||
dcbe0d84 AD |
1969 | dev_info(&pdev->dev, "driver initialized\n"); |
1970 | ||
1971 | return 0; | |
1972 | ||
0a454258 PU |
1973 | err_pm_disable: |
1974 | pm_runtime_disable(&pdev->dev); | |
dcbe0d84 AD |
1975 | err_dma_release: |
1976 | if (spi->dma_tx) | |
1977 | dma_release_channel(spi->dma_tx); | |
1978 | if (spi->dma_rx) | |
1979 | dma_release_channel(spi->dma_rx); | |
1980 | err_clk_disable: | |
1981 | clk_disable_unprepare(spi->clk); | |
1982 | err_master_put: | |
1983 | spi_master_put(master); | |
1984 | ||
1985 | return ret; | |
1986 | } | |
1987 | ||
1988 | static int stm32_spi_remove(struct platform_device *pdev) | |
1989 | { | |
1990 | struct spi_master *master = platform_get_drvdata(pdev); | |
1991 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
1992 | ||
55166853 | 1993 | spi->cfg->disable(spi); |
dcbe0d84 AD |
1994 | |
1995 | if (master->dma_tx) | |
1996 | dma_release_channel(master->dma_tx); | |
1997 | if (master->dma_rx) | |
1998 | dma_release_channel(master->dma_rx); | |
1999 | ||
2000 | clk_disable_unprepare(spi->clk); | |
2001 | ||
038ac869 AD |
2002 | pm_runtime_disable(&pdev->dev); |
2003 | ||
db96bf97 AD |
2004 | pinctrl_pm_select_sleep_state(&pdev->dev); |
2005 | ||
dcbe0d84 AD |
2006 | return 0; |
2007 | } | |
2008 | ||
038ac869 AD |
2009 | #ifdef CONFIG_PM |
2010 | static int stm32_spi_runtime_suspend(struct device *dev) | |
2011 | { | |
2012 | struct spi_master *master = dev_get_drvdata(dev); | |
2013 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
2014 | ||
2015 | clk_disable_unprepare(spi->clk); | |
2016 | ||
db96bf97 | 2017 | return pinctrl_pm_select_sleep_state(dev); |
038ac869 AD |
2018 | } |
2019 | ||
2020 | static int stm32_spi_runtime_resume(struct device *dev) | |
2021 | { | |
2022 | struct spi_master *master = dev_get_drvdata(dev); | |
2023 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
db96bf97 AD |
2024 | int ret; |
2025 | ||
2026 | ret = pinctrl_pm_select_default_state(dev); | |
2027 | if (ret) | |
2028 | return ret; | |
038ac869 AD |
2029 | |
2030 | return clk_prepare_enable(spi->clk); | |
2031 | } | |
2032 | #endif | |
2033 | ||
dcbe0d84 AD |
2034 | #ifdef CONFIG_PM_SLEEP |
2035 | static int stm32_spi_suspend(struct device *dev) | |
2036 | { | |
2037 | struct spi_master *master = dev_get_drvdata(dev); | |
dcbe0d84 AD |
2038 | int ret; |
2039 | ||
2040 | ret = spi_master_suspend(master); | |
2041 | if (ret) | |
2042 | return ret; | |
2043 | ||
038ac869 | 2044 | return pm_runtime_force_suspend(dev); |
dcbe0d84 AD |
2045 | } |
2046 | ||
2047 | static int stm32_spi_resume(struct device *dev) | |
2048 | { | |
2049 | struct spi_master *master = dev_get_drvdata(dev); | |
2050 | struct stm32_spi *spi = spi_master_get_devdata(master); | |
2051 | int ret; | |
2052 | ||
038ac869 | 2053 | ret = pm_runtime_force_resume(dev); |
dcbe0d84 AD |
2054 | if (ret) |
2055 | return ret; | |
038ac869 | 2056 | |
dcbe0d84 | 2057 | ret = spi_master_resume(master); |
db96bf97 | 2058 | if (ret) { |
dcbe0d84 | 2059 | clk_disable_unprepare(spi->clk); |
db96bf97 AD |
2060 | return ret; |
2061 | } | |
dcbe0d84 | 2062 | |
db96bf97 | 2063 | ret = pm_runtime_get_sync(dev); |
c170a5a3 | 2064 | if (ret < 0) { |
db96bf97 AD |
2065 | dev_err(dev, "Unable to power device:%d\n", ret); |
2066 | return ret; | |
2067 | } | |
2068 | ||
2069 | spi->cfg->config(spi); | |
2070 | ||
2071 | pm_runtime_mark_last_busy(dev); | |
2072 | pm_runtime_put_autosuspend(dev); | |
2073 | ||
2074 | return 0; | |
dcbe0d84 AD |
2075 | } |
2076 | #endif | |
2077 | ||
038ac869 AD |
2078 | static const struct dev_pm_ops stm32_spi_pm_ops = { |
2079 | SET_SYSTEM_SLEEP_PM_OPS(stm32_spi_suspend, stm32_spi_resume) | |
2080 | SET_RUNTIME_PM_OPS(stm32_spi_runtime_suspend, | |
2081 | stm32_spi_runtime_resume, NULL) | |
2082 | }; | |
dcbe0d84 AD |
2083 | |
2084 | static struct platform_driver stm32_spi_driver = { | |
2085 | .probe = stm32_spi_probe, | |
2086 | .remove = stm32_spi_remove, | |
2087 | .driver = { | |
2088 | .name = DRIVER_NAME, | |
2089 | .pm = &stm32_spi_pm_ops, | |
2090 | .of_match_table = stm32_spi_of_match, | |
2091 | }, | |
2092 | }; | |
2093 | ||
2094 | module_platform_driver(stm32_spi_driver); | |
2095 | ||
2096 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2097 | MODULE_DESCRIPTION("STMicroelectronics STM32 SPI Controller driver"); | |
2098 | MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); | |
2099 | MODULE_LICENSE("GPL v2"); |