[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-sun6i.c

/*
 * Copyright (C) 2012 - 2014 Allwinner Tech
 * Pan Nan <pannan@allwinnertech.com>
 *
 * Copyright (C) 2014 Maxime Ripard
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>

#include <linux/spi/spi.h>

#define SUN6I_FIFO_DEPTH		128
#define SUN8I_FIFO_DEPTH		64

#define SUN6I_GBL_CTL_REG		0x04
#define SUN6I_GBL_CTL_BUS_ENABLE		BIT(0)
#define SUN6I_GBL_CTL_MASTER			BIT(1)
#define SUN6I_GBL_CTL_TP			BIT(7)
#define SUN6I_GBL_CTL_RST			BIT(31)

#define SUN6I_TFR_CTL_REG		0x08
#define SUN6I_TFR_CTL_CPHA			BIT(0)
#define SUN6I_TFR_CTL_CPOL			BIT(1)
#define SUN6I_TFR_CTL_SPOL			BIT(2)
#define SUN6I_TFR_CTL_CS_MASK			0x30
#define SUN6I_TFR_CTL_CS(cs)			(((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
#define SUN6I_TFR_CTL_CS_MANUAL			BIT(6)
#define SUN6I_TFR_CTL_CS_LEVEL			BIT(7)
#define SUN6I_TFR_CTL_DHB			BIT(8)
#define SUN6I_TFR_CTL_FBS			BIT(12)
#define SUN6I_TFR_CTL_XCH			BIT(31)

#define SUN6I_INT_CTL_REG		0x10
#define SUN6I_INT_CTL_RF_RDY			BIT(0)
#define SUN6I_INT_CTL_TF_ERQ			BIT(4)
#define SUN6I_INT_CTL_RF_OVF			BIT(8)
#define SUN6I_INT_CTL_TC			BIT(12)

#define SUN6I_INT_STA_REG		0x14

#define SUN6I_FIFO_CTL_REG		0x18
#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK	0xff
#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS	0
#define SUN6I_FIFO_CTL_RF_RST			BIT(15)
#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK	0xff
#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS	16
#define SUN6I_FIFO_CTL_TF_RST			BIT(31)

#define SUN6I_FIFO_STA_REG		0x1c
#define SUN6I_FIFO_STA_RF_CNT_MASK		0x7f
#define SUN6I_FIFO_STA_RF_CNT_BITS		0
#define SUN6I_FIFO_STA_TF_CNT_MASK		0x7f
#define SUN6I_FIFO_STA_TF_CNT_BITS		16

#define SUN6I_CLK_CTL_REG		0x24
#define SUN6I_CLK_CTL_CDR2_MASK			0xff
#define SUN6I_CLK_CTL_CDR2(div)			(((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
#define SUN6I_CLK_CTL_CDR1_MASK			0xf
#define SUN6I_CLK_CTL_CDR1(div)			(((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
#define SUN6I_CLK_CTL_DRS			BIT(12)

#define SUN6I_MAX_XFER_SIZE		0xffffff

#define SUN6I_BURST_CNT_REG		0x30
#define SUN6I_BURST_CNT(cnt)			((cnt) & SUN6I_MAX_XFER_SIZE)

#define SUN6I_XMIT_CNT_REG		0x34
#define SUN6I_XMIT_CNT(cnt)			((cnt) & SUN6I_MAX_XFER_SIZE)

#define SUN6I_BURST_CTL_CNT_REG		0x38
#define SUN6I_BURST_CTL_CNT_STC(cnt)		((cnt) & SUN6I_MAX_XFER_SIZE)

#define SUN6I_TXDATA_REG		0x200
#define SUN6I_RXDATA_REG		0x300

struct sun6i_spi {
	struct spi_master	*master;
	void __iomem		*base_addr;
	struct clk		*hclk;
	struct clk		*mclk;
	struct reset_control	*rstc;

	struct completion	done;

	const u8		*tx_buf;
	u8			*rx_buf;
	int			len;
	unsigned long		fifo_depth;
};

static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
{
	return readl(sspi->base_addr + reg);
}

static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
{
	writel(value, sspi->base_addr + reg);
}

static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
{
	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);

	reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;

	return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
}

static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
{
	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);

	reg |= mask;
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
}

static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
{
	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);

	reg &= ~mask;
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
}

static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
{
	u32 reg, cnt;
	u8 byte;

	/* See how much data is available */
	reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
	reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
	cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;

	if (len > cnt)
		len = cnt;

	while (len--) {
		byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
		if (sspi->rx_buf)
			*sspi->rx_buf++ = byte;
	}
}

static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
{
	u32 cnt;
	u8 byte;

	/* See how much data we can fit */
	cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);

	len = min3(len, (int)cnt, sspi->len);

	while (len--) {
		byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
		writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
		sspi->len--;
	}
}

static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
{
	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
	u32 reg;

	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	reg &= ~SUN6I_TFR_CTL_CS_MASK;
	reg |= SUN6I_TFR_CTL_CS(spi->chip_select);

	if (enable)
		reg |= SUN6I_TFR_CTL_CS_LEVEL;
	else
		reg &= ~SUN6I_TFR_CTL_CS_LEVEL;

	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
}

static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
{
	return SUN6I_MAX_XFER_SIZE - 1;
}

static int sun6i_spi_transfer_one(struct spi_master *master,
				  struct spi_device *spi,
				  struct spi_transfer *tfr)
{
	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	unsigned int mclk_rate, div, timeout;
	unsigned int start, end, tx_time;
	unsigned int trig_level;
	unsigned int tx_len = 0;
	int ret = 0;
	u32 reg;

	if (tfr->len > SUN6I_MAX_XFER_SIZE)
		return -EINVAL;

	reinit_completion(&sspi->done);
	sspi->tx_buf = tfr->tx_buf;
	sspi->rx_buf = tfr->rx_buf;
	sspi->len = tfr->len;

	/* Clear pending interrupts */
	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);

	/* Reset FIFO */
	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
			SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);

	/*
	 * Setup FIFO interrupt trigger level
	 * Here we choose 3/4 of the full fifo depth, as it's the hardcoded
	 * value used in old generation of Allwinner SPI controller.
	 * (See spi-sun4i.c)
	 */
	trig_level = sspi->fifo_depth / 4 * 3;
	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
			(trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) |
			(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));

	/*
	 * Setup the transfer control register: Chip Select,
	 * polarities, etc.
	 */
	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);

	if (spi->mode & SPI_CPOL)
		reg |= SUN6I_TFR_CTL_CPOL;
	else
		reg &= ~SUN6I_TFR_CTL_CPOL;

	if (spi->mode & SPI_CPHA)
		reg |= SUN6I_TFR_CTL_CPHA;
	else
		reg &= ~SUN6I_TFR_CTL_CPHA;

	if (spi->mode & SPI_LSB_FIRST)
		reg |= SUN6I_TFR_CTL_FBS;
	else
		reg &= ~SUN6I_TFR_CTL_FBS;

	/*
	 * If it's a TX only transfer, we don't want to fill the RX
	 * FIFO with bogus data
	 */
	if (sspi->rx_buf)
		reg &= ~SUN6I_TFR_CTL_DHB;
	else
		reg |= SUN6I_TFR_CTL_DHB;

	/* We want to control the chip select manually */
	reg |= SUN6I_TFR_CTL_CS_MANUAL;

	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);

	/* Ensure that we have a parent clock fast enough */
	mclk_rate = clk_get_rate(sspi->mclk);
	if (mclk_rate < (2 * tfr->speed_hz)) {
		clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
		mclk_rate = clk_get_rate(sspi->mclk);
	}

	/*
	 * Setup clock divider.
	 *
	 * We have two choices there. Either we can use the clock
	 * divide rate 1, which is calculated thanks to this formula:
	 * SPI_CLK = MOD_CLK / (2 ^ cdr)
	 * Or we can use CDR2, which is calculated with the formula:
	 * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
	 * Wether we use the former or the latter is set through the
	 * DRS bit.
	 *
	 * First try CDR2, and if we can't reach the expected
	 * frequency, fall back to CDR1.
	 */
	div = mclk_rate / (2 * tfr->speed_hz);
	if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
		if (div > 0)
			div--;

		reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
	} else {
		div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
		reg = SUN6I_CLK_CTL_CDR1(div);
	}

	sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);

	/* Setup the transfer now... */
	if (sspi->tx_buf)
		tx_len = tfr->len;

	/* Setup the counters */
	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
			SUN6I_BURST_CTL_CNT_STC(tx_len));

	/* Fill the TX FIFO */
	sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);

	/* Enable the interrupts */
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
	sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC |
					 SUN6I_INT_CTL_RF_RDY);
	if (tx_len > sspi->fifo_depth)
		sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);

	/* Start the transfer */
	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);

	tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
	start = jiffies;
	timeout = wait_for_completion_timeout(&sspi->done,
					      msecs_to_jiffies(tx_time));
	end = jiffies;
	if (!timeout) {
		dev_warn(&master->dev,
			 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
			 dev_name(&spi->dev), tfr->len, tfr->speed_hz,
			 jiffies_to_msecs(end - start), tx_time);
		ret = -ETIMEDOUT;
		goto out;
	}

out:
	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);

	return ret;
}

static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
{
	struct sun6i_spi *sspi = dev_id;
	u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);

	/* Transfer complete */
	if (status & SUN6I_INT_CTL_TC) {
		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
		sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
		complete(&sspi->done);
		return IRQ_HANDLED;
	}

	/* Receive FIFO 3/4 full */
	if (status & SUN6I_INT_CTL_RF_RDY) {
		sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
		/* Only clear the interrupt _after_ draining the FIFO */
		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
		return IRQ_HANDLED;
	}

	/* Transmit FIFO 3/4 empty */
	if (status & SUN6I_INT_CTL_TF_ERQ) {
		sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);

		if (!sspi->len)
			/* nothing left to transmit */
			sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);

		/* Only clear the interrupt _after_ re-seeding the FIFO */
		sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);

		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static int sun6i_spi_runtime_resume(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	int ret;

	ret = clk_prepare_enable(sspi->hclk);
	if (ret) {
		dev_err(dev, "Couldn't enable AHB clock\n");
		goto out;
	}

	ret = clk_prepare_enable(sspi->mclk);
	if (ret) {
		dev_err(dev, "Couldn't enable module clock\n");
		goto err;
	}

	ret = reset_control_deassert(sspi->rstc);
	if (ret) {
		dev_err(dev, "Couldn't deassert the device from reset\n");
		goto err2;
	}

	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
			SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);

	return 0;

err2:
	clk_disable_unprepare(sspi->mclk);
err:
	clk_disable_unprepare(sspi->hclk);
out:
	return ret;
}

static int sun6i_spi_runtime_suspend(struct device *dev)
{
	struct spi_master *master = dev_get_drvdata(dev);
	struct sun6i_spi *sspi = spi_master_get_devdata(master);

	reset_control_assert(sspi->rstc);
	clk_disable_unprepare(sspi->mclk);
	clk_disable_unprepare(sspi->hclk);

	return 0;
}

static int sun6i_spi_probe(struct platform_device *pdev)
{
	struct spi_master *master;
	struct sun6i_spi *sspi;
	struct resource	*res;
	int ret = 0, irq;

	master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
	if (!master) {
		dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
		return -ENOMEM;
	}

	platform_set_drvdata(pdev, master);
	sspi = spi_master_get_devdata(master);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(sspi->base_addr)) {
		ret = PTR_ERR(sspi->base_addr);
		goto err_free_master;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq < 0) {
		dev_err(&pdev->dev, "No spi IRQ specified\n");
		ret = -ENXIO;
		goto err_free_master;
	}

	ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
			       0, "sun6i-spi", sspi);
	if (ret) {
		dev_err(&pdev->dev, "Cannot request IRQ\n");
		goto err_free_master;
	}

	sspi->master = master;
	sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);

	master->max_speed_hz = 100 * 1000 * 1000;
	master->min_speed_hz = 3 * 1000;
	master->set_cs = sun6i_spi_set_cs;
	master->transfer_one = sun6i_spi_transfer_one;
	master->num_chipselect = 4;
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
	master->bits_per_word_mask = SPI_BPW_MASK(8);
	master->dev.of_node = pdev->dev.of_node;
	master->auto_runtime_pm = true;
	master->max_transfer_size = sun6i_spi_max_transfer_size;

	sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
	if (IS_ERR(sspi->hclk)) {
		dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
		ret = PTR_ERR(sspi->hclk);
		goto err_free_master;
	}

	sspi->mclk = devm_clk_get(&pdev->dev, "mod");
	if (IS_ERR(sspi->mclk)) {
		dev_err(&pdev->dev, "Unable to acquire module clock\n");
		ret = PTR_ERR(sspi->mclk);
		goto err_free_master;
	}

	init_completion(&sspi->done);

	sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
	if (IS_ERR(sspi->rstc)) {
		dev_err(&pdev->dev, "Couldn't get reset controller\n");
		ret = PTR_ERR(sspi->rstc);
		goto err_free_master;
	}

	/*
	 * This wake-up/shutdown pattern is to be able to have the
	 * device woken up, even if runtime_pm is disabled
	 */
	ret = sun6i_spi_runtime_resume(&pdev->dev);
	if (ret) {
		dev_err(&pdev->dev, "Couldn't resume the device\n");
		goto err_free_master;
	}

	pm_runtime_set_active(&pdev->dev);
	pm_runtime_enable(&pdev->dev);
	pm_runtime_idle(&pdev->dev);

	ret = devm_spi_register_master(&pdev->dev, master);
	if (ret) {
		dev_err(&pdev->dev, "cannot register SPI master\n");
		goto err_pm_disable;
	}

	return 0;

err_pm_disable:
	pm_runtime_disable(&pdev->dev);
	sun6i_spi_runtime_suspend(&pdev->dev);
err_free_master:
	spi_master_put(master);
	return ret;
}

static int sun6i_spi_remove(struct platform_device *pdev)
{
	pm_runtime_force_suspend(&pdev->dev);

	return 0;
}

static const struct of_device_id sun6i_spi_match[] = {
	{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
	{ .compatible = "allwinner,sun8i-h3-spi",  .data = (void *)SUN8I_FIFO_DEPTH },
	{}
};
MODULE_DEVICE_TABLE(of, sun6i_spi_match);

static const struct dev_pm_ops sun6i_spi_pm_ops = {
	.runtime_resume		= sun6i_spi_runtime_resume,
	.runtime_suspend	= sun6i_spi_runtime_suspend,
};

static struct platform_driver sun6i_spi_driver = {
	.probe	= sun6i_spi_probe,
	.remove	= sun6i_spi_remove,
	.driver	= {
		.name		= "sun6i-spi",
		.of_match_table	= sun6i_spi_match,
		.pm		= &sun6i_spi_pm_ops,
	},
};
module_platform_driver(sun6i_spi_driver);

MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
3558fe90 MR	1	/*
	2	* Copyright (C) 2012 - 2014 Allwinner Tech
	3	* Pan Nan <pannan@allwinnertech.com>
	4	*
	5	* Copyright (C) 2014 Maxime Ripard
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*/
	13
	14	#include <linux/clk.h>
	15	#include <linux/delay.h>
	16	#include <linux/device.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/io.h>
	19	#include <linux/module.h>
10565dfd	20	#include <linux/of_device.h>
3558fe90 MR	21	#include <linux/platform_device.h>
	22	#include <linux/pm_runtime.h>
	23	#include <linux/reset.h>
3558fe90 MR	24
	25	#include <linux/spi/spi.h>
	26
	27	#define SUN6I_FIFO_DEPTH 128
10565dfd	28	#define SUN8I_FIFO_DEPTH 64
3558fe90 MR	29
	30	#define SUN6I_GBL_CTL_REG 0x04
	31	#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
	32	#define SUN6I_GBL_CTL_MASTER BIT(1)
	33	#define SUN6I_GBL_CTL_TP BIT(7)
	34	#define SUN6I_GBL_CTL_RST BIT(31)
	35
	36	#define SUN6I_TFR_CTL_REG 0x08
	37	#define SUN6I_TFR_CTL_CPHA BIT(0)
	38	#define SUN6I_TFR_CTL_CPOL BIT(1)
	39	#define SUN6I_TFR_CTL_SPOL BIT(2)
d31ad46f AL	40	#define SUN6I_TFR_CTL_CS_MASK 0x30
d31ad46f AL	41	#define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
3558fe90 MR	42	#define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
	43	#define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
	44	#define SUN6I_TFR_CTL_DHB BIT(8)
	45	#define SUN6I_TFR_CTL_FBS BIT(12)
	46	#define SUN6I_TFR_CTL_XCH BIT(31)
	47
	48	#define SUN6I_INT_CTL_REG 0x10
913f536c IZ	49	#define SUN6I_INT_CTL_RF_RDY BIT(0)
913f536c IZ	50	#define SUN6I_INT_CTL_TF_ERQ BIT(4)
3558fe90 MR	51	#define SUN6I_INT_CTL_RF_OVF BIT(8)
	52	#define SUN6I_INT_CTL_TC BIT(12)
	53
	54	#define SUN6I_INT_STA_REG 0x14
	55
	56	#define SUN6I_FIFO_CTL_REG 0x18
913f536c IZ	57	#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff
913f536c IZ	58	#define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0
3558fe90	59	#define SUN6I_FIFO_CTL_RF_RST BIT(15)
913f536c IZ	60	#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff
913f536c IZ	61	#define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16
3558fe90 MR	62	#define SUN6I_FIFO_CTL_TF_RST BIT(31)
	63
	64	#define SUN6I_FIFO_STA_REG 0x1c
	65	#define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
	66	#define SUN6I_FIFO_STA_RF_CNT_BITS 0
	67	#define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
	68	#define SUN6I_FIFO_STA_TF_CNT_BITS 16
	69
	70	#define SUN6I_CLK_CTL_REG 0x24
	71	#define SUN6I_CLK_CTL_CDR2_MASK 0xff
	72	#define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
	73	#define SUN6I_CLK_CTL_CDR1_MASK 0xf
	74	#define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
	75	#define SUN6I_CLK_CTL_DRS BIT(12)
	76
913f536c IZ	77	#define SUN6I_MAX_XFER_SIZE 0xffffff
913f536c IZ	78
3558fe90	79	#define SUN6I_BURST_CNT_REG 0x30
913f536c	80	#define SUN6I_BURST_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
3558fe90 MR	81
3558fe90 MR	82	#define SUN6I_XMIT_CNT_REG 0x34
913f536c	83	#define SUN6I_XMIT_CNT(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
3558fe90 MR	84
3558fe90 MR	85	#define SUN6I_BURST_CTL_CNT_REG 0x38
913f536c	86	#define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & SUN6I_MAX_XFER_SIZE)
3558fe90 MR	87
	88	#define SUN6I_TXDATA_REG 0x200
	89	#define SUN6I_RXDATA_REG 0x300
	90
	91	struct sun6i_spi {
	92	struct spi_master *master;
	93	void __iomem *base_addr;
	94	struct clk *hclk;
	95	struct clk *mclk;
	96	struct reset_control *rstc;
	97
	98	struct completion done;
	99
	100	const u8 *tx_buf;
	101	u8 *rx_buf;
	102	int len;
10565dfd	103	unsigned long fifo_depth;
3558fe90 MR	104	};
	105
	106	static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
	107	{
	108	return readl(sspi->base_addr + reg);
	109	}
	110
	111	static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
	112	{
	113	writel(value, sspi->base_addr + reg);
	114	}
	115
913f536c IZ	116	static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi)
	117	{
	118	u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
	119
	120	reg >>= SUN6I_FIFO_STA_TF_CNT_BITS;
	121
	122	return reg & SUN6I_FIFO_STA_TF_CNT_MASK;
	123	}
	124
	125	static inline void sun6i_spi_enable_interrupt(struct sun6i_spi *sspi, u32 mask)
	126	{
	127	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
	128
	129	reg \|= mask;
	130	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
	131	}
	132
	133	static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask)
	134	{
	135	u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG);
	136
	137	reg &= ~mask;
	138	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg);
	139	}
	140
3558fe90 MR	141	static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
	142	{
	143	u32 reg, cnt;
	144	u8 byte;
	145
	146	/* See how much data is available */
	147	reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
	148	reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
	149	cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
	150
	151	if (len > cnt)
	152	len = cnt;
	153
	154	while (len--) {
	155	byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
	156	if (sspi->rx_buf)
	157	*sspi->rx_buf++ = byte;
	158	}
	159	}
	160
	161	static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
	162	{
913f536c	163	u32 cnt;
3558fe90 MR	164	u8 byte;
3558fe90 MR	165
913f536c IZ	166	/* See how much data we can fit */
	167	cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
	168
	169	len = min3(len, (int)cnt, sspi->len);
3558fe90 MR	170
	171	while (len--) {
	172	byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
	173	writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
	174	sspi->len--;
	175	}
	176	}
	177
	178	static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
	179	{
	180	struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
	181	u32 reg;
	182
	183	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	184	reg &= ~SUN6I_TFR_CTL_CS_MASK;
	185	reg \|= SUN6I_TFR_CTL_CS(spi->chip_select);
	186
	187	if (enable)
	188	reg \|= SUN6I_TFR_CTL_CS_LEVEL;
	189	else
	190	reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
	191
	192	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
	193	}
	194
794912cf MS	195	static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
794912cf MS	196	{
3288d5cb	197	return SUN6I_MAX_XFER_SIZE - 1;
794912cf	198	}
3558fe90 MR	199
	200	static int sun6i_spi_transfer_one(struct spi_master *master,
	201	struct spi_device *spi,
	202	struct spi_transfer *tfr)
	203	{
	204	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	205	unsigned int mclk_rate, div, timeout;
719bd654	206	unsigned int start, end, tx_time;
913f536c	207	unsigned int trig_level;
3558fe90 MR	208	unsigned int tx_len = 0;
	209	int ret = 0;
	210	u32 reg;
	211
913f536c	212	if (tfr->len > SUN6I_MAX_XFER_SIZE)
3558fe90 MR	213	return -EINVAL;
	214
	215	reinit_completion(&sspi->done);
	216	sspi->tx_buf = tfr->tx_buf;
	217	sspi->rx_buf = tfr->rx_buf;
	218	sspi->len = tfr->len;
	219
	220	/* Clear pending interrupts */
	221	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
	222
	223	/* Reset FIFO */
	224	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
	225	SUN6I_FIFO_CTL_RF_RST \| SUN6I_FIFO_CTL_TF_RST);
	226
913f536c IZ	227	/*
	228	* Setup FIFO interrupt trigger level
	229	* Here we choose 3/4 of the full fifo depth, as it's the hardcoded
	230	* value used in old generation of Allwinner SPI controller.
	231	* (See spi-sun4i.c)
	232	*/
	233	trig_level = sspi->fifo_depth / 4 * 3;
	234	sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
	235	(trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) \|
	236	(trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS));
	237
3558fe90 MR	238	/*
	239	* Setup the transfer control register: Chip Select,
	240	* polarities, etc.
	241	*/
	242	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	243
	244	if (spi->mode & SPI_CPOL)
	245	reg \|= SUN6I_TFR_CTL_CPOL;
	246	else
	247	reg &= ~SUN6I_TFR_CTL_CPOL;
	248
	249	if (spi->mode & SPI_CPHA)
	250	reg \|= SUN6I_TFR_CTL_CPHA;
	251	else
	252	reg &= ~SUN6I_TFR_CTL_CPHA;
	253
	254	if (spi->mode & SPI_LSB_FIRST)
	255	reg \|= SUN6I_TFR_CTL_FBS;
	256	else
	257	reg &= ~SUN6I_TFR_CTL_FBS;
	258
	259	/*
	260	* If it's a TX only transfer, we don't want to fill the RX
	261	* FIFO with bogus data
	262	*/
	263	if (sspi->rx_buf)
	264	reg &= ~SUN6I_TFR_CTL_DHB;
	265	else
	266	reg \|= SUN6I_TFR_CTL_DHB;
	267
	268	/* We want to control the chip select manually */
	269	reg \|= SUN6I_TFR_CTL_CS_MANUAL;
	270
	271	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
	272
	273	/* Ensure that we have a parent clock fast enough */
	274	mclk_rate = clk_get_rate(sspi->mclk);
47284e3e MW	275	if (mclk_rate < (2 * tfr->speed_hz)) {
47284e3e MW	276	clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
3558fe90 MR	277	mclk_rate = clk_get_rate(sspi->mclk);
	278	}
	279
	280	/*
	281	* Setup clock divider.
	282	*
	283	* We have two choices there. Either we can use the clock
	284	* divide rate 1, which is calculated thanks to this formula:
	285	* SPI_CLK = MOD_CLK / (2 ^ cdr)
	286	* Or we can use CDR2, which is calculated with the formula:
	287	* SPI_CLK = MOD_CLK / (2 * (cdr + 1))
	288	* Wether we use the former or the latter is set through the
	289	* DRS bit.
	290	*
	291	* First try CDR2, and if we can't reach the expected
	292	* frequency, fall back to CDR1.
	293	*/
47284e3e	294	div = mclk_rate / (2 * tfr->speed_hz);
3558fe90 MR	295	if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
	296	if (div > 0)
	297	div--;
	298
	299	reg = SUN6I_CLK_CTL_CDR2(div) \| SUN6I_CLK_CTL_DRS;
	300	} else {
47284e3e	301	div = ilog2(mclk_rate) - ilog2(tfr->speed_hz);
3558fe90 MR	302	reg = SUN6I_CLK_CTL_CDR1(div);
	303	}
	304
	305	sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
	306
	307	/* Setup the transfer now... */
	308	if (sspi->tx_buf)
	309	tx_len = tfr->len;
	310
	311	/* Setup the counters */
	312	sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
	313	sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
	314	sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
	315	SUN6I_BURST_CTL_CNT_STC(tx_len));
	316
	317	/* Fill the TX FIFO */
10565dfd	318	sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
3558fe90 MR	319
	320	/* Enable the interrupts */
	321	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
913f536c IZ	322	sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TC \|
	323	SUN6I_INT_CTL_RF_RDY);
	324	if (tx_len > sspi->fifo_depth)
	325	sun6i_spi_enable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
3558fe90 MR	326
	327	/* Start the transfer */
	328	reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
	329	sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg \| SUN6I_TFR_CTL_XCH);
	330
719bd654 MS	331	tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
719bd654 MS	332	start = jiffies;
3558fe90	333	timeout = wait_for_completion_timeout(&sspi->done,
719bd654 MS	334	msecs_to_jiffies(tx_time));
719bd654 MS	335	end = jiffies;
3558fe90	336	if (!timeout) {
719bd654 MS	337	dev_warn(&master->dev,
	338	"%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
	339	dev_name(&spi->dev), tfr->len, tfr->speed_hz,
	340	jiffies_to_msecs(end - start), tx_time);
3558fe90 MR	341	ret = -ETIMEDOUT;
	342	goto out;
	343	}
	344
3558fe90 MR	345	out:
	346	sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
	347
	348	return ret;
	349	}
	350
	351	static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
	352	{
	353	struct sun6i_spi *sspi = dev_id;
	354	u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
	355
	356	/* Transfer complete */
	357	if (status & SUN6I_INT_CTL_TC) {
	358	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
913f536c	359	sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
3558fe90 MR	360	complete(&sspi->done);
	361	return IRQ_HANDLED;
	362	}
	363
913f536c IZ	364	/* Receive FIFO 3/4 full */
	365	if (status & SUN6I_INT_CTL_RF_RDY) {
	366	sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
	367	/* Only clear the interrupt _after_ draining the FIFO */
	368	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY);
	369	return IRQ_HANDLED;
	370	}
	371
	372	/* Transmit FIFO 3/4 empty */
	373	if (status & SUN6I_INT_CTL_TF_ERQ) {
	374	sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
	375
	376	if (!sspi->len)
	377	/* nothing left to transmit */
	378	sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ);
	379
	380	/* Only clear the interrupt _after_ re-seeding the FIFO */
	381	sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ);
	382
	383	return IRQ_HANDLED;
	384	}
	385
3558fe90 MR	386	return IRQ_NONE;
	387	}
	388
	389	static int sun6i_spi_runtime_resume(struct device *dev)
	390	{
	391	struct spi_master *master = dev_get_drvdata(dev);
	392	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	393	int ret;
	394
	395	ret = clk_prepare_enable(sspi->hclk);
	396	if (ret) {
	397	dev_err(dev, "Couldn't enable AHB clock\n");
	398	goto out;
	399	}
	400
	401	ret = clk_prepare_enable(sspi->mclk);
	402	if (ret) {
	403	dev_err(dev, "Couldn't enable module clock\n");
	404	goto err;
	405	}
	406
	407	ret = reset_control_deassert(sspi->rstc);
	408	if (ret) {
	409	dev_err(dev, "Couldn't deassert the device from reset\n");
	410	goto err2;
	411	}
	412
	413	sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
	414	SUN6I_GBL_CTL_BUS_ENABLE \| SUN6I_GBL_CTL_MASTER \| SUN6I_GBL_CTL_TP);
	415
	416	return 0;
	417
	418	err2:
	419	clk_disable_unprepare(sspi->mclk);
	420	err:
	421	clk_disable_unprepare(sspi->hclk);
	422	out:
	423	return ret;
	424	}
	425
	426	static int sun6i_spi_runtime_suspend(struct device *dev)
	427	{
	428	struct spi_master *master = dev_get_drvdata(dev);
	429	struct sun6i_spi *sspi = spi_master_get_devdata(master);
	430
	431	reset_control_assert(sspi->rstc);
	432	clk_disable_unprepare(sspi->mclk);
	433	clk_disable_unprepare(sspi->hclk);
	434
	435	return 0;
	436	}
	437
	438	static int sun6i_spi_probe(struct platform_device *pdev)
	439	{
	440	struct spi_master *master;
	441	struct sun6i_spi *sspi;
	442	struct resource *res;
	443	int ret = 0, irq;
	444
	445	master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
	446	if (!master) {
	447	dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
	448	return -ENOMEM;
	449	}
450
451	platform_set_drvdata(pdev, master);
452	sspi = spi_master_get_devdata(master);
453
454	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
455	sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
456	if (IS_ERR(sspi->base_addr)) {
457	ret = PTR_ERR(sspi->base_addr);
458	goto err_free_master;
459	}
460
461	irq = platform_get_irq(pdev, 0);
462	if (irq < 0) {
463	dev_err(&pdev->dev, "No spi IRQ specified\n");
464	ret = -ENXIO;
465	goto err_free_master;
466	}
467
468	ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
469	0, "sun6i-spi", sspi);
470	if (ret) {
471	dev_err(&pdev->dev, "Cannot request IRQ\n");
472	goto err_free_master;
473	}
474
475	sspi->master = master;
10565dfd MK	476	sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
10565dfd MK	477
0b06d8cf MS	478	master->max_speed_hz = 100 * 1000 * 1000;
0b06d8cf MS	479	master->min_speed_hz = 3 * 1000;
3558fe90 MR	480	master->set_cs = sun6i_spi_set_cs;
	481	master->transfer_one = sun6i_spi_transfer_one;
	482	master->num_chipselect = 4;
	483	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \| SPI_LSB_FIRST;
743a46b8	484	master->bits_per_word_mask = SPI_BPW_MASK(8);
3558fe90 MR	485	master->dev.of_node = pdev->dev.of_node;
3558fe90 MR	486	master->auto_runtime_pm = true;
794912cf	487	master->max_transfer_size = sun6i_spi_max_transfer_size;
3558fe90 MR	488
	489	sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
	490	if (IS_ERR(sspi->hclk)) {
	491	dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
	492	ret = PTR_ERR(sspi->hclk);
	493	goto err_free_master;
	494	}
	495
	496	sspi->mclk = devm_clk_get(&pdev->dev, "mod");
	497	if (IS_ERR(sspi->mclk)) {
	498	dev_err(&pdev->dev, "Unable to acquire module clock\n");
	499	ret = PTR_ERR(sspi->mclk);
	500	goto err_free_master;
	501	}
	502
	503	init_completion(&sspi->done);
	504
36bc7491	505	sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
3558fe90 MR	506	if (IS_ERR(sspi->rstc)) {
	507	dev_err(&pdev->dev, "Couldn't get reset controller\n");
	508	ret = PTR_ERR(sspi->rstc);
	509	goto err_free_master;
	510	}
	511
	512	/*
	513	* This wake-up/shutdown pattern is to be able to have the
	514	* device woken up, even if runtime_pm is disabled
	515	*/
	516	ret = sun6i_spi_runtime_resume(&pdev->dev);
	517	if (ret) {
	518	dev_err(&pdev->dev, "Couldn't resume the device\n");
	519	goto err_free_master;
	520	}
	521
	522	pm_runtime_set_active(&pdev->dev);
	523	pm_runtime_enable(&pdev->dev);
	524	pm_runtime_idle(&pdev->dev);
	525
	526	ret = devm_spi_register_master(&pdev->dev, master);
	527	if (ret) {
	528	dev_err(&pdev->dev, "cannot register SPI master\n");
	529	goto err_pm_disable;
	530	}
	531
	532	return 0;
	533
	534	err_pm_disable:
	535	pm_runtime_disable(&pdev->dev);
	536	sun6i_spi_runtime_suspend(&pdev->dev);
	537	err_free_master:
	538	spi_master_put(master);
	539	return ret;
	540	}
	541
	542	static int sun6i_spi_remove(struct platform_device *pdev)
	543	{
90336062	544	pm_runtime_force_suspend(&pdev->dev);
3558fe90 MR	545
	546	return 0;
	547	}
	548
	549	static const struct of_device_id sun6i_spi_match[] = {
10565dfd MK	550	{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
10565dfd MK	551	{ .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
3558fe90 MR	552	{}
	553	};
	554	MODULE_DEVICE_TABLE(of, sun6i_spi_match);
	555
	556	static const struct dev_pm_ops sun6i_spi_pm_ops = {
	557	.runtime_resume = sun6i_spi_runtime_resume,
	558	.runtime_suspend = sun6i_spi_runtime_suspend,
	559	};
	560
	561	static struct platform_driver sun6i_spi_driver = {
	562	.probe = sun6i_spi_probe,
	563	.remove = sun6i_spi_remove,
	564	.driver = {
	565	.name = "sun6i-spi",
3558fe90 MR	566	.of_match_table = sun6i_spi_match,
	567	.pm = &sun6i_spi_pm_ops,
	568	},
	569	};
	570	module_platform_driver(sun6i_spi_driver);
	571
	572	MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
	573	MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
	574	MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
	575	MODULE_LICENSE("GPL");