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dc4dc360 LD |
1 | /* |
2 | * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller. | |
3 | * | |
4 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
19 | #include <linux/clk.h> | |
20 | #include <linux/completion.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/dmaengine.h> | |
23 | #include <linux/dma-mapping.h> | |
24 | #include <linux/dmapool.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/kthread.h> | |
31 | #include <linux/module.h> | |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/pm_runtime.h> | |
34 | #include <linux/of.h> | |
35 | #include <linux/of_device.h> | |
36 | #include <linux/spi/spi.h> | |
37 | #include <linux/spi/spi-tegra.h> | |
61fd290d | 38 | #include <linux/clk/tegra.h> |
dc4dc360 LD |
39 | |
40 | #define SLINK_COMMAND 0x000 | |
41 | #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) | |
42 | #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) | |
43 | #define SLINK_BOTH_EN (1 << 10) | |
44 | #define SLINK_CS_SW (1 << 11) | |
45 | #define SLINK_CS_VALUE (1 << 12) | |
46 | #define SLINK_CS_POLARITY (1 << 13) | |
47 | #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) | |
48 | #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) | |
49 | #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) | |
50 | #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) | |
51 | #define SLINK_IDLE_SDA_MASK (3 << 16) | |
52 | #define SLINK_CS_POLARITY1 (1 << 20) | |
53 | #define SLINK_CK_SDA (1 << 21) | |
54 | #define SLINK_CS_POLARITY2 (1 << 22) | |
55 | #define SLINK_CS_POLARITY3 (1 << 23) | |
56 | #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) | |
57 | #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) | |
58 | #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) | |
59 | #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) | |
60 | #define SLINK_IDLE_SCLK_MASK (3 << 24) | |
61 | #define SLINK_M_S (1 << 28) | |
62 | #define SLINK_WAIT (1 << 29) | |
63 | #define SLINK_GO (1 << 30) | |
64 | #define SLINK_ENB (1 << 31) | |
65 | ||
66 | #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA) | |
67 | ||
68 | #define SLINK_COMMAND2 0x004 | |
69 | #define SLINK_LSBFE (1 << 0) | |
70 | #define SLINK_SSOE (1 << 1) | |
71 | #define SLINK_SPIE (1 << 4) | |
72 | #define SLINK_BIDIROE (1 << 6) | |
73 | #define SLINK_MODFEN (1 << 7) | |
74 | #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) | |
75 | #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) | |
76 | #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) | |
77 | #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) | |
78 | #define SLINK_FIFO_REFILLS_0 (0 << 22) | |
79 | #define SLINK_FIFO_REFILLS_1 (1 << 22) | |
80 | #define SLINK_FIFO_REFILLS_2 (2 << 22) | |
81 | #define SLINK_FIFO_REFILLS_3 (3 << 22) | |
82 | #define SLINK_FIFO_REFILLS_MASK (3 << 22) | |
83 | #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) | |
84 | #define SLINK_SPC0 (1 << 29) | |
85 | #define SLINK_TXEN (1 << 30) | |
86 | #define SLINK_RXEN (1 << 31) | |
87 | ||
88 | #define SLINK_STATUS 0x008 | |
89 | #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) | |
90 | #define SLINK_WORD(val) (((val) >> 5) & 0x1f) | |
91 | #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) | |
92 | #define SLINK_MODF (1 << 16) | |
93 | #define SLINK_RX_UNF (1 << 18) | |
94 | #define SLINK_TX_OVF (1 << 19) | |
95 | #define SLINK_TX_FULL (1 << 20) | |
96 | #define SLINK_TX_EMPTY (1 << 21) | |
97 | #define SLINK_RX_FULL (1 << 22) | |
98 | #define SLINK_RX_EMPTY (1 << 23) | |
99 | #define SLINK_TX_UNF (1 << 24) | |
100 | #define SLINK_RX_OVF (1 << 25) | |
101 | #define SLINK_TX_FLUSH (1 << 26) | |
102 | #define SLINK_RX_FLUSH (1 << 27) | |
103 | #define SLINK_SCLK (1 << 28) | |
104 | #define SLINK_ERR (1 << 29) | |
105 | #define SLINK_RDY (1 << 30) | |
106 | #define SLINK_BSY (1 << 31) | |
107 | #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \ | |
108 | SLINK_TX_UNF | SLINK_RX_OVF) | |
109 | ||
110 | #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY) | |
111 | ||
112 | #define SLINK_MAS_DATA 0x010 | |
113 | #define SLINK_SLAVE_DATA 0x014 | |
114 | ||
115 | #define SLINK_DMA_CTL 0x018 | |
116 | #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) | |
117 | #define SLINK_TX_TRIG_1 (0 << 16) | |
118 | #define SLINK_TX_TRIG_4 (1 << 16) | |
119 | #define SLINK_TX_TRIG_8 (2 << 16) | |
120 | #define SLINK_TX_TRIG_16 (3 << 16) | |
121 | #define SLINK_TX_TRIG_MASK (3 << 16) | |
122 | #define SLINK_RX_TRIG_1 (0 << 18) | |
123 | #define SLINK_RX_TRIG_4 (1 << 18) | |
124 | #define SLINK_RX_TRIG_8 (2 << 18) | |
125 | #define SLINK_RX_TRIG_16 (3 << 18) | |
126 | #define SLINK_RX_TRIG_MASK (3 << 18) | |
127 | #define SLINK_PACKED (1 << 20) | |
128 | #define SLINK_PACK_SIZE_4 (0 << 21) | |
129 | #define SLINK_PACK_SIZE_8 (1 << 21) | |
130 | #define SLINK_PACK_SIZE_16 (2 << 21) | |
131 | #define SLINK_PACK_SIZE_32 (3 << 21) | |
132 | #define SLINK_PACK_SIZE_MASK (3 << 21) | |
133 | #define SLINK_IE_TXC (1 << 26) | |
134 | #define SLINK_IE_RXC (1 << 27) | |
135 | #define SLINK_DMA_EN (1 << 31) | |
136 | ||
137 | #define SLINK_STATUS2 0x01c | |
138 | #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) | |
139 | #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) | |
140 | #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) | |
141 | ||
142 | #define SLINK_TX_FIFO 0x100 | |
143 | #define SLINK_RX_FIFO 0x180 | |
144 | ||
145 | #define DATA_DIR_TX (1 << 0) | |
146 | #define DATA_DIR_RX (1 << 1) | |
147 | ||
148 | #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000)) | |
149 | ||
150 | #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) | |
151 | #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20) | |
152 | #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0) | |
153 | ||
154 | #define SLINK_STATUS2_RESET \ | |
155 | (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16) | |
156 | ||
157 | #define MAX_CHIP_SELECT 4 | |
158 | #define SLINK_FIFO_DEPTH 32 | |
159 | ||
160 | struct tegra_slink_chip_data { | |
161 | bool cs_hold_time; | |
162 | }; | |
163 | ||
164 | struct tegra_slink_data { | |
165 | struct device *dev; | |
166 | struct spi_master *master; | |
167 | const struct tegra_slink_chip_data *chip_data; | |
168 | spinlock_t lock; | |
169 | ||
170 | struct clk *clk; | |
171 | void __iomem *base; | |
172 | phys_addr_t phys; | |
173 | unsigned irq; | |
174 | int dma_req_sel; | |
175 | u32 spi_max_frequency; | |
176 | u32 cur_speed; | |
177 | ||
178 | struct spi_device *cur_spi; | |
179 | unsigned cur_pos; | |
180 | unsigned cur_len; | |
181 | unsigned words_per_32bit; | |
182 | unsigned bytes_per_word; | |
183 | unsigned curr_dma_words; | |
184 | unsigned cur_direction; | |
185 | ||
186 | unsigned cur_rx_pos; | |
187 | unsigned cur_tx_pos; | |
188 | ||
189 | unsigned dma_buf_size; | |
190 | unsigned max_buf_size; | |
191 | bool is_curr_dma_xfer; | |
192 | bool is_hw_based_cs; | |
193 | ||
194 | struct completion rx_dma_complete; | |
195 | struct completion tx_dma_complete; | |
196 | ||
197 | u32 tx_status; | |
198 | u32 rx_status; | |
199 | u32 status_reg; | |
200 | bool is_packed; | |
201 | unsigned long packed_size; | |
202 | ||
203 | u32 command_reg; | |
204 | u32 command2_reg; | |
205 | u32 dma_control_reg; | |
206 | u32 def_command_reg; | |
207 | u32 def_command2_reg; | |
208 | ||
209 | struct completion xfer_completion; | |
210 | struct spi_transfer *curr_xfer; | |
211 | struct dma_chan *rx_dma_chan; | |
212 | u32 *rx_dma_buf; | |
213 | dma_addr_t rx_dma_phys; | |
214 | struct dma_async_tx_descriptor *rx_dma_desc; | |
215 | ||
216 | struct dma_chan *tx_dma_chan; | |
217 | u32 *tx_dma_buf; | |
218 | dma_addr_t tx_dma_phys; | |
219 | struct dma_async_tx_descriptor *tx_dma_desc; | |
220 | }; | |
221 | ||
222 | static int tegra_slink_runtime_suspend(struct device *dev); | |
223 | static int tegra_slink_runtime_resume(struct device *dev); | |
224 | ||
225 | static inline unsigned long tegra_slink_readl(struct tegra_slink_data *tspi, | |
226 | unsigned long reg) | |
227 | { | |
228 | return readl(tspi->base + reg); | |
229 | } | |
230 | ||
231 | static inline void tegra_slink_writel(struct tegra_slink_data *tspi, | |
232 | unsigned long val, unsigned long reg) | |
233 | { | |
234 | writel(val, tspi->base + reg); | |
235 | ||
236 | /* Read back register to make sure that register writes completed */ | |
237 | if (reg != SLINK_TX_FIFO) | |
238 | readl(tspi->base + SLINK_MAS_DATA); | |
239 | } | |
240 | ||
241 | static void tegra_slink_clear_status(struct tegra_slink_data *tspi) | |
242 | { | |
243 | unsigned long val; | |
244 | unsigned long val_write = 0; | |
245 | ||
246 | val = tegra_slink_readl(tspi, SLINK_STATUS); | |
247 | ||
248 | /* Write 1 to clear status register */ | |
249 | val_write = SLINK_RDY | SLINK_FIFO_ERROR; | |
250 | tegra_slink_writel(tspi, val_write, SLINK_STATUS); | |
251 | } | |
252 | ||
253 | static unsigned long tegra_slink_get_packed_size(struct tegra_slink_data *tspi, | |
254 | struct spi_transfer *t) | |
255 | { | |
256 | unsigned long val; | |
257 | ||
258 | switch (tspi->bytes_per_word) { | |
259 | case 0: | |
260 | val = SLINK_PACK_SIZE_4; | |
261 | break; | |
262 | case 1: | |
263 | val = SLINK_PACK_SIZE_8; | |
264 | break; | |
265 | case 2: | |
266 | val = SLINK_PACK_SIZE_16; | |
267 | break; | |
268 | case 4: | |
269 | val = SLINK_PACK_SIZE_32; | |
270 | break; | |
271 | default: | |
272 | val = 0; | |
273 | } | |
274 | return val; | |
275 | } | |
276 | ||
277 | static unsigned tegra_slink_calculate_curr_xfer_param( | |
278 | struct spi_device *spi, struct tegra_slink_data *tspi, | |
279 | struct spi_transfer *t) | |
280 | { | |
281 | unsigned remain_len = t->len - tspi->cur_pos; | |
282 | unsigned max_word; | |
283 | unsigned bits_per_word ; | |
284 | unsigned max_len; | |
285 | unsigned total_fifo_words; | |
286 | ||
766ed704 | 287 | bits_per_word = t->bits_per_word; |
dc4dc360 LD |
288 | tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1; |
289 | ||
290 | if (bits_per_word == 8 || bits_per_word == 16) { | |
291 | tspi->is_packed = 1; | |
292 | tspi->words_per_32bit = 32/bits_per_word; | |
293 | } else { | |
294 | tspi->is_packed = 0; | |
295 | tspi->words_per_32bit = 1; | |
296 | } | |
297 | tspi->packed_size = tegra_slink_get_packed_size(tspi, t); | |
298 | ||
299 | if (tspi->is_packed) { | |
300 | max_len = min(remain_len, tspi->max_buf_size); | |
301 | tspi->curr_dma_words = max_len/tspi->bytes_per_word; | |
302 | total_fifo_words = max_len/4; | |
303 | } else { | |
304 | max_word = (remain_len - 1) / tspi->bytes_per_word + 1; | |
305 | max_word = min(max_word, tspi->max_buf_size/4); | |
306 | tspi->curr_dma_words = max_word; | |
307 | total_fifo_words = max_word; | |
308 | } | |
309 | return total_fifo_words; | |
310 | } | |
311 | ||
312 | static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf( | |
313 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
314 | { | |
315 | unsigned nbytes; | |
316 | unsigned tx_empty_count; | |
317 | unsigned long fifo_status; | |
318 | unsigned max_n_32bit; | |
319 | unsigned i, count; | |
320 | unsigned long x; | |
321 | unsigned int written_words; | |
322 | unsigned fifo_words_left; | |
323 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; | |
324 | ||
325 | fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); | |
326 | tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status); | |
327 | ||
328 | if (tspi->is_packed) { | |
329 | fifo_words_left = tx_empty_count * tspi->words_per_32bit; | |
330 | written_words = min(fifo_words_left, tspi->curr_dma_words); | |
331 | nbytes = written_words * tspi->bytes_per_word; | |
332 | max_n_32bit = DIV_ROUND_UP(nbytes, 4); | |
333 | for (count = 0; count < max_n_32bit; count++) { | |
334 | x = 0; | |
335 | for (i = 0; (i < 4) && nbytes; i++, nbytes--) | |
336 | x |= (*tx_buf++) << (i*8); | |
337 | tegra_slink_writel(tspi, x, SLINK_TX_FIFO); | |
338 | } | |
339 | } else { | |
340 | max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); | |
341 | written_words = max_n_32bit; | |
342 | nbytes = written_words * tspi->bytes_per_word; | |
343 | for (count = 0; count < max_n_32bit; count++) { | |
344 | x = 0; | |
345 | for (i = 0; nbytes && (i < tspi->bytes_per_word); | |
346 | i++, nbytes--) | |
347 | x |= ((*tx_buf++) << i*8); | |
348 | tegra_slink_writel(tspi, x, SLINK_TX_FIFO); | |
349 | } | |
350 | } | |
351 | tspi->cur_tx_pos += written_words * tspi->bytes_per_word; | |
352 | return written_words; | |
353 | } | |
354 | ||
355 | static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( | |
356 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
357 | { | |
358 | unsigned rx_full_count; | |
359 | unsigned long fifo_status; | |
360 | unsigned i, count; | |
361 | unsigned long x; | |
362 | unsigned int read_words = 0; | |
363 | unsigned len; | |
364 | u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; | |
365 | ||
366 | fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); | |
367 | rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status); | |
368 | if (tspi->is_packed) { | |
369 | len = tspi->curr_dma_words * tspi->bytes_per_word; | |
370 | for (count = 0; count < rx_full_count; count++) { | |
371 | x = tegra_slink_readl(tspi, SLINK_RX_FIFO); | |
372 | for (i = 0; len && (i < 4); i++, len--) | |
373 | *rx_buf++ = (x >> i*8) & 0xFF; | |
374 | } | |
375 | tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | |
376 | read_words += tspi->curr_dma_words; | |
377 | } else { | |
dc4dc360 LD |
378 | for (count = 0; count < rx_full_count; count++) { |
379 | x = tegra_slink_readl(tspi, SLINK_RX_FIFO); | |
380 | for (i = 0; (i < tspi->bytes_per_word); i++) | |
381 | *rx_buf++ = (x >> (i*8)) & 0xFF; | |
382 | } | |
383 | tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; | |
384 | read_words += rx_full_count; | |
385 | } | |
386 | return read_words; | |
387 | } | |
388 | ||
389 | static void tegra_slink_copy_client_txbuf_to_spi_txbuf( | |
390 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
391 | { | |
392 | unsigned len; | |
393 | ||
394 | /* Make the dma buffer to read by cpu */ | |
395 | dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, | |
396 | tspi->dma_buf_size, DMA_TO_DEVICE); | |
397 | ||
398 | if (tspi->is_packed) { | |
399 | len = tspi->curr_dma_words * tspi->bytes_per_word; | |
400 | memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); | |
401 | } else { | |
402 | unsigned int i; | |
403 | unsigned int count; | |
404 | u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; | |
405 | unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; | |
406 | unsigned int x; | |
407 | ||
408 | for (count = 0; count < tspi->curr_dma_words; count++) { | |
409 | x = 0; | |
410 | for (i = 0; consume && (i < tspi->bytes_per_word); | |
411 | i++, consume--) | |
412 | x |= ((*tx_buf++) << i * 8); | |
413 | tspi->tx_dma_buf[count] = x; | |
414 | } | |
415 | } | |
416 | tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | |
417 | ||
418 | /* Make the dma buffer to read by dma */ | |
419 | dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, | |
420 | tspi->dma_buf_size, DMA_TO_DEVICE); | |
421 | } | |
422 | ||
423 | static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( | |
424 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
425 | { | |
426 | unsigned len; | |
427 | ||
428 | /* Make the dma buffer to read by cpu */ | |
429 | dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, | |
430 | tspi->dma_buf_size, DMA_FROM_DEVICE); | |
431 | ||
432 | if (tspi->is_packed) { | |
433 | len = tspi->curr_dma_words * tspi->bytes_per_word; | |
434 | memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); | |
435 | } else { | |
436 | unsigned int i; | |
437 | unsigned int count; | |
438 | unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; | |
439 | unsigned int x; | |
440 | unsigned int rx_mask, bits_per_word; | |
441 | ||
766ed704 | 442 | bits_per_word = t->bits_per_word; |
dc4dc360 LD |
443 | rx_mask = (1 << bits_per_word) - 1; |
444 | for (count = 0; count < tspi->curr_dma_words; count++) { | |
445 | x = tspi->rx_dma_buf[count]; | |
446 | x &= rx_mask; | |
447 | for (i = 0; (i < tspi->bytes_per_word); i++) | |
448 | *rx_buf++ = (x >> (i*8)) & 0xFF; | |
449 | } | |
450 | } | |
451 | tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; | |
452 | ||
453 | /* Make the dma buffer to read by dma */ | |
454 | dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, | |
455 | tspi->dma_buf_size, DMA_FROM_DEVICE); | |
456 | } | |
457 | ||
458 | static void tegra_slink_dma_complete(void *args) | |
459 | { | |
460 | struct completion *dma_complete = args; | |
461 | ||
462 | complete(dma_complete); | |
463 | } | |
464 | ||
465 | static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len) | |
466 | { | |
467 | INIT_COMPLETION(tspi->tx_dma_complete); | |
468 | tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, | |
469 | tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, | |
faa98f7e | 470 | DMA_PREP_INTERRUPT); |
dc4dc360 LD |
471 | if (!tspi->tx_dma_desc) { |
472 | dev_err(tspi->dev, "Not able to get desc for Tx\n"); | |
473 | return -EIO; | |
474 | } | |
475 | ||
476 | tspi->tx_dma_desc->callback = tegra_slink_dma_complete; | |
477 | tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; | |
478 | ||
479 | dmaengine_submit(tspi->tx_dma_desc); | |
480 | dma_async_issue_pending(tspi->tx_dma_chan); | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len) | |
485 | { | |
486 | INIT_COMPLETION(tspi->rx_dma_complete); | |
487 | tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, | |
488 | tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, | |
faa98f7e | 489 | DMA_PREP_INTERRUPT); |
dc4dc360 LD |
490 | if (!tspi->rx_dma_desc) { |
491 | dev_err(tspi->dev, "Not able to get desc for Rx\n"); | |
492 | return -EIO; | |
493 | } | |
494 | ||
495 | tspi->rx_dma_desc->callback = tegra_slink_dma_complete; | |
496 | tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; | |
497 | ||
498 | dmaengine_submit(tspi->rx_dma_desc); | |
499 | dma_async_issue_pending(tspi->rx_dma_chan); | |
500 | return 0; | |
501 | } | |
502 | ||
503 | static int tegra_slink_start_dma_based_transfer( | |
504 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
505 | { | |
506 | unsigned long val; | |
507 | unsigned long test_val; | |
508 | unsigned int len; | |
509 | int ret = 0; | |
510 | unsigned long status; | |
511 | ||
512 | /* Make sure that Rx and Tx fifo are empty */ | |
513 | status = tegra_slink_readl(tspi, SLINK_STATUS); | |
514 | if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { | |
515 | dev_err(tspi->dev, | |
516 | "Rx/Tx fifo are not empty status 0x%08lx\n", status); | |
517 | return -EIO; | |
518 | } | |
519 | ||
520 | val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); | |
521 | val |= tspi->packed_size; | |
522 | if (tspi->is_packed) | |
523 | len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, | |
524 | 4) * 4; | |
525 | else | |
526 | len = tspi->curr_dma_words * 4; | |
527 | ||
528 | /* Set attention level based on length of transfer */ | |
529 | if (len & 0xF) | |
530 | val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; | |
531 | else if (((len) >> 4) & 0x1) | |
532 | val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; | |
533 | else | |
534 | val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; | |
535 | ||
536 | if (tspi->cur_direction & DATA_DIR_TX) | |
537 | val |= SLINK_IE_TXC; | |
538 | ||
539 | if (tspi->cur_direction & DATA_DIR_RX) | |
540 | val |= SLINK_IE_RXC; | |
541 | ||
542 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
543 | tspi->dma_control_reg = val; | |
544 | ||
545 | if (tspi->cur_direction & DATA_DIR_TX) { | |
546 | tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t); | |
547 | wmb(); | |
548 | ret = tegra_slink_start_tx_dma(tspi, len); | |
549 | if (ret < 0) { | |
550 | dev_err(tspi->dev, | |
551 | "Starting tx dma failed, err %d\n", ret); | |
552 | return ret; | |
553 | } | |
554 | ||
555 | /* Wait for tx fifo to be fill before starting slink */ | |
556 | test_val = tegra_slink_readl(tspi, SLINK_STATUS); | |
557 | while (!(test_val & SLINK_TX_FULL)) | |
558 | test_val = tegra_slink_readl(tspi, SLINK_STATUS); | |
559 | } | |
560 | ||
561 | if (tspi->cur_direction & DATA_DIR_RX) { | |
562 | /* Make the dma buffer to read by dma */ | |
563 | dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, | |
564 | tspi->dma_buf_size, DMA_FROM_DEVICE); | |
565 | ||
566 | ret = tegra_slink_start_rx_dma(tspi, len); | |
567 | if (ret < 0) { | |
568 | dev_err(tspi->dev, | |
569 | "Starting rx dma failed, err %d\n", ret); | |
570 | if (tspi->cur_direction & DATA_DIR_TX) | |
571 | dmaengine_terminate_all(tspi->tx_dma_chan); | |
572 | return ret; | |
573 | } | |
574 | } | |
575 | tspi->is_curr_dma_xfer = true; | |
576 | if (tspi->is_packed) { | |
577 | val |= SLINK_PACKED; | |
578 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
579 | /* HW need small delay after settign Packed mode */ | |
580 | udelay(1); | |
581 | } | |
582 | tspi->dma_control_reg = val; | |
583 | ||
584 | val |= SLINK_DMA_EN; | |
585 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
586 | return ret; | |
587 | } | |
588 | ||
589 | static int tegra_slink_start_cpu_based_transfer( | |
590 | struct tegra_slink_data *tspi, struct spi_transfer *t) | |
591 | { | |
592 | unsigned long val; | |
593 | unsigned cur_words; | |
594 | ||
595 | val = tspi->packed_size; | |
596 | if (tspi->cur_direction & DATA_DIR_TX) | |
597 | val |= SLINK_IE_TXC; | |
598 | ||
599 | if (tspi->cur_direction & DATA_DIR_RX) | |
600 | val |= SLINK_IE_RXC; | |
601 | ||
602 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
603 | tspi->dma_control_reg = val; | |
604 | ||
605 | if (tspi->cur_direction & DATA_DIR_TX) | |
606 | cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t); | |
607 | else | |
608 | cur_words = tspi->curr_dma_words; | |
609 | val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); | |
610 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
611 | tspi->dma_control_reg = val; | |
612 | ||
613 | tspi->is_curr_dma_xfer = false; | |
614 | if (tspi->is_packed) { | |
615 | val |= SLINK_PACKED; | |
616 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
617 | udelay(1); | |
618 | wmb(); | |
619 | } | |
620 | tspi->dma_control_reg = val; | |
621 | val |= SLINK_DMA_EN; | |
622 | tegra_slink_writel(tspi, val, SLINK_DMA_CTL); | |
623 | return 0; | |
624 | } | |
625 | ||
626 | static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, | |
627 | bool dma_to_memory) | |
628 | { | |
629 | struct dma_chan *dma_chan; | |
630 | u32 *dma_buf; | |
631 | dma_addr_t dma_phys; | |
632 | int ret; | |
633 | struct dma_slave_config dma_sconfig; | |
634 | dma_cap_mask_t mask; | |
635 | ||
636 | dma_cap_zero(mask); | |
637 | dma_cap_set(DMA_SLAVE, mask); | |
638 | dma_chan = dma_request_channel(mask, NULL, NULL); | |
639 | if (!dma_chan) { | |
640 | dev_err(tspi->dev, | |
641 | "Dma channel is not available, will try later\n"); | |
642 | return -EPROBE_DEFER; | |
643 | } | |
644 | ||
645 | dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, | |
646 | &dma_phys, GFP_KERNEL); | |
647 | if (!dma_buf) { | |
648 | dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); | |
649 | dma_release_channel(dma_chan); | |
650 | return -ENOMEM; | |
651 | } | |
652 | ||
653 | dma_sconfig.slave_id = tspi->dma_req_sel; | |
654 | if (dma_to_memory) { | |
655 | dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; | |
656 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
657 | dma_sconfig.src_maxburst = 0; | |
658 | } else { | |
659 | dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; | |
660 | dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
661 | dma_sconfig.dst_maxburst = 0; | |
662 | } | |
663 | ||
664 | ret = dmaengine_slave_config(dma_chan, &dma_sconfig); | |
665 | if (ret) | |
666 | goto scrub; | |
667 | if (dma_to_memory) { | |
668 | tspi->rx_dma_chan = dma_chan; | |
669 | tspi->rx_dma_buf = dma_buf; | |
670 | tspi->rx_dma_phys = dma_phys; | |
671 | } else { | |
672 | tspi->tx_dma_chan = dma_chan; | |
673 | tspi->tx_dma_buf = dma_buf; | |
674 | tspi->tx_dma_phys = dma_phys; | |
675 | } | |
676 | return 0; | |
677 | ||
678 | scrub: | |
679 | dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); | |
680 | dma_release_channel(dma_chan); | |
681 | return ret; | |
682 | } | |
683 | ||
684 | static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi, | |
685 | bool dma_to_memory) | |
686 | { | |
687 | u32 *dma_buf; | |
688 | dma_addr_t dma_phys; | |
689 | struct dma_chan *dma_chan; | |
690 | ||
691 | if (dma_to_memory) { | |
692 | dma_buf = tspi->rx_dma_buf; | |
693 | dma_chan = tspi->rx_dma_chan; | |
694 | dma_phys = tspi->rx_dma_phys; | |
695 | tspi->rx_dma_chan = NULL; | |
696 | tspi->rx_dma_buf = NULL; | |
697 | } else { | |
698 | dma_buf = tspi->tx_dma_buf; | |
699 | dma_chan = tspi->tx_dma_chan; | |
700 | dma_phys = tspi->tx_dma_phys; | |
701 | tspi->tx_dma_buf = NULL; | |
702 | tspi->tx_dma_chan = NULL; | |
703 | } | |
704 | if (!dma_chan) | |
705 | return; | |
706 | ||
707 | dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); | |
708 | dma_release_channel(dma_chan); | |
709 | } | |
710 | ||
711 | static int tegra_slink_start_transfer_one(struct spi_device *spi, | |
712 | struct spi_transfer *t, bool is_first_of_msg, | |
713 | bool is_single_xfer) | |
714 | { | |
715 | struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); | |
716 | u32 speed; | |
717 | u8 bits_per_word; | |
718 | unsigned total_fifo_words; | |
719 | int ret; | |
720 | struct tegra_spi_device_controller_data *cdata = spi->controller_data; | |
721 | unsigned long command; | |
722 | unsigned long command2; | |
723 | ||
e6811d1d | 724 | bits_per_word = t->bits_per_word; |
beb96c2a | 725 | speed = t->speed_hz; |
dc4dc360 LD |
726 | if (speed != tspi->cur_speed) { |
727 | clk_set_rate(tspi->clk, speed * 4); | |
728 | tspi->cur_speed = speed; | |
729 | } | |
730 | ||
731 | tspi->cur_spi = spi; | |
732 | tspi->cur_pos = 0; | |
733 | tspi->cur_rx_pos = 0; | |
734 | tspi->cur_tx_pos = 0; | |
735 | tspi->curr_xfer = t; | |
736 | total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t); | |
737 | ||
738 | if (is_first_of_msg) { | |
739 | tegra_slink_clear_status(tspi); | |
740 | ||
741 | command = tspi->def_command_reg; | |
742 | command |= SLINK_BIT_LENGTH(bits_per_word - 1); | |
743 | ||
744 | command2 = tspi->def_command2_reg; | |
745 | command2 |= SLINK_SS_EN_CS(spi->chip_select); | |
746 | ||
747 | /* possibly use the hw based chip select */ | |
748 | tspi->is_hw_based_cs = false; | |
749 | if (cdata && cdata->is_hw_based_cs && is_single_xfer && | |
750 | ((tspi->curr_dma_words * tspi->bytes_per_word) == | |
751 | (t->len - tspi->cur_pos))) { | |
752 | int setup_count; | |
753 | int sts2; | |
754 | ||
755 | setup_count = cdata->cs_setup_clk_count >> 1; | |
756 | setup_count = max(setup_count, 3); | |
757 | command2 |= SLINK_SS_SETUP(setup_count); | |
758 | if (tspi->chip_data->cs_hold_time) { | |
759 | int hold_count; | |
760 | ||
761 | hold_count = cdata->cs_hold_clk_count; | |
762 | hold_count = max(hold_count, 0xF); | |
763 | sts2 = tegra_slink_readl(tspi, SLINK_STATUS2); | |
764 | sts2 &= ~SLINK_SS_HOLD_TIME(0xF); | |
765 | sts2 |= SLINK_SS_HOLD_TIME(hold_count); | |
766 | tegra_slink_writel(tspi, sts2, SLINK_STATUS2); | |
767 | } | |
768 | tspi->is_hw_based_cs = true; | |
769 | } | |
770 | ||
771 | if (tspi->is_hw_based_cs) | |
772 | command &= ~SLINK_CS_SW; | |
773 | else | |
774 | command |= SLINK_CS_SW | SLINK_CS_VALUE; | |
775 | ||
776 | command &= ~SLINK_MODES; | |
777 | if (spi->mode & SPI_CPHA) | |
778 | command |= SLINK_CK_SDA; | |
779 | ||
780 | if (spi->mode & SPI_CPOL) | |
781 | command |= SLINK_IDLE_SCLK_DRIVE_HIGH; | |
782 | else | |
783 | command |= SLINK_IDLE_SCLK_DRIVE_LOW; | |
784 | } else { | |
785 | command = tspi->command_reg; | |
786 | command &= ~SLINK_BIT_LENGTH(~0); | |
787 | command |= SLINK_BIT_LENGTH(bits_per_word - 1); | |
788 | ||
789 | command2 = tspi->command2_reg; | |
790 | command2 &= ~(SLINK_RXEN | SLINK_TXEN); | |
791 | } | |
792 | ||
793 | tegra_slink_writel(tspi, command, SLINK_COMMAND); | |
794 | tspi->command_reg = command; | |
795 | ||
796 | tspi->cur_direction = 0; | |
797 | if (t->rx_buf) { | |
798 | command2 |= SLINK_RXEN; | |
799 | tspi->cur_direction |= DATA_DIR_RX; | |
800 | } | |
801 | if (t->tx_buf) { | |
802 | command2 |= SLINK_TXEN; | |
803 | tspi->cur_direction |= DATA_DIR_TX; | |
804 | } | |
805 | tegra_slink_writel(tspi, command2, SLINK_COMMAND2); | |
806 | tspi->command2_reg = command2; | |
807 | ||
808 | if (total_fifo_words > SLINK_FIFO_DEPTH) | |
809 | ret = tegra_slink_start_dma_based_transfer(tspi, t); | |
810 | else | |
811 | ret = tegra_slink_start_cpu_based_transfer(tspi, t); | |
812 | return ret; | |
813 | } | |
814 | ||
815 | static int tegra_slink_setup(struct spi_device *spi) | |
816 | { | |
817 | struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); | |
818 | unsigned long val; | |
819 | unsigned long flags; | |
820 | int ret; | |
821 | unsigned int cs_pol_bit[MAX_CHIP_SELECT] = { | |
822 | SLINK_CS_POLARITY, | |
823 | SLINK_CS_POLARITY1, | |
824 | SLINK_CS_POLARITY2, | |
825 | SLINK_CS_POLARITY3, | |
826 | }; | |
827 | ||
828 | dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", | |
829 | spi->bits_per_word, | |
830 | spi->mode & SPI_CPOL ? "" : "~", | |
831 | spi->mode & SPI_CPHA ? "" : "~", | |
832 | spi->max_speed_hz); | |
833 | ||
834 | BUG_ON(spi->chip_select >= MAX_CHIP_SELECT); | |
835 | ||
beb96c2a LD |
836 | /* Set speed to the spi max fequency if spi device has not set */ |
837 | spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency; | |
dc4dc360 LD |
838 | ret = pm_runtime_get_sync(tspi->dev); |
839 | if (ret < 0) { | |
840 | dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); | |
841 | return ret; | |
842 | } | |
843 | ||
844 | spin_lock_irqsave(&tspi->lock, flags); | |
845 | val = tspi->def_command_reg; | |
846 | if (spi->mode & SPI_CS_HIGH) | |
847 | val |= cs_pol_bit[spi->chip_select]; | |
848 | else | |
849 | val &= ~cs_pol_bit[spi->chip_select]; | |
850 | tspi->def_command_reg = val; | |
851 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); | |
852 | spin_unlock_irqrestore(&tspi->lock, flags); | |
853 | ||
854 | pm_runtime_put(tspi->dev); | |
855 | return 0; | |
856 | } | |
857 | ||
dc4dc360 LD |
858 | static int tegra_slink_transfer_one_message(struct spi_master *master, |
859 | struct spi_message *msg) | |
860 | { | |
861 | bool is_first_msg = true; | |
862 | int single_xfer; | |
863 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
864 | struct spi_transfer *xfer; | |
865 | struct spi_device *spi = msg->spi; | |
866 | int ret; | |
867 | ||
868 | msg->status = 0; | |
869 | msg->actual_length = 0; | |
d558c473 LD |
870 | ret = pm_runtime_get_sync(tspi->dev); |
871 | if (ret < 0) { | |
872 | dev_err(tspi->dev, "runtime get failed: %d\n", ret); | |
873 | goto done; | |
874 | } | |
875 | ||
dc4dc360 LD |
876 | single_xfer = list_is_singular(&msg->transfers); |
877 | list_for_each_entry(xfer, &msg->transfers, transfer_list) { | |
878 | INIT_COMPLETION(tspi->xfer_completion); | |
879 | ret = tegra_slink_start_transfer_one(spi, xfer, | |
880 | is_first_msg, single_xfer); | |
881 | if (ret < 0) { | |
882 | dev_err(tspi->dev, | |
883 | "spi can not start transfer, err %d\n", ret); | |
884 | goto exit; | |
885 | } | |
886 | is_first_msg = false; | |
887 | ret = wait_for_completion_timeout(&tspi->xfer_completion, | |
888 | SLINK_DMA_TIMEOUT); | |
889 | if (WARN_ON(ret == 0)) { | |
890 | dev_err(tspi->dev, | |
891 | "spi trasfer timeout, err %d\n", ret); | |
892 | ret = -EIO; | |
893 | goto exit; | |
894 | } | |
895 | ||
896 | if (tspi->tx_status || tspi->rx_status) { | |
897 | dev_err(tspi->dev, "Error in Transfer\n"); | |
898 | ret = -EIO; | |
899 | goto exit; | |
900 | } | |
901 | msg->actual_length += xfer->len; | |
902 | if (xfer->cs_change && xfer->delay_usecs) { | |
903 | tegra_slink_writel(tspi, tspi->def_command_reg, | |
904 | SLINK_COMMAND); | |
905 | udelay(xfer->delay_usecs); | |
906 | } | |
907 | } | |
908 | ret = 0; | |
909 | exit: | |
910 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); | |
911 | tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); | |
d558c473 LD |
912 | pm_runtime_put(tspi->dev); |
913 | done: | |
dc4dc360 LD |
914 | msg->status = ret; |
915 | spi_finalize_current_message(master); | |
916 | return ret; | |
917 | } | |
918 | ||
919 | static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) | |
920 | { | |
921 | struct spi_transfer *t = tspi->curr_xfer; | |
922 | unsigned long flags; | |
923 | ||
924 | spin_lock_irqsave(&tspi->lock, flags); | |
925 | if (tspi->tx_status || tspi->rx_status || | |
926 | (tspi->status_reg & SLINK_BSY)) { | |
927 | dev_err(tspi->dev, | |
928 | "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); | |
929 | dev_err(tspi->dev, | |
930 | "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | |
931 | tspi->command2_reg, tspi->dma_control_reg); | |
932 | tegra_periph_reset_assert(tspi->clk); | |
933 | udelay(2); | |
934 | tegra_periph_reset_deassert(tspi->clk); | |
935 | complete(&tspi->xfer_completion); | |
936 | goto exit; | |
937 | } | |
938 | ||
939 | if (tspi->cur_direction & DATA_DIR_RX) | |
940 | tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t); | |
941 | ||
942 | if (tspi->cur_direction & DATA_DIR_TX) | |
943 | tspi->cur_pos = tspi->cur_tx_pos; | |
944 | else | |
945 | tspi->cur_pos = tspi->cur_rx_pos; | |
946 | ||
947 | if (tspi->cur_pos == t->len) { | |
948 | complete(&tspi->xfer_completion); | |
949 | goto exit; | |
950 | } | |
951 | ||
952 | tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); | |
953 | tegra_slink_start_cpu_based_transfer(tspi, t); | |
954 | exit: | |
955 | spin_unlock_irqrestore(&tspi->lock, flags); | |
956 | return IRQ_HANDLED; | |
957 | } | |
958 | ||
959 | static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) | |
960 | { | |
961 | struct spi_transfer *t = tspi->curr_xfer; | |
962 | long wait_status; | |
963 | int err = 0; | |
964 | unsigned total_fifo_words; | |
965 | unsigned long flags; | |
966 | ||
967 | /* Abort dmas if any error */ | |
968 | if (tspi->cur_direction & DATA_DIR_TX) { | |
969 | if (tspi->tx_status) { | |
970 | dmaengine_terminate_all(tspi->tx_dma_chan); | |
971 | err += 1; | |
972 | } else { | |
973 | wait_status = wait_for_completion_interruptible_timeout( | |
974 | &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); | |
975 | if (wait_status <= 0) { | |
976 | dmaengine_terminate_all(tspi->tx_dma_chan); | |
977 | dev_err(tspi->dev, "TxDma Xfer failed\n"); | |
978 | err += 1; | |
979 | } | |
980 | } | |
981 | } | |
982 | ||
983 | if (tspi->cur_direction & DATA_DIR_RX) { | |
984 | if (tspi->rx_status) { | |
985 | dmaengine_terminate_all(tspi->rx_dma_chan); | |
986 | err += 2; | |
987 | } else { | |
988 | wait_status = wait_for_completion_interruptible_timeout( | |
989 | &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); | |
990 | if (wait_status <= 0) { | |
991 | dmaengine_terminate_all(tspi->rx_dma_chan); | |
992 | dev_err(tspi->dev, "RxDma Xfer failed\n"); | |
993 | err += 2; | |
994 | } | |
995 | } | |
996 | } | |
997 | ||
998 | spin_lock_irqsave(&tspi->lock, flags); | |
999 | if (err) { | |
1000 | dev_err(tspi->dev, | |
1001 | "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); | |
1002 | dev_err(tspi->dev, | |
1003 | "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, | |
1004 | tspi->command2_reg, tspi->dma_control_reg); | |
1005 | tegra_periph_reset_assert(tspi->clk); | |
1006 | udelay(2); | |
1007 | tegra_periph_reset_deassert(tspi->clk); | |
1008 | complete(&tspi->xfer_completion); | |
1009 | spin_unlock_irqrestore(&tspi->lock, flags); | |
1010 | return IRQ_HANDLED; | |
1011 | } | |
1012 | ||
1013 | if (tspi->cur_direction & DATA_DIR_RX) | |
1014 | tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t); | |
1015 | ||
1016 | if (tspi->cur_direction & DATA_DIR_TX) | |
1017 | tspi->cur_pos = tspi->cur_tx_pos; | |
1018 | else | |
1019 | tspi->cur_pos = tspi->cur_rx_pos; | |
1020 | ||
1021 | if (tspi->cur_pos == t->len) { | |
1022 | complete(&tspi->xfer_completion); | |
1023 | goto exit; | |
1024 | } | |
1025 | ||
1026 | /* Continue transfer in current message */ | |
1027 | total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, | |
1028 | tspi, t); | |
1029 | if (total_fifo_words > SLINK_FIFO_DEPTH) | |
1030 | err = tegra_slink_start_dma_based_transfer(tspi, t); | |
1031 | else | |
1032 | err = tegra_slink_start_cpu_based_transfer(tspi, t); | |
1033 | ||
1034 | exit: | |
1035 | spin_unlock_irqrestore(&tspi->lock, flags); | |
1036 | return IRQ_HANDLED; | |
1037 | } | |
1038 | ||
1039 | static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data) | |
1040 | { | |
1041 | struct tegra_slink_data *tspi = context_data; | |
1042 | ||
1043 | if (!tspi->is_curr_dma_xfer) | |
1044 | return handle_cpu_based_xfer(tspi); | |
1045 | return handle_dma_based_xfer(tspi); | |
1046 | } | |
1047 | ||
1048 | static irqreturn_t tegra_slink_isr(int irq, void *context_data) | |
1049 | { | |
1050 | struct tegra_slink_data *tspi = context_data; | |
1051 | ||
1052 | tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); | |
1053 | if (tspi->cur_direction & DATA_DIR_TX) | |
1054 | tspi->tx_status = tspi->status_reg & | |
1055 | (SLINK_TX_OVF | SLINK_TX_UNF); | |
1056 | ||
1057 | if (tspi->cur_direction & DATA_DIR_RX) | |
1058 | tspi->rx_status = tspi->status_reg & | |
1059 | (SLINK_RX_OVF | SLINK_RX_UNF); | |
1060 | tegra_slink_clear_status(tspi); | |
1061 | ||
1062 | return IRQ_WAKE_THREAD; | |
1063 | } | |
1064 | ||
1065 | static struct tegra_spi_platform_data *tegra_slink_parse_dt( | |
1066 | struct platform_device *pdev) | |
1067 | { | |
1068 | struct tegra_spi_platform_data *pdata; | |
1069 | const unsigned int *prop; | |
1070 | struct device_node *np = pdev->dev.of_node; | |
1071 | u32 of_dma[2]; | |
1072 | ||
1073 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
1074 | if (!pdata) { | |
1075 | dev_err(&pdev->dev, "Memory alloc for pdata failed\n"); | |
1076 | return NULL; | |
1077 | } | |
1078 | ||
1079 | if (of_property_read_u32_array(np, "nvidia,dma-request-selector", | |
1080 | of_dma, 2) >= 0) | |
1081 | pdata->dma_req_sel = of_dma[1]; | |
1082 | ||
1083 | prop = of_get_property(np, "spi-max-frequency", NULL); | |
1084 | if (prop) | |
1085 | pdata->spi_max_frequency = be32_to_cpup(prop); | |
1086 | ||
1087 | return pdata; | |
1088 | } | |
1089 | ||
1090 | const struct tegra_slink_chip_data tegra30_spi_cdata = { | |
1091 | .cs_hold_time = true, | |
1092 | }; | |
1093 | ||
1094 | const struct tegra_slink_chip_data tegra20_spi_cdata = { | |
1095 | .cs_hold_time = false, | |
1096 | }; | |
1097 | ||
fd4a319b | 1098 | static struct of_device_id tegra_slink_of_match[] = { |
dc4dc360 | 1099 | { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, }, |
24bc8971 | 1100 | { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, }, |
dc4dc360 LD |
1101 | {} |
1102 | }; | |
1103 | MODULE_DEVICE_TABLE(of, tegra_slink_of_match); | |
1104 | ||
fd4a319b | 1105 | static int tegra_slink_probe(struct platform_device *pdev) |
dc4dc360 LD |
1106 | { |
1107 | struct spi_master *master; | |
1108 | struct tegra_slink_data *tspi; | |
1109 | struct resource *r; | |
1110 | struct tegra_spi_platform_data *pdata = pdev->dev.platform_data; | |
1111 | int ret, spi_irq; | |
1112 | const struct tegra_slink_chip_data *cdata = NULL; | |
1113 | const struct of_device_id *match; | |
1114 | ||
1115 | match = of_match_device(of_match_ptr(tegra_slink_of_match), &pdev->dev); | |
1116 | if (!match) { | |
1117 | dev_err(&pdev->dev, "Error: No device match found\n"); | |
1118 | return -ENODEV; | |
1119 | } | |
1120 | cdata = match->data; | |
1121 | if (!pdata && pdev->dev.of_node) | |
1122 | pdata = tegra_slink_parse_dt(pdev); | |
1123 | ||
1124 | if (!pdata) { | |
1125 | dev_err(&pdev->dev, "No platform data, exiting\n"); | |
1126 | return -ENODEV; | |
1127 | } | |
1128 | ||
1129 | if (!pdata->spi_max_frequency) | |
1130 | pdata->spi_max_frequency = 25000000; /* 25MHz */ | |
1131 | ||
1132 | master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); | |
1133 | if (!master) { | |
1134 | dev_err(&pdev->dev, "master allocation failed\n"); | |
1135 | return -ENOMEM; | |
1136 | } | |
1137 | ||
1138 | /* the spi->mode bits understood by this driver: */ | |
1139 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
1140 | master->setup = tegra_slink_setup; | |
dc4dc360 | 1141 | master->transfer_one_message = tegra_slink_transfer_one_message; |
dc4dc360 LD |
1142 | master->num_chipselect = MAX_CHIP_SELECT; |
1143 | master->bus_num = -1; | |
1144 | ||
1145 | dev_set_drvdata(&pdev->dev, master); | |
1146 | tspi = spi_master_get_devdata(master); | |
1147 | tspi->master = master; | |
1148 | tspi->dma_req_sel = pdata->dma_req_sel; | |
1149 | tspi->dev = &pdev->dev; | |
1150 | tspi->chip_data = cdata; | |
1151 | spin_lock_init(&tspi->lock); | |
1152 | ||
1153 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1154 | if (!r) { | |
1155 | dev_err(&pdev->dev, "No IO memory resource\n"); | |
1156 | ret = -ENODEV; | |
1157 | goto exit_free_master; | |
1158 | } | |
1159 | tspi->phys = r->start; | |
b0ee5605 TR |
1160 | tspi->base = devm_ioremap_resource(&pdev->dev, r); |
1161 | if (IS_ERR(tspi->base)) { | |
1162 | ret = PTR_ERR(tspi->base); | |
dc4dc360 LD |
1163 | goto exit_free_master; |
1164 | } | |
1165 | ||
1166 | spi_irq = platform_get_irq(pdev, 0); | |
1167 | tspi->irq = spi_irq; | |
1168 | ret = request_threaded_irq(tspi->irq, tegra_slink_isr, | |
1169 | tegra_slink_isr_thread, IRQF_ONESHOT, | |
1170 | dev_name(&pdev->dev), tspi); | |
1171 | if (ret < 0) { | |
1172 | dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", | |
1173 | tspi->irq); | |
1174 | goto exit_free_master; | |
1175 | } | |
1176 | ||
3cb91902 | 1177 | tspi->clk = devm_clk_get(&pdev->dev, NULL); |
dc4dc360 LD |
1178 | if (IS_ERR(tspi->clk)) { |
1179 | dev_err(&pdev->dev, "can not get clock\n"); | |
1180 | ret = PTR_ERR(tspi->clk); | |
1181 | goto exit_free_irq; | |
1182 | } | |
1183 | ||
1184 | tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; | |
1185 | tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; | |
1186 | tspi->spi_max_frequency = pdata->spi_max_frequency; | |
1187 | ||
1188 | if (pdata->dma_req_sel) { | |
1189 | ret = tegra_slink_init_dma_param(tspi, true); | |
1190 | if (ret < 0) { | |
1191 | dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret); | |
1192 | goto exit_free_irq; | |
1193 | } | |
1194 | ||
1195 | ret = tegra_slink_init_dma_param(tspi, false); | |
1196 | if (ret < 0) { | |
1197 | dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret); | |
1198 | goto exit_rx_dma_free; | |
1199 | } | |
1200 | tspi->max_buf_size = tspi->dma_buf_size; | |
1201 | init_completion(&tspi->tx_dma_complete); | |
1202 | init_completion(&tspi->rx_dma_complete); | |
1203 | } | |
1204 | ||
1205 | init_completion(&tspi->xfer_completion); | |
1206 | ||
1207 | pm_runtime_enable(&pdev->dev); | |
1208 | if (!pm_runtime_enabled(&pdev->dev)) { | |
1209 | ret = tegra_slink_runtime_resume(&pdev->dev); | |
1210 | if (ret) | |
1211 | goto exit_pm_disable; | |
1212 | } | |
1213 | ||
1214 | ret = pm_runtime_get_sync(&pdev->dev); | |
1215 | if (ret < 0) { | |
1216 | dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); | |
1217 | goto exit_pm_disable; | |
1218 | } | |
1219 | tspi->def_command_reg = SLINK_M_S; | |
1220 | tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; | |
1221 | tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); | |
1222 | tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); | |
1223 | pm_runtime_put(&pdev->dev); | |
1224 | ||
1225 | master->dev.of_node = pdev->dev.of_node; | |
1226 | ret = spi_register_master(master); | |
1227 | if (ret < 0) { | |
1228 | dev_err(&pdev->dev, "can not register to master err %d\n", ret); | |
1229 | goto exit_pm_disable; | |
1230 | } | |
1231 | return ret; | |
1232 | ||
1233 | exit_pm_disable: | |
1234 | pm_runtime_disable(&pdev->dev); | |
1235 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
1236 | tegra_slink_runtime_suspend(&pdev->dev); | |
1237 | tegra_slink_deinit_dma_param(tspi, false); | |
1238 | exit_rx_dma_free: | |
1239 | tegra_slink_deinit_dma_param(tspi, true); | |
1240 | exit_free_irq: | |
1241 | free_irq(spi_irq, tspi); | |
1242 | exit_free_master: | |
1243 | spi_master_put(master); | |
1244 | return ret; | |
1245 | } | |
1246 | ||
fd4a319b | 1247 | static int tegra_slink_remove(struct platform_device *pdev) |
dc4dc360 LD |
1248 | { |
1249 | struct spi_master *master = dev_get_drvdata(&pdev->dev); | |
1250 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
1251 | ||
1252 | free_irq(tspi->irq, tspi); | |
1253 | spi_unregister_master(master); | |
1254 | ||
1255 | if (tspi->tx_dma_chan) | |
1256 | tegra_slink_deinit_dma_param(tspi, false); | |
1257 | ||
1258 | if (tspi->rx_dma_chan) | |
1259 | tegra_slink_deinit_dma_param(tspi, true); | |
1260 | ||
1261 | pm_runtime_disable(&pdev->dev); | |
1262 | if (!pm_runtime_status_suspended(&pdev->dev)) | |
1263 | tegra_slink_runtime_suspend(&pdev->dev); | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | #ifdef CONFIG_PM_SLEEP | |
1269 | static int tegra_slink_suspend(struct device *dev) | |
1270 | { | |
1271 | struct spi_master *master = dev_get_drvdata(dev); | |
1272 | ||
1273 | return spi_master_suspend(master); | |
1274 | } | |
1275 | ||
1276 | static int tegra_slink_resume(struct device *dev) | |
1277 | { | |
1278 | struct spi_master *master = dev_get_drvdata(dev); | |
1279 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
1280 | int ret; | |
1281 | ||
1282 | ret = pm_runtime_get_sync(dev); | |
1283 | if (ret < 0) { | |
1284 | dev_err(dev, "pm runtime failed, e = %d\n", ret); | |
1285 | return ret; | |
1286 | } | |
1287 | tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); | |
1288 | tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); | |
1289 | pm_runtime_put(dev); | |
1290 | ||
1291 | return spi_master_resume(master); | |
1292 | } | |
1293 | #endif | |
1294 | ||
1295 | static int tegra_slink_runtime_suspend(struct device *dev) | |
1296 | { | |
1297 | struct spi_master *master = dev_get_drvdata(dev); | |
1298 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
1299 | ||
1300 | /* Flush all write which are in PPSB queue by reading back */ | |
1301 | tegra_slink_readl(tspi, SLINK_MAS_DATA); | |
1302 | ||
1303 | clk_disable_unprepare(tspi->clk); | |
1304 | return 0; | |
1305 | } | |
1306 | ||
1307 | static int tegra_slink_runtime_resume(struct device *dev) | |
1308 | { | |
1309 | struct spi_master *master = dev_get_drvdata(dev); | |
1310 | struct tegra_slink_data *tspi = spi_master_get_devdata(master); | |
1311 | int ret; | |
1312 | ||
1313 | ret = clk_prepare_enable(tspi->clk); | |
1314 | if (ret < 0) { | |
1315 | dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); | |
1316 | return ret; | |
1317 | } | |
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | static const struct dev_pm_ops slink_pm_ops = { | |
1322 | SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend, | |
1323 | tegra_slink_runtime_resume, NULL) | |
1324 | SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume) | |
1325 | }; | |
1326 | static struct platform_driver tegra_slink_driver = { | |
1327 | .driver = { | |
1328 | .name = "spi-tegra-slink", | |
1329 | .owner = THIS_MODULE, | |
1330 | .pm = &slink_pm_ops, | |
1331 | .of_match_table = of_match_ptr(tegra_slink_of_match), | |
1332 | }, | |
1333 | .probe = tegra_slink_probe, | |
fd4a319b | 1334 | .remove = tegra_slink_remove, |
dc4dc360 LD |
1335 | }; |
1336 | module_platform_driver(tegra_slink_driver); | |
1337 | ||
1338 | MODULE_ALIAS("platform:spi-tegra-slink"); | |
1339 | MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver"); | |
1340 | MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); | |
1341 | MODULE_LICENSE("GPL v2"); |