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spi/tegra-sflash: assume CONFIG_OF, remove platform data
[mirror_ubuntu-jammy-kernel.git] / drivers / spi / spi-tegra20-slink.c
CommitLineData
dc4dc360
LD		 1/*
2 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller.
3 *
4 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
20#include <linux/completion.h>
21#include <linux/delay.h>
22#include <linux/dmaengine.h>
23#include <linux/dma-mapping.h>
24#include <linux/dmapool.h>
25#include <linux/err.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kernel.h>
30#include <linux/kthread.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
33#include <linux/pm_runtime.h>
34#include <linux/of.h>
35#include <linux/of_device.h>
36#include <linux/spi/spi.h>
37#include <linux/spi/spi-tegra.h>
61fd290d 38#include <linux/clk/tegra.h>
dc4dc360
LD		 39
40#define SLINK_COMMAND 0x000
41#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
42#define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
43#define SLINK_BOTH_EN (1 << 10)
44#define SLINK_CS_SW (1 << 11)
45#define SLINK_CS_VALUE (1 << 12)
46#define SLINK_CS_POLARITY (1 << 13)
47#define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
48#define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
49#define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
50#define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
51#define SLINK_IDLE_SDA_MASK (3 << 16)
52#define SLINK_CS_POLARITY1 (1 << 20)
53#define SLINK_CK_SDA (1 << 21)
54#define SLINK_CS_POLARITY2 (1 << 22)
55#define SLINK_CS_POLARITY3 (1 << 23)
56#define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
57#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
58#define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
59#define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
60#define SLINK_IDLE_SCLK_MASK (3 << 24)
61#define SLINK_M_S (1 << 28)
62#define SLINK_WAIT (1 << 29)
63#define SLINK_GO (1 << 30)
64#define SLINK_ENB (1 << 31)
65
66#define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA)
67
68#define SLINK_COMMAND2 0x004
69#define SLINK_LSBFE (1 << 0)
70#define SLINK_SSOE (1 << 1)
71#define SLINK_SPIE (1 << 4)
72#define SLINK_BIDIROE (1 << 6)
73#define SLINK_MODFEN (1 << 7)
74#define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
75#define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
76#define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
77#define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
78#define SLINK_FIFO_REFILLS_0 (0 << 22)
79#define SLINK_FIFO_REFILLS_1 (1 << 22)
80#define SLINK_FIFO_REFILLS_2 (2 << 22)
81#define SLINK_FIFO_REFILLS_3 (3 << 22)
82#define SLINK_FIFO_REFILLS_MASK (3 << 22)
83#define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
84#define SLINK_SPC0 (1 << 29)
85#define SLINK_TXEN (1 << 30)
86#define SLINK_RXEN (1 << 31)
87
88#define SLINK_STATUS 0x008
89#define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
90#define SLINK_WORD(val) (((val) >> 5) & 0x1f)
91#define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
92#define SLINK_MODF (1 << 16)
93#define SLINK_RX_UNF (1 << 18)
94#define SLINK_TX_OVF (1 << 19)
95#define SLINK_TX_FULL (1 << 20)
96#define SLINK_TX_EMPTY (1 << 21)
97#define SLINK_RX_FULL (1 << 22)
98#define SLINK_RX_EMPTY (1 << 23)
99#define SLINK_TX_UNF (1 << 24)
100#define SLINK_RX_OVF (1 << 25)
101#define SLINK_TX_FLUSH (1 << 26)
102#define SLINK_RX_FLUSH (1 << 27)
103#define SLINK_SCLK (1 << 28)
104#define SLINK_ERR (1 << 29)
105#define SLINK_RDY (1 << 30)
106#define SLINK_BSY (1 << 31)
107#define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \
108 SLINK_TX_UNF | SLINK_RX_OVF)
109
110#define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY)
111
112#define SLINK_MAS_DATA 0x010
113#define SLINK_SLAVE_DATA 0x014
114
115#define SLINK_DMA_CTL 0x018
116#define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
117#define SLINK_TX_TRIG_1 (0 << 16)
118#define SLINK_TX_TRIG_4 (1 << 16)
119#define SLINK_TX_TRIG_8 (2 << 16)
120#define SLINK_TX_TRIG_16 (3 << 16)
121#define SLINK_TX_TRIG_MASK (3 << 16)
122#define SLINK_RX_TRIG_1 (0 << 18)
123#define SLINK_RX_TRIG_4 (1 << 18)
124#define SLINK_RX_TRIG_8 (2 << 18)
125#define SLINK_RX_TRIG_16 (3 << 18)
126#define SLINK_RX_TRIG_MASK (3 << 18)
127#define SLINK_PACKED (1 << 20)
128#define SLINK_PACK_SIZE_4 (0 << 21)
129#define SLINK_PACK_SIZE_8 (1 << 21)
130#define SLINK_PACK_SIZE_16 (2 << 21)
131#define SLINK_PACK_SIZE_32 (3 << 21)
132#define SLINK_PACK_SIZE_MASK (3 << 21)
133#define SLINK_IE_TXC (1 << 26)
134#define SLINK_IE_RXC (1 << 27)
135#define SLINK_DMA_EN (1 << 31)
136
137#define SLINK_STATUS2 0x01c
138#define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
139#define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16)
140#define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6)
141
142#define SLINK_TX_FIFO 0x100
143#define SLINK_RX_FIFO 0x180
144
145#define DATA_DIR_TX (1 << 0)
146#define DATA_DIR_RX (1 << 1)
147
148#define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000))
149
150#define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
151#define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20)
152#define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0)
153
154#define SLINK_STATUS2_RESET \
155 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16)
156
157#define MAX_CHIP_SELECT 4
158#define SLINK_FIFO_DEPTH 32
159
160struct tegra_slink_chip_data {
161 bool cs_hold_time;
162};
163
164struct tegra_slink_data {
165 struct device *dev;
166 struct spi_master *master;
167 const struct tegra_slink_chip_data *chip_data;
168 spinlock_t lock;
169
170 struct clk *clk;
171 void __iomem *base;
172 phys_addr_t phys;
173 unsigned irq;
174 int dma_req_sel;
175 u32 spi_max_frequency;
176 u32 cur_speed;
177
178 struct spi_device *cur_spi;
179 unsigned cur_pos;
180 unsigned cur_len;
181 unsigned words_per_32bit;
182 unsigned bytes_per_word;
183 unsigned curr_dma_words;
184 unsigned cur_direction;
185
186 unsigned cur_rx_pos;
187 unsigned cur_tx_pos;
188
189 unsigned dma_buf_size;
190 unsigned max_buf_size;
191 bool is_curr_dma_xfer;
dc4dc360
LD		 192
193 struct completion rx_dma_complete;
194 struct completion tx_dma_complete;
195
196 u32 tx_status;
197 u32 rx_status;
198 u32 status_reg;
199 bool is_packed;
200 unsigned long packed_size;
201
202 u32 command_reg;
203 u32 command2_reg;
204 u32 dma_control_reg;
205 u32 def_command_reg;
206 u32 def_command2_reg;
207
208 struct completion xfer_completion;
209 struct spi_transfer *curr_xfer;
210 struct dma_chan *rx_dma_chan;
211 u32 *rx_dma_buf;
212 dma_addr_t rx_dma_phys;
213 struct dma_async_tx_descriptor *rx_dma_desc;
214
215 struct dma_chan *tx_dma_chan;
216 u32 *tx_dma_buf;
217 dma_addr_t tx_dma_phys;
218 struct dma_async_tx_descriptor *tx_dma_desc;
219};
220
221static int tegra_slink_runtime_suspend(struct device *dev);
222static int tegra_slink_runtime_resume(struct device *dev);
223
224static inline unsigned long tegra_slink_readl(struct tegra_slink_data *tspi,
225 unsigned long reg)
226{
227 return readl(tspi->base + reg);
228}
229
230static inline void tegra_slink_writel(struct tegra_slink_data *tspi,
231 unsigned long val, unsigned long reg)
232{
233 writel(val, tspi->base + reg);
234
235 /* Read back register to make sure that register writes completed */
236 if (reg != SLINK_TX_FIFO)
237 readl(tspi->base + SLINK_MAS_DATA);
238}
239
240static void tegra_slink_clear_status(struct tegra_slink_data *tspi)
241{
242 unsigned long val;
243 unsigned long val_write = 0;
244
245 val = tegra_slink_readl(tspi, SLINK_STATUS);
246
247 /* Write 1 to clear status register */
248 val_write = SLINK_RDY | SLINK_FIFO_ERROR;
249 tegra_slink_writel(tspi, val_write, SLINK_STATUS);
250}
251
252static unsigned long tegra_slink_get_packed_size(struct tegra_slink_data *tspi,
253 struct spi_transfer *t)
254{
255 unsigned long val;
256
257 switch (tspi->bytes_per_word) {
258 case 0:
259 val = SLINK_PACK_SIZE_4;
260 break;
261 case 1:
262 val = SLINK_PACK_SIZE_8;
263 break;
264 case 2:
265 val = SLINK_PACK_SIZE_16;
266 break;
267 case 4:
268 val = SLINK_PACK_SIZE_32;
269 break;
270 default:
271 val = 0;
272 }
273 return val;
274}
275
276static unsigned tegra_slink_calculate_curr_xfer_param(
277 struct spi_device *spi, struct tegra_slink_data *tspi,
278 struct spi_transfer *t)
279{
280 unsigned remain_len = t->len - tspi->cur_pos;
281 unsigned max_word;
282 unsigned bits_per_word ;
283 unsigned max_len;
284 unsigned total_fifo_words;
285
766ed704 286 bits_per_word = t->bits_per_word;
dc4dc360
LD		 287 tspi->bytes_per_word = (bits_per_word - 1) / 8 + 1;
288
289 if (bits_per_word == 8 || bits_per_word == 16) {
290 tspi->is_packed = 1;
291 tspi->words_per_32bit = 32/bits_per_word;
292 } else {
293 tspi->is_packed = 0;
294 tspi->words_per_32bit = 1;
295 }
296 tspi->packed_size = tegra_slink_get_packed_size(tspi, t);
297
298 if (tspi->is_packed) {
299 max_len = min(remain_len, tspi->max_buf_size);
300 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
301 total_fifo_words = max_len/4;
302 } else {
303 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
304 max_word = min(max_word, tspi->max_buf_size/4);
305 tspi->curr_dma_words = max_word;
306 total_fifo_words = max_word;
307 }
308 return total_fifo_words;
309}
310
311static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf(
312 struct tegra_slink_data *tspi, struct spi_transfer *t)
313{
314 unsigned nbytes;
315 unsigned tx_empty_count;
316 unsigned long fifo_status;
317 unsigned max_n_32bit;
318 unsigned i, count;
319 unsigned long x;
320 unsigned int written_words;
321 unsigned fifo_words_left;
322 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
323
324 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
325 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status);
326
327 if (tspi->is_packed) {
328 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
329 written_words = min(fifo_words_left, tspi->curr_dma_words);
330 nbytes = written_words * tspi->bytes_per_word;
331 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
332 for (count = 0; count < max_n_32bit; count++) {
333 x = 0;
334 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
335 x |= (*tx_buf++) << (i*8);
336 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
337 }
338 } else {
339 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
340 written_words = max_n_32bit;
341 nbytes = written_words * tspi->bytes_per_word;
342 for (count = 0; count < max_n_32bit; count++) {
343 x = 0;
344 for (i = 0; nbytes && (i < tspi->bytes_per_word);
345 i++, nbytes--)
346 x |= ((*tx_buf++) << i*8);
347 tegra_slink_writel(tspi, x, SLINK_TX_FIFO);
348 }
349 }
350 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
351 return written_words;
352}
353
354static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf(
355 struct tegra_slink_data *tspi, struct spi_transfer *t)
356{
357 unsigned rx_full_count;
358 unsigned long fifo_status;
359 unsigned i, count;
360 unsigned long x;
361 unsigned int read_words = 0;
362 unsigned len;
363 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
364
365 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2);
366 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status);
367 if (tspi->is_packed) {
368 len = tspi->curr_dma_words * tspi->bytes_per_word;
369 for (count = 0; count < rx_full_count; count++) {
370 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
371 for (i = 0; len && (i < 4); i++, len--)
372 *rx_buf++ = (x >> i*8) & 0xFF;
373 }
374 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
375 read_words += tspi->curr_dma_words;
376 } else {
dc4dc360
LD		 377 for (count = 0; count < rx_full_count; count++) {
378 x = tegra_slink_readl(tspi, SLINK_RX_FIFO);
379 for (i = 0; (i < tspi->bytes_per_word); i++)
380 *rx_buf++ = (x >> (i*8)) & 0xFF;
381 }
382 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
383 read_words += rx_full_count;
384 }
385 return read_words;
386}
387
388static void tegra_slink_copy_client_txbuf_to_spi_txbuf(
389 struct tegra_slink_data *tspi, struct spi_transfer *t)
390{
391 unsigned len;
392
393 /* Make the dma buffer to read by cpu */
394 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
395 tspi->dma_buf_size, DMA_TO_DEVICE);
396
397 if (tspi->is_packed) {
398 len = tspi->curr_dma_words * tspi->bytes_per_word;
399 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
400 } else {
401 unsigned int i;
402 unsigned int count;
403 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
404 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
405 unsigned int x;
406
407 for (count = 0; count < tspi->curr_dma_words; count++) {
408 x = 0;
409 for (i = 0; consume && (i < tspi->bytes_per_word);
410 i++, consume--)
411 x |= ((*tx_buf++) << i * 8);
412 tspi->tx_dma_buf[count] = x;
413 }
414 }
415 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
416
417 /* Make the dma buffer to read by dma */
418 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
419 tspi->dma_buf_size, DMA_TO_DEVICE);
420}
421
422static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf(
423 struct tegra_slink_data *tspi, struct spi_transfer *t)
424{
425 unsigned len;
426
427 /* Make the dma buffer to read by cpu */
428 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
429 tspi->dma_buf_size, DMA_FROM_DEVICE);
430
431 if (tspi->is_packed) {
432 len = tspi->curr_dma_words * tspi->bytes_per_word;
433 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
434 } else {
435 unsigned int i;
436 unsigned int count;
437 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
438 unsigned int x;
439 unsigned int rx_mask, bits_per_word;
440
766ed704 441 bits_per_word = t->bits_per_word;
dc4dc360
LD		 442 rx_mask = (1 << bits_per_word) - 1;
443 for (count = 0; count < tspi->curr_dma_words; count++) {
444 x = tspi->rx_dma_buf[count];
445 x &= rx_mask;
446 for (i = 0; (i < tspi->bytes_per_word); i++)
447 *rx_buf++ = (x >> (i*8)) & 0xFF;
448 }
449 }
450 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
451
452 /* Make the dma buffer to read by dma */
453 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
454 tspi->dma_buf_size, DMA_FROM_DEVICE);
455}
456
457static void tegra_slink_dma_complete(void *args)
458{
459 struct completion *dma_complete = args;
460
461 complete(dma_complete);
462}
463
464static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len)
465{
466 INIT_COMPLETION(tspi->tx_dma_complete);
467 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
468 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
72919f34 469 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
dc4dc360
LD		 470 if (!tspi->tx_dma_desc) {
471 dev_err(tspi->dev, "Not able to get desc for Tx\n");
472 return -EIO;
473 }
474
475 tspi->tx_dma_desc->callback = tegra_slink_dma_complete;
476 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
477
478 dmaengine_submit(tspi->tx_dma_desc);
479 dma_async_issue_pending(tspi->tx_dma_chan);
480 return 0;
481}
482
483static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len)
484{
485 INIT_COMPLETION(tspi->rx_dma_complete);
486 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
487 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
72919f34 488 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
dc4dc360
LD		 489 if (!tspi->rx_dma_desc) {
490 dev_err(tspi->dev, "Not able to get desc for Rx\n");
491 return -EIO;
492 }
493
494 tspi->rx_dma_desc->callback = tegra_slink_dma_complete;
495 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
496
497 dmaengine_submit(tspi->rx_dma_desc);
498 dma_async_issue_pending(tspi->rx_dma_chan);
499 return 0;
500}
501
502static int tegra_slink_start_dma_based_transfer(
503 struct tegra_slink_data *tspi, struct spi_transfer *t)
504{
505 unsigned long val;
506 unsigned long test_val;
507 unsigned int len;
508 int ret = 0;
509 unsigned long status;
510
511 /* Make sure that Rx and Tx fifo are empty */
512 status = tegra_slink_readl(tspi, SLINK_STATUS);
513 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) {
514 dev_err(tspi->dev,
515 "Rx/Tx fifo are not empty status 0x%08lx\n", status);
516 return -EIO;
517 }
518
519 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1);
520 val |= tspi->packed_size;
521 if (tspi->is_packed)
522 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
523 4) * 4;
524 else
525 len = tspi->curr_dma_words * 4;
526
527 /* Set attention level based on length of transfer */
528 if (len & 0xF)
529 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
530 else if (((len) >> 4) & 0x1)
531 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
532 else
533 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
534
535 if (tspi->cur_direction & DATA_DIR_TX)
536 val |= SLINK_IE_TXC;
537
538 if (tspi->cur_direction & DATA_DIR_RX)
539 val |= SLINK_IE_RXC;
540
541 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
542 tspi->dma_control_reg = val;
543
544 if (tspi->cur_direction & DATA_DIR_TX) {
545 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t);
546 wmb();
547 ret = tegra_slink_start_tx_dma(tspi, len);
548 if (ret < 0) {
549 dev_err(tspi->dev,
550 "Starting tx dma failed, err %d\n", ret);
551 return ret;
552 }
553
554 /* Wait for tx fifo to be fill before starting slink */
555 test_val = tegra_slink_readl(tspi, SLINK_STATUS);
556 while (!(test_val & SLINK_TX_FULL))
557 test_val = tegra_slink_readl(tspi, SLINK_STATUS);
558 }
559
560 if (tspi->cur_direction & DATA_DIR_RX) {
561 /* Make the dma buffer to read by dma */
562 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
563 tspi->dma_buf_size, DMA_FROM_DEVICE);
564
565 ret = tegra_slink_start_rx_dma(tspi, len);
566 if (ret < 0) {
567 dev_err(tspi->dev,
568 "Starting rx dma failed, err %d\n", ret);
569 if (tspi->cur_direction & DATA_DIR_TX)
570 dmaengine_terminate_all(tspi->tx_dma_chan);
571 return ret;
572 }
573 }
574 tspi->is_curr_dma_xfer = true;
575 if (tspi->is_packed) {
576 val |= SLINK_PACKED;
577 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
578 /* HW need small delay after settign Packed mode */
579 udelay(1);
580 }
581 tspi->dma_control_reg = val;
582
583 val |= SLINK_DMA_EN;
584 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
585 return ret;
586}
587
588static int tegra_slink_start_cpu_based_transfer(
589 struct tegra_slink_data *tspi, struct spi_transfer *t)
590{
591 unsigned long val;
592 unsigned cur_words;
593
594 val = tspi->packed_size;
595 if (tspi->cur_direction & DATA_DIR_TX)
596 val |= SLINK_IE_TXC;
597
598 if (tspi->cur_direction & DATA_DIR_RX)
599 val |= SLINK_IE_RXC;
600
601 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
602 tspi->dma_control_reg = val;
603
604 if (tspi->cur_direction & DATA_DIR_TX)
605 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t);
606 else
607 cur_words = tspi->curr_dma_words;
608 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1);
609 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
610 tspi->dma_control_reg = val;
611
612 tspi->is_curr_dma_xfer = false;
613 if (tspi->is_packed) {
614 val |= SLINK_PACKED;
615 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
616 udelay(1);
617 wmb();
618 }
619 tspi->dma_control_reg = val;
620 val |= SLINK_DMA_EN;
621 tegra_slink_writel(tspi, val, SLINK_DMA_CTL);
622 return 0;
623}
624
625static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi,
626 bool dma_to_memory)
627{
628 struct dma_chan *dma_chan;
629 u32 *dma_buf;
630 dma_addr_t dma_phys;
631 int ret;
632 struct dma_slave_config dma_sconfig;
633 dma_cap_mask_t mask;
634
635 dma_cap_zero(mask);
636 dma_cap_set(DMA_SLAVE, mask);
637 dma_chan = dma_request_channel(mask, NULL, NULL);
638 if (!dma_chan) {
639 dev_err(tspi->dev,
640 "Dma channel is not available, will try later\n");
641 return -EPROBE_DEFER;
642 }
643
644 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
645 &dma_phys, GFP_KERNEL);
646 if (!dma_buf) {
647 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
648 dma_release_channel(dma_chan);
649 return -ENOMEM;
650 }
651
652 dma_sconfig.slave_id = tspi->dma_req_sel;
653 if (dma_to_memory) {
654 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
655 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
656 dma_sconfig.src_maxburst = 0;
657 } else {
658 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO;
659 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
660 dma_sconfig.dst_maxburst = 0;
661 }
662
663 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
664 if (ret)
665 goto scrub;
666 if (dma_to_memory) {
667 tspi->rx_dma_chan = dma_chan;
668 tspi->rx_dma_buf = dma_buf;
669 tspi->rx_dma_phys = dma_phys;
670 } else {
671 tspi->tx_dma_chan = dma_chan;
672 tspi->tx_dma_buf = dma_buf;
673 tspi->tx_dma_phys = dma_phys;
674 }
675 return 0;
676
677scrub:
678 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
679 dma_release_channel(dma_chan);
680 return ret;
681}
682
683static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi,
684 bool dma_to_memory)
685{
686 u32 *dma_buf;
687 dma_addr_t dma_phys;
688 struct dma_chan *dma_chan;
689
690 if (dma_to_memory) {
691 dma_buf = tspi->rx_dma_buf;
692 dma_chan = tspi->rx_dma_chan;
693 dma_phys = tspi->rx_dma_phys;
694 tspi->rx_dma_chan = NULL;
695 tspi->rx_dma_buf = NULL;
696 } else {
697 dma_buf = tspi->tx_dma_buf;
698 dma_chan = tspi->tx_dma_chan;
699 dma_phys = tspi->tx_dma_phys;
700 tspi->tx_dma_buf = NULL;
701 tspi->tx_dma_chan = NULL;
702 }
703 if (!dma_chan)
704 return;
705
706 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
707 dma_release_channel(dma_chan);
708}
709
710static int tegra_slink_start_transfer_one(struct spi_device *spi,
711 struct spi_transfer *t, bool is_first_of_msg,
712 bool is_single_xfer)
713{
714 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
715 u32 speed;
716 u8 bits_per_word;
717 unsigned total_fifo_words;
718 int ret;
dc4dc360
LD		 719 unsigned long command;
720 unsigned long command2;
721
e6811d1d 722 bits_per_word = t->bits_per_word;
beb96c2a 723 speed = t->speed_hz;
dc4dc360
LD		 724 if (speed != tspi->cur_speed) {
725 clk_set_rate(tspi->clk, speed * 4);
726 tspi->cur_speed = speed;
727 }
728
729 tspi->cur_spi = spi;
730 tspi->cur_pos = 0;
731 tspi->cur_rx_pos = 0;
732 tspi->cur_tx_pos = 0;
733 tspi->curr_xfer = t;
734 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t);
735
736 if (is_first_of_msg) {
737 tegra_slink_clear_status(tspi);
738
739 command = tspi->def_command_reg;
740 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
ede2738a 741 command |= SLINK_CS_SW | SLINK_CS_VALUE;
dc4dc360
LD		 742
743 command2 = tspi->def_command2_reg;
744 command2 |= SLINK_SS_EN_CS(spi->chip_select);
745
dc4dc360
LD		 746 command &= ~SLINK_MODES;
747 if (spi->mode & SPI_CPHA)
748 command |= SLINK_CK_SDA;
749
750 if (spi->mode & SPI_CPOL)
751 command |= SLINK_IDLE_SCLK_DRIVE_HIGH;
752 else
753 command |= SLINK_IDLE_SCLK_DRIVE_LOW;
754 } else {
755 command = tspi->command_reg;
756 command &= ~SLINK_BIT_LENGTH(~0);
757 command |= SLINK_BIT_LENGTH(bits_per_word - 1);
758
759 command2 = tspi->command2_reg;
760 command2 &= ~(SLINK_RXEN | SLINK_TXEN);
761 }
762
763 tegra_slink_writel(tspi, command, SLINK_COMMAND);
764 tspi->command_reg = command;
765
766 tspi->cur_direction = 0;
767 if (t->rx_buf) {
768 command2 |= SLINK_RXEN;
769 tspi->cur_direction |= DATA_DIR_RX;
770 }
771 if (t->tx_buf) {
772 command2 |= SLINK_TXEN;
773 tspi->cur_direction |= DATA_DIR_TX;
774 }
775 tegra_slink_writel(tspi, command2, SLINK_COMMAND2);
776 tspi->command2_reg = command2;
777
778 if (total_fifo_words > SLINK_FIFO_DEPTH)
779 ret = tegra_slink_start_dma_based_transfer(tspi, t);
780 else
781 ret = tegra_slink_start_cpu_based_transfer(tspi, t);
782 return ret;
783}
784
785static int tegra_slink_setup(struct spi_device *spi)
786{
787 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master);
788 unsigned long val;
789 unsigned long flags;
790 int ret;
791 unsigned int cs_pol_bit[MAX_CHIP_SELECT] = {
792 SLINK_CS_POLARITY,
793 SLINK_CS_POLARITY1,
794 SLINK_CS_POLARITY2,
795 SLINK_CS_POLARITY3,
796 };
797
798 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
799 spi->bits_per_word,
800 spi->mode & SPI_CPOL ? "" : "~",
801 spi->mode & SPI_CPHA ? "" : "~",
802 spi->max_speed_hz);
803
804 BUG_ON(spi->chip_select >= MAX_CHIP_SELECT);
805
beb96c2a
LD		 806 /* Set speed to the spi max fequency if spi device has not set */
807 spi->max_speed_hz = spi->max_speed_hz ? : tspi->spi_max_frequency;
dc4dc360
LD		 808 ret = pm_runtime_get_sync(tspi->dev);
809 if (ret < 0) {
810 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
811 return ret;
812 }
813
814 spin_lock_irqsave(&tspi->lock, flags);
815 val = tspi->def_command_reg;
816 if (spi->mode & SPI_CS_HIGH)
817 val |= cs_pol_bit[spi->chip_select];
818 else
819 val &= ~cs_pol_bit[spi->chip_select];
820 tspi->def_command_reg = val;
821 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
822 spin_unlock_irqrestore(&tspi->lock, flags);
823
824 pm_runtime_put(tspi->dev);
825 return 0;
826}
827
dc4dc360
LD		 828static int tegra_slink_transfer_one_message(struct spi_master *master,
829 struct spi_message *msg)
830{
831 bool is_first_msg = true;
832 int single_xfer;
833 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
834 struct spi_transfer *xfer;
835 struct spi_device *spi = msg->spi;
836 int ret;
837
838 msg->status = 0;
839 msg->actual_length = 0;
d558c473
LD		 840 ret = pm_runtime_get_sync(tspi->dev);
841 if (ret < 0) {
842 dev_err(tspi->dev, "runtime get failed: %d\n", ret);
843 goto done;
844 }
845
dc4dc360
LD		 846 single_xfer = list_is_singular(&msg->transfers);
847 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
848 INIT_COMPLETION(tspi->xfer_completion);
849 ret = tegra_slink_start_transfer_one(spi, xfer,
850 is_first_msg, single_xfer);
851 if (ret < 0) {
852 dev_err(tspi->dev,
853 "spi can not start transfer, err %d\n", ret);
854 goto exit;
855 }
856 is_first_msg = false;
857 ret = wait_for_completion_timeout(&tspi->xfer_completion,
858 SLINK_DMA_TIMEOUT);
859 if (WARN_ON(ret == 0)) {
860 dev_err(tspi->dev,
861 "spi trasfer timeout, err %d\n", ret);
862 ret = -EIO;
863 goto exit;
864 }
865
866 if (tspi->tx_status || tspi->rx_status) {
867 dev_err(tspi->dev, "Error in Transfer\n");
868 ret = -EIO;
869 goto exit;
870 }
871 msg->actual_length += xfer->len;
872 if (xfer->cs_change && xfer->delay_usecs) {
873 tegra_slink_writel(tspi, tspi->def_command_reg,
874 SLINK_COMMAND);
875 udelay(xfer->delay_usecs);
876 }
877 }
878 ret = 0;
879exit:
880 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
881 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
d558c473
LD		 882 pm_runtime_put(tspi->dev);
883done:
dc4dc360
LD		 884 msg->status = ret;
885 spi_finalize_current_message(master);
886 return ret;
887}
888
889static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi)
890{
891 struct spi_transfer *t = tspi->curr_xfer;
892 unsigned long flags;
893
894 spin_lock_irqsave(&tspi->lock, flags);
895 if (tspi->tx_status || tspi->rx_status ||
896 (tspi->status_reg & SLINK_BSY)) {
897 dev_err(tspi->dev,
898 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg);
899 dev_err(tspi->dev,
900 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
901 tspi->command2_reg, tspi->dma_control_reg);
902 tegra_periph_reset_assert(tspi->clk);
903 udelay(2);
904 tegra_periph_reset_deassert(tspi->clk);
905 complete(&tspi->xfer_completion);
906 goto exit;
907 }
908
909 if (tspi->cur_direction & DATA_DIR_RX)
910 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t);
911
912 if (tspi->cur_direction & DATA_DIR_TX)
913 tspi->cur_pos = tspi->cur_tx_pos;
914 else
915 tspi->cur_pos = tspi->cur_rx_pos;
916
917 if (tspi->cur_pos == t->len) {
918 complete(&tspi->xfer_completion);
919 goto exit;
920 }
921
922 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
923 tegra_slink_start_cpu_based_transfer(tspi, t);
924exit:
925 spin_unlock_irqrestore(&tspi->lock, flags);
926 return IRQ_HANDLED;
927}
928
929static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi)
930{
931 struct spi_transfer *t = tspi->curr_xfer;
932 long wait_status;
933 int err = 0;
934 unsigned total_fifo_words;
935 unsigned long flags;
936
937 /* Abort dmas if any error */
938 if (tspi->cur_direction & DATA_DIR_TX) {
939 if (tspi->tx_status) {
940 dmaengine_terminate_all(tspi->tx_dma_chan);
941 err += 1;
942 } else {
943 wait_status = wait_for_completion_interruptible_timeout(
944 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT);
945 if (wait_status <= 0) {
946 dmaengine_terminate_all(tspi->tx_dma_chan);
947 dev_err(tspi->dev, "TxDma Xfer failed\n");
948 err += 1;
949 }
950 }
951 }
952
953 if (tspi->cur_direction & DATA_DIR_RX) {
954 if (tspi->rx_status) {
955 dmaengine_terminate_all(tspi->rx_dma_chan);
956 err += 2;
957 } else {
958 wait_status = wait_for_completion_interruptible_timeout(
959 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT);
960 if (wait_status <= 0) {
961 dmaengine_terminate_all(tspi->rx_dma_chan);
962 dev_err(tspi->dev, "RxDma Xfer failed\n");
963 err += 2;
964 }
965 }
966 }
967
968 spin_lock_irqsave(&tspi->lock, flags);
969 if (err) {
970 dev_err(tspi->dev,
971 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg);
972 dev_err(tspi->dev,
973 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg,
974 tspi->command2_reg, tspi->dma_control_reg);
975 tegra_periph_reset_assert(tspi->clk);
976 udelay(2);
977 tegra_periph_reset_deassert(tspi->clk);
978 complete(&tspi->xfer_completion);
979 spin_unlock_irqrestore(&tspi->lock, flags);
980 return IRQ_HANDLED;
981 }
982
983 if (tspi->cur_direction & DATA_DIR_RX)
984 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
985
986 if (tspi->cur_direction & DATA_DIR_TX)
987 tspi->cur_pos = tspi->cur_tx_pos;
988 else
989 tspi->cur_pos = tspi->cur_rx_pos;
990
991 if (tspi->cur_pos == t->len) {
992 complete(&tspi->xfer_completion);
993 goto exit;
994 }
995
996 /* Continue transfer in current message */
997 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi,
998 tspi, t);
999 if (total_fifo_words > SLINK_FIFO_DEPTH)
1000 err = tegra_slink_start_dma_based_transfer(tspi, t);
1001 else
1002 err = tegra_slink_start_cpu_based_transfer(tspi, t);
1003
1004exit:
1005 spin_unlock_irqrestore(&tspi->lock, flags);
1006 return IRQ_HANDLED;
1007}
1008
1009static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data)
1010{
1011 struct tegra_slink_data *tspi = context_data;
1012
1013 if (!tspi->is_curr_dma_xfer)
1014 return handle_cpu_based_xfer(tspi);
1015 return handle_dma_based_xfer(tspi);
1016}
1017
1018static irqreturn_t tegra_slink_isr(int irq, void *context_data)
1019{
1020 struct tegra_slink_data *tspi = context_data;
1021
1022 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS);
1023 if (tspi->cur_direction & DATA_DIR_TX)
1024 tspi->tx_status = tspi->status_reg &
1025 (SLINK_TX_OVF | SLINK_TX_UNF);
1026
1027 if (tspi->cur_direction & DATA_DIR_RX)
1028 tspi->rx_status = tspi->status_reg &
1029 (SLINK_RX_OVF | SLINK_RX_UNF);
1030 tegra_slink_clear_status(tspi);
1031
1032 return IRQ_WAKE_THREAD;
1033}
1034
1035static struct tegra_spi_platform_data *tegra_slink_parse_dt(
1036 struct platform_device *pdev)
1037{
1038 struct tegra_spi_platform_data *pdata;
1039 const unsigned int *prop;
1040 struct device_node *np = pdev->dev.of_node;
1041 u32 of_dma[2];
1042
1043 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1044 if (!pdata) {
1045 dev_err(&pdev->dev, "Memory alloc for pdata failed\n");
1046 return NULL;
1047 }
1048
1049 if (of_property_read_u32_array(np, "nvidia,dma-request-selector",
1050 of_dma, 2) >= 0)
1051 pdata->dma_req_sel = of_dma[1];
1052
1053 prop = of_get_property(np, "spi-max-frequency", NULL);
1054 if (prop)
1055 pdata->spi_max_frequency = be32_to_cpup(prop);
1056
1057 return pdata;
1058}
1059
1060const struct tegra_slink_chip_data tegra30_spi_cdata = {
1061 .cs_hold_time = true,
1062};
1063
1064const struct tegra_slink_chip_data tegra20_spi_cdata = {
1065 .cs_hold_time = false,
1066};
1067
fd4a319b 1068static struct of_device_id tegra_slink_of_match[] = {
dc4dc360 1069 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, },
24bc8971 1070 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, },
dc4dc360
LD		 1071 {}
1072};
1073MODULE_DEVICE_TABLE(of, tegra_slink_of_match);
1074
fd4a319b 1075static int tegra_slink_probe(struct platform_device *pdev)
dc4dc360
LD		 1076{
1077 struct spi_master *master;
1078 struct tegra_slink_data *tspi;
1079 struct resource *r;
1080 struct tegra_spi_platform_data *pdata = pdev->dev.platform_data;
1081 int ret, spi_irq;
1082 const struct tegra_slink_chip_data *cdata = NULL;
1083 const struct of_device_id *match;
1084
1085 match = of_match_device(of_match_ptr(tegra_slink_of_match), &pdev->dev);
1086 if (!match) {
1087 dev_err(&pdev->dev, "Error: No device match found\n");
1088 return -ENODEV;
1089 }
1090 cdata = match->data;
1091 if (!pdata && pdev->dev.of_node)
1092 pdata = tegra_slink_parse_dt(pdev);
1093
1094 if (!pdata) {
1095 dev_err(&pdev->dev, "No platform data, exiting\n");
1096 return -ENODEV;
1097 }
1098
1099 if (!pdata->spi_max_frequency)
1100 pdata->spi_max_frequency = 25000000; /* 25MHz */
1101
1102 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1103 if (!master) {
1104 dev_err(&pdev->dev, "master allocation failed\n");
1105 return -ENOMEM;
1106 }
1107
1108 /* the spi->mode bits understood by this driver: */
1109 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1110 master->setup = tegra_slink_setup;
dc4dc360 1111 master->transfer_one_message = tegra_slink_transfer_one_message;
dc4dc360
LD		 1112 master->num_chipselect = MAX_CHIP_SELECT;
1113 master->bus_num = -1;
1114
1115 dev_set_drvdata(&pdev->dev, master);
1116 tspi = spi_master_get_devdata(master);
1117 tspi->master = master;
1118 tspi->dma_req_sel = pdata->dma_req_sel;
1119 tspi->dev = &pdev->dev;
1120 tspi->chip_data = cdata;
1121 spin_lock_init(&tspi->lock);
1122
1123 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1124 if (!r) {
1125 dev_err(&pdev->dev, "No IO memory resource\n");
1126 ret = -ENODEV;
1127 goto exit_free_master;
1128 }
1129 tspi->phys = r->start;
b0ee5605
TR		 1130 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1131 if (IS_ERR(tspi->base)) {
1132 ret = PTR_ERR(tspi->base);
dc4dc360
LD		 1133 goto exit_free_master;
1134 }
1135
1136 spi_irq = platform_get_irq(pdev, 0);
1137 tspi->irq = spi_irq;
1138 ret = request_threaded_irq(tspi->irq, tegra_slink_isr,
1139 tegra_slink_isr_thread, IRQF_ONESHOT,
1140 dev_name(&pdev->dev), tspi);
1141 if (ret < 0) {
1142 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1143 tspi->irq);
1144 goto exit_free_master;
1145 }
1146
3cb91902 1147 tspi->clk = devm_clk_get(&pdev->dev, NULL);
dc4dc360
LD		 1148 if (IS_ERR(tspi->clk)) {
1149 dev_err(&pdev->dev, "can not get clock\n");
1150 ret = PTR_ERR(tspi->clk);
1151 goto exit_free_irq;
1152 }
1153
1154 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2;
1155 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1156 tspi->spi_max_frequency = pdata->spi_max_frequency;
1157
1158 if (pdata->dma_req_sel) {
1159 ret = tegra_slink_init_dma_param(tspi, true);
1160 if (ret < 0) {
1161 dev_err(&pdev->dev, "RxDma Init failed, err %d\n", ret);
1162 goto exit_free_irq;
1163 }
1164
1165 ret = tegra_slink_init_dma_param(tspi, false);
1166 if (ret < 0) {
1167 dev_err(&pdev->dev, "TxDma Init failed, err %d\n", ret);
1168 goto exit_rx_dma_free;
1169 }
1170 tspi->max_buf_size = tspi->dma_buf_size;
1171 init_completion(&tspi->tx_dma_complete);
1172 init_completion(&tspi->rx_dma_complete);
1173 }
1174
1175 init_completion(&tspi->xfer_completion);
1176
1177 pm_runtime_enable(&pdev->dev);
1178 if (!pm_runtime_enabled(&pdev->dev)) {
1179 ret = tegra_slink_runtime_resume(&pdev->dev);
1180 if (ret)
1181 goto exit_pm_disable;
1182 }
1183
1184 ret = pm_runtime_get_sync(&pdev->dev);
1185 if (ret < 0) {
1186 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1187 goto exit_pm_disable;
1188 }
1189 tspi->def_command_reg = SLINK_M_S;
1190 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN;
1191 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND);
1192 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2);
1193 pm_runtime_put(&pdev->dev);
1194
1195 master->dev.of_node = pdev->dev.of_node;
1196 ret = spi_register_master(master);
1197 if (ret < 0) {
1198 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1199 goto exit_pm_disable;
1200 }
1201 return ret;
1202
1203exit_pm_disable:
1204 pm_runtime_disable(&pdev->dev);
1205 if (!pm_runtime_status_suspended(&pdev->dev))
1206 tegra_slink_runtime_suspend(&pdev->dev);
1207 tegra_slink_deinit_dma_param(tspi, false);
1208exit_rx_dma_free:
1209 tegra_slink_deinit_dma_param(tspi, true);
1210exit_free_irq:
1211 free_irq(spi_irq, tspi);
1212exit_free_master:
1213 spi_master_put(master);
1214 return ret;
1215}
1216
fd4a319b 1217static int tegra_slink_remove(struct platform_device *pdev)
dc4dc360
LD		 1218{
1219 struct spi_master *master = dev_get_drvdata(&pdev->dev);
1220 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1221
1222 free_irq(tspi->irq, tspi);
1223 spi_unregister_master(master);
1224
1225 if (tspi->tx_dma_chan)
1226 tegra_slink_deinit_dma_param(tspi, false);
1227
1228 if (tspi->rx_dma_chan)
1229 tegra_slink_deinit_dma_param(tspi, true);
1230
1231 pm_runtime_disable(&pdev->dev);
1232 if (!pm_runtime_status_suspended(&pdev->dev))
1233 tegra_slink_runtime_suspend(&pdev->dev);
1234
1235 return 0;
1236}
1237
1238#ifdef CONFIG_PM_SLEEP
1239static int tegra_slink_suspend(struct device *dev)
1240{
1241 struct spi_master *master = dev_get_drvdata(dev);
1242
1243 return spi_master_suspend(master);
1244}
1245
1246static int tegra_slink_resume(struct device *dev)
1247{
1248 struct spi_master *master = dev_get_drvdata(dev);
1249 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1250 int ret;
1251
1252 ret = pm_runtime_get_sync(dev);
1253 if (ret < 0) {
1254 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1255 return ret;
1256 }
1257 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND);
1258 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2);
1259 pm_runtime_put(dev);
1260
1261 return spi_master_resume(master);
1262}
1263#endif
1264
1265static int tegra_slink_runtime_suspend(struct device *dev)
1266{
1267 struct spi_master *master = dev_get_drvdata(dev);
1268 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1269
1270 /* Flush all write which are in PPSB queue by reading back */
1271 tegra_slink_readl(tspi, SLINK_MAS_DATA);
1272
1273 clk_disable_unprepare(tspi->clk);
1274 return 0;
1275}
1276
1277static int tegra_slink_runtime_resume(struct device *dev)
1278{
1279 struct spi_master *master = dev_get_drvdata(dev);
1280 struct tegra_slink_data *tspi = spi_master_get_devdata(master);
1281 int ret;
1282
1283 ret = clk_prepare_enable(tspi->clk);
1284 if (ret < 0) {
1285 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1286 return ret;
1287 }
1288 return 0;
1289}
1290
1291static const struct dev_pm_ops slink_pm_ops = {
1292 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend,
1293 tegra_slink_runtime_resume, NULL)
1294 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume)
1295};
1296static struct platform_driver tegra_slink_driver = {
1297 .driver = {
1298 .name = "spi-tegra-slink",
1299 .owner = THIS_MODULE,
1300 .pm = &slink_pm_ops,
1301 .of_match_table = of_match_ptr(tegra_slink_of_match),
1302 },
1303 .probe = tegra_slink_probe,
fd4a319b 1304 .remove = tegra_slink_remove,
dc4dc360
LD		 1305};
1306module_platform_driver(tegra_slink_driver);
1307
1308MODULE_ALIAS("platform:spi-tegra-slink");
1309MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver");
1310MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1311MODULE_LICENSE("GPL v2");
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