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505a1495 SP |
1 | /* |
2 | * TI QSPI driver | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com | |
5 | * Author: Sourav Poddar <sourav.poddar@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GPLv2. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/dmaengine.h> | |
24 | #include <linux/omap-dma.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/clk.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/slab.h> | |
30 | #include <linux/pm_runtime.h> | |
31 | #include <linux/of.h> | |
32 | #include <linux/of_device.h> | |
33 | #include <linux/pinctrl/consumer.h> | |
34 | ||
35 | #include <linux/spi/spi.h> | |
36 | ||
37 | struct ti_qspi_regs { | |
38 | u32 clkctrl; | |
39 | }; | |
40 | ||
41 | struct ti_qspi { | |
42 | struct completion transfer_complete; | |
43 | ||
505a1495 SP |
44 | /* list synchronization */ |
45 | struct mutex list_lock; | |
46 | ||
47 | struct spi_master *master; | |
48 | void __iomem *base; | |
6b3938ae SP |
49 | void __iomem *ctrl_base; |
50 | void __iomem *mmap_base; | |
505a1495 SP |
51 | struct clk *fclk; |
52 | struct device *dev; | |
53 | ||
54 | struct ti_qspi_regs ctx_reg; | |
55 | ||
56 | u32 spi_max_frequency; | |
57 | u32 cmd; | |
58 | u32 dc; | |
6b3938ae SP |
59 | |
60 | bool ctrl_mod; | |
505a1495 SP |
61 | }; |
62 | ||
63 | #define QSPI_PID (0x0) | |
64 | #define QSPI_SYSCONFIG (0x10) | |
65 | #define QSPI_INTR_STATUS_RAW_SET (0x20) | |
66 | #define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24) | |
67 | #define QSPI_INTR_ENABLE_SET_REG (0x28) | |
68 | #define QSPI_INTR_ENABLE_CLEAR_REG (0x2c) | |
69 | #define QSPI_SPI_CLOCK_CNTRL_REG (0x40) | |
70 | #define QSPI_SPI_DC_REG (0x44) | |
71 | #define QSPI_SPI_CMD_REG (0x48) | |
72 | #define QSPI_SPI_STATUS_REG (0x4c) | |
73 | #define QSPI_SPI_DATA_REG (0x50) | |
74 | #define QSPI_SPI_SETUP0_REG (0x54) | |
75 | #define QSPI_SPI_SWITCH_REG (0x64) | |
76 | #define QSPI_SPI_SETUP1_REG (0x58) | |
77 | #define QSPI_SPI_SETUP2_REG (0x5c) | |
78 | #define QSPI_SPI_SETUP3_REG (0x60) | |
79 | #define QSPI_SPI_DATA_REG_1 (0x68) | |
80 | #define QSPI_SPI_DATA_REG_2 (0x6c) | |
81 | #define QSPI_SPI_DATA_REG_3 (0x70) | |
82 | ||
83 | #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000) | |
84 | ||
85 | #define QSPI_FCLK 192000000 | |
86 | ||
87 | /* Clock Control */ | |
88 | #define QSPI_CLK_EN (1 << 31) | |
89 | #define QSPI_CLK_DIV_MAX 0xffff | |
90 | ||
91 | /* Command */ | |
92 | #define QSPI_EN_CS(n) (n << 28) | |
93 | #define QSPI_WLEN(n) ((n - 1) << 19) | |
94 | #define QSPI_3_PIN (1 << 18) | |
95 | #define QSPI_RD_SNGL (1 << 16) | |
96 | #define QSPI_WR_SNGL (2 << 16) | |
97 | #define QSPI_RD_DUAL (3 << 16) | |
98 | #define QSPI_RD_QUAD (7 << 16) | |
99 | #define QSPI_INVAL (4 << 16) | |
100 | #define QSPI_WC_CMD_INT_EN (1 << 14) | |
101 | #define QSPI_FLEN(n) ((n - 1) << 0) | |
102 | ||
103 | /* STATUS REGISTER */ | |
104 | #define WC 0x02 | |
105 | ||
106 | /* INTERRUPT REGISTER */ | |
107 | #define QSPI_WC_INT_EN (1 << 1) | |
108 | #define QSPI_WC_INT_DISABLE (1 << 1) | |
109 | ||
110 | /* Device Control */ | |
111 | #define QSPI_DD(m, n) (m << (3 + n * 8)) | |
112 | #define QSPI_CKPHA(n) (1 << (2 + n * 8)) | |
113 | #define QSPI_CSPOL(n) (1 << (1 + n * 8)) | |
114 | #define QSPI_CKPOL(n) (1 << (n * 8)) | |
115 | ||
116 | #define QSPI_FRAME 4096 | |
117 | ||
118 | #define QSPI_AUTOSUSPEND_TIMEOUT 2000 | |
119 | ||
120 | static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, | |
121 | unsigned long reg) | |
122 | { | |
123 | return readl(qspi->base + reg); | |
124 | } | |
125 | ||
126 | static inline void ti_qspi_write(struct ti_qspi *qspi, | |
127 | unsigned long val, unsigned long reg) | |
128 | { | |
129 | writel(val, qspi->base + reg); | |
130 | } | |
131 | ||
132 | static int ti_qspi_setup(struct spi_device *spi) | |
133 | { | |
134 | struct ti_qspi *qspi = spi_master_get_devdata(spi->master); | |
135 | struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; | |
136 | int clk_div = 0, ret; | |
137 | u32 clk_ctrl_reg, clk_rate, clk_mask; | |
138 | ||
139 | if (spi->master->busy) { | |
140 | dev_dbg(qspi->dev, "master busy doing other trasnfers\n"); | |
141 | return -EBUSY; | |
142 | } | |
143 | ||
144 | if (!qspi->spi_max_frequency) { | |
145 | dev_err(qspi->dev, "spi max frequency not defined\n"); | |
146 | return -EINVAL; | |
147 | } | |
148 | ||
149 | clk_rate = clk_get_rate(qspi->fclk); | |
150 | ||
151 | clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1; | |
152 | ||
153 | if (clk_div < 0) { | |
154 | dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n"); | |
155 | return -EINVAL; | |
156 | } | |
157 | ||
158 | if (clk_div > QSPI_CLK_DIV_MAX) { | |
159 | dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n", | |
160 | QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); | |
161 | return -EINVAL; | |
162 | } | |
163 | ||
164 | dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", | |
165 | qspi->spi_max_frequency, clk_div); | |
166 | ||
167 | ret = pm_runtime_get_sync(qspi->dev); | |
05b96675 | 168 | if (ret < 0) { |
505a1495 SP |
169 | dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); |
170 | return ret; | |
171 | } | |
172 | ||
173 | clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); | |
174 | ||
175 | clk_ctrl_reg &= ~QSPI_CLK_EN; | |
176 | ||
177 | /* disable SCLK */ | |
178 | ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); | |
179 | ||
180 | /* enable SCLK */ | |
181 | clk_mask = QSPI_CLK_EN | clk_div; | |
182 | ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); | |
183 | ctx_reg->clkctrl = clk_mask; | |
184 | ||
185 | pm_runtime_mark_last_busy(qspi->dev); | |
186 | ret = pm_runtime_put_autosuspend(qspi->dev); | |
187 | if (ret < 0) { | |
188 | dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); | |
189 | return ret; | |
190 | } | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
195 | static void ti_qspi_restore_ctx(struct ti_qspi *qspi) | |
196 | { | |
197 | struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; | |
198 | ||
199 | ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); | |
200 | } | |
201 | ||
202 | static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) | |
203 | { | |
204 | int wlen, count, ret; | |
205 | unsigned int cmd; | |
206 | const u8 *txbuf; | |
207 | ||
208 | txbuf = t->tx_buf; | |
209 | cmd = qspi->cmd | QSPI_WR_SNGL; | |
210 | count = t->len; | |
3ab54620 | 211 | wlen = t->bits_per_word >> 3; /* in bytes */ |
505a1495 SP |
212 | |
213 | while (count) { | |
214 | switch (wlen) { | |
3ab54620 | 215 | case 1: |
505a1495 SP |
216 | dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", |
217 | cmd, qspi->dc, *txbuf); | |
218 | writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); | |
505a1495 | 219 | break; |
3ab54620 | 220 | case 2: |
505a1495 SP |
221 | dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", |
222 | cmd, qspi->dc, *txbuf); | |
223 | writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); | |
505a1495 | 224 | break; |
3ab54620 | 225 | case 4: |
505a1495 SP |
226 | dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", |
227 | cmd, qspi->dc, *txbuf); | |
228 | writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); | |
505a1495 SP |
229 | break; |
230 | } | |
3ab54620 AL |
231 | |
232 | ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); | |
233 | ret = wait_for_completion_timeout(&qspi->transfer_complete, | |
234 | QSPI_COMPLETION_TIMEOUT); | |
235 | if (ret == 0) { | |
236 | dev_err(qspi->dev, "write timed out\n"); | |
237 | return -ETIMEDOUT; | |
238 | } | |
239 | txbuf += wlen; | |
240 | count -= wlen; | |
505a1495 SP |
241 | } |
242 | ||
243 | return 0; | |
244 | } | |
245 | ||
246 | static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) | |
247 | { | |
248 | int wlen, count, ret; | |
249 | unsigned int cmd; | |
250 | u8 *rxbuf; | |
251 | ||
252 | rxbuf = t->rx_buf; | |
70e2e976 SP |
253 | cmd = qspi->cmd; |
254 | switch (t->rx_nbits) { | |
255 | case SPI_NBITS_DUAL: | |
256 | cmd |= QSPI_RD_DUAL; | |
257 | break; | |
258 | case SPI_NBITS_QUAD: | |
259 | cmd |= QSPI_RD_QUAD; | |
260 | break; | |
261 | default: | |
262 | cmd |= QSPI_RD_SNGL; | |
263 | break; | |
264 | } | |
505a1495 | 265 | count = t->len; |
3ab54620 | 266 | wlen = t->bits_per_word >> 3; /* in bytes */ |
505a1495 SP |
267 | |
268 | while (count) { | |
269 | dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); | |
270 | ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); | |
271 | ret = wait_for_completion_timeout(&qspi->transfer_complete, | |
272 | QSPI_COMPLETION_TIMEOUT); | |
273 | if (ret == 0) { | |
274 | dev_err(qspi->dev, "read timed out\n"); | |
275 | return -ETIMEDOUT; | |
276 | } | |
277 | switch (wlen) { | |
3ab54620 | 278 | case 1: |
505a1495 | 279 | *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG); |
505a1495 | 280 | break; |
3ab54620 | 281 | case 2: |
505a1495 | 282 | *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); |
505a1495 | 283 | break; |
3ab54620 | 284 | case 4: |
505a1495 | 285 | *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); |
505a1495 SP |
286 | break; |
287 | } | |
3ab54620 AL |
288 | rxbuf += wlen; |
289 | count -= wlen; | |
505a1495 SP |
290 | } |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
295 | static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t) | |
296 | { | |
297 | int ret; | |
298 | ||
299 | if (t->tx_buf) { | |
300 | ret = qspi_write_msg(qspi, t); | |
301 | if (ret) { | |
302 | dev_dbg(qspi->dev, "Error while writing\n"); | |
303 | return ret; | |
304 | } | |
305 | } | |
306 | ||
307 | if (t->rx_buf) { | |
308 | ret = qspi_read_msg(qspi, t); | |
309 | if (ret) { | |
310 | dev_dbg(qspi->dev, "Error while reading\n"); | |
311 | return ret; | |
312 | } | |
313 | } | |
314 | ||
315 | return 0; | |
316 | } | |
317 | ||
318 | static int ti_qspi_start_transfer_one(struct spi_master *master, | |
319 | struct spi_message *m) | |
320 | { | |
321 | struct ti_qspi *qspi = spi_master_get_devdata(master); | |
322 | struct spi_device *spi = m->spi; | |
323 | struct spi_transfer *t; | |
324 | int status = 0, ret; | |
325 | int frame_length; | |
326 | ||
327 | /* setup device control reg */ | |
328 | qspi->dc = 0; | |
329 | ||
330 | if (spi->mode & SPI_CPHA) | |
331 | qspi->dc |= QSPI_CKPHA(spi->chip_select); | |
332 | if (spi->mode & SPI_CPOL) | |
333 | qspi->dc |= QSPI_CKPOL(spi->chip_select); | |
334 | if (spi->mode & SPI_CS_HIGH) | |
335 | qspi->dc |= QSPI_CSPOL(spi->chip_select); | |
336 | ||
337 | frame_length = (m->frame_length << 3) / spi->bits_per_word; | |
338 | ||
339 | frame_length = clamp(frame_length, 0, QSPI_FRAME); | |
340 | ||
341 | /* setup command reg */ | |
342 | qspi->cmd = 0; | |
343 | qspi->cmd |= QSPI_EN_CS(spi->chip_select); | |
344 | qspi->cmd |= QSPI_FLEN(frame_length); | |
345 | qspi->cmd |= QSPI_WC_CMD_INT_EN; | |
346 | ||
347 | ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG); | |
348 | ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); | |
349 | ||
350 | mutex_lock(&qspi->list_lock); | |
351 | ||
352 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
353 | qspi->cmd |= QSPI_WLEN(t->bits_per_word); | |
354 | ||
355 | ret = qspi_transfer_msg(qspi, t); | |
356 | if (ret) { | |
357 | dev_dbg(qspi->dev, "transfer message failed\n"); | |
b6460366 | 358 | mutex_unlock(&qspi->list_lock); |
505a1495 SP |
359 | return -EINVAL; |
360 | } | |
361 | ||
362 | m->actual_length += t->len; | |
363 | } | |
364 | ||
365 | mutex_unlock(&qspi->list_lock); | |
366 | ||
367 | m->status = status; | |
368 | spi_finalize_current_message(master); | |
369 | ||
370 | ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); | |
371 | ||
372 | return status; | |
373 | } | |
374 | ||
375 | static irqreturn_t ti_qspi_isr(int irq, void *dev_id) | |
376 | { | |
377 | struct ti_qspi *qspi = dev_id; | |
378 | u16 int_stat; | |
3b3a8001 | 379 | u32 stat; |
505a1495 SP |
380 | |
381 | irqreturn_t ret = IRQ_HANDLED; | |
382 | ||
505a1495 | 383 | int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR); |
3b3a8001 | 384 | stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); |
505a1495 SP |
385 | |
386 | if (!int_stat) { | |
387 | dev_dbg(qspi->dev, "No IRQ triggered\n"); | |
388 | ret = IRQ_NONE; | |
389 | goto out; | |
390 | } | |
391 | ||
505a1495 SP |
392 | ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, |
393 | QSPI_INTR_STATUS_ENABLED_CLEAR); | |
3b3a8001 SAS |
394 | if (stat & WC) |
395 | complete(&qspi->transfer_complete); | |
505a1495 | 396 | out: |
505a1495 SP |
397 | return ret; |
398 | } | |
399 | ||
505a1495 SP |
400 | static int ti_qspi_runtime_resume(struct device *dev) |
401 | { | |
402 | struct ti_qspi *qspi; | |
505a1495 | 403 | |
f17414c4 | 404 | qspi = dev_get_drvdata(dev); |
505a1495 SP |
405 | ti_qspi_restore_ctx(qspi); |
406 | ||
407 | return 0; | |
408 | } | |
409 | ||
410 | static const struct of_device_id ti_qspi_match[] = { | |
411 | {.compatible = "ti,dra7xxx-qspi" }, | |
09222fc3 | 412 | {.compatible = "ti,am4372-qspi" }, |
505a1495 SP |
413 | {}, |
414 | }; | |
e1432d30 | 415 | MODULE_DEVICE_TABLE(of, ti_qspi_match); |
505a1495 SP |
416 | |
417 | static int ti_qspi_probe(struct platform_device *pdev) | |
418 | { | |
419 | struct ti_qspi *qspi; | |
420 | struct spi_master *master; | |
6b3938ae | 421 | struct resource *r, *res_ctrl, *res_mmap; |
505a1495 SP |
422 | struct device_node *np = pdev->dev.of_node; |
423 | u32 max_freq; | |
424 | int ret = 0, num_cs, irq; | |
425 | ||
426 | master = spi_alloc_master(&pdev->dev, sizeof(*qspi)); | |
427 | if (!master) | |
428 | return -ENOMEM; | |
429 | ||
633795b9 | 430 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; |
505a1495 | 431 | |
505a1495 SP |
432 | master->flags = SPI_MASTER_HALF_DUPLEX; |
433 | master->setup = ti_qspi_setup; | |
434 | master->auto_runtime_pm = true; | |
435 | master->transfer_one_message = ti_qspi_start_transfer_one; | |
436 | master->dev.of_node = pdev->dev.of_node; | |
aa188f90 AL |
437 | master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | |
438 | SPI_BPW_MASK(8); | |
505a1495 SP |
439 | |
440 | if (!of_property_read_u32(np, "num-cs", &num_cs)) | |
441 | master->num_chipselect = num_cs; | |
442 | ||
505a1495 SP |
443 | qspi = spi_master_get_devdata(master); |
444 | qspi->master = master; | |
445 | qspi->dev = &pdev->dev; | |
160a0613 | 446 | platform_set_drvdata(pdev, qspi); |
505a1495 | 447 | |
6b3938ae SP |
448 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); |
449 | if (r == NULL) { | |
450 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
451 | if (r == NULL) { | |
452 | dev_err(&pdev->dev, "missing platform data\n"); | |
453 | return -ENODEV; | |
454 | } | |
455 | } | |
505a1495 | 456 | |
6b3938ae SP |
457 | res_mmap = platform_get_resource_byname(pdev, |
458 | IORESOURCE_MEM, "qspi_mmap"); | |
459 | if (res_mmap == NULL) { | |
460 | res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
461 | if (res_mmap == NULL) { | |
462 | dev_err(&pdev->dev, | |
463 | "memory mapped resource not required\n"); | |
464 | return -ENODEV; | |
465 | } | |
466 | } | |
467 | ||
468 | res_ctrl = platform_get_resource_byname(pdev, | |
469 | IORESOURCE_MEM, "qspi_ctrlmod"); | |
470 | if (res_ctrl == NULL) { | |
471 | res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2); | |
472 | if (res_ctrl == NULL) { | |
473 | dev_dbg(&pdev->dev, | |
474 | "control module resources not required\n"); | |
475 | } | |
476 | } | |
505a1495 SP |
477 | |
478 | irq = platform_get_irq(pdev, 0); | |
479 | if (irq < 0) { | |
480 | dev_err(&pdev->dev, "no irq resource?\n"); | |
481 | return irq; | |
482 | } | |
483 | ||
505a1495 SP |
484 | mutex_init(&qspi->list_lock); |
485 | ||
486 | qspi->base = devm_ioremap_resource(&pdev->dev, r); | |
487 | if (IS_ERR(qspi->base)) { | |
488 | ret = PTR_ERR(qspi->base); | |
489 | goto free_master; | |
490 | } | |
491 | ||
6b3938ae SP |
492 | if (res_ctrl) { |
493 | qspi->ctrl_mod = true; | |
494 | qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl); | |
495 | if (IS_ERR(qspi->ctrl_base)) { | |
496 | ret = PTR_ERR(qspi->ctrl_base); | |
497 | goto free_master; | |
498 | } | |
499 | } | |
500 | ||
501 | if (res_mmap) { | |
502 | qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap); | |
503 | if (IS_ERR(qspi->mmap_base)) { | |
504 | ret = PTR_ERR(qspi->mmap_base); | |
505 | goto free_master; | |
506 | } | |
507 | } | |
508 | ||
3b3a8001 | 509 | ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0, |
505a1495 SP |
510 | dev_name(&pdev->dev), qspi); |
511 | if (ret < 0) { | |
512 | dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", | |
513 | irq); | |
514 | goto free_master; | |
515 | } | |
516 | ||
517 | qspi->fclk = devm_clk_get(&pdev->dev, "fck"); | |
518 | if (IS_ERR(qspi->fclk)) { | |
519 | ret = PTR_ERR(qspi->fclk); | |
520 | dev_err(&pdev->dev, "could not get clk: %d\n", ret); | |
521 | } | |
522 | ||
523 | init_completion(&qspi->transfer_complete); | |
524 | ||
525 | pm_runtime_use_autosuspend(&pdev->dev); | |
526 | pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT); | |
527 | pm_runtime_enable(&pdev->dev); | |
528 | ||
529 | if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) | |
530 | qspi->spi_max_frequency = max_freq; | |
531 | ||
7388c03b | 532 | ret = devm_spi_register_master(&pdev->dev, master); |
505a1495 SP |
533 | if (ret) |
534 | goto free_master; | |
535 | ||
536 | return 0; | |
537 | ||
538 | free_master: | |
539 | spi_master_put(master); | |
540 | return ret; | |
541 | } | |
542 | ||
543 | static int ti_qspi_remove(struct platform_device *pdev) | |
544 | { | |
e3d8bee3 | 545 | struct ti_qspi *qspi = platform_get_drvdata(pdev); |
cbcabb7a SP |
546 | int ret; |
547 | ||
cbcabb7a SP |
548 | ret = pm_runtime_get_sync(qspi->dev); |
549 | if (ret < 0) { | |
550 | dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); | |
551 | return ret; | |
552 | } | |
505a1495 | 553 | |
3b3a8001 | 554 | ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG); |
505a1495 | 555 | |
cbcabb7a SP |
556 | pm_runtime_put(qspi->dev); |
557 | pm_runtime_disable(&pdev->dev); | |
558 | ||
505a1495 SP |
559 | return 0; |
560 | } | |
561 | ||
562 | static const struct dev_pm_ops ti_qspi_pm_ops = { | |
563 | .runtime_resume = ti_qspi_runtime_resume, | |
564 | }; | |
565 | ||
566 | static struct platform_driver ti_qspi_driver = { | |
567 | .probe = ti_qspi_probe, | |
dabefd56 | 568 | .remove = ti_qspi_remove, |
505a1495 | 569 | .driver = { |
5a33d30f | 570 | .name = "ti-qspi", |
505a1495 SP |
571 | .owner = THIS_MODULE, |
572 | .pm = &ti_qspi_pm_ops, | |
573 | .of_match_table = ti_qspi_match, | |
574 | } | |
575 | }; | |
576 | ||
577 | module_platform_driver(ti_qspi_driver); | |
578 | ||
579 | MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>"); | |
580 | MODULE_LICENSE("GPL v2"); | |
581 | MODULE_DESCRIPTION("TI QSPI controller driver"); | |
5a33d30f | 582 | MODULE_ALIAS("platform:ti-qspi"); |