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1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // spi-uniphier.c - Socionext UniPhier SPI controller driver | |
3 | // Copyright 2012 Panasonic Corporation | |
4 | // Copyright 2016-2018 Socionext Inc. | |
5 | ||
6 | #include <linux/kernel.h> | |
7 | #include <linux/bitfield.h> | |
8 | #include <linux/bitops.h> | |
9 | #include <linux/clk.h> | |
10 | #include <linux/interrupt.h> | |
11 | #include <linux/io.h> | |
12 | #include <linux/module.h> | |
5ba155a4 KH |
13 | #include <linux/platform_device.h> |
14 | #include <linux/spi/spi.h> | |
15 | ||
16 | #include <asm/unaligned.h> | |
17 | ||
18 | #define SSI_TIMEOUT_MS 2000 | |
19 | #define SSI_MAX_CLK_DIVIDER 254 | |
20 | #define SSI_MIN_CLK_DIVIDER 4 | |
21 | ||
22 | struct uniphier_spi_priv { | |
23 | void __iomem *base; | |
24 | struct clk *clk; | |
25 | struct spi_master *master; | |
26 | struct completion xfer_done; | |
27 | ||
28 | int error; | |
29 | unsigned int tx_bytes; | |
30 | unsigned int rx_bytes; | |
31 | const u8 *tx_buf; | |
32 | u8 *rx_buf; | |
33 | ||
34 | bool is_save_param; | |
35 | u8 bits_per_word; | |
36 | u16 mode; | |
37 | u32 speed_hz; | |
38 | }; | |
39 | ||
40 | #define SSI_CTL 0x00 | |
41 | #define SSI_CTL_EN BIT(0) | |
42 | ||
43 | #define SSI_CKS 0x04 | |
44 | #define SSI_CKS_CKRAT_MASK GENMASK(7, 0) | |
45 | #define SSI_CKS_CKPHS BIT(14) | |
46 | #define SSI_CKS_CKINIT BIT(13) | |
47 | #define SSI_CKS_CKDLY BIT(12) | |
48 | ||
49 | #define SSI_TXWDS 0x08 | |
50 | #define SSI_TXWDS_WDLEN_MASK GENMASK(13, 8) | |
51 | #define SSI_TXWDS_TDTF_MASK GENMASK(7, 6) | |
52 | #define SSI_TXWDS_DTLEN_MASK GENMASK(5, 0) | |
53 | ||
54 | #define SSI_RXWDS 0x0c | |
55 | #define SSI_RXWDS_DTLEN_MASK GENMASK(5, 0) | |
56 | ||
57 | #define SSI_FPS 0x10 | |
58 | #define SSI_FPS_FSPOL BIT(15) | |
59 | #define SSI_FPS_FSTRT BIT(14) | |
60 | ||
61 | #define SSI_SR 0x14 | |
62 | #define SSI_SR_RNE BIT(0) | |
63 | ||
64 | #define SSI_IE 0x18 | |
65 | #define SSI_IE_RCIE BIT(3) | |
66 | #define SSI_IE_RORIE BIT(0) | |
67 | ||
68 | #define SSI_IS 0x1c | |
69 | #define SSI_IS_RXRS BIT(9) | |
70 | #define SSI_IS_RCID BIT(3) | |
71 | #define SSI_IS_RORID BIT(0) | |
72 | ||
73 | #define SSI_IC 0x1c | |
74 | #define SSI_IC_TCIC BIT(4) | |
75 | #define SSI_IC_RCIC BIT(3) | |
76 | #define SSI_IC_RORIC BIT(0) | |
77 | ||
78 | #define SSI_FC 0x20 | |
79 | #define SSI_FC_TXFFL BIT(12) | |
80 | #define SSI_FC_TXFTH_MASK GENMASK(11, 8) | |
81 | #define SSI_FC_RXFFL BIT(4) | |
82 | #define SSI_FC_RXFTH_MASK GENMASK(3, 0) | |
83 | ||
84 | #define SSI_TXDR 0x24 | |
85 | #define SSI_RXDR 0x24 | |
86 | ||
87 | #define SSI_FIFO_DEPTH 8U | |
88 | ||
89 | static inline unsigned int bytes_per_word(unsigned int bits) | |
90 | { | |
91 | return bits <= 8 ? 1 : (bits <= 16 ? 2 : 4); | |
92 | } | |
93 | ||
94 | static inline void uniphier_spi_irq_enable(struct spi_device *spi, u32 mask) | |
95 | { | |
96 | struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); | |
97 | u32 val; | |
98 | ||
99 | val = readl(priv->base + SSI_IE); | |
100 | val |= mask; | |
101 | writel(val, priv->base + SSI_IE); | |
102 | } | |
103 | ||
104 | static inline void uniphier_spi_irq_disable(struct spi_device *spi, u32 mask) | |
105 | { | |
106 | struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); | |
107 | u32 val; | |
108 | ||
109 | val = readl(priv->base + SSI_IE); | |
110 | val &= ~mask; | |
111 | writel(val, priv->base + SSI_IE); | |
112 | } | |
113 | ||
114 | static void uniphier_spi_set_mode(struct spi_device *spi) | |
115 | { | |
116 | struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); | |
117 | u32 val1, val2; | |
118 | ||
119 | /* | |
120 | * clock setting | |
121 | * CKPHS capture timing. 0:rising edge, 1:falling edge | |
122 | * CKINIT clock initial level. 0:low, 1:high | |
123 | * CKDLY clock delay. 0:no delay, 1:delay depending on FSTRT | |
124 | * (FSTRT=0: 1 clock, FSTRT=1: 0.5 clock) | |
125 | * | |
126 | * frame setting | |
127 | * FSPOL frame signal porarity. 0: low, 1: high | |
128 | * FSTRT start frame timing | |
129 | * 0: rising edge of clock, 1: falling edge of clock | |
130 | */ | |
131 | switch (spi->mode & (SPI_CPOL | SPI_CPHA)) { | |
132 | case SPI_MODE_0: | |
133 | /* CKPHS=1, CKINIT=0, CKDLY=1, FSTRT=0 */ | |
134 | val1 = SSI_CKS_CKPHS | SSI_CKS_CKDLY; | |
135 | val2 = 0; | |
136 | break; | |
137 | case SPI_MODE_1: | |
138 | /* CKPHS=0, CKINIT=0, CKDLY=0, FSTRT=1 */ | |
139 | val1 = 0; | |
140 | val2 = SSI_FPS_FSTRT; | |
141 | break; | |
142 | case SPI_MODE_2: | |
143 | /* CKPHS=0, CKINIT=1, CKDLY=1, FSTRT=1 */ | |
144 | val1 = SSI_CKS_CKINIT | SSI_CKS_CKDLY; | |
145 | val2 = SSI_FPS_FSTRT; | |
146 | break; | |
147 | case SPI_MODE_3: | |
148 | /* CKPHS=1, CKINIT=1, CKDLY=0, FSTRT=0 */ | |
149 | val1 = SSI_CKS_CKPHS | SSI_CKS_CKINIT; | |
150 | val2 = 0; | |
151 | break; | |
152 | } | |
153 | ||
154 | if (!(spi->mode & SPI_CS_HIGH)) | |
155 | val2 |= SSI_FPS_FSPOL; | |
156 | ||
157 | writel(val1, priv->base + SSI_CKS); | |
158 | writel(val2, priv->base + SSI_FPS); | |
159 | ||
160 | val1 = 0; | |
161 | if (spi->mode & SPI_LSB_FIRST) | |
162 | val1 |= FIELD_PREP(SSI_TXWDS_TDTF_MASK, 1); | |
163 | writel(val1, priv->base + SSI_TXWDS); | |
164 | writel(val1, priv->base + SSI_RXWDS); | |
165 | } | |
166 | ||
167 | static void uniphier_spi_set_transfer_size(struct spi_device *spi, int size) | |
168 | { | |
169 | struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); | |
170 | u32 val; | |
171 | ||
172 | val = readl(priv->base + SSI_TXWDS); | |
173 | val &= ~(SSI_TXWDS_WDLEN_MASK | SSI_TXWDS_DTLEN_MASK); | |
174 | val |= FIELD_PREP(SSI_TXWDS_WDLEN_MASK, size); | |
175 | val |= FIELD_PREP(SSI_TXWDS_DTLEN_MASK, size); | |
176 | writel(val, priv->base + SSI_TXWDS); | |
177 | ||
178 | val = readl(priv->base + SSI_RXWDS); | |
179 | val &= ~SSI_RXWDS_DTLEN_MASK; | |
180 | val |= FIELD_PREP(SSI_RXWDS_DTLEN_MASK, size); | |
181 | writel(val, priv->base + SSI_RXWDS); | |
182 | } | |
183 | ||
184 | static void uniphier_spi_set_baudrate(struct spi_device *spi, | |
185 | unsigned int speed) | |
186 | { | |
187 | struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); | |
188 | u32 val, ckdiv; | |
189 | ||
190 | /* | |
191 | * the supported rates are even numbers from 4 to 254. (4,6,8...254) | |
192 | * round up as we look for equal or less speed | |
193 | */ | |
194 | ckdiv = DIV_ROUND_UP(clk_get_rate(priv->clk), speed); | |
195 | ckdiv = round_up(ckdiv, 2); | |
196 | ||
197 | val = readl(priv->base + SSI_CKS); | |
198 | val &= ~SSI_CKS_CKRAT_MASK; | |
199 | val |= ckdiv & SSI_CKS_CKRAT_MASK; | |
200 | writel(val, priv->base + SSI_CKS); | |
201 | } | |
202 | ||
203 | static void uniphier_spi_setup_transfer(struct spi_device *spi, | |
204 | struct spi_transfer *t) | |
205 | { | |
206 | struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); | |
207 | u32 val; | |
208 | ||
209 | priv->error = 0; | |
210 | priv->tx_buf = t->tx_buf; | |
211 | priv->rx_buf = t->rx_buf; | |
212 | priv->tx_bytes = priv->rx_bytes = t->len; | |
213 | ||
214 | if (!priv->is_save_param || priv->mode != spi->mode) { | |
215 | uniphier_spi_set_mode(spi); | |
216 | priv->mode = spi->mode; | |
217 | } | |
218 | ||
219 | if (!priv->is_save_param || priv->bits_per_word != t->bits_per_word) { | |
220 | uniphier_spi_set_transfer_size(spi, t->bits_per_word); | |
221 | priv->bits_per_word = t->bits_per_word; | |
222 | } | |
223 | ||
224 | if (!priv->is_save_param || priv->speed_hz != t->speed_hz) { | |
225 | uniphier_spi_set_baudrate(spi, t->speed_hz); | |
226 | priv->speed_hz = t->speed_hz; | |
227 | } | |
228 | ||
229 | if (!priv->is_save_param) | |
230 | priv->is_save_param = true; | |
231 | ||
232 | /* reset FIFOs */ | |
233 | val = SSI_FC_TXFFL | SSI_FC_RXFFL; | |
234 | writel(val, priv->base + SSI_FC); | |
235 | } | |
236 | ||
237 | static void uniphier_spi_send(struct uniphier_spi_priv *priv) | |
238 | { | |
239 | int wsize; | |
240 | u32 val = 0; | |
241 | ||
242 | wsize = min(bytes_per_word(priv->bits_per_word), priv->tx_bytes); | |
243 | priv->tx_bytes -= wsize; | |
244 | ||
245 | if (priv->tx_buf) { | |
246 | switch (wsize) { | |
247 | case 1: | |
248 | val = *priv->tx_buf; | |
249 | break; | |
250 | case 2: | |
251 | val = get_unaligned_le16(priv->tx_buf); | |
252 | break; | |
253 | case 4: | |
254 | val = get_unaligned_le32(priv->tx_buf); | |
255 | break; | |
256 | } | |
257 | ||
258 | priv->tx_buf += wsize; | |
259 | } | |
260 | ||
261 | writel(val, priv->base + SSI_TXDR); | |
262 | } | |
263 | ||
264 | static void uniphier_spi_recv(struct uniphier_spi_priv *priv) | |
265 | { | |
266 | int rsize; | |
267 | u32 val; | |
268 | ||
269 | rsize = min(bytes_per_word(priv->bits_per_word), priv->rx_bytes); | |
270 | priv->rx_bytes -= rsize; | |
271 | ||
272 | val = readl(priv->base + SSI_RXDR); | |
273 | ||
274 | if (priv->rx_buf) { | |
275 | switch (rsize) { | |
276 | case 1: | |
277 | *priv->rx_buf = val; | |
278 | break; | |
279 | case 2: | |
280 | put_unaligned_le16(val, priv->rx_buf); | |
281 | break; | |
282 | case 4: | |
283 | put_unaligned_le32(val, priv->rx_buf); | |
284 | break; | |
285 | } | |
286 | ||
287 | priv->rx_buf += rsize; | |
288 | } | |
289 | } | |
290 | ||
291 | static void uniphier_spi_fill_tx_fifo(struct uniphier_spi_priv *priv) | |
292 | { | |
293 | unsigned int tx_count; | |
294 | u32 val; | |
295 | ||
296 | tx_count = DIV_ROUND_UP(priv->tx_bytes, | |
297 | bytes_per_word(priv->bits_per_word)); | |
298 | tx_count = min(tx_count, SSI_FIFO_DEPTH); | |
299 | ||
300 | /* set fifo threshold */ | |
301 | val = readl(priv->base + SSI_FC); | |
302 | val &= ~(SSI_FC_TXFTH_MASK | SSI_FC_RXFTH_MASK); | |
303 | val |= FIELD_PREP(SSI_FC_TXFTH_MASK, tx_count); | |
304 | val |= FIELD_PREP(SSI_FC_RXFTH_MASK, tx_count); | |
305 | writel(val, priv->base + SSI_FC); | |
306 | ||
307 | while (tx_count--) | |
308 | uniphier_spi_send(priv); | |
309 | } | |
310 | ||
311 | static void uniphier_spi_set_cs(struct spi_device *spi, bool enable) | |
312 | { | |
313 | struct uniphier_spi_priv *priv = spi_master_get_devdata(spi->master); | |
314 | u32 val; | |
315 | ||
316 | val = readl(priv->base + SSI_FPS); | |
317 | ||
318 | if (enable) | |
319 | val |= SSI_FPS_FSPOL; | |
320 | else | |
321 | val &= ~SSI_FPS_FSPOL; | |
322 | ||
323 | writel(val, priv->base + SSI_FPS); | |
324 | } | |
325 | ||
326 | static int uniphier_spi_transfer_one(struct spi_master *master, | |
327 | struct spi_device *spi, | |
328 | struct spi_transfer *t) | |
329 | { | |
330 | struct uniphier_spi_priv *priv = spi_master_get_devdata(master); | |
e4671df0 KH |
331 | struct device *dev = master->dev.parent; |
332 | unsigned long time_left; | |
5ba155a4 | 333 | |
2b947137 KH |
334 | /* Terminate and return success for 0 byte length transfer */ |
335 | if (!t->len) | |
336 | return 0; | |
337 | ||
5ba155a4 KH |
338 | uniphier_spi_setup_transfer(spi, t); |
339 | ||
340 | reinit_completion(&priv->xfer_done); | |
341 | ||
342 | uniphier_spi_fill_tx_fifo(priv); | |
343 | ||
344 | uniphier_spi_irq_enable(spi, SSI_IE_RCIE | SSI_IE_RORIE); | |
345 | ||
e4671df0 KH |
346 | time_left = wait_for_completion_timeout(&priv->xfer_done, |
347 | msecs_to_jiffies(SSI_TIMEOUT_MS)); | |
5ba155a4 KH |
348 | |
349 | uniphier_spi_irq_disable(spi, SSI_IE_RCIE | SSI_IE_RORIE); | |
350 | ||
e4671df0 KH |
351 | if (!time_left) { |
352 | dev_err(dev, "transfer timeout.\n"); | |
353 | return -ETIMEDOUT; | |
354 | } | |
5ba155a4 KH |
355 | |
356 | return priv->error; | |
357 | } | |
358 | ||
359 | static int uniphier_spi_prepare_transfer_hardware(struct spi_master *master) | |
360 | { | |
361 | struct uniphier_spi_priv *priv = spi_master_get_devdata(master); | |
362 | ||
363 | writel(SSI_CTL_EN, priv->base + SSI_CTL); | |
364 | ||
365 | return 0; | |
366 | } | |
367 | ||
368 | static int uniphier_spi_unprepare_transfer_hardware(struct spi_master *master) | |
369 | { | |
370 | struct uniphier_spi_priv *priv = spi_master_get_devdata(master); | |
371 | ||
372 | writel(0, priv->base + SSI_CTL); | |
373 | ||
374 | return 0; | |
375 | } | |
376 | ||
377 | static irqreturn_t uniphier_spi_handler(int irq, void *dev_id) | |
378 | { | |
379 | struct uniphier_spi_priv *priv = dev_id; | |
380 | u32 val, stat; | |
381 | ||
382 | stat = readl(priv->base + SSI_IS); | |
383 | val = SSI_IC_TCIC | SSI_IC_RCIC | SSI_IC_RORIC; | |
384 | writel(val, priv->base + SSI_IC); | |
385 | ||
386 | /* rx fifo overrun */ | |
387 | if (stat & SSI_IS_RORID) { | |
388 | priv->error = -EIO; | |
389 | goto done; | |
390 | } | |
391 | ||
392 | /* rx complete */ | |
393 | if ((stat & SSI_IS_RCID) && (stat & SSI_IS_RXRS)) { | |
394 | while ((readl(priv->base + SSI_SR) & SSI_SR_RNE) && | |
395 | (priv->rx_bytes - priv->tx_bytes) > 0) | |
396 | uniphier_spi_recv(priv); | |
397 | ||
398 | if ((readl(priv->base + SSI_SR) & SSI_SR_RNE) || | |
399 | (priv->rx_bytes != priv->tx_bytes)) { | |
400 | priv->error = -EIO; | |
401 | goto done; | |
402 | } else if (priv->rx_bytes == 0) | |
403 | goto done; | |
404 | ||
405 | /* next tx transfer */ | |
406 | uniphier_spi_fill_tx_fifo(priv); | |
407 | ||
408 | return IRQ_HANDLED; | |
409 | } | |
410 | ||
411 | return IRQ_NONE; | |
412 | ||
413 | done: | |
414 | complete(&priv->xfer_done); | |
415 | return IRQ_HANDLED; | |
416 | } | |
417 | ||
418 | static int uniphier_spi_probe(struct platform_device *pdev) | |
419 | { | |
420 | struct uniphier_spi_priv *priv; | |
421 | struct spi_master *master; | |
422 | struct resource *res; | |
423 | unsigned long clk_rate; | |
424 | int irq; | |
425 | int ret; | |
426 | ||
427 | master = spi_alloc_master(&pdev->dev, sizeof(*priv)); | |
428 | if (!master) | |
429 | return -ENOMEM; | |
430 | ||
431 | platform_set_drvdata(pdev, master); | |
432 | ||
433 | priv = spi_master_get_devdata(master); | |
434 | priv->master = master; | |
435 | priv->is_save_param = false; | |
436 | ||
437 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
438 | priv->base = devm_ioremap_resource(&pdev->dev, res); | |
439 | if (IS_ERR(priv->base)) { | |
440 | ret = PTR_ERR(priv->base); | |
441 | goto out_master_put; | |
442 | } | |
443 | ||
444 | priv->clk = devm_clk_get(&pdev->dev, NULL); | |
445 | if (IS_ERR(priv->clk)) { | |
446 | dev_err(&pdev->dev, "failed to get clock\n"); | |
447 | ret = PTR_ERR(priv->clk); | |
448 | goto out_master_put; | |
449 | } | |
450 | ||
451 | ret = clk_prepare_enable(priv->clk); | |
452 | if (ret) | |
453 | goto out_master_put; | |
454 | ||
455 | irq = platform_get_irq(pdev, 0); | |
456 | if (irq < 0) { | |
457 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
458 | ret = irq; | |
459 | goto out_disable_clk; | |
460 | } | |
461 | ||
462 | ret = devm_request_irq(&pdev->dev, irq, uniphier_spi_handler, | |
463 | 0, "uniphier-spi", priv); | |
464 | if (ret) { | |
465 | dev_err(&pdev->dev, "failed to request IRQ\n"); | |
466 | goto out_disable_clk; | |
467 | } | |
468 | ||
469 | init_completion(&priv->xfer_done); | |
470 | ||
471 | clk_rate = clk_get_rate(priv->clk); | |
472 | ||
473 | master->max_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MIN_CLK_DIVIDER); | |
474 | master->min_speed_hz = DIV_ROUND_UP(clk_rate, SSI_MAX_CLK_DIVIDER); | |
475 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; | |
476 | master->dev.of_node = pdev->dev.of_node; | |
477 | master->bus_num = pdev->id; | |
478 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); | |
479 | ||
480 | master->set_cs = uniphier_spi_set_cs; | |
481 | master->transfer_one = uniphier_spi_transfer_one; | |
482 | master->prepare_transfer_hardware | |
483 | = uniphier_spi_prepare_transfer_hardware; | |
484 | master->unprepare_transfer_hardware | |
485 | = uniphier_spi_unprepare_transfer_hardware; | |
486 | master->num_chipselect = 1; | |
487 | ||
488 | ret = devm_spi_register_master(&pdev->dev, master); | |
489 | if (ret) | |
490 | goto out_disable_clk; | |
491 | ||
492 | return 0; | |
493 | ||
494 | out_disable_clk: | |
495 | clk_disable_unprepare(priv->clk); | |
496 | ||
497 | out_master_put: | |
498 | spi_master_put(master); | |
499 | return ret; | |
500 | } | |
501 | ||
502 | static int uniphier_spi_remove(struct platform_device *pdev) | |
503 | { | |
504 | struct uniphier_spi_priv *priv = platform_get_drvdata(pdev); | |
505 | ||
506 | clk_disable_unprepare(priv->clk); | |
507 | ||
508 | return 0; | |
509 | } | |
510 | ||
511 | static const struct of_device_id uniphier_spi_match[] = { | |
512 | { .compatible = "socionext,uniphier-scssi" }, | |
513 | { /* sentinel */ } | |
514 | }; | |
515 | MODULE_DEVICE_TABLE(of, uniphier_spi_match); | |
516 | ||
517 | static struct platform_driver uniphier_spi_driver = { | |
518 | .probe = uniphier_spi_probe, | |
519 | .remove = uniphier_spi_remove, | |
520 | .driver = { | |
521 | .name = "uniphier-spi", | |
522 | .of_match_table = uniphier_spi_match, | |
523 | }, | |
524 | }; | |
525 | module_platform_driver(uniphier_spi_driver); | |
526 | ||
527 | MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); | |
528 | MODULE_AUTHOR("Keiji Hayashibara <hayashibara.keiji@socionext.com>"); | |
529 | MODULE_DESCRIPTION("Socionext UniPhier SPI controller driver"); | |
530 | MODULE_LICENSE("GPL v2"); |