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Commit | Line | Data |
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a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
131b17d4 | 16 | #include <linux/io.h> |
a5f6abd4 | 17 | #include <linux/ioport.h> |
131b17d4 | 18 | #include <linux/irq.h> |
a5f6abd4 WB |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/workqueue.h> | |
a5f6abd4 | 25 | |
a5f6abd4 | 26 | #include <asm/dma.h> |
131b17d4 | 27 | #include <asm/portmux.h> |
a5f6abd4 | 28 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
29 | #include <asm/cacheflush.h> |
30 | ||
a32c691d BW |
31 | #define DRV_NAME "bfin-spi" |
32 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 33 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
34 | #define DRV_VERSION "1.0" |
35 | ||
36 | MODULE_AUTHOR(DRV_AUTHOR); | |
37 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
38 | MODULE_LICENSE("GPL"); |
39 | ||
bb90eb00 BW |
40 | #define START_STATE ((void *)0) |
41 | #define RUNNING_STATE ((void *)1) | |
42 | #define DONE_STATE ((void *)2) | |
43 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 44 | |
b9f139a7 | 45 | struct master_data; |
9c4542c7 MF |
46 | |
47 | struct transfer_ops { | |
b9f139a7 MF |
48 | void (*write) (struct master_data *); |
49 | void (*read) (struct master_data *); | |
50 | void (*duplex) (struct master_data *); | |
9c4542c7 MF |
51 | }; |
52 | ||
b9f139a7 | 53 | struct master_data { |
a5f6abd4 WB |
54 | /* Driver model hookup */ |
55 | struct platform_device *pdev; | |
56 | ||
57 | /* SPI framework hookup */ | |
58 | struct spi_master *master; | |
59 | ||
bb90eb00 | 60 | /* Regs base of SPI controller */ |
f452126c | 61 | void __iomem *regs_base; |
bb90eb00 | 62 | |
003d9226 BW |
63 | /* Pin request list */ |
64 | u16 *pin_req; | |
65 | ||
a5f6abd4 WB |
66 | /* BFIN hookup */ |
67 | struct bfin5xx_spi_master *master_info; | |
68 | ||
69 | /* Driver message queue */ | |
70 | struct workqueue_struct *workqueue; | |
71 | struct work_struct pump_messages; | |
72 | spinlock_t lock; | |
73 | struct list_head queue; | |
74 | int busy; | |
f4f50c3f | 75 | bool running; |
a5f6abd4 WB |
76 | |
77 | /* Message Transfer pump */ | |
78 | struct tasklet_struct pump_transfers; | |
79 | ||
80 | /* Current message transfer state info */ | |
81 | struct spi_message *cur_msg; | |
82 | struct spi_transfer *cur_transfer; | |
b9f139a7 | 83 | struct slave_data *cur_chip; |
a5f6abd4 WB |
84 | size_t len_in_bytes; |
85 | size_t len; | |
86 | void *tx; | |
87 | void *tx_end; | |
88 | void *rx; | |
89 | void *rx_end; | |
bb90eb00 BW |
90 | |
91 | /* DMA stuffs */ | |
92 | int dma_channel; | |
a5f6abd4 | 93 | int dma_mapped; |
bb90eb00 | 94 | int dma_requested; |
a5f6abd4 WB |
95 | dma_addr_t rx_dma; |
96 | dma_addr_t tx_dma; | |
bb90eb00 | 97 | |
f6a6d966 YL |
98 | int irq_requested; |
99 | int spi_irq; | |
100 | ||
a5f6abd4 WB |
101 | size_t rx_map_len; |
102 | size_t tx_map_len; | |
103 | u8 n_bytes; | |
b052fd0a BS |
104 | u16 ctrl_reg; |
105 | u16 flag_reg; | |
106 | ||
fad91c89 | 107 | int cs_change; |
9c4542c7 | 108 | const struct transfer_ops *ops; |
a5f6abd4 WB |
109 | }; |
110 | ||
b9f139a7 | 111 | struct slave_data { |
a5f6abd4 WB |
112 | u16 ctl_reg; |
113 | u16 baud; | |
114 | u16 flag; | |
115 | ||
116 | u8 chip_select_num; | |
a5f6abd4 | 117 | u8 enable_dma; |
62310e51 | 118 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 119 | u32 cs_gpio; |
93b61bdd | 120 | u16 idle_tx_val; |
f6a6d966 | 121 | u8 pio_interrupt; /* use spi data irq */ |
9c4542c7 | 122 | const struct transfer_ops *ops; |
a5f6abd4 WB |
123 | }; |
124 | ||
bb90eb00 | 125 | #define DEFINE_SPI_REG(reg, off) \ |
b9f139a7 | 126 | static inline u16 read_##reg(struct master_data *drv_data) \ |
bb90eb00 | 127 | { return bfin_read16(drv_data->regs_base + off); } \ |
b9f139a7 | 128 | static inline void write_##reg(struct master_data *drv_data, u16 v) \ |
bb90eb00 BW |
129 | { bfin_write16(drv_data->regs_base + off, v); } |
130 | ||
131 | DEFINE_SPI_REG(CTRL, 0x00) | |
132 | DEFINE_SPI_REG(FLAG, 0x04) | |
133 | DEFINE_SPI_REG(STAT, 0x08) | |
134 | DEFINE_SPI_REG(TDBR, 0x0C) | |
135 | DEFINE_SPI_REG(RDBR, 0x10) | |
136 | DEFINE_SPI_REG(BAUD, 0x14) | |
137 | DEFINE_SPI_REG(SHAW, 0x18) | |
138 | ||
b9f139a7 | 139 | static void bfin_spi_enable(struct master_data *drv_data) |
a5f6abd4 WB |
140 | { |
141 | u16 cr; | |
142 | ||
bb90eb00 BW |
143 | cr = read_CTRL(drv_data); |
144 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
145 | } |
146 | ||
b9f139a7 | 147 | static void bfin_spi_disable(struct master_data *drv_data) |
a5f6abd4 WB |
148 | { |
149 | u16 cr; | |
150 | ||
bb90eb00 BW |
151 | cr = read_CTRL(drv_data); |
152 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
153 | } |
154 | ||
155 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
156 | static u16 hz_to_spi_baud(u32 speed_hz) | |
157 | { | |
158 | u_long sclk = get_sclk(); | |
159 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
160 | ||
161 | if ((sclk % (2 * speed_hz)) > 0) | |
162 | spi_baud++; | |
163 | ||
7513e006 MH |
164 | if (spi_baud < MIN_SPI_BAUD_VAL) |
165 | spi_baud = MIN_SPI_BAUD_VAL; | |
166 | ||
a5f6abd4 WB |
167 | return spi_baud; |
168 | } | |
169 | ||
b9f139a7 | 170 | static int bfin_spi_flush(struct master_data *drv_data) |
a5f6abd4 WB |
171 | { |
172 | unsigned long limit = loops_per_jiffy << 1; | |
173 | ||
174 | /* wait for stop and clear stat */ | |
b4bd2aba | 175 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 176 | cpu_relax(); |
a5f6abd4 | 177 | |
bb90eb00 | 178 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
179 | |
180 | return limit; | |
181 | } | |
182 | ||
fad91c89 | 183 | /* Chip select operation functions for cs_change flag */ |
b9f139a7 | 184 | static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 185 | { |
d3cc71f7 | 186 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 187 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 188 | |
8221610e | 189 | flag &= ~chip->flag; |
fad91c89 | 190 | |
42c78b2b MH |
191 | write_FLAG(drv_data, flag); |
192 | } else { | |
193 | gpio_set_value(chip->cs_gpio, 0); | |
194 | } | |
fad91c89 BW |
195 | } |
196 | ||
b9f139a7 | 197 | static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 198 | { |
d3cc71f7 | 199 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 200 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 201 | |
8221610e | 202 | flag |= chip->flag; |
fad91c89 | 203 | |
42c78b2b MH |
204 | write_FLAG(drv_data, flag); |
205 | } else { | |
206 | gpio_set_value(chip->cs_gpio, 1); | |
207 | } | |
62310e51 BW |
208 | |
209 | /* Move delay here for consistency */ | |
210 | if (chip->cs_chg_udelay) | |
211 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
212 | } |
213 | ||
8221610e | 214 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
b9f139a7 | 215 | static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip) |
8221610e | 216 | { |
d3cc71f7 BS |
217 | if (chip->chip_select_num < MAX_CTRL_CS) { |
218 | u16 flag = read_FLAG(drv_data); | |
8221610e | 219 | |
d3cc71f7 | 220 | flag |= (chip->flag >> 8); |
8221610e | 221 | |
d3cc71f7 BS |
222 | write_FLAG(drv_data, flag); |
223 | } | |
8221610e BS |
224 | } |
225 | ||
b9f139a7 | 226 | static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip) |
8221610e | 227 | { |
d3cc71f7 BS |
228 | if (chip->chip_select_num < MAX_CTRL_CS) { |
229 | u16 flag = read_FLAG(drv_data); | |
8221610e | 230 | |
d3cc71f7 | 231 | flag &= ~(chip->flag >> 8); |
8221610e | 232 | |
d3cc71f7 BS |
233 | write_FLAG(drv_data, flag); |
234 | } | |
8221610e BS |
235 | } |
236 | ||
a5f6abd4 | 237 | /* stop controller and re-config current chip*/ |
b9f139a7 | 238 | static void bfin_spi_restore_state(struct master_data *drv_data) |
a5f6abd4 | 239 | { |
b9f139a7 | 240 | struct slave_data *chip = drv_data->cur_chip; |
12e17c42 | 241 | |
a5f6abd4 | 242 | /* Clear status and disable clock */ |
bb90eb00 | 243 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 244 | bfin_spi_disable(drv_data); |
88b40369 | 245 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 246 | |
9677b0de BS |
247 | SSYNC(); |
248 | ||
5fec5b5a | 249 | /* Load the registers */ |
bb90eb00 | 250 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 251 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
252 | |
253 | bfin_spi_enable(drv_data); | |
138f97cd | 254 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
255 | } |
256 | ||
93b61bdd | 257 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
b9f139a7 | 258 | static inline void bfin_spi_dummy_read(struct master_data *drv_data) |
a5f6abd4 | 259 | { |
93b61bdd | 260 | (void) read_RDBR(drv_data); |
a5f6abd4 WB |
261 | } |
262 | ||
b9f139a7 | 263 | static void bfin_spi_u8_writer(struct master_data *drv_data) |
a5f6abd4 | 264 | { |
93b61bdd WM |
265 | /* clear RXS (we check for RXS inside the loop) */ |
266 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 267 | |
a5f6abd4 | 268 | while (drv_data->tx < drv_data->tx_end) { |
93b61bdd WM |
269 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
270 | /* wait until transfer finished. | |
271 | checking SPIF or TXS may not guarantee transfer completion */ | |
272 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
d8c05008 | 273 | cpu_relax(); |
93b61bdd WM |
274 | /* discard RX data and clear RXS */ |
275 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 276 | } |
a5f6abd4 WB |
277 | } |
278 | ||
b9f139a7 | 279 | static void bfin_spi_u8_reader(struct master_data *drv_data) |
a5f6abd4 | 280 | { |
93b61bdd | 281 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 282 | |
93b61bdd | 283 | /* discard old RX data and clear RXS */ |
138f97cd | 284 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 285 | |
93b61bdd WM |
286 | while (drv_data->rx < drv_data->rx_end) { |
287 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 288 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 289 | cpu_relax(); |
93b61bdd | 290 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 | 291 | } |
a5f6abd4 WB |
292 | } |
293 | ||
b9f139a7 | 294 | static void bfin_spi_u8_duplex(struct master_data *drv_data) |
a5f6abd4 | 295 | { |
93b61bdd WM |
296 | /* discard old RX data and clear RXS */ |
297 | bfin_spi_dummy_read(drv_data); | |
298 | ||
a5f6abd4 | 299 | while (drv_data->rx < drv_data->rx_end) { |
93b61bdd | 300 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 301 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 302 | cpu_relax(); |
93b61bdd | 303 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 WB |
304 | } |
305 | } | |
306 | ||
9c4542c7 MF |
307 | static const struct transfer_ops bfin_transfer_ops_u8 = { |
308 | .write = bfin_spi_u8_writer, | |
309 | .read = bfin_spi_u8_reader, | |
310 | .duplex = bfin_spi_u8_duplex, | |
311 | }; | |
312 | ||
b9f139a7 | 313 | static void bfin_spi_u16_writer(struct master_data *drv_data) |
a5f6abd4 | 314 | { |
93b61bdd WM |
315 | /* clear RXS (we check for RXS inside the loop) */ |
316 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 317 | |
a5f6abd4 | 318 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 319 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 320 | drv_data->tx += 2; |
93b61bdd WM |
321 | /* wait until transfer finished. |
322 | checking SPIF or TXS may not guarantee transfer completion */ | |
323 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
324 | cpu_relax(); | |
325 | /* discard RX data and clear RXS */ | |
326 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 327 | } |
a5f6abd4 WB |
328 | } |
329 | ||
b9f139a7 | 330 | static void bfin_spi_u16_reader(struct master_data *drv_data) |
a5f6abd4 | 331 | { |
93b61bdd | 332 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 333 | |
93b61bdd | 334 | /* discard old RX data and clear RXS */ |
138f97cd | 335 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 336 | |
93b61bdd WM |
337 | while (drv_data->rx < drv_data->rx_end) { |
338 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 339 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 340 | cpu_relax(); |
bb90eb00 | 341 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
342 | drv_data->rx += 2; |
343 | } | |
a5f6abd4 WB |
344 | } |
345 | ||
b9f139a7 | 346 | static void bfin_spi_u16_duplex(struct master_data *drv_data) |
a5f6abd4 | 347 | { |
93b61bdd WM |
348 | /* discard old RX data and clear RXS */ |
349 | bfin_spi_dummy_read(drv_data); | |
350 | ||
351 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 352 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 353 | drv_data->tx += 2; |
bb90eb00 | 354 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 355 | cpu_relax(); |
bb90eb00 | 356 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 357 | drv_data->rx += 2; |
a5f6abd4 WB |
358 | } |
359 | } | |
360 | ||
9c4542c7 MF |
361 | static const struct transfer_ops bfin_transfer_ops_u16 = { |
362 | .write = bfin_spi_u16_writer, | |
363 | .read = bfin_spi_u16_reader, | |
364 | .duplex = bfin_spi_u16_duplex, | |
365 | }; | |
366 | ||
a5f6abd4 | 367 | /* test if ther is more transfer to be done */ |
b9f139a7 | 368 | static void *bfin_spi_next_transfer(struct master_data *drv_data) |
a5f6abd4 WB |
369 | { |
370 | struct spi_message *msg = drv_data->cur_msg; | |
371 | struct spi_transfer *trans = drv_data->cur_transfer; | |
372 | ||
373 | /* Move to next transfer */ | |
374 | if (trans->transfer_list.next != &msg->transfers) { | |
375 | drv_data->cur_transfer = | |
376 | list_entry(trans->transfer_list.next, | |
377 | struct spi_transfer, transfer_list); | |
378 | return RUNNING_STATE; | |
379 | } else | |
380 | return DONE_STATE; | |
381 | } | |
382 | ||
383 | /* | |
384 | * caller already set message->status; | |
385 | * dma and pio irqs are blocked give finished message back | |
386 | */ | |
b9f139a7 | 387 | static void bfin_spi_giveback(struct master_data *drv_data) |
a5f6abd4 | 388 | { |
b9f139a7 | 389 | struct slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
390 | struct spi_transfer *last_transfer; |
391 | unsigned long flags; | |
392 | struct spi_message *msg; | |
393 | ||
394 | spin_lock_irqsave(&drv_data->lock, flags); | |
395 | msg = drv_data->cur_msg; | |
396 | drv_data->cur_msg = NULL; | |
397 | drv_data->cur_transfer = NULL; | |
398 | drv_data->cur_chip = NULL; | |
399 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
400 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
401 | ||
402 | last_transfer = list_entry(msg->transfers.prev, | |
403 | struct spi_transfer, transfer_list); | |
404 | ||
405 | msg->state = NULL; | |
406 | ||
fad91c89 | 407 | if (!drv_data->cs_change) |
138f97cd | 408 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 409 | |
b9b2a76a YL |
410 | /* Not stop spi in autobuffer mode */ |
411 | if (drv_data->tx_dma != 0xFFFF) | |
412 | bfin_spi_disable(drv_data); | |
413 | ||
a5f6abd4 WB |
414 | if (msg->complete) |
415 | msg->complete(msg->context); | |
416 | } | |
417 | ||
f6a6d966 YL |
418 | /* spi data irq handler */ |
419 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
420 | { | |
b9f139a7 MF |
421 | struct master_data *drv_data = dev_id; |
422 | struct slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
423 | struct spi_message *msg = drv_data->cur_msg; |
424 | int n_bytes = drv_data->n_bytes; | |
425 | ||
426 | /* wait until transfer finished. */ | |
427 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
428 | cpu_relax(); | |
429 | ||
430 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
431 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
432 | /* last read */ | |
433 | if (drv_data->rx) { | |
434 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
435 | if (n_bytes == 2) | |
436 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
437 | else if (n_bytes == 1) | |
438 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
439 | drv_data->rx += n_bytes; | |
440 | } | |
441 | ||
442 | msg->actual_length += drv_data->len_in_bytes; | |
443 | if (drv_data->cs_change) | |
444 | bfin_spi_cs_deactive(drv_data, chip); | |
445 | /* Move to next transfer */ | |
446 | msg->state = bfin_spi_next_transfer(drv_data); | |
447 | ||
7370ed6b | 448 | disable_irq_nosync(drv_data->spi_irq); |
f6a6d966 YL |
449 | |
450 | /* Schedule transfer tasklet */ | |
451 | tasklet_schedule(&drv_data->pump_transfers); | |
452 | return IRQ_HANDLED; | |
453 | } | |
454 | ||
455 | if (drv_data->rx && drv_data->tx) { | |
456 | /* duplex */ | |
457 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
458 | if (drv_data->n_bytes == 2) { | |
459 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
460 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
461 | } else if (drv_data->n_bytes == 1) { | |
462 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
463 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
464 | } | |
465 | } else if (drv_data->rx) { | |
466 | /* read */ | |
467 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
468 | if (drv_data->n_bytes == 2) | |
469 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
470 | else if (drv_data->n_bytes == 1) | |
471 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
472 | write_TDBR(drv_data, chip->idle_tx_val); | |
473 | } else if (drv_data->tx) { | |
474 | /* write */ | |
475 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
476 | bfin_spi_dummy_read(drv_data); | |
477 | if (drv_data->n_bytes == 2) | |
478 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
479 | else if (drv_data->n_bytes == 1) | |
480 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
481 | } | |
482 | ||
483 | if (drv_data->tx) | |
484 | drv_data->tx += n_bytes; | |
485 | if (drv_data->rx) | |
486 | drv_data->rx += n_bytes; | |
487 | ||
488 | return IRQ_HANDLED; | |
489 | } | |
490 | ||
138f97cd | 491 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 492 | { |
b9f139a7 MF |
493 | struct master_data *drv_data = dev_id; |
494 | struct slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 495 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 496 | unsigned long timeout; |
d24bd1d0 | 497 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 498 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 499 | |
d24bd1d0 MF |
500 | dev_dbg(&drv_data->pdev->dev, |
501 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
502 | dmastat, spistat); | |
503 | ||
bb90eb00 | 504 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
505 | |
506 | /* | |
d6fe89b0 BW |
507 | * wait for the last transaction shifted out. HRM states: |
508 | * at this point there may still be data in the SPI DMA FIFO waiting | |
509 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
510 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
511 | */ |
512 | if (drv_data->tx != NULL) { | |
90008a64 MF |
513 | while ((read_STAT(drv_data) & BIT_STAT_TXS) || |
514 | (read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 515 | cpu_relax(); |
a5f6abd4 WB |
516 | } |
517 | ||
aaaf939c MF |
518 | dev_dbg(&drv_data->pdev->dev, |
519 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
520 | dmastat, read_STAT(drv_data)); | |
521 | ||
522 | timeout = jiffies + HZ; | |
90008a64 | 523 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
aaaf939c MF |
524 | if (!time_before(jiffies, timeout)) { |
525 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
526 | break; | |
527 | } else | |
528 | cpu_relax(); | |
a5f6abd4 | 529 | |
90008a64 | 530 | if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) { |
04b95d2f MF |
531 | msg->state = ERROR_STATE; |
532 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
533 | } else { | |
534 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 535 | |
04b95d2f | 536 | if (drv_data->cs_change) |
138f97cd | 537 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 538 | |
04b95d2f | 539 | /* Move to next transfer */ |
138f97cd | 540 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 541 | } |
a5f6abd4 WB |
542 | |
543 | /* Schedule transfer tasklet */ | |
544 | tasklet_schedule(&drv_data->pump_transfers); | |
545 | ||
546 | /* free the irq handler before next transfer */ | |
88b40369 BW |
547 | dev_dbg(&drv_data->pdev->dev, |
548 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
549 | drv_data->dma_channel); |
550 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
551 | |
552 | return IRQ_HANDLED; | |
553 | } | |
554 | ||
138f97cd | 555 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 556 | { |
b9f139a7 | 557 | struct master_data *drv_data = (struct master_data *)data; |
a5f6abd4 WB |
558 | struct spi_message *message = NULL; |
559 | struct spi_transfer *transfer = NULL; | |
560 | struct spi_transfer *previous = NULL; | |
b9f139a7 | 561 | struct slave_data *chip = NULL; |
033f44bd | 562 | unsigned int bits_per_word; |
88b40369 BW |
563 | u8 width; |
564 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 565 | u32 tranf_success = 1; |
8eeb12e5 | 566 | u8 full_duplex = 0; |
a5f6abd4 WB |
567 | |
568 | /* Get current state information */ | |
569 | message = drv_data->cur_msg; | |
570 | transfer = drv_data->cur_transfer; | |
571 | chip = drv_data->cur_chip; | |
092e1fda | 572 | |
a5f6abd4 WB |
573 | /* |
574 | * if msg is error or done, report it back using complete() callback | |
575 | */ | |
576 | ||
577 | /* Handle for abort */ | |
578 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 579 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 580 | message->status = -EIO; |
138f97cd | 581 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
582 | return; |
583 | } | |
584 | ||
585 | /* Handle end of message */ | |
586 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 587 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 588 | message->status = 0; |
138f97cd | 589 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
590 | return; |
591 | } | |
592 | ||
593 | /* Delay if requested at end of transfer */ | |
594 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 595 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
596 | previous = list_entry(transfer->transfer_list.prev, |
597 | struct spi_transfer, transfer_list); | |
598 | if (previous->delay_usecs) | |
599 | udelay(previous->delay_usecs); | |
600 | } | |
601 | ||
ab09e040 | 602 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 603 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
604 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
605 | message->status = -EIO; | |
138f97cd | 606 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
607 | return; |
608 | } | |
609 | ||
93b61bdd WM |
610 | if (transfer->len == 0) { |
611 | /* Move to next transfer of this msg */ | |
612 | message->state = bfin_spi_next_transfer(drv_data); | |
613 | /* Schedule next transfer tasklet */ | |
614 | tasklet_schedule(&drv_data->pump_transfers); | |
615 | } | |
616 | ||
a5f6abd4 WB |
617 | if (transfer->tx_buf != NULL) { |
618 | drv_data->tx = (void *)transfer->tx_buf; | |
619 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
620 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
621 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
622 | } else { |
623 | drv_data->tx = NULL; | |
624 | } | |
625 | ||
626 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 627 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
628 | drv_data->rx = transfer->rx_buf; |
629 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
630 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
631 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
632 | } else { |
633 | drv_data->rx = NULL; | |
634 | } | |
635 | ||
636 | drv_data->rx_dma = transfer->rx_dma; | |
637 | drv_data->tx_dma = transfer->tx_dma; | |
638 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 639 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 640 | |
092e1fda | 641 | /* Bits per word setup */ |
033f44bd MF |
642 | bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word; |
643 | if (bits_per_word == 8) { | |
092e1fda BW |
644 | drv_data->n_bytes = 1; |
645 | width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 646 | drv_data->ops = &bfin_transfer_ops_u8; |
033f44bd | 647 | } else { |
092e1fda BW |
648 | drv_data->n_bytes = 2; |
649 | width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 650 | drv_data->ops = &bfin_transfer_ops_u16; |
092e1fda BW |
651 | } |
652 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
653 | cr |= (width << 8); | |
654 | write_CTRL(drv_data, cr); | |
655 | ||
a5f6abd4 WB |
656 | if (width == CFG_SPI_WORDSIZE16) { |
657 | drv_data->len = (transfer->len) >> 1; | |
658 | } else { | |
659 | drv_data->len = transfer->len; | |
660 | } | |
4fb98efa | 661 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 MF |
662 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
663 | drv_data->ops, chip->ops, &bfin_transfer_ops_u8); | |
a5f6abd4 | 664 | |
a5f6abd4 WB |
665 | message->state = RUNNING_STATE; |
666 | dma_config = 0; | |
667 | ||
092e1fda BW |
668 | /* Speed setup (surely valid because already checked) */ |
669 | if (transfer->speed_hz) | |
670 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
671 | else | |
672 | write_BAUD(drv_data, chip->baud); | |
673 | ||
bb90eb00 BW |
674 | write_STAT(drv_data, BIT_STAT_CLR); |
675 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
b9b2a76a | 676 | if (drv_data->cs_change) |
138f97cd | 677 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 678 | |
88b40369 BW |
679 | dev_dbg(&drv_data->pdev->dev, |
680 | "now pumping a transfer: width is %d, len is %d\n", | |
681 | width, transfer->len); | |
a5f6abd4 WB |
682 | |
683 | /* | |
8cf5858c VM |
684 | * Try to map dma buffer and do a dma transfer. If successful use, |
685 | * different way to r/w according to the enable_dma settings and if | |
686 | * we are not doing a full duplex transfer (since the hardware does | |
687 | * not support full duplex DMA transfers). | |
a5f6abd4 | 688 | */ |
8eeb12e5 VM |
689 | if (!full_duplex && drv_data->cur_chip->enable_dma |
690 | && drv_data->len > 6) { | |
a5f6abd4 | 691 | |
11d6f599 | 692 | unsigned long dma_start_addr, flags; |
7aec3566 | 693 | |
bb90eb00 BW |
694 | disable_dma(drv_data->dma_channel); |
695 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
696 | |
697 | /* config dma channel */ | |
88b40369 | 698 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 699 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 | 700 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 | 701 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
702 | dma_width = WDSIZE_16; |
703 | } else { | |
bb90eb00 | 704 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
705 | dma_width = WDSIZE_8; |
706 | } | |
707 | ||
3f479a65 | 708 | /* poll for SPI completion before start */ |
bb90eb00 | 709 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 710 | cpu_relax(); |
3f479a65 | 711 | |
a5f6abd4 WB |
712 | /* dirty hack for autobuffer DMA mode */ |
713 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
714 | dev_dbg(&drv_data->pdev->dev, |
715 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
716 | |
717 | /* no irq in autobuffer mode */ | |
718 | dma_config = | |
719 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
720 | set_dma_config(drv_data->dma_channel, dma_config); |
721 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 722 | (unsigned long)drv_data->tx); |
bb90eb00 | 723 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 724 | |
07612e5f | 725 | /* start SPI transfer */ |
11d6f599 | 726 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
727 | |
728 | /* just return here, there can only be one transfer | |
729 | * in this mode | |
730 | */ | |
a5f6abd4 | 731 | message->status = 0; |
138f97cd | 732 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
733 | return; |
734 | } | |
735 | ||
736 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 737 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
738 | if (drv_data->rx != NULL) { |
739 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
740 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
741 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 742 | |
8cf5858c | 743 | /* invalidate caches, if needed */ |
67834fa9 | 744 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
745 | invalidate_dcache_range((unsigned long) drv_data->rx, |
746 | (unsigned long) (drv_data->rx + | |
ace32865 | 747 | drv_data->len_in_bytes)); |
8cf5858c | 748 | |
7aec3566 MF |
749 | dma_config |= WNR; |
750 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 751 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 752 | |
a5f6abd4 | 753 | } else if (drv_data->tx != NULL) { |
88b40369 | 754 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 755 | |
8cf5858c | 756 | /* flush caches, if needed */ |
67834fa9 | 757 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
758 | flush_dcache_range((unsigned long) drv_data->tx, |
759 | (unsigned long) (drv_data->tx + | |
ace32865 | 760 | drv_data->len_in_bytes)); |
8cf5858c | 761 | |
7aec3566 | 762 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 763 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
764 | |
765 | } else | |
766 | BUG(); | |
767 | ||
11d6f599 MF |
768 | /* oh man, here there be monsters ... and i dont mean the |
769 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
770 | * your data, kick your dog, and love it all. do *not* try | |
771 | * and change these lines unless you (1) heavily test DMA | |
772 | * with SPI flashes on a loaded system (e.g. ping floods), | |
773 | * (2) know just how broken the DMA engine interaction with | |
774 | * the SPI peripheral is, and (3) have someone else to blame | |
775 | * when you screw it all up anyways. | |
776 | */ | |
7aec3566 | 777 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
778 | set_dma_config(drv_data->dma_channel, dma_config); |
779 | local_irq_save(flags); | |
a963ea83 | 780 | SSYNC(); |
11d6f599 | 781 | write_CTRL(drv_data, cr); |
a963ea83 | 782 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
783 | dma_enable_irq(drv_data->dma_channel); |
784 | local_irq_restore(flags); | |
07612e5f | 785 | |
f6a6d966 YL |
786 | return; |
787 | } | |
a5f6abd4 | 788 | |
f6a6d966 YL |
789 | if (chip->pio_interrupt) { |
790 | /* use write mode. spi irq should have been disabled */ | |
791 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
93b61bdd WM |
792 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
793 | ||
f6a6d966 YL |
794 | /* discard old RX data and clear RXS */ |
795 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 796 | |
f6a6d966 YL |
797 | /* start transfer */ |
798 | if (drv_data->tx == NULL) | |
799 | write_TDBR(drv_data, chip->idle_tx_val); | |
800 | else { | |
033f44bd | 801 | if (bits_per_word == 8) |
f6a6d966 | 802 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
033f44bd | 803 | else |
f6a6d966 YL |
804 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
805 | drv_data->tx += drv_data->n_bytes; | |
806 | } | |
a5f6abd4 | 807 | |
f6a6d966 YL |
808 | /* once TDBR is empty, interrupt is triggered */ |
809 | enable_irq(drv_data->spi_irq); | |
810 | return; | |
811 | } | |
a5f6abd4 | 812 | |
f6a6d966 YL |
813 | /* IO mode */ |
814 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
815 | ||
816 | /* we always use SPI_WRITE mode. SPI_READ mode | |
817 | seems to have problems with setting up the | |
818 | output value in TDBR prior to the transfer. */ | |
819 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); | |
820 | ||
821 | if (full_duplex) { | |
822 | /* full duplex mode */ | |
823 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
824 | (drv_data->rx_end - drv_data->rx)); | |
825 | dev_dbg(&drv_data->pdev->dev, | |
826 | "IO duplex: cr is 0x%x\n", cr); | |
827 | ||
9c4542c7 | 828 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
829 | |
830 | if (drv_data->tx != drv_data->tx_end) | |
831 | tranf_success = 0; | |
832 | } else if (drv_data->tx != NULL) { | |
833 | /* write only half duplex */ | |
834 | dev_dbg(&drv_data->pdev->dev, | |
835 | "IO write: cr is 0x%x\n", cr); | |
836 | ||
9c4542c7 | 837 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
838 | |
839 | if (drv_data->tx != drv_data->tx_end) | |
840 | tranf_success = 0; | |
841 | } else if (drv_data->rx != NULL) { | |
842 | /* read only half duplex */ | |
843 | dev_dbg(&drv_data->pdev->dev, | |
844 | "IO read: cr is 0x%x\n", cr); | |
845 | ||
9c4542c7 | 846 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
847 | if (drv_data->rx != drv_data->rx_end) |
848 | tranf_success = 0; | |
849 | } | |
a5f6abd4 | 850 | |
f6a6d966 YL |
851 | if (!tranf_success) { |
852 | dev_dbg(&drv_data->pdev->dev, | |
853 | "IO write error!\n"); | |
854 | message->state = ERROR_STATE; | |
855 | } else { | |
856 | /* Update total byte transfered */ | |
857 | message->actual_length += drv_data->len_in_bytes; | |
858 | /* Move to next transfer of this msg */ | |
859 | message->state = bfin_spi_next_transfer(drv_data); | |
860 | if (drv_data->cs_change) | |
861 | bfin_spi_cs_deactive(drv_data, chip); | |
a5f6abd4 | 862 | } |
f6a6d966 YL |
863 | |
864 | /* Schedule next transfer tasklet */ | |
865 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
866 | } |
867 | ||
868 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 869 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 870 | { |
b9f139a7 | 871 | struct master_data *drv_data; |
a5f6abd4 WB |
872 | unsigned long flags; |
873 | ||
b9f139a7 | 874 | drv_data = container_of(work, struct master_data, pump_messages); |
131b17d4 | 875 | |
a5f6abd4 WB |
876 | /* Lock queue and check for queue work */ |
877 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 878 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
879 | /* pumper kicked off but no work to do */ |
880 | drv_data->busy = 0; | |
881 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
882 | return; | |
883 | } | |
884 | ||
885 | /* Make sure we are not already running a message */ | |
886 | if (drv_data->cur_msg) { | |
887 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
888 | return; | |
889 | } | |
890 | ||
891 | /* Extract head of queue */ | |
892 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
893 | struct spi_message, queue); | |
5fec5b5a BW |
894 | |
895 | /* Setup the SSP using the per chip configuration */ | |
896 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 897 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 898 | |
a5f6abd4 WB |
899 | list_del_init(&drv_data->cur_msg->queue); |
900 | ||
901 | /* Initial message state */ | |
902 | drv_data->cur_msg->state = START_STATE; | |
903 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
904 | struct spi_transfer, transfer_list); | |
905 | ||
5fec5b5a BW |
906 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
907 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
908 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
909 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
910 | |
911 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
912 | "the first transfer len is %d\n", |
913 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
914 | |
915 | /* Mark as busy and launch transfers */ | |
916 | tasklet_schedule(&drv_data->pump_transfers); | |
917 | ||
918 | drv_data->busy = 1; | |
919 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
920 | } | |
921 | ||
922 | /* | |
923 | * got a msg to transfer, queue it in drv_data->queue. | |
924 | * And kick off message pumper | |
925 | */ | |
138f97cd | 926 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 927 | { |
b9f139a7 | 928 | struct master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
929 | unsigned long flags; |
930 | ||
931 | spin_lock_irqsave(&drv_data->lock, flags); | |
932 | ||
f4f50c3f | 933 | if (!drv_data->running) { |
a5f6abd4 WB |
934 | spin_unlock_irqrestore(&drv_data->lock, flags); |
935 | return -ESHUTDOWN; | |
936 | } | |
937 | ||
938 | msg->actual_length = 0; | |
939 | msg->status = -EINPROGRESS; | |
940 | msg->state = START_STATE; | |
941 | ||
88b40369 | 942 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
943 | list_add_tail(&msg->queue, &drv_data->queue); |
944 | ||
f4f50c3f | 945 | if (drv_data->running && !drv_data->busy) |
a5f6abd4 WB |
946 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
947 | ||
948 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
949 | ||
950 | return 0; | |
951 | } | |
952 | ||
12e17c42 SZ |
953 | #define MAX_SPI_SSEL 7 |
954 | ||
4160bde2 | 955 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
956 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
957 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
958 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
959 | ||
960 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
961 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
962 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
963 | ||
964 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
965 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
966 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
967 | }; | |
968 | ||
ab09e040 | 969 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 970 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 971 | { |
ac01e97d | 972 | struct bfin5xx_spi_chip *chip_info; |
b9f139a7 MF |
973 | struct slave_data *chip = NULL; |
974 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
ac01e97d | 975 | int ret = -EINVAL; |
a5f6abd4 | 976 | |
a5f6abd4 | 977 | /* Only alloc (or use chip_info) on first setup */ |
ac01e97d | 978 | chip_info = NULL; |
a5f6abd4 WB |
979 | chip = spi_get_ctldata(spi); |
980 | if (chip == NULL) { | |
ac01e97d DM |
981 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
982 | if (!chip) { | |
983 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
984 | ret = -ENOMEM; | |
985 | goto error; | |
986 | } | |
a5f6abd4 WB |
987 | |
988 | chip->enable_dma = 0; | |
989 | chip_info = spi->controller_data; | |
990 | } | |
991 | ||
992 | /* chip_info isn't always needed */ | |
993 | if (chip_info) { | |
2ed35516 MF |
994 | /* Make sure people stop trying to set fields via ctl_reg |
995 | * when they should actually be using common SPI framework. | |
90008a64 | 996 | * Currently we let through: WOM EMISO PSSE GM SZ. |
2ed35516 MF |
997 | * Not sure if a user actually needs/uses any of these, |
998 | * but let's assume (for now) they do. | |
999 | */ | |
90008a64 MF |
1000 | if (chip_info->ctl_reg & ~(BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | \ |
1001 | BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ)) { | |
2ed35516 MF |
1002 | dev_err(&spi->dev, "do not set bits in ctl_reg " |
1003 | "that the SPI framework manages\n"); | |
ac01e97d | 1004 | goto error; |
2ed35516 MF |
1005 | } |
1006 | ||
a5f6abd4 WB |
1007 | chip->enable_dma = chip_info->enable_dma != 0 |
1008 | && drv_data->master_info->enable_dma; | |
1009 | chip->ctl_reg = chip_info->ctl_reg; | |
a5f6abd4 | 1010 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
93b61bdd | 1011 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1012 | chip->pio_interrupt = chip_info->pio_interrupt; |
033f44bd MF |
1013 | spi->bits_per_word = chip_info->bits_per_word; |
1014 | } | |
1015 | ||
1016 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) { | |
1017 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1018 | spi->bits_per_word); | |
1019 | goto error; | |
a5f6abd4 WB |
1020 | } |
1021 | ||
1022 | /* translate common spi framework into our register */ | |
1023 | if (spi->mode & SPI_CPOL) | |
90008a64 | 1024 | chip->ctl_reg |= BIT_CTL_CPOL; |
a5f6abd4 | 1025 | if (spi->mode & SPI_CPHA) |
90008a64 | 1026 | chip->ctl_reg |= BIT_CTL_CPHA; |
a5f6abd4 | 1027 | if (spi->mode & SPI_LSB_FIRST) |
90008a64 | 1028 | chip->ctl_reg |= BIT_CTL_LSBF; |
a5f6abd4 | 1029 | /* we dont support running in slave mode (yet?) */ |
90008a64 | 1030 | chip->ctl_reg |= BIT_CTL_MASTER; |
a5f6abd4 | 1031 | |
a5f6abd4 WB |
1032 | /* |
1033 | * Notice: for blackfin, the speed_hz is the value of register | |
1034 | * SPI_BAUD, not the real baudrate | |
1035 | */ | |
1036 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
a5f6abd4 | 1037 | chip->chip_select_num = spi->chip_select; |
d3cc71f7 BS |
1038 | if (chip->chip_select_num < MAX_CTRL_CS) |
1039 | chip->flag = (1 << spi->chip_select) << 8; | |
1040 | else | |
1041 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; | |
a5f6abd4 | 1042 | |
f6a6d966 YL |
1043 | if (chip->enable_dma && chip->pio_interrupt) { |
1044 | dev_err(&spi->dev, "enable_dma is set, " | |
1045 | "do not set pio_interrupt\n"); | |
1046 | goto error; | |
1047 | } | |
ac01e97d DM |
1048 | /* |
1049 | * if any one SPI chip is registered and wants DMA, request the | |
1050 | * DMA channel for it | |
1051 | */ | |
1052 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1053 | /* register dma irq handler */ | |
1054 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1055 | if (ret) { | |
1056 | dev_err(&spi->dev, | |
1057 | "Unable to request BlackFin SPI DMA channel\n"); | |
1058 | goto error; | |
1059 | } | |
1060 | drv_data->dma_requested = 1; | |
1061 | ||
1062 | ret = set_dma_callback(drv_data->dma_channel, | |
1063 | bfin_spi_dma_irq_handler, drv_data); | |
1064 | if (ret) { | |
1065 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1066 | goto error; | |
1067 | } | |
1068 | dma_disable_irq(drv_data->dma_channel); | |
1069 | } | |
1070 | ||
f6a6d966 YL |
1071 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1072 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
1073 | IRQF_DISABLED, "BFIN_SPI", drv_data); | |
1074 | if (ret) { | |
1075 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1076 | goto error; | |
1077 | } | |
1078 | drv_data->irq_requested = 1; | |
1079 | /* we use write mode, spi irq has to be disabled here */ | |
1080 | disable_irq(drv_data->spi_irq); | |
1081 | } | |
1082 | ||
d3cc71f7 | 1083 | if (chip->chip_select_num >= MAX_CTRL_CS) { |
ac01e97d DM |
1084 | ret = gpio_request(chip->cs_gpio, spi->modalias); |
1085 | if (ret) { | |
1086 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1087 | goto pin_error; | |
1088 | } | |
1089 | gpio_direction_output(chip->cs_gpio, 1); | |
a5f6abd4 WB |
1090 | } |
1091 | ||
898eb71c | 1092 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
033f44bd | 1093 | spi->modalias, spi->bits_per_word, chip->enable_dma); |
88b40369 | 1094 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1095 | chip->ctl_reg, chip->flag); |
1096 | ||
1097 | spi_set_ctldata(spi, chip); | |
1098 | ||
12e17c42 | 1099 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
d3cc71f7 | 1100 | if (chip->chip_select_num < MAX_CTRL_CS) { |
ac01e97d DM |
1101 | ret = peripheral_request(ssel[spi->master->bus_num] |
1102 | [chip->chip_select_num-1], spi->modalias); | |
1103 | if (ret) { | |
1104 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1105 | goto pin_error; | |
1106 | } | |
1107 | } | |
12e17c42 | 1108 | |
8221610e | 1109 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1110 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1111 | |
a5f6abd4 | 1112 | return 0; |
ac01e97d DM |
1113 | |
1114 | pin_error: | |
d3cc71f7 | 1115 | if (chip->chip_select_num >= MAX_CTRL_CS) |
ac01e97d DM |
1116 | gpio_free(chip->cs_gpio); |
1117 | else | |
1118 | peripheral_free(ssel[spi->master->bus_num] | |
1119 | [chip->chip_select_num - 1]); | |
1120 | error: | |
1121 | if (chip) { | |
1122 | if (drv_data->dma_requested) | |
1123 | free_dma(drv_data->dma_channel); | |
1124 | drv_data->dma_requested = 0; | |
1125 | ||
1126 | kfree(chip); | |
1127 | /* prevent free 'chip' twice */ | |
1128 | spi_set_ctldata(spi, NULL); | |
1129 | } | |
1130 | ||
1131 | return ret; | |
a5f6abd4 WB |
1132 | } |
1133 | ||
1134 | /* | |
1135 | * callback for spi framework. | |
1136 | * clean driver specific data | |
1137 | */ | |
138f97cd | 1138 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1139 | { |
b9f139a7 MF |
1140 | struct slave_data *chip = spi_get_ctldata(spi); |
1141 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1142 | |
e7d02e3c MF |
1143 | if (!chip) |
1144 | return; | |
1145 | ||
d3cc71f7 | 1146 | if (chip->chip_select_num < MAX_CTRL_CS) { |
12e17c42 SZ |
1147 | peripheral_free(ssel[spi->master->bus_num] |
1148 | [chip->chip_select_num-1]); | |
8221610e | 1149 | bfin_spi_cs_disable(drv_data, chip); |
d3cc71f7 | 1150 | } else |
42c78b2b MH |
1151 | gpio_free(chip->cs_gpio); |
1152 | ||
a5f6abd4 | 1153 | kfree(chip); |
ac01e97d DM |
1154 | /* prevent free 'chip' twice */ |
1155 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1156 | } |
1157 | ||
b9f139a7 | 1158 | static inline int bfin_spi_init_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1159 | { |
1160 | INIT_LIST_HEAD(&drv_data->queue); | |
1161 | spin_lock_init(&drv_data->lock); | |
1162 | ||
f4f50c3f | 1163 | drv_data->running = false; |
a5f6abd4 WB |
1164 | drv_data->busy = 0; |
1165 | ||
1166 | /* init transfer tasklet */ | |
1167 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1168 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1169 | |
1170 | /* init messages workqueue */ | |
138f97cd | 1171 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1172 | drv_data->workqueue = create_singlethread_workqueue( |
1173 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1174 | if (drv_data->workqueue == NULL) |
1175 | return -EBUSY; | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
b9f139a7 | 1180 | static inline int bfin_spi_start_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1181 | { |
1182 | unsigned long flags; | |
1183 | ||
1184 | spin_lock_irqsave(&drv_data->lock, flags); | |
1185 | ||
f4f50c3f | 1186 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1187 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1188 | return -EBUSY; | |
1189 | } | |
1190 | ||
f4f50c3f | 1191 | drv_data->running = true; |
a5f6abd4 WB |
1192 | drv_data->cur_msg = NULL; |
1193 | drv_data->cur_transfer = NULL; | |
1194 | drv_data->cur_chip = NULL; | |
1195 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1196 | ||
1197 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1198 | ||
1199 | return 0; | |
1200 | } | |
1201 | ||
b9f139a7 | 1202 | static inline int bfin_spi_stop_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1203 | { |
1204 | unsigned long flags; | |
1205 | unsigned limit = 500; | |
1206 | int status = 0; | |
1207 | ||
1208 | spin_lock_irqsave(&drv_data->lock, flags); | |
1209 | ||
1210 | /* | |
1211 | * This is a bit lame, but is optimized for the common execution path. | |
1212 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1213 | * execution path (pump_messages) would be required to call wake_up or | |
1214 | * friends on every SPI message. Do this instead | |
1215 | */ | |
f4f50c3f | 1216 | drv_data->running = false; |
a5f6abd4 WB |
1217 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { |
1218 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1219 | msleep(10); | |
1220 | spin_lock_irqsave(&drv_data->lock, flags); | |
1221 | } | |
1222 | ||
1223 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1224 | status = -EBUSY; | |
1225 | ||
1226 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1227 | ||
1228 | return status; | |
1229 | } | |
1230 | ||
b9f139a7 | 1231 | static inline int bfin_spi_destroy_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1232 | { |
1233 | int status; | |
1234 | ||
138f97cd | 1235 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1236 | if (status != 0) |
1237 | return status; | |
1238 | ||
1239 | destroy_workqueue(drv_data->workqueue); | |
1240 | ||
1241 | return 0; | |
1242 | } | |
1243 | ||
138f97cd | 1244 | static int __init bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1245 | { |
1246 | struct device *dev = &pdev->dev; | |
1247 | struct bfin5xx_spi_master *platform_info; | |
1248 | struct spi_master *master; | |
2a045131 | 1249 | struct master_data *drv_data; |
a32c691d | 1250 | struct resource *res; |
a5f6abd4 WB |
1251 | int status = 0; |
1252 | ||
1253 | platform_info = dev->platform_data; | |
1254 | ||
1255 | /* Allocate master with space for drv_data */ | |
2a045131 | 1256 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1257 | if (!master) { |
1258 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1259 | return -ENOMEM; | |
1260 | } | |
131b17d4 | 1261 | |
a5f6abd4 WB |
1262 | drv_data = spi_master_get_devdata(master); |
1263 | drv_data->master = master; | |
1264 | drv_data->master_info = platform_info; | |
1265 | drv_data->pdev = pdev; | |
003d9226 | 1266 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1267 | |
e7db06b5 DB |
1268 | /* the spi->mode bits supported by this driver: */ |
1269 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
1270 | ||
a5f6abd4 WB |
1271 | master->bus_num = pdev->id; |
1272 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1273 | master->cleanup = bfin_spi_cleanup; |
1274 | master->setup = bfin_spi_setup; | |
1275 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1276 | |
a32c691d BW |
1277 | /* Find and map our resources */ |
1278 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1279 | if (res == NULL) { | |
1280 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1281 | status = -ENOENT; | |
1282 | goto out_error_get_res; | |
1283 | } | |
1284 | ||
74947b89 | 1285 | drv_data->regs_base = ioremap(res->start, resource_size(res)); |
f452126c | 1286 | if (drv_data->regs_base == NULL) { |
a32c691d BW |
1287 | dev_err(dev, "Cannot map IO\n"); |
1288 | status = -ENXIO; | |
1289 | goto out_error_ioremap; | |
1290 | } | |
1291 | ||
f6a6d966 YL |
1292 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1293 | if (res == NULL) { | |
a32c691d BW |
1294 | dev_err(dev, "No DMA channel specified\n"); |
1295 | status = -ENOENT; | |
f6a6d966 YL |
1296 | goto out_error_free_io; |
1297 | } | |
1298 | drv_data->dma_channel = res->start; | |
1299 | ||
1300 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1301 | if (drv_data->spi_irq < 0) { | |
1302 | dev_err(dev, "No spi pio irq specified\n"); | |
1303 | status = -ENOENT; | |
1304 | goto out_error_free_io; | |
a32c691d BW |
1305 | } |
1306 | ||
a5f6abd4 | 1307 | /* Initial and start queue */ |
138f97cd | 1308 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1309 | if (status != 0) { |
a32c691d | 1310 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1311 | goto out_error_queue_alloc; |
1312 | } | |
a32c691d | 1313 | |
138f97cd | 1314 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1315 | if (status != 0) { |
a32c691d | 1316 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1317 | goto out_error_queue_alloc; |
1318 | } | |
1319 | ||
f9e522ca VM |
1320 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1321 | if (status != 0) { | |
1322 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1323 | goto out_error_queue_alloc; | |
1324 | } | |
1325 | ||
bb8beecd WM |
1326 | /* Reset SPI registers. If these registers were used by the boot loader, |
1327 | * the sky may fall on your head if you enable the dma controller. | |
1328 | */ | |
1329 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1330 | write_FLAG(drv_data, 0xFF00); | |
1331 | ||
a5f6abd4 WB |
1332 | /* Register with the SPI framework */ |
1333 | platform_set_drvdata(pdev, drv_data); | |
1334 | status = spi_register_master(master); | |
1335 | if (status != 0) { | |
a32c691d | 1336 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1337 | goto out_error_queue_alloc; |
1338 | } | |
a32c691d | 1339 | |
f452126c | 1340 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1341 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1342 | drv_data->dma_channel); | |
a5f6abd4 WB |
1343 | return status; |
1344 | ||
cc2f81a6 | 1345 | out_error_queue_alloc: |
138f97cd | 1346 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1347 | out_error_free_io: |
bb90eb00 | 1348 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1349 | out_error_ioremap: |
1350 | out_error_get_res: | |
a5f6abd4 | 1351 | spi_master_put(master); |
cc2f81a6 | 1352 | |
a5f6abd4 WB |
1353 | return status; |
1354 | } | |
1355 | ||
1356 | /* stop hardware and remove the driver */ | |
138f97cd | 1357 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1358 | { |
b9f139a7 | 1359 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1360 | int status = 0; |
1361 | ||
1362 | if (!drv_data) | |
1363 | return 0; | |
1364 | ||
1365 | /* Remove the queue */ | |
138f97cd | 1366 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1367 | if (status != 0) |
1368 | return status; | |
1369 | ||
1370 | /* Disable the SSP at the peripheral and SOC level */ | |
1371 | bfin_spi_disable(drv_data); | |
1372 | ||
1373 | /* Release DMA */ | |
1374 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1375 | if (dma_channel_active(drv_data->dma_channel)) |
1376 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1377 | } |
1378 | ||
f6a6d966 YL |
1379 | if (drv_data->irq_requested) { |
1380 | free_irq(drv_data->spi_irq, drv_data); | |
1381 | drv_data->irq_requested = 0; | |
1382 | } | |
1383 | ||
a5f6abd4 WB |
1384 | /* Disconnect from the SPI framework */ |
1385 | spi_unregister_master(drv_data->master); | |
1386 | ||
003d9226 | 1387 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1388 | |
a5f6abd4 WB |
1389 | /* Prevent double remove */ |
1390 | platform_set_drvdata(pdev, NULL); | |
1391 | ||
1392 | return 0; | |
1393 | } | |
1394 | ||
1395 | #ifdef CONFIG_PM | |
138f97cd | 1396 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 | 1397 | { |
b9f139a7 | 1398 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1399 | int status = 0; |
1400 | ||
138f97cd | 1401 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1402 | if (status != 0) |
1403 | return status; | |
1404 | ||
b052fd0a BS |
1405 | drv_data->ctrl_reg = read_CTRL(drv_data); |
1406 | drv_data->flag_reg = read_FLAG(drv_data); | |
1407 | ||
1408 | /* | |
1409 | * reset SPI_CTL and SPI_FLG registers | |
1410 | */ | |
1411 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1412 | write_FLAG(drv_data, 0xFF00); | |
a5f6abd4 WB |
1413 | |
1414 | return 0; | |
1415 | } | |
1416 | ||
138f97cd | 1417 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 | 1418 | { |
b9f139a7 | 1419 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1420 | int status = 0; |
1421 | ||
b052fd0a BS |
1422 | write_CTRL(drv_data, drv_data->ctrl_reg); |
1423 | write_FLAG(drv_data, drv_data->flag_reg); | |
a5f6abd4 WB |
1424 | |
1425 | /* Start the queue running */ | |
138f97cd | 1426 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1427 | if (status != 0) { |
1428 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1429 | return status; | |
1430 | } | |
1431 | ||
1432 | return 0; | |
1433 | } | |
1434 | #else | |
138f97cd MF |
1435 | #define bfin_spi_suspend NULL |
1436 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1437 | #endif /* CONFIG_PM */ |
1438 | ||
7e38c3c4 | 1439 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1440 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1441 | .driver = { |
a32c691d | 1442 | .name = DRV_NAME, |
88b40369 BW |
1443 | .owner = THIS_MODULE, |
1444 | }, | |
138f97cd MF |
1445 | .suspend = bfin_spi_suspend, |
1446 | .resume = bfin_spi_resume, | |
1447 | .remove = __devexit_p(bfin_spi_remove), | |
a5f6abd4 WB |
1448 | }; |
1449 | ||
138f97cd | 1450 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1451 | { |
138f97cd | 1452 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1453 | } |
138f97cd | 1454 | module_init(bfin_spi_init); |
a5f6abd4 | 1455 | |
138f97cd | 1456 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1457 | { |
138f97cd | 1458 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1459 | } |
138f97cd | 1460 | module_exit(bfin_spi_exit); |