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Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
131b17d4 | 16 | #include <linux/io.h> |
a5f6abd4 | 17 | #include <linux/ioport.h> |
131b17d4 | 18 | #include <linux/irq.h> |
a5f6abd4 WB |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/workqueue.h> | |
a5f6abd4 | 25 | |
a5f6abd4 | 26 | #include <asm/dma.h> |
131b17d4 | 27 | #include <asm/portmux.h> |
a5f6abd4 | 28 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
29 | #include <asm/cacheflush.h> |
30 | ||
a32c691d BW |
31 | #define DRV_NAME "bfin-spi" |
32 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 33 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
34 | #define DRV_VERSION "1.0" |
35 | ||
36 | MODULE_AUTHOR(DRV_AUTHOR); | |
37 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
38 | MODULE_LICENSE("GPL"); |
39 | ||
bb90eb00 BW |
40 | #define START_STATE ((void *)0) |
41 | #define RUNNING_STATE ((void *)1) | |
42 | #define DONE_STATE ((void *)2) | |
43 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 44 | |
b9f139a7 | 45 | struct master_data; |
9c4542c7 MF |
46 | |
47 | struct transfer_ops { | |
b9f139a7 MF |
48 | void (*write) (struct master_data *); |
49 | void (*read) (struct master_data *); | |
50 | void (*duplex) (struct master_data *); | |
9c4542c7 MF |
51 | }; |
52 | ||
b9f139a7 | 53 | struct master_data { |
a5f6abd4 WB |
54 | /* Driver model hookup */ |
55 | struct platform_device *pdev; | |
56 | ||
57 | /* SPI framework hookup */ | |
58 | struct spi_master *master; | |
59 | ||
bb90eb00 | 60 | /* Regs base of SPI controller */ |
f452126c | 61 | void __iomem *regs_base; |
bb90eb00 | 62 | |
003d9226 BW |
63 | /* Pin request list */ |
64 | u16 *pin_req; | |
65 | ||
a5f6abd4 WB |
66 | /* BFIN hookup */ |
67 | struct bfin5xx_spi_master *master_info; | |
68 | ||
69 | /* Driver message queue */ | |
70 | struct workqueue_struct *workqueue; | |
71 | struct work_struct pump_messages; | |
72 | spinlock_t lock; | |
73 | struct list_head queue; | |
74 | int busy; | |
f4f50c3f | 75 | bool running; |
a5f6abd4 WB |
76 | |
77 | /* Message Transfer pump */ | |
78 | struct tasklet_struct pump_transfers; | |
79 | ||
80 | /* Current message transfer state info */ | |
81 | struct spi_message *cur_msg; | |
82 | struct spi_transfer *cur_transfer; | |
b9f139a7 | 83 | struct slave_data *cur_chip; |
a5f6abd4 WB |
84 | size_t len_in_bytes; |
85 | size_t len; | |
86 | void *tx; | |
87 | void *tx_end; | |
88 | void *rx; | |
89 | void *rx_end; | |
bb90eb00 BW |
90 | |
91 | /* DMA stuffs */ | |
92 | int dma_channel; | |
a5f6abd4 | 93 | int dma_mapped; |
bb90eb00 | 94 | int dma_requested; |
a5f6abd4 WB |
95 | dma_addr_t rx_dma; |
96 | dma_addr_t tx_dma; | |
bb90eb00 | 97 | |
f6a6d966 YL |
98 | int irq_requested; |
99 | int spi_irq; | |
100 | ||
a5f6abd4 WB |
101 | size_t rx_map_len; |
102 | size_t tx_map_len; | |
103 | u8 n_bytes; | |
fad91c89 | 104 | int cs_change; |
9c4542c7 | 105 | const struct transfer_ops *ops; |
a5f6abd4 WB |
106 | }; |
107 | ||
b9f139a7 | 108 | struct slave_data { |
a5f6abd4 WB |
109 | u16 ctl_reg; |
110 | u16 baud; | |
111 | u16 flag; | |
112 | ||
113 | u8 chip_select_num; | |
114 | u8 n_bytes; | |
88b40369 | 115 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
116 | u8 enable_dma; |
117 | u8 bits_per_word; /* 8 or 16 */ | |
62310e51 | 118 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 119 | u32 cs_gpio; |
93b61bdd | 120 | u16 idle_tx_val; |
f6a6d966 | 121 | u8 pio_interrupt; /* use spi data irq */ |
9c4542c7 | 122 | const struct transfer_ops *ops; |
a5f6abd4 WB |
123 | }; |
124 | ||
bb90eb00 | 125 | #define DEFINE_SPI_REG(reg, off) \ |
b9f139a7 | 126 | static inline u16 read_##reg(struct master_data *drv_data) \ |
bb90eb00 | 127 | { return bfin_read16(drv_data->regs_base + off); } \ |
b9f139a7 | 128 | static inline void write_##reg(struct master_data *drv_data, u16 v) \ |
bb90eb00 BW |
129 | { bfin_write16(drv_data->regs_base + off, v); } |
130 | ||
131 | DEFINE_SPI_REG(CTRL, 0x00) | |
132 | DEFINE_SPI_REG(FLAG, 0x04) | |
133 | DEFINE_SPI_REG(STAT, 0x08) | |
134 | DEFINE_SPI_REG(TDBR, 0x0C) | |
135 | DEFINE_SPI_REG(RDBR, 0x10) | |
136 | DEFINE_SPI_REG(BAUD, 0x14) | |
137 | DEFINE_SPI_REG(SHAW, 0x18) | |
138 | ||
b9f139a7 | 139 | static void bfin_spi_enable(struct master_data *drv_data) |
a5f6abd4 WB |
140 | { |
141 | u16 cr; | |
142 | ||
bb90eb00 BW |
143 | cr = read_CTRL(drv_data); |
144 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
145 | } |
146 | ||
b9f139a7 | 147 | static void bfin_spi_disable(struct master_data *drv_data) |
a5f6abd4 WB |
148 | { |
149 | u16 cr; | |
150 | ||
bb90eb00 BW |
151 | cr = read_CTRL(drv_data); |
152 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
153 | } |
154 | ||
155 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
156 | static u16 hz_to_spi_baud(u32 speed_hz) | |
157 | { | |
158 | u_long sclk = get_sclk(); | |
159 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
160 | ||
161 | if ((sclk % (2 * speed_hz)) > 0) | |
162 | spi_baud++; | |
163 | ||
7513e006 MH |
164 | if (spi_baud < MIN_SPI_BAUD_VAL) |
165 | spi_baud = MIN_SPI_BAUD_VAL; | |
166 | ||
a5f6abd4 WB |
167 | return spi_baud; |
168 | } | |
169 | ||
b9f139a7 | 170 | static int bfin_spi_flush(struct master_data *drv_data) |
a5f6abd4 WB |
171 | { |
172 | unsigned long limit = loops_per_jiffy << 1; | |
173 | ||
174 | /* wait for stop and clear stat */ | |
b4bd2aba | 175 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 176 | cpu_relax(); |
a5f6abd4 | 177 | |
bb90eb00 | 178 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
179 | |
180 | return limit; | |
181 | } | |
182 | ||
fad91c89 | 183 | /* Chip select operation functions for cs_change flag */ |
b9f139a7 | 184 | static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 185 | { |
42c78b2b MH |
186 | if (likely(chip->chip_select_num)) { |
187 | u16 flag = read_FLAG(drv_data); | |
fad91c89 | 188 | |
8221610e | 189 | flag &= ~chip->flag; |
fad91c89 | 190 | |
42c78b2b MH |
191 | write_FLAG(drv_data, flag); |
192 | } else { | |
193 | gpio_set_value(chip->cs_gpio, 0); | |
194 | } | |
fad91c89 BW |
195 | } |
196 | ||
b9f139a7 | 197 | static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 198 | { |
42c78b2b MH |
199 | if (likely(chip->chip_select_num)) { |
200 | u16 flag = read_FLAG(drv_data); | |
fad91c89 | 201 | |
8221610e | 202 | flag |= chip->flag; |
fad91c89 | 203 | |
42c78b2b MH |
204 | write_FLAG(drv_data, flag); |
205 | } else { | |
206 | gpio_set_value(chip->cs_gpio, 1); | |
207 | } | |
62310e51 BW |
208 | |
209 | /* Move delay here for consistency */ | |
210 | if (chip->cs_chg_udelay) | |
211 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
212 | } |
213 | ||
8221610e | 214 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
b9f139a7 | 215 | static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip) |
8221610e BS |
216 | { |
217 | u16 flag = read_FLAG(drv_data); | |
218 | ||
219 | flag |= (chip->flag >> 8); | |
220 | ||
221 | write_FLAG(drv_data, flag); | |
222 | } | |
223 | ||
b9f139a7 | 224 | static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip) |
8221610e BS |
225 | { |
226 | u16 flag = read_FLAG(drv_data); | |
227 | ||
228 | flag &= ~(chip->flag >> 8); | |
229 | ||
230 | write_FLAG(drv_data, flag); | |
231 | } | |
232 | ||
a5f6abd4 | 233 | /* stop controller and re-config current chip*/ |
b9f139a7 | 234 | static void bfin_spi_restore_state(struct master_data *drv_data) |
a5f6abd4 | 235 | { |
b9f139a7 | 236 | struct slave_data *chip = drv_data->cur_chip; |
12e17c42 | 237 | |
a5f6abd4 | 238 | /* Clear status and disable clock */ |
bb90eb00 | 239 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 240 | bfin_spi_disable(drv_data); |
88b40369 | 241 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 242 | |
5fec5b5a | 243 | /* Load the registers */ |
bb90eb00 | 244 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 245 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
246 | |
247 | bfin_spi_enable(drv_data); | |
138f97cd | 248 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
249 | } |
250 | ||
93b61bdd | 251 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
b9f139a7 | 252 | static inline void bfin_spi_dummy_read(struct master_data *drv_data) |
a5f6abd4 | 253 | { |
93b61bdd | 254 | (void) read_RDBR(drv_data); |
a5f6abd4 WB |
255 | } |
256 | ||
b9f139a7 | 257 | static void bfin_spi_u8_writer(struct master_data *drv_data) |
a5f6abd4 | 258 | { |
93b61bdd WM |
259 | /* clear RXS (we check for RXS inside the loop) */ |
260 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 261 | |
a5f6abd4 | 262 | while (drv_data->tx < drv_data->tx_end) { |
93b61bdd WM |
263 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
264 | /* wait until transfer finished. | |
265 | checking SPIF or TXS may not guarantee transfer completion */ | |
266 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
d8c05008 | 267 | cpu_relax(); |
93b61bdd WM |
268 | /* discard RX data and clear RXS */ |
269 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 270 | } |
a5f6abd4 WB |
271 | } |
272 | ||
b9f139a7 | 273 | static void bfin_spi_u8_reader(struct master_data *drv_data) |
a5f6abd4 | 274 | { |
93b61bdd | 275 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 276 | |
93b61bdd | 277 | /* discard old RX data and clear RXS */ |
138f97cd | 278 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 279 | |
93b61bdd WM |
280 | while (drv_data->rx < drv_data->rx_end) { |
281 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 282 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 283 | cpu_relax(); |
93b61bdd | 284 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 | 285 | } |
a5f6abd4 WB |
286 | } |
287 | ||
b9f139a7 | 288 | static void bfin_spi_u8_duplex(struct master_data *drv_data) |
a5f6abd4 | 289 | { |
93b61bdd WM |
290 | /* discard old RX data and clear RXS */ |
291 | bfin_spi_dummy_read(drv_data); | |
292 | ||
a5f6abd4 | 293 | while (drv_data->rx < drv_data->rx_end) { |
93b61bdd | 294 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 295 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 296 | cpu_relax(); |
93b61bdd | 297 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 WB |
298 | } |
299 | } | |
300 | ||
9c4542c7 MF |
301 | static const struct transfer_ops bfin_transfer_ops_u8 = { |
302 | .write = bfin_spi_u8_writer, | |
303 | .read = bfin_spi_u8_reader, | |
304 | .duplex = bfin_spi_u8_duplex, | |
305 | }; | |
306 | ||
b9f139a7 | 307 | static void bfin_spi_u16_writer(struct master_data *drv_data) |
a5f6abd4 | 308 | { |
93b61bdd WM |
309 | /* clear RXS (we check for RXS inside the loop) */ |
310 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 311 | |
a5f6abd4 | 312 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 313 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 314 | drv_data->tx += 2; |
93b61bdd WM |
315 | /* wait until transfer finished. |
316 | checking SPIF or TXS may not guarantee transfer completion */ | |
317 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
318 | cpu_relax(); | |
319 | /* discard RX data and clear RXS */ | |
320 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 321 | } |
a5f6abd4 WB |
322 | } |
323 | ||
b9f139a7 | 324 | static void bfin_spi_u16_reader(struct master_data *drv_data) |
a5f6abd4 | 325 | { |
93b61bdd | 326 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 327 | |
93b61bdd | 328 | /* discard old RX data and clear RXS */ |
138f97cd | 329 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 330 | |
93b61bdd WM |
331 | while (drv_data->rx < drv_data->rx_end) { |
332 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 333 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 334 | cpu_relax(); |
bb90eb00 | 335 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
336 | drv_data->rx += 2; |
337 | } | |
a5f6abd4 WB |
338 | } |
339 | ||
b9f139a7 | 340 | static void bfin_spi_u16_duplex(struct master_data *drv_data) |
a5f6abd4 | 341 | { |
93b61bdd WM |
342 | /* discard old RX data and clear RXS */ |
343 | bfin_spi_dummy_read(drv_data); | |
344 | ||
345 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 346 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 347 | drv_data->tx += 2; |
bb90eb00 | 348 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 349 | cpu_relax(); |
bb90eb00 | 350 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 351 | drv_data->rx += 2; |
a5f6abd4 WB |
352 | } |
353 | } | |
354 | ||
9c4542c7 MF |
355 | static const struct transfer_ops bfin_transfer_ops_u16 = { |
356 | .write = bfin_spi_u16_writer, | |
357 | .read = bfin_spi_u16_reader, | |
358 | .duplex = bfin_spi_u16_duplex, | |
359 | }; | |
360 | ||
a5f6abd4 | 361 | /* test if ther is more transfer to be done */ |
b9f139a7 | 362 | static void *bfin_spi_next_transfer(struct master_data *drv_data) |
a5f6abd4 WB |
363 | { |
364 | struct spi_message *msg = drv_data->cur_msg; | |
365 | struct spi_transfer *trans = drv_data->cur_transfer; | |
366 | ||
367 | /* Move to next transfer */ | |
368 | if (trans->transfer_list.next != &msg->transfers) { | |
369 | drv_data->cur_transfer = | |
370 | list_entry(trans->transfer_list.next, | |
371 | struct spi_transfer, transfer_list); | |
372 | return RUNNING_STATE; | |
373 | } else | |
374 | return DONE_STATE; | |
375 | } | |
376 | ||
377 | /* | |
378 | * caller already set message->status; | |
379 | * dma and pio irqs are blocked give finished message back | |
380 | */ | |
b9f139a7 | 381 | static void bfin_spi_giveback(struct master_data *drv_data) |
a5f6abd4 | 382 | { |
b9f139a7 | 383 | struct slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
384 | struct spi_transfer *last_transfer; |
385 | unsigned long flags; | |
386 | struct spi_message *msg; | |
387 | ||
388 | spin_lock_irqsave(&drv_data->lock, flags); | |
389 | msg = drv_data->cur_msg; | |
390 | drv_data->cur_msg = NULL; | |
391 | drv_data->cur_transfer = NULL; | |
392 | drv_data->cur_chip = NULL; | |
393 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
394 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
395 | ||
396 | last_transfer = list_entry(msg->transfers.prev, | |
397 | struct spi_transfer, transfer_list); | |
398 | ||
399 | msg->state = NULL; | |
400 | ||
fad91c89 | 401 | if (!drv_data->cs_change) |
138f97cd | 402 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 403 | |
b9b2a76a YL |
404 | /* Not stop spi in autobuffer mode */ |
405 | if (drv_data->tx_dma != 0xFFFF) | |
406 | bfin_spi_disable(drv_data); | |
407 | ||
a5f6abd4 WB |
408 | if (msg->complete) |
409 | msg->complete(msg->context); | |
410 | } | |
411 | ||
f6a6d966 YL |
412 | /* spi data irq handler */ |
413 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
414 | { | |
b9f139a7 MF |
415 | struct master_data *drv_data = dev_id; |
416 | struct slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
417 | struct spi_message *msg = drv_data->cur_msg; |
418 | int n_bytes = drv_data->n_bytes; | |
419 | ||
420 | /* wait until transfer finished. */ | |
421 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
422 | cpu_relax(); | |
423 | ||
424 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
425 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
426 | /* last read */ | |
427 | if (drv_data->rx) { | |
428 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
429 | if (n_bytes == 2) | |
430 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
431 | else if (n_bytes == 1) | |
432 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
433 | drv_data->rx += n_bytes; | |
434 | } | |
435 | ||
436 | msg->actual_length += drv_data->len_in_bytes; | |
437 | if (drv_data->cs_change) | |
438 | bfin_spi_cs_deactive(drv_data, chip); | |
439 | /* Move to next transfer */ | |
440 | msg->state = bfin_spi_next_transfer(drv_data); | |
441 | ||
442 | disable_irq(drv_data->spi_irq); | |
443 | ||
444 | /* Schedule transfer tasklet */ | |
445 | tasklet_schedule(&drv_data->pump_transfers); | |
446 | return IRQ_HANDLED; | |
447 | } | |
448 | ||
449 | if (drv_data->rx && drv_data->tx) { | |
450 | /* duplex */ | |
451 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
452 | if (drv_data->n_bytes == 2) { | |
453 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
454 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
455 | } else if (drv_data->n_bytes == 1) { | |
456 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
457 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
458 | } | |
459 | } else if (drv_data->rx) { | |
460 | /* read */ | |
461 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
462 | if (drv_data->n_bytes == 2) | |
463 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
464 | else if (drv_data->n_bytes == 1) | |
465 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
466 | write_TDBR(drv_data, chip->idle_tx_val); | |
467 | } else if (drv_data->tx) { | |
468 | /* write */ | |
469 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
470 | bfin_spi_dummy_read(drv_data); | |
471 | if (drv_data->n_bytes == 2) | |
472 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
473 | else if (drv_data->n_bytes == 1) | |
474 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
475 | } | |
476 | ||
477 | if (drv_data->tx) | |
478 | drv_data->tx += n_bytes; | |
479 | if (drv_data->rx) | |
480 | drv_data->rx += n_bytes; | |
481 | ||
482 | return IRQ_HANDLED; | |
483 | } | |
484 | ||
138f97cd | 485 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 486 | { |
b9f139a7 MF |
487 | struct master_data *drv_data = dev_id; |
488 | struct slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 489 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 490 | unsigned long timeout; |
d24bd1d0 | 491 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 492 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 493 | |
d24bd1d0 MF |
494 | dev_dbg(&drv_data->pdev->dev, |
495 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
496 | dmastat, spistat); | |
497 | ||
bb90eb00 | 498 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
499 | |
500 | /* | |
d6fe89b0 BW |
501 | * wait for the last transaction shifted out. HRM states: |
502 | * at this point there may still be data in the SPI DMA FIFO waiting | |
503 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
504 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
505 | */ |
506 | if (drv_data->tx != NULL) { | |
bb90eb00 BW |
507 | while ((read_STAT(drv_data) & TXS) || |
508 | (read_STAT(drv_data) & TXS)) | |
d8c05008 | 509 | cpu_relax(); |
a5f6abd4 WB |
510 | } |
511 | ||
aaaf939c MF |
512 | dev_dbg(&drv_data->pdev->dev, |
513 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
514 | dmastat, read_STAT(drv_data)); | |
515 | ||
516 | timeout = jiffies + HZ; | |
bb90eb00 | 517 | while (!(read_STAT(drv_data) & SPIF)) |
aaaf939c MF |
518 | if (!time_before(jiffies, timeout)) { |
519 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
520 | break; | |
521 | } else | |
522 | cpu_relax(); | |
a5f6abd4 | 523 | |
40a2945b | 524 | if ((dmastat & DMA_ERR) && (spistat & RBSY)) { |
04b95d2f MF |
525 | msg->state = ERROR_STATE; |
526 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
527 | } else { | |
528 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 529 | |
04b95d2f | 530 | if (drv_data->cs_change) |
138f97cd | 531 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 532 | |
04b95d2f | 533 | /* Move to next transfer */ |
138f97cd | 534 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 535 | } |
a5f6abd4 WB |
536 | |
537 | /* Schedule transfer tasklet */ | |
538 | tasklet_schedule(&drv_data->pump_transfers); | |
539 | ||
540 | /* free the irq handler before next transfer */ | |
88b40369 BW |
541 | dev_dbg(&drv_data->pdev->dev, |
542 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
543 | drv_data->dma_channel); |
544 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
545 | |
546 | return IRQ_HANDLED; | |
547 | } | |
548 | ||
138f97cd | 549 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 550 | { |
b9f139a7 | 551 | struct master_data *drv_data = (struct master_data *)data; |
a5f6abd4 WB |
552 | struct spi_message *message = NULL; |
553 | struct spi_transfer *transfer = NULL; | |
554 | struct spi_transfer *previous = NULL; | |
b9f139a7 | 555 | struct slave_data *chip = NULL; |
88b40369 BW |
556 | u8 width; |
557 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 558 | u32 tranf_success = 1; |
8eeb12e5 | 559 | u8 full_duplex = 0; |
a5f6abd4 WB |
560 | |
561 | /* Get current state information */ | |
562 | message = drv_data->cur_msg; | |
563 | transfer = drv_data->cur_transfer; | |
564 | chip = drv_data->cur_chip; | |
092e1fda | 565 | |
a5f6abd4 WB |
566 | /* |
567 | * if msg is error or done, report it back using complete() callback | |
568 | */ | |
569 | ||
570 | /* Handle for abort */ | |
571 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 572 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 573 | message->status = -EIO; |
138f97cd | 574 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
575 | return; |
576 | } | |
577 | ||
578 | /* Handle end of message */ | |
579 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 580 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 581 | message->status = 0; |
138f97cd | 582 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
583 | return; |
584 | } | |
585 | ||
586 | /* Delay if requested at end of transfer */ | |
587 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 588 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
589 | previous = list_entry(transfer->transfer_list.prev, |
590 | struct spi_transfer, transfer_list); | |
591 | if (previous->delay_usecs) | |
592 | udelay(previous->delay_usecs); | |
593 | } | |
594 | ||
ab09e040 | 595 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 596 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
597 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
598 | message->status = -EIO; | |
138f97cd | 599 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
600 | return; |
601 | } | |
602 | ||
93b61bdd WM |
603 | if (transfer->len == 0) { |
604 | /* Move to next transfer of this msg */ | |
605 | message->state = bfin_spi_next_transfer(drv_data); | |
606 | /* Schedule next transfer tasklet */ | |
607 | tasklet_schedule(&drv_data->pump_transfers); | |
608 | } | |
609 | ||
a5f6abd4 WB |
610 | if (transfer->tx_buf != NULL) { |
611 | drv_data->tx = (void *)transfer->tx_buf; | |
612 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
613 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
614 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
615 | } else { |
616 | drv_data->tx = NULL; | |
617 | } | |
618 | ||
619 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 620 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
621 | drv_data->rx = transfer->rx_buf; |
622 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
623 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
624 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
625 | } else { |
626 | drv_data->rx = NULL; | |
627 | } | |
628 | ||
629 | drv_data->rx_dma = transfer->rx_dma; | |
630 | drv_data->tx_dma = transfer->tx_dma; | |
631 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 632 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 633 | |
092e1fda BW |
634 | /* Bits per word setup */ |
635 | switch (transfer->bits_per_word) { | |
636 | case 8: | |
637 | drv_data->n_bytes = 1; | |
638 | width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 639 | drv_data->ops = &bfin_transfer_ops_u8; |
092e1fda BW |
640 | break; |
641 | ||
642 | case 16: | |
643 | drv_data->n_bytes = 2; | |
644 | width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 645 | drv_data->ops = &bfin_transfer_ops_u16; |
092e1fda BW |
646 | break; |
647 | ||
648 | default: | |
649 | /* No change, the same as default setting */ | |
f6a6d966 | 650 | transfer->bits_per_word = chip->bits_per_word; |
092e1fda BW |
651 | drv_data->n_bytes = chip->n_bytes; |
652 | width = chip->width; | |
9c4542c7 | 653 | drv_data->ops = chip->ops; |
092e1fda BW |
654 | break; |
655 | } | |
656 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
657 | cr |= (width << 8); | |
658 | write_CTRL(drv_data, cr); | |
659 | ||
a5f6abd4 WB |
660 | if (width == CFG_SPI_WORDSIZE16) { |
661 | drv_data->len = (transfer->len) >> 1; | |
662 | } else { | |
663 | drv_data->len = transfer->len; | |
664 | } | |
4fb98efa | 665 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 MF |
666 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
667 | drv_data->ops, chip->ops, &bfin_transfer_ops_u8); | |
a5f6abd4 | 668 | |
a5f6abd4 WB |
669 | message->state = RUNNING_STATE; |
670 | dma_config = 0; | |
671 | ||
092e1fda BW |
672 | /* Speed setup (surely valid because already checked) */ |
673 | if (transfer->speed_hz) | |
674 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
675 | else | |
676 | write_BAUD(drv_data, chip->baud); | |
677 | ||
bb90eb00 BW |
678 | write_STAT(drv_data, BIT_STAT_CLR); |
679 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
b9b2a76a | 680 | if (drv_data->cs_change) |
138f97cd | 681 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 682 | |
88b40369 BW |
683 | dev_dbg(&drv_data->pdev->dev, |
684 | "now pumping a transfer: width is %d, len is %d\n", | |
685 | width, transfer->len); | |
a5f6abd4 WB |
686 | |
687 | /* | |
8cf5858c VM |
688 | * Try to map dma buffer and do a dma transfer. If successful use, |
689 | * different way to r/w according to the enable_dma settings and if | |
690 | * we are not doing a full duplex transfer (since the hardware does | |
691 | * not support full duplex DMA transfers). | |
a5f6abd4 | 692 | */ |
8eeb12e5 VM |
693 | if (!full_duplex && drv_data->cur_chip->enable_dma |
694 | && drv_data->len > 6) { | |
a5f6abd4 | 695 | |
11d6f599 | 696 | unsigned long dma_start_addr, flags; |
7aec3566 | 697 | |
bb90eb00 BW |
698 | disable_dma(drv_data->dma_channel); |
699 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
700 | |
701 | /* config dma channel */ | |
88b40369 | 702 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 703 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 | 704 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 | 705 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
706 | dma_width = WDSIZE_16; |
707 | } else { | |
bb90eb00 | 708 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
709 | dma_width = WDSIZE_8; |
710 | } | |
711 | ||
3f479a65 | 712 | /* poll for SPI completion before start */ |
bb90eb00 | 713 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 714 | cpu_relax(); |
3f479a65 | 715 | |
a5f6abd4 WB |
716 | /* dirty hack for autobuffer DMA mode */ |
717 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
718 | dev_dbg(&drv_data->pdev->dev, |
719 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
720 | |
721 | /* no irq in autobuffer mode */ | |
722 | dma_config = | |
723 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
724 | set_dma_config(drv_data->dma_channel, dma_config); |
725 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 726 | (unsigned long)drv_data->tx); |
bb90eb00 | 727 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 728 | |
07612e5f | 729 | /* start SPI transfer */ |
11d6f599 | 730 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
731 | |
732 | /* just return here, there can only be one transfer | |
733 | * in this mode | |
734 | */ | |
a5f6abd4 | 735 | message->status = 0; |
138f97cd | 736 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
737 | return; |
738 | } | |
739 | ||
740 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 741 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
742 | if (drv_data->rx != NULL) { |
743 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
744 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
745 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 746 | |
8cf5858c | 747 | /* invalidate caches, if needed */ |
67834fa9 | 748 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
749 | invalidate_dcache_range((unsigned long) drv_data->rx, |
750 | (unsigned long) (drv_data->rx + | |
ace32865 | 751 | drv_data->len_in_bytes)); |
8cf5858c | 752 | |
7aec3566 MF |
753 | dma_config |= WNR; |
754 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 755 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 756 | |
a5f6abd4 | 757 | } else if (drv_data->tx != NULL) { |
88b40369 | 758 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 759 | |
8cf5858c | 760 | /* flush caches, if needed */ |
67834fa9 | 761 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
762 | flush_dcache_range((unsigned long) drv_data->tx, |
763 | (unsigned long) (drv_data->tx + | |
ace32865 | 764 | drv_data->len_in_bytes)); |
8cf5858c | 765 | |
7aec3566 | 766 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 767 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
768 | |
769 | } else | |
770 | BUG(); | |
771 | ||
11d6f599 MF |
772 | /* oh man, here there be monsters ... and i dont mean the |
773 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
774 | * your data, kick your dog, and love it all. do *not* try | |
775 | * and change these lines unless you (1) heavily test DMA | |
776 | * with SPI flashes on a loaded system (e.g. ping floods), | |
777 | * (2) know just how broken the DMA engine interaction with | |
778 | * the SPI peripheral is, and (3) have someone else to blame | |
779 | * when you screw it all up anyways. | |
780 | */ | |
7aec3566 | 781 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
782 | set_dma_config(drv_data->dma_channel, dma_config); |
783 | local_irq_save(flags); | |
a963ea83 | 784 | SSYNC(); |
11d6f599 | 785 | write_CTRL(drv_data, cr); |
a963ea83 | 786 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
787 | dma_enable_irq(drv_data->dma_channel); |
788 | local_irq_restore(flags); | |
07612e5f | 789 | |
f6a6d966 YL |
790 | return; |
791 | } | |
a5f6abd4 | 792 | |
f6a6d966 YL |
793 | if (chip->pio_interrupt) { |
794 | /* use write mode. spi irq should have been disabled */ | |
795 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
93b61bdd WM |
796 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
797 | ||
f6a6d966 YL |
798 | /* discard old RX data and clear RXS */ |
799 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 800 | |
f6a6d966 YL |
801 | /* start transfer */ |
802 | if (drv_data->tx == NULL) | |
803 | write_TDBR(drv_data, chip->idle_tx_val); | |
804 | else { | |
805 | if (transfer->bits_per_word == 8) | |
806 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
807 | else if (transfer->bits_per_word == 16) | |
808 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
809 | drv_data->tx += drv_data->n_bytes; | |
810 | } | |
a5f6abd4 | 811 | |
f6a6d966 YL |
812 | /* once TDBR is empty, interrupt is triggered */ |
813 | enable_irq(drv_data->spi_irq); | |
814 | return; | |
815 | } | |
a5f6abd4 | 816 | |
f6a6d966 YL |
817 | /* IO mode */ |
818 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
819 | ||
820 | /* we always use SPI_WRITE mode. SPI_READ mode | |
821 | seems to have problems with setting up the | |
822 | output value in TDBR prior to the transfer. */ | |
823 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); | |
824 | ||
825 | if (full_duplex) { | |
826 | /* full duplex mode */ | |
827 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
828 | (drv_data->rx_end - drv_data->rx)); | |
829 | dev_dbg(&drv_data->pdev->dev, | |
830 | "IO duplex: cr is 0x%x\n", cr); | |
831 | ||
9c4542c7 | 832 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
833 | |
834 | if (drv_data->tx != drv_data->tx_end) | |
835 | tranf_success = 0; | |
836 | } else if (drv_data->tx != NULL) { | |
837 | /* write only half duplex */ | |
838 | dev_dbg(&drv_data->pdev->dev, | |
839 | "IO write: cr is 0x%x\n", cr); | |
840 | ||
9c4542c7 | 841 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
842 | |
843 | if (drv_data->tx != drv_data->tx_end) | |
844 | tranf_success = 0; | |
845 | } else if (drv_data->rx != NULL) { | |
846 | /* read only half duplex */ | |
847 | dev_dbg(&drv_data->pdev->dev, | |
848 | "IO read: cr is 0x%x\n", cr); | |
849 | ||
9c4542c7 | 850 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
851 | if (drv_data->rx != drv_data->rx_end) |
852 | tranf_success = 0; | |
853 | } | |
a5f6abd4 | 854 | |
f6a6d966 YL |
855 | if (!tranf_success) { |
856 | dev_dbg(&drv_data->pdev->dev, | |
857 | "IO write error!\n"); | |
858 | message->state = ERROR_STATE; | |
859 | } else { | |
860 | /* Update total byte transfered */ | |
861 | message->actual_length += drv_data->len_in_bytes; | |
862 | /* Move to next transfer of this msg */ | |
863 | message->state = bfin_spi_next_transfer(drv_data); | |
864 | if (drv_data->cs_change) | |
865 | bfin_spi_cs_deactive(drv_data, chip); | |
a5f6abd4 | 866 | } |
f6a6d966 YL |
867 | |
868 | /* Schedule next transfer tasklet */ | |
869 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
870 | } |
871 | ||
872 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 873 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 874 | { |
b9f139a7 | 875 | struct master_data *drv_data; |
a5f6abd4 WB |
876 | unsigned long flags; |
877 | ||
b9f139a7 | 878 | drv_data = container_of(work, struct master_data, pump_messages); |
131b17d4 | 879 | |
a5f6abd4 WB |
880 | /* Lock queue and check for queue work */ |
881 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 882 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
883 | /* pumper kicked off but no work to do */ |
884 | drv_data->busy = 0; | |
885 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
886 | return; | |
887 | } | |
888 | ||
889 | /* Make sure we are not already running a message */ | |
890 | if (drv_data->cur_msg) { | |
891 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
892 | return; | |
893 | } | |
894 | ||
895 | /* Extract head of queue */ | |
896 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
897 | struct spi_message, queue); | |
5fec5b5a BW |
898 | |
899 | /* Setup the SSP using the per chip configuration */ | |
900 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 901 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 902 | |
a5f6abd4 WB |
903 | list_del_init(&drv_data->cur_msg->queue); |
904 | ||
905 | /* Initial message state */ | |
906 | drv_data->cur_msg->state = START_STATE; | |
907 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
908 | struct spi_transfer, transfer_list); | |
909 | ||
5fec5b5a BW |
910 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
911 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
912 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
913 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
914 | |
915 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
916 | "the first transfer len is %d\n", |
917 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
918 | |
919 | /* Mark as busy and launch transfers */ | |
920 | tasklet_schedule(&drv_data->pump_transfers); | |
921 | ||
922 | drv_data->busy = 1; | |
923 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
924 | } | |
925 | ||
926 | /* | |
927 | * got a msg to transfer, queue it in drv_data->queue. | |
928 | * And kick off message pumper | |
929 | */ | |
138f97cd | 930 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 931 | { |
b9f139a7 | 932 | struct master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
933 | unsigned long flags; |
934 | ||
935 | spin_lock_irqsave(&drv_data->lock, flags); | |
936 | ||
f4f50c3f | 937 | if (!drv_data->running) { |
a5f6abd4 WB |
938 | spin_unlock_irqrestore(&drv_data->lock, flags); |
939 | return -ESHUTDOWN; | |
940 | } | |
941 | ||
942 | msg->actual_length = 0; | |
943 | msg->status = -EINPROGRESS; | |
944 | msg->state = START_STATE; | |
945 | ||
88b40369 | 946 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
947 | list_add_tail(&msg->queue, &drv_data->queue); |
948 | ||
f4f50c3f | 949 | if (drv_data->running && !drv_data->busy) |
a5f6abd4 WB |
950 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
951 | ||
952 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
12e17c42 SZ |
957 | #define MAX_SPI_SSEL 7 |
958 | ||
4160bde2 | 959 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
960 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
961 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
962 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
963 | ||
964 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
965 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
966 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
967 | ||
968 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
969 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
970 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
971 | }; | |
972 | ||
ab09e040 | 973 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 974 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 975 | { |
ac01e97d | 976 | struct bfin5xx_spi_chip *chip_info; |
b9f139a7 MF |
977 | struct slave_data *chip = NULL; |
978 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
ac01e97d | 979 | int ret = -EINVAL; |
a5f6abd4 | 980 | |
a5f6abd4 | 981 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) |
ac01e97d | 982 | goto error; |
a5f6abd4 WB |
983 | |
984 | /* Only alloc (or use chip_info) on first setup */ | |
ac01e97d | 985 | chip_info = NULL; |
a5f6abd4 WB |
986 | chip = spi_get_ctldata(spi); |
987 | if (chip == NULL) { | |
ac01e97d DM |
988 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
989 | if (!chip) { | |
990 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
991 | ret = -ENOMEM; | |
992 | goto error; | |
993 | } | |
a5f6abd4 WB |
994 | |
995 | chip->enable_dma = 0; | |
996 | chip_info = spi->controller_data; | |
997 | } | |
998 | ||
999 | /* chip_info isn't always needed */ | |
1000 | if (chip_info) { | |
2ed35516 MF |
1001 | /* Make sure people stop trying to set fields via ctl_reg |
1002 | * when they should actually be using common SPI framework. | |
1003 | * Currently we let through: WOM EMISO PSSE GM SZ TIMOD. | |
1004 | * Not sure if a user actually needs/uses any of these, | |
1005 | * but let's assume (for now) they do. | |
1006 | */ | |
1007 | if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) { | |
1008 | dev_err(&spi->dev, "do not set bits in ctl_reg " | |
1009 | "that the SPI framework manages\n"); | |
ac01e97d | 1010 | goto error; |
2ed35516 MF |
1011 | } |
1012 | ||
a5f6abd4 WB |
1013 | chip->enable_dma = chip_info->enable_dma != 0 |
1014 | && drv_data->master_info->enable_dma; | |
1015 | chip->ctl_reg = chip_info->ctl_reg; | |
1016 | chip->bits_per_word = chip_info->bits_per_word; | |
a5f6abd4 | 1017 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
42c78b2b | 1018 | chip->cs_gpio = chip_info->cs_gpio; |
93b61bdd | 1019 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1020 | chip->pio_interrupt = chip_info->pio_interrupt; |
a5f6abd4 WB |
1021 | } |
1022 | ||
1023 | /* translate common spi framework into our register */ | |
1024 | if (spi->mode & SPI_CPOL) | |
1025 | chip->ctl_reg |= CPOL; | |
1026 | if (spi->mode & SPI_CPHA) | |
1027 | chip->ctl_reg |= CPHA; | |
1028 | if (spi->mode & SPI_LSB_FIRST) | |
1029 | chip->ctl_reg |= LSBF; | |
1030 | /* we dont support running in slave mode (yet?) */ | |
1031 | chip->ctl_reg |= MSTR; | |
1032 | ||
a5f6abd4 WB |
1033 | /* |
1034 | * Notice: for blackfin, the speed_hz is the value of register | |
1035 | * SPI_BAUD, not the real baudrate | |
1036 | */ | |
1037 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
8221610e | 1038 | chip->flag = (1 << (spi->chip_select)) << 8; |
a5f6abd4 WB |
1039 | chip->chip_select_num = spi->chip_select; |
1040 | ||
1041 | switch (chip->bits_per_word) { | |
1042 | case 8: | |
1043 | chip->n_bytes = 1; | |
1044 | chip->width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 1045 | chip->ops = &bfin_transfer_ops_u8; |
a5f6abd4 WB |
1046 | break; |
1047 | ||
1048 | case 16: | |
1049 | chip->n_bytes = 2; | |
1050 | chip->width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 1051 | chip->ops = &bfin_transfer_ops_u16; |
a5f6abd4 WB |
1052 | break; |
1053 | ||
1054 | default: | |
1055 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1056 | chip->bits_per_word); | |
ac01e97d DM |
1057 | goto error; |
1058 | } | |
1059 | ||
f6a6d966 YL |
1060 | if (chip->enable_dma && chip->pio_interrupt) { |
1061 | dev_err(&spi->dev, "enable_dma is set, " | |
1062 | "do not set pio_interrupt\n"); | |
1063 | goto error; | |
1064 | } | |
ac01e97d DM |
1065 | /* |
1066 | * if any one SPI chip is registered and wants DMA, request the | |
1067 | * DMA channel for it | |
1068 | */ | |
1069 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1070 | /* register dma irq handler */ | |
1071 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1072 | if (ret) { | |
1073 | dev_err(&spi->dev, | |
1074 | "Unable to request BlackFin SPI DMA channel\n"); | |
1075 | goto error; | |
1076 | } | |
1077 | drv_data->dma_requested = 1; | |
1078 | ||
1079 | ret = set_dma_callback(drv_data->dma_channel, | |
1080 | bfin_spi_dma_irq_handler, drv_data); | |
1081 | if (ret) { | |
1082 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1083 | goto error; | |
1084 | } | |
1085 | dma_disable_irq(drv_data->dma_channel); | |
1086 | } | |
1087 | ||
f6a6d966 YL |
1088 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1089 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
1090 | IRQF_DISABLED, "BFIN_SPI", drv_data); | |
1091 | if (ret) { | |
1092 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1093 | goto error; | |
1094 | } | |
1095 | drv_data->irq_requested = 1; | |
1096 | /* we use write mode, spi irq has to be disabled here */ | |
1097 | disable_irq(drv_data->spi_irq); | |
1098 | } | |
1099 | ||
ac01e97d DM |
1100 | if (chip->chip_select_num == 0) { |
1101 | ret = gpio_request(chip->cs_gpio, spi->modalias); | |
1102 | if (ret) { | |
1103 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1104 | goto pin_error; | |
1105 | } | |
1106 | gpio_direction_output(chip->cs_gpio, 1); | |
a5f6abd4 WB |
1107 | } |
1108 | ||
898eb71c | 1109 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1110 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1111 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1112 | chip->ctl_reg, chip->flag); |
1113 | ||
1114 | spi_set_ctldata(spi, chip); | |
1115 | ||
12e17c42 | 1116 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
ac01e97d DM |
1117 | if (chip->chip_select_num > 0 && |
1118 | chip->chip_select_num <= spi->master->num_chipselect) { | |
1119 | ret = peripheral_request(ssel[spi->master->bus_num] | |
1120 | [chip->chip_select_num-1], spi->modalias); | |
1121 | if (ret) { | |
1122 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1123 | goto pin_error; | |
1124 | } | |
1125 | } | |
12e17c42 | 1126 | |
8221610e | 1127 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1128 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1129 | |
a5f6abd4 | 1130 | return 0; |
ac01e97d DM |
1131 | |
1132 | pin_error: | |
1133 | if (chip->chip_select_num == 0) | |
1134 | gpio_free(chip->cs_gpio); | |
1135 | else | |
1136 | peripheral_free(ssel[spi->master->bus_num] | |
1137 | [chip->chip_select_num - 1]); | |
1138 | error: | |
1139 | if (chip) { | |
1140 | if (drv_data->dma_requested) | |
1141 | free_dma(drv_data->dma_channel); | |
1142 | drv_data->dma_requested = 0; | |
1143 | ||
1144 | kfree(chip); | |
1145 | /* prevent free 'chip' twice */ | |
1146 | spi_set_ctldata(spi, NULL); | |
1147 | } | |
1148 | ||
1149 | return ret; | |
a5f6abd4 WB |
1150 | } |
1151 | ||
1152 | /* | |
1153 | * callback for spi framework. | |
1154 | * clean driver specific data | |
1155 | */ | |
138f97cd | 1156 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1157 | { |
b9f139a7 MF |
1158 | struct slave_data *chip = spi_get_ctldata(spi); |
1159 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1160 | |
e7d02e3c MF |
1161 | if (!chip) |
1162 | return; | |
1163 | ||
12e17c42 | 1164 | if ((chip->chip_select_num > 0) |
8221610e | 1165 | && (chip->chip_select_num <= spi->master->num_chipselect)) { |
12e17c42 SZ |
1166 | peripheral_free(ssel[spi->master->bus_num] |
1167 | [chip->chip_select_num-1]); | |
8221610e BS |
1168 | bfin_spi_cs_disable(drv_data, chip); |
1169 | } | |
12e17c42 | 1170 | |
42c78b2b MH |
1171 | if (chip->chip_select_num == 0) |
1172 | gpio_free(chip->cs_gpio); | |
1173 | ||
a5f6abd4 | 1174 | kfree(chip); |
ac01e97d DM |
1175 | /* prevent free 'chip' twice */ |
1176 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1177 | } |
1178 | ||
b9f139a7 | 1179 | static inline int bfin_spi_init_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1180 | { |
1181 | INIT_LIST_HEAD(&drv_data->queue); | |
1182 | spin_lock_init(&drv_data->lock); | |
1183 | ||
f4f50c3f | 1184 | drv_data->running = false; |
a5f6abd4 WB |
1185 | drv_data->busy = 0; |
1186 | ||
1187 | /* init transfer tasklet */ | |
1188 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1189 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1190 | |
1191 | /* init messages workqueue */ | |
138f97cd | 1192 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1193 | drv_data->workqueue = create_singlethread_workqueue( |
1194 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1195 | if (drv_data->workqueue == NULL) |
1196 | return -EBUSY; | |
1197 | ||
1198 | return 0; | |
1199 | } | |
1200 | ||
b9f139a7 | 1201 | static inline int bfin_spi_start_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1202 | { |
1203 | unsigned long flags; | |
1204 | ||
1205 | spin_lock_irqsave(&drv_data->lock, flags); | |
1206 | ||
f4f50c3f | 1207 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1208 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1209 | return -EBUSY; | |
1210 | } | |
1211 | ||
f4f50c3f | 1212 | drv_data->running = true; |
a5f6abd4 WB |
1213 | drv_data->cur_msg = NULL; |
1214 | drv_data->cur_transfer = NULL; | |
1215 | drv_data->cur_chip = NULL; | |
1216 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1217 | ||
1218 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1219 | ||
1220 | return 0; | |
1221 | } | |
1222 | ||
b9f139a7 | 1223 | static inline int bfin_spi_stop_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1224 | { |
1225 | unsigned long flags; | |
1226 | unsigned limit = 500; | |
1227 | int status = 0; | |
1228 | ||
1229 | spin_lock_irqsave(&drv_data->lock, flags); | |
1230 | ||
1231 | /* | |
1232 | * This is a bit lame, but is optimized for the common execution path. | |
1233 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1234 | * execution path (pump_messages) would be required to call wake_up or | |
1235 | * friends on every SPI message. Do this instead | |
1236 | */ | |
f4f50c3f | 1237 | drv_data->running = false; |
a5f6abd4 WB |
1238 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { |
1239 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1240 | msleep(10); | |
1241 | spin_lock_irqsave(&drv_data->lock, flags); | |
1242 | } | |
1243 | ||
1244 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1245 | status = -EBUSY; | |
1246 | ||
1247 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1248 | ||
1249 | return status; | |
1250 | } | |
1251 | ||
b9f139a7 | 1252 | static inline int bfin_spi_destroy_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1253 | { |
1254 | int status; | |
1255 | ||
138f97cd | 1256 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1257 | if (status != 0) |
1258 | return status; | |
1259 | ||
1260 | destroy_workqueue(drv_data->workqueue); | |
1261 | ||
1262 | return 0; | |
1263 | } | |
1264 | ||
138f97cd | 1265 | static int __init bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1266 | { |
1267 | struct device *dev = &pdev->dev; | |
1268 | struct bfin5xx_spi_master *platform_info; | |
1269 | struct spi_master *master; | |
2a045131 | 1270 | struct master_data *drv_data; |
a32c691d | 1271 | struct resource *res; |
a5f6abd4 WB |
1272 | int status = 0; |
1273 | ||
1274 | platform_info = dev->platform_data; | |
1275 | ||
1276 | /* Allocate master with space for drv_data */ | |
2a045131 | 1277 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1278 | if (!master) { |
1279 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1280 | return -ENOMEM; | |
1281 | } | |
131b17d4 | 1282 | |
a5f6abd4 WB |
1283 | drv_data = spi_master_get_devdata(master); |
1284 | drv_data->master = master; | |
1285 | drv_data->master_info = platform_info; | |
1286 | drv_data->pdev = pdev; | |
003d9226 | 1287 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1288 | |
e7db06b5 DB |
1289 | /* the spi->mode bits supported by this driver: */ |
1290 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
1291 | ||
a5f6abd4 WB |
1292 | master->bus_num = pdev->id; |
1293 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1294 | master->cleanup = bfin_spi_cleanup; |
1295 | master->setup = bfin_spi_setup; | |
1296 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1297 | |
a32c691d BW |
1298 | /* Find and map our resources */ |
1299 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1300 | if (res == NULL) { | |
1301 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1302 | status = -ENOENT; | |
1303 | goto out_error_get_res; | |
1304 | } | |
1305 | ||
74947b89 | 1306 | drv_data->regs_base = ioremap(res->start, resource_size(res)); |
f452126c | 1307 | if (drv_data->regs_base == NULL) { |
a32c691d BW |
1308 | dev_err(dev, "Cannot map IO\n"); |
1309 | status = -ENXIO; | |
1310 | goto out_error_ioremap; | |
1311 | } | |
1312 | ||
f6a6d966 YL |
1313 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1314 | if (res == NULL) { | |
a32c691d BW |
1315 | dev_err(dev, "No DMA channel specified\n"); |
1316 | status = -ENOENT; | |
f6a6d966 YL |
1317 | goto out_error_free_io; |
1318 | } | |
1319 | drv_data->dma_channel = res->start; | |
1320 | ||
1321 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1322 | if (drv_data->spi_irq < 0) { | |
1323 | dev_err(dev, "No spi pio irq specified\n"); | |
1324 | status = -ENOENT; | |
1325 | goto out_error_free_io; | |
a32c691d BW |
1326 | } |
1327 | ||
a5f6abd4 | 1328 | /* Initial and start queue */ |
138f97cd | 1329 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1330 | if (status != 0) { |
a32c691d | 1331 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1332 | goto out_error_queue_alloc; |
1333 | } | |
a32c691d | 1334 | |
138f97cd | 1335 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1336 | if (status != 0) { |
a32c691d | 1337 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1338 | goto out_error_queue_alloc; |
1339 | } | |
1340 | ||
f9e522ca VM |
1341 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1342 | if (status != 0) { | |
1343 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1344 | goto out_error_queue_alloc; | |
1345 | } | |
1346 | ||
bb8beecd WM |
1347 | /* Reset SPI registers. If these registers were used by the boot loader, |
1348 | * the sky may fall on your head if you enable the dma controller. | |
1349 | */ | |
1350 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1351 | write_FLAG(drv_data, 0xFF00); | |
1352 | ||
a5f6abd4 WB |
1353 | /* Register with the SPI framework */ |
1354 | platform_set_drvdata(pdev, drv_data); | |
1355 | status = spi_register_master(master); | |
1356 | if (status != 0) { | |
a32c691d | 1357 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1358 | goto out_error_queue_alloc; |
1359 | } | |
a32c691d | 1360 | |
f452126c | 1361 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1362 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1363 | drv_data->dma_channel); | |
a5f6abd4 WB |
1364 | return status; |
1365 | ||
cc2f81a6 | 1366 | out_error_queue_alloc: |
138f97cd | 1367 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1368 | out_error_free_io: |
bb90eb00 | 1369 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1370 | out_error_ioremap: |
1371 | out_error_get_res: | |
a5f6abd4 | 1372 | spi_master_put(master); |
cc2f81a6 | 1373 | |
a5f6abd4 WB |
1374 | return status; |
1375 | } | |
1376 | ||
1377 | /* stop hardware and remove the driver */ | |
138f97cd | 1378 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1379 | { |
b9f139a7 | 1380 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1381 | int status = 0; |
1382 | ||
1383 | if (!drv_data) | |
1384 | return 0; | |
1385 | ||
1386 | /* Remove the queue */ | |
138f97cd | 1387 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1388 | if (status != 0) |
1389 | return status; | |
1390 | ||
1391 | /* Disable the SSP at the peripheral and SOC level */ | |
1392 | bfin_spi_disable(drv_data); | |
1393 | ||
1394 | /* Release DMA */ | |
1395 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1396 | if (dma_channel_active(drv_data->dma_channel)) |
1397 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1398 | } |
1399 | ||
f6a6d966 YL |
1400 | if (drv_data->irq_requested) { |
1401 | free_irq(drv_data->spi_irq, drv_data); | |
1402 | drv_data->irq_requested = 0; | |
1403 | } | |
1404 | ||
a5f6abd4 WB |
1405 | /* Disconnect from the SPI framework */ |
1406 | spi_unregister_master(drv_data->master); | |
1407 | ||
003d9226 | 1408 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1409 | |
a5f6abd4 WB |
1410 | /* Prevent double remove */ |
1411 | platform_set_drvdata(pdev, NULL); | |
1412 | ||
1413 | return 0; | |
1414 | } | |
1415 | ||
1416 | #ifdef CONFIG_PM | |
138f97cd | 1417 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 | 1418 | { |
b9f139a7 | 1419 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1420 | int status = 0; |
1421 | ||
138f97cd | 1422 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1423 | if (status != 0) |
1424 | return status; | |
1425 | ||
1426 | /* stop hardware */ | |
1427 | bfin_spi_disable(drv_data); | |
1428 | ||
1429 | return 0; | |
1430 | } | |
1431 | ||
138f97cd | 1432 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 | 1433 | { |
b9f139a7 | 1434 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1435 | int status = 0; |
1436 | ||
1437 | /* Enable the SPI interface */ | |
1438 | bfin_spi_enable(drv_data); | |
1439 | ||
1440 | /* Start the queue running */ | |
138f97cd | 1441 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1442 | if (status != 0) { |
1443 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1444 | return status; | |
1445 | } | |
1446 | ||
1447 | return 0; | |
1448 | } | |
1449 | #else | |
138f97cd MF |
1450 | #define bfin_spi_suspend NULL |
1451 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1452 | #endif /* CONFIG_PM */ |
1453 | ||
7e38c3c4 | 1454 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1455 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1456 | .driver = { |
a32c691d | 1457 | .name = DRV_NAME, |
88b40369 BW |
1458 | .owner = THIS_MODULE, |
1459 | }, | |
138f97cd MF |
1460 | .suspend = bfin_spi_suspend, |
1461 | .resume = bfin_spi_resume, | |
1462 | .remove = __devexit_p(bfin_spi_remove), | |
a5f6abd4 WB |
1463 | }; |
1464 | ||
138f97cd | 1465 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1466 | { |
138f97cd | 1467 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1468 | } |
138f97cd | 1469 | module_init(bfin_spi_init); |
a5f6abd4 | 1470 | |
138f97cd | 1471 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1472 | { |
138f97cd | 1473 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1474 | } |
138f97cd | 1475 | module_exit(bfin_spi_exit); |