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Commit | Line | Data |
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a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
131b17d4 | 16 | #include <linux/io.h> |
a5f6abd4 | 17 | #include <linux/ioport.h> |
131b17d4 | 18 | #include <linux/irq.h> |
a5f6abd4 WB |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/workqueue.h> | |
a5f6abd4 | 25 | |
a5f6abd4 | 26 | #include <asm/dma.h> |
131b17d4 | 27 | #include <asm/portmux.h> |
a5f6abd4 | 28 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
29 | #include <asm/cacheflush.h> |
30 | ||
a32c691d BW |
31 | #define DRV_NAME "bfin-spi" |
32 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 33 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
34 | #define DRV_VERSION "1.0" |
35 | ||
36 | MODULE_AUTHOR(DRV_AUTHOR); | |
37 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
38 | MODULE_LICENSE("GPL"); |
39 | ||
bb90eb00 BW |
40 | #define START_STATE ((void *)0) |
41 | #define RUNNING_STATE ((void *)1) | |
42 | #define DONE_STATE ((void *)2) | |
43 | #define ERROR_STATE ((void *)-1) | |
44 | #define QUEUE_RUNNING 0 | |
45 | #define QUEUE_STOPPED 1 | |
a5f6abd4 | 46 | |
93b61bdd WM |
47 | /* Value to send if no TX value is supplied */ |
48 | #define SPI_IDLE_TXVAL 0x0000 | |
49 | ||
a5f6abd4 WB |
50 | struct driver_data { |
51 | /* Driver model hookup */ | |
52 | struct platform_device *pdev; | |
53 | ||
54 | /* SPI framework hookup */ | |
55 | struct spi_master *master; | |
56 | ||
bb90eb00 | 57 | /* Regs base of SPI controller */ |
f452126c | 58 | void __iomem *regs_base; |
bb90eb00 | 59 | |
003d9226 BW |
60 | /* Pin request list */ |
61 | u16 *pin_req; | |
62 | ||
a5f6abd4 WB |
63 | /* BFIN hookup */ |
64 | struct bfin5xx_spi_master *master_info; | |
65 | ||
66 | /* Driver message queue */ | |
67 | struct workqueue_struct *workqueue; | |
68 | struct work_struct pump_messages; | |
69 | spinlock_t lock; | |
70 | struct list_head queue; | |
71 | int busy; | |
72 | int run; | |
73 | ||
74 | /* Message Transfer pump */ | |
75 | struct tasklet_struct pump_transfers; | |
76 | ||
77 | /* Current message transfer state info */ | |
78 | struct spi_message *cur_msg; | |
79 | struct spi_transfer *cur_transfer; | |
80 | struct chip_data *cur_chip; | |
81 | size_t len_in_bytes; | |
82 | size_t len; | |
83 | void *tx; | |
84 | void *tx_end; | |
85 | void *rx; | |
86 | void *rx_end; | |
bb90eb00 BW |
87 | |
88 | /* DMA stuffs */ | |
89 | int dma_channel; | |
a5f6abd4 | 90 | int dma_mapped; |
bb90eb00 | 91 | int dma_requested; |
a5f6abd4 WB |
92 | dma_addr_t rx_dma; |
93 | dma_addr_t tx_dma; | |
bb90eb00 | 94 | |
a5f6abd4 WB |
95 | size_t rx_map_len; |
96 | size_t tx_map_len; | |
97 | u8 n_bytes; | |
fad91c89 | 98 | int cs_change; |
a5f6abd4 WB |
99 | void (*write) (struct driver_data *); |
100 | void (*read) (struct driver_data *); | |
101 | void (*duplex) (struct driver_data *); | |
102 | }; | |
103 | ||
104 | struct chip_data { | |
105 | u16 ctl_reg; | |
106 | u16 baud; | |
107 | u16 flag; | |
108 | ||
109 | u8 chip_select_num; | |
110 | u8 n_bytes; | |
88b40369 | 111 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
112 | u8 enable_dma; |
113 | u8 bits_per_word; /* 8 or 16 */ | |
114 | u8 cs_change_per_word; | |
62310e51 | 115 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 116 | u32 cs_gpio; |
93b61bdd | 117 | u16 idle_tx_val; |
a5f6abd4 WB |
118 | void (*write) (struct driver_data *); |
119 | void (*read) (struct driver_data *); | |
120 | void (*duplex) (struct driver_data *); | |
121 | }; | |
122 | ||
bb90eb00 BW |
123 | #define DEFINE_SPI_REG(reg, off) \ |
124 | static inline u16 read_##reg(struct driver_data *drv_data) \ | |
125 | { return bfin_read16(drv_data->regs_base + off); } \ | |
126 | static inline void write_##reg(struct driver_data *drv_data, u16 v) \ | |
127 | { bfin_write16(drv_data->regs_base + off, v); } | |
128 | ||
129 | DEFINE_SPI_REG(CTRL, 0x00) | |
130 | DEFINE_SPI_REG(FLAG, 0x04) | |
131 | DEFINE_SPI_REG(STAT, 0x08) | |
132 | DEFINE_SPI_REG(TDBR, 0x0C) | |
133 | DEFINE_SPI_REG(RDBR, 0x10) | |
134 | DEFINE_SPI_REG(BAUD, 0x14) | |
135 | DEFINE_SPI_REG(SHAW, 0x18) | |
136 | ||
88b40369 | 137 | static void bfin_spi_enable(struct driver_data *drv_data) |
a5f6abd4 WB |
138 | { |
139 | u16 cr; | |
140 | ||
bb90eb00 BW |
141 | cr = read_CTRL(drv_data); |
142 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
143 | } |
144 | ||
88b40369 | 145 | static void bfin_spi_disable(struct driver_data *drv_data) |
a5f6abd4 WB |
146 | { |
147 | u16 cr; | |
148 | ||
bb90eb00 BW |
149 | cr = read_CTRL(drv_data); |
150 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
151 | } |
152 | ||
153 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
154 | static u16 hz_to_spi_baud(u32 speed_hz) | |
155 | { | |
156 | u_long sclk = get_sclk(); | |
157 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
158 | ||
159 | if ((sclk % (2 * speed_hz)) > 0) | |
160 | spi_baud++; | |
161 | ||
7513e006 MH |
162 | if (spi_baud < MIN_SPI_BAUD_VAL) |
163 | spi_baud = MIN_SPI_BAUD_VAL; | |
164 | ||
a5f6abd4 WB |
165 | return spi_baud; |
166 | } | |
167 | ||
138f97cd | 168 | static int bfin_spi_flush(struct driver_data *drv_data) |
a5f6abd4 WB |
169 | { |
170 | unsigned long limit = loops_per_jiffy << 1; | |
171 | ||
172 | /* wait for stop and clear stat */ | |
b4bd2aba | 173 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 174 | cpu_relax(); |
a5f6abd4 | 175 | |
bb90eb00 | 176 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
177 | |
178 | return limit; | |
179 | } | |
180 | ||
fad91c89 | 181 | /* Chip select operation functions for cs_change flag */ |
138f97cd | 182 | static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 183 | { |
42c78b2b MH |
184 | if (likely(chip->chip_select_num)) { |
185 | u16 flag = read_FLAG(drv_data); | |
fad91c89 | 186 | |
42c78b2b MH |
187 | flag |= chip->flag; |
188 | flag &= ~(chip->flag << 8); | |
fad91c89 | 189 | |
42c78b2b MH |
190 | write_FLAG(drv_data, flag); |
191 | } else { | |
192 | gpio_set_value(chip->cs_gpio, 0); | |
193 | } | |
fad91c89 BW |
194 | } |
195 | ||
138f97cd | 196 | static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 197 | { |
42c78b2b MH |
198 | if (likely(chip->chip_select_num)) { |
199 | u16 flag = read_FLAG(drv_data); | |
fad91c89 | 200 | |
42c78b2b MH |
201 | flag &= ~chip->flag; |
202 | flag |= (chip->flag << 8); | |
fad91c89 | 203 | |
42c78b2b MH |
204 | write_FLAG(drv_data, flag); |
205 | } else { | |
206 | gpio_set_value(chip->cs_gpio, 1); | |
207 | } | |
62310e51 BW |
208 | |
209 | /* Move delay here for consistency */ | |
210 | if (chip->cs_chg_udelay) | |
211 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
212 | } |
213 | ||
a5f6abd4 | 214 | /* stop controller and re-config current chip*/ |
138f97cd | 215 | static void bfin_spi_restore_state(struct driver_data *drv_data) |
a5f6abd4 WB |
216 | { |
217 | struct chip_data *chip = drv_data->cur_chip; | |
12e17c42 | 218 | |
a5f6abd4 | 219 | /* Clear status and disable clock */ |
bb90eb00 | 220 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 221 | bfin_spi_disable(drv_data); |
88b40369 | 222 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 223 | |
5fec5b5a | 224 | /* Load the registers */ |
bb90eb00 | 225 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 226 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
227 | |
228 | bfin_spi_enable(drv_data); | |
138f97cd | 229 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
230 | } |
231 | ||
93b61bdd WM |
232 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
233 | static inline void bfin_spi_dummy_read(struct driver_data *drv_data) | |
a5f6abd4 | 234 | { |
93b61bdd | 235 | (void) read_RDBR(drv_data); |
a5f6abd4 WB |
236 | } |
237 | ||
138f97cd | 238 | static void bfin_spi_null_writer(struct driver_data *drv_data) |
a5f6abd4 WB |
239 | { |
240 | u8 n_bytes = drv_data->n_bytes; | |
93b61bdd WM |
241 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
242 | ||
243 | /* clear RXS (we check for RXS inside the loop) */ | |
244 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 WB |
245 | |
246 | while (drv_data->tx < drv_data->tx_end) { | |
93b61bdd | 247 | write_TDBR(drv_data, tx_val); |
a5f6abd4 | 248 | drv_data->tx += n_bytes; |
93b61bdd WM |
249 | /* wait until transfer finished. |
250 | checking SPIF or TXS may not guarantee transfer completion */ | |
251 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
252 | cpu_relax(); | |
253 | /* discard RX data and clear RXS */ | |
254 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 WB |
255 | } |
256 | } | |
257 | ||
138f97cd | 258 | static void bfin_spi_null_reader(struct driver_data *drv_data) |
a5f6abd4 WB |
259 | { |
260 | u8 n_bytes = drv_data->n_bytes; | |
93b61bdd WM |
261 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
262 | ||
263 | /* discard old RX data and clear RXS */ | |
138f97cd | 264 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 WB |
265 | |
266 | while (drv_data->rx < drv_data->rx_end) { | |
93b61bdd WM |
267 | write_TDBR(drv_data, tx_val); |
268 | drv_data->rx += n_bytes; | |
bb90eb00 | 269 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 270 | cpu_relax(); |
138f97cd | 271 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 WB |
272 | } |
273 | } | |
274 | ||
138f97cd | 275 | static void bfin_spi_u8_writer(struct driver_data *drv_data) |
a5f6abd4 | 276 | { |
93b61bdd WM |
277 | /* clear RXS (we check for RXS inside the loop) */ |
278 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 279 | |
a5f6abd4 | 280 | while (drv_data->tx < drv_data->tx_end) { |
93b61bdd WM |
281 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
282 | /* wait until transfer finished. | |
283 | checking SPIF or TXS may not guarantee transfer completion */ | |
284 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
d8c05008 | 285 | cpu_relax(); |
93b61bdd WM |
286 | /* discard RX data and clear RXS */ |
287 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 288 | } |
a5f6abd4 WB |
289 | } |
290 | ||
138f97cd | 291 | static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data) |
a5f6abd4 WB |
292 | { |
293 | struct chip_data *chip = drv_data->cur_chip; | |
294 | ||
93b61bdd WM |
295 | /* clear RXS (we check for RXS inside the loop) */ |
296 | bfin_spi_dummy_read(drv_data); | |
297 | ||
a5f6abd4 | 298 | while (drv_data->tx < drv_data->tx_end) { |
138f97cd | 299 | bfin_spi_cs_active(drv_data, chip); |
93b61bdd WM |
300 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
301 | /* make sure transfer finished before deactiving CS */ | |
302 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
e26aa015 | 303 | cpu_relax(); |
93b61bdd | 304 | bfin_spi_dummy_read(drv_data); |
138f97cd | 305 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 306 | } |
a5f6abd4 WB |
307 | } |
308 | ||
138f97cd | 309 | static void bfin_spi_u8_reader(struct driver_data *drv_data) |
a5f6abd4 | 310 | { |
93b61bdd | 311 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 312 | |
93b61bdd | 313 | /* discard old RX data and clear RXS */ |
138f97cd | 314 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 315 | |
93b61bdd WM |
316 | while (drv_data->rx < drv_data->rx_end) { |
317 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 318 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 319 | cpu_relax(); |
93b61bdd | 320 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 | 321 | } |
a5f6abd4 WB |
322 | } |
323 | ||
138f97cd | 324 | static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data) |
a5f6abd4 WB |
325 | { |
326 | struct chip_data *chip = drv_data->cur_chip; | |
93b61bdd WM |
327 | u16 tx_val = chip->idle_tx_val; |
328 | ||
329 | /* discard old RX data and clear RXS */ | |
330 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 331 | |
e26aa015 | 332 | while (drv_data->rx < drv_data->rx_end) { |
138f97cd | 333 | bfin_spi_cs_active(drv_data, chip); |
93b61bdd | 334 | write_TDBR(drv_data, tx_val); |
e26aa015 BW |
335 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
336 | cpu_relax(); | |
93b61bdd | 337 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
138f97cd | 338 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 339 | } |
a5f6abd4 WB |
340 | } |
341 | ||
138f97cd | 342 | static void bfin_spi_u8_duplex(struct driver_data *drv_data) |
a5f6abd4 | 343 | { |
93b61bdd WM |
344 | /* discard old RX data and clear RXS */ |
345 | bfin_spi_dummy_read(drv_data); | |
346 | ||
a5f6abd4 | 347 | while (drv_data->rx < drv_data->rx_end) { |
93b61bdd | 348 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 349 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 350 | cpu_relax(); |
93b61bdd | 351 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 WB |
352 | } |
353 | } | |
354 | ||
138f97cd | 355 | static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data) |
a5f6abd4 WB |
356 | { |
357 | struct chip_data *chip = drv_data->cur_chip; | |
358 | ||
93b61bdd WM |
359 | /* discard old RX data and clear RXS */ |
360 | bfin_spi_dummy_read(drv_data); | |
361 | ||
a5f6abd4 | 362 | while (drv_data->rx < drv_data->rx_end) { |
138f97cd | 363 | bfin_spi_cs_active(drv_data, chip); |
93b61bdd | 364 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 365 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 366 | cpu_relax(); |
93b61bdd | 367 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
138f97cd | 368 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 369 | } |
a5f6abd4 WB |
370 | } |
371 | ||
138f97cd | 372 | static void bfin_spi_u16_writer(struct driver_data *drv_data) |
a5f6abd4 | 373 | { |
93b61bdd WM |
374 | /* clear RXS (we check for RXS inside the loop) */ |
375 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 376 | |
a5f6abd4 | 377 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 378 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 379 | drv_data->tx += 2; |
93b61bdd WM |
380 | /* wait until transfer finished. |
381 | checking SPIF or TXS may not guarantee transfer completion */ | |
382 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
383 | cpu_relax(); | |
384 | /* discard RX data and clear RXS */ | |
385 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 386 | } |
a5f6abd4 WB |
387 | } |
388 | ||
138f97cd | 389 | static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data) |
a5f6abd4 WB |
390 | { |
391 | struct chip_data *chip = drv_data->cur_chip; | |
392 | ||
93b61bdd WM |
393 | /* clear RXS (we check for RXS inside the loop) */ |
394 | bfin_spi_dummy_read(drv_data); | |
395 | ||
a5f6abd4 | 396 | while (drv_data->tx < drv_data->tx_end) { |
138f97cd | 397 | bfin_spi_cs_active(drv_data, chip); |
bb90eb00 | 398 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd WM |
399 | drv_data->tx += 2; |
400 | /* make sure transfer finished before deactiving CS */ | |
401 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
13f3e642 | 402 | cpu_relax(); |
93b61bdd | 403 | bfin_spi_dummy_read(drv_data); |
138f97cd | 404 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 405 | } |
a5f6abd4 WB |
406 | } |
407 | ||
138f97cd | 408 | static void bfin_spi_u16_reader(struct driver_data *drv_data) |
a5f6abd4 | 409 | { |
93b61bdd | 410 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 411 | |
93b61bdd | 412 | /* discard old RX data and clear RXS */ |
138f97cd | 413 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 414 | |
93b61bdd WM |
415 | while (drv_data->rx < drv_data->rx_end) { |
416 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 417 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 418 | cpu_relax(); |
bb90eb00 | 419 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
420 | drv_data->rx += 2; |
421 | } | |
a5f6abd4 WB |
422 | } |
423 | ||
138f97cd | 424 | static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data) |
a5f6abd4 WB |
425 | { |
426 | struct chip_data *chip = drv_data->cur_chip; | |
93b61bdd | 427 | u16 tx_val = chip->idle_tx_val; |
a5f6abd4 | 428 | |
93b61bdd | 429 | /* discard old RX data and clear RXS */ |
138f97cd | 430 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 431 | |
93b61bdd WM |
432 | while (drv_data->rx < drv_data->rx_end) { |
433 | bfin_spi_cs_active(drv_data, chip); | |
434 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 435 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 436 | cpu_relax(); |
bb90eb00 | 437 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 438 | drv_data->rx += 2; |
93b61bdd | 439 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 440 | } |
a5f6abd4 WB |
441 | } |
442 | ||
138f97cd | 443 | static void bfin_spi_u16_duplex(struct driver_data *drv_data) |
a5f6abd4 | 444 | { |
93b61bdd WM |
445 | /* discard old RX data and clear RXS */ |
446 | bfin_spi_dummy_read(drv_data); | |
447 | ||
448 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 449 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 450 | drv_data->tx += 2; |
bb90eb00 | 451 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 452 | cpu_relax(); |
bb90eb00 | 453 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 454 | drv_data->rx += 2; |
a5f6abd4 WB |
455 | } |
456 | } | |
457 | ||
138f97cd | 458 | static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data) |
a5f6abd4 WB |
459 | { |
460 | struct chip_data *chip = drv_data->cur_chip; | |
461 | ||
93b61bdd WM |
462 | /* discard old RX data and clear RXS */ |
463 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 464 | |
93b61bdd WM |
465 | while (drv_data->rx < drv_data->rx_end) { |
466 | bfin_spi_cs_active(drv_data, chip); | |
bb90eb00 | 467 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 468 | drv_data->tx += 2; |
bb90eb00 | 469 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 470 | cpu_relax(); |
bb90eb00 | 471 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 472 | drv_data->rx += 2; |
93b61bdd | 473 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 474 | } |
a5f6abd4 WB |
475 | } |
476 | ||
477 | /* test if ther is more transfer to be done */ | |
138f97cd | 478 | static void *bfin_spi_next_transfer(struct driver_data *drv_data) |
a5f6abd4 WB |
479 | { |
480 | struct spi_message *msg = drv_data->cur_msg; | |
481 | struct spi_transfer *trans = drv_data->cur_transfer; | |
482 | ||
483 | /* Move to next transfer */ | |
484 | if (trans->transfer_list.next != &msg->transfers) { | |
485 | drv_data->cur_transfer = | |
486 | list_entry(trans->transfer_list.next, | |
487 | struct spi_transfer, transfer_list); | |
488 | return RUNNING_STATE; | |
489 | } else | |
490 | return DONE_STATE; | |
491 | } | |
492 | ||
493 | /* | |
494 | * caller already set message->status; | |
495 | * dma and pio irqs are blocked give finished message back | |
496 | */ | |
138f97cd | 497 | static void bfin_spi_giveback(struct driver_data *drv_data) |
a5f6abd4 | 498 | { |
fad91c89 | 499 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
500 | struct spi_transfer *last_transfer; |
501 | unsigned long flags; | |
502 | struct spi_message *msg; | |
503 | ||
504 | spin_lock_irqsave(&drv_data->lock, flags); | |
505 | msg = drv_data->cur_msg; | |
506 | drv_data->cur_msg = NULL; | |
507 | drv_data->cur_transfer = NULL; | |
508 | drv_data->cur_chip = NULL; | |
509 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
510 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
511 | ||
512 | last_transfer = list_entry(msg->transfers.prev, | |
513 | struct spi_transfer, transfer_list); | |
514 | ||
515 | msg->state = NULL; | |
516 | ||
fad91c89 | 517 | if (!drv_data->cs_change) |
138f97cd | 518 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 519 | |
b9b2a76a YL |
520 | /* Not stop spi in autobuffer mode */ |
521 | if (drv_data->tx_dma != 0xFFFF) | |
522 | bfin_spi_disable(drv_data); | |
523 | ||
a5f6abd4 WB |
524 | if (msg->complete) |
525 | msg->complete(msg->context); | |
526 | } | |
527 | ||
138f97cd | 528 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 529 | { |
15aafa2f | 530 | struct driver_data *drv_data = dev_id; |
fad91c89 | 531 | struct chip_data *chip = drv_data->cur_chip; |
bb90eb00 | 532 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 533 | unsigned long timeout; |
d24bd1d0 | 534 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 535 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 536 | |
d24bd1d0 MF |
537 | dev_dbg(&drv_data->pdev->dev, |
538 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
539 | dmastat, spistat); | |
540 | ||
bb90eb00 | 541 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 | 542 | |
d6fe89b0 | 543 | /* Wait for DMA to complete */ |
bb90eb00 | 544 | while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN) |
d8c05008 | 545 | cpu_relax(); |
d6fe89b0 | 546 | |
a5f6abd4 | 547 | /* |
d6fe89b0 BW |
548 | * wait for the last transaction shifted out. HRM states: |
549 | * at this point there may still be data in the SPI DMA FIFO waiting | |
550 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
551 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
552 | */ |
553 | if (drv_data->tx != NULL) { | |
bb90eb00 BW |
554 | while ((read_STAT(drv_data) & TXS) || |
555 | (read_STAT(drv_data) & TXS)) | |
d8c05008 | 556 | cpu_relax(); |
a5f6abd4 WB |
557 | } |
558 | ||
aaaf939c MF |
559 | dev_dbg(&drv_data->pdev->dev, |
560 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
561 | dmastat, read_STAT(drv_data)); | |
562 | ||
563 | timeout = jiffies + HZ; | |
bb90eb00 | 564 | while (!(read_STAT(drv_data) & SPIF)) |
aaaf939c MF |
565 | if (!time_before(jiffies, timeout)) { |
566 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
567 | break; | |
568 | } else | |
569 | cpu_relax(); | |
a5f6abd4 | 570 | |
40a2945b | 571 | if ((dmastat & DMA_ERR) && (spistat & RBSY)) { |
04b95d2f MF |
572 | msg->state = ERROR_STATE; |
573 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
574 | } else { | |
575 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 576 | |
04b95d2f | 577 | if (drv_data->cs_change) |
138f97cd | 578 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 579 | |
04b95d2f | 580 | /* Move to next transfer */ |
138f97cd | 581 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 582 | } |
a5f6abd4 WB |
583 | |
584 | /* Schedule transfer tasklet */ | |
585 | tasklet_schedule(&drv_data->pump_transfers); | |
586 | ||
587 | /* free the irq handler before next transfer */ | |
88b40369 BW |
588 | dev_dbg(&drv_data->pdev->dev, |
589 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
590 | drv_data->dma_channel); |
591 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
592 | |
593 | return IRQ_HANDLED; | |
594 | } | |
595 | ||
138f97cd | 596 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 WB |
597 | { |
598 | struct driver_data *drv_data = (struct driver_data *)data; | |
599 | struct spi_message *message = NULL; | |
600 | struct spi_transfer *transfer = NULL; | |
601 | struct spi_transfer *previous = NULL; | |
602 | struct chip_data *chip = NULL; | |
88b40369 BW |
603 | u8 width; |
604 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 605 | u32 tranf_success = 1; |
8eeb12e5 | 606 | u8 full_duplex = 0; |
a5f6abd4 WB |
607 | |
608 | /* Get current state information */ | |
609 | message = drv_data->cur_msg; | |
610 | transfer = drv_data->cur_transfer; | |
611 | chip = drv_data->cur_chip; | |
092e1fda | 612 | |
a5f6abd4 WB |
613 | /* |
614 | * if msg is error or done, report it back using complete() callback | |
615 | */ | |
616 | ||
617 | /* Handle for abort */ | |
618 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 619 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 620 | message->status = -EIO; |
138f97cd | 621 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
622 | return; |
623 | } | |
624 | ||
625 | /* Handle end of message */ | |
626 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 627 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 628 | message->status = 0; |
138f97cd | 629 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
630 | return; |
631 | } | |
632 | ||
633 | /* Delay if requested at end of transfer */ | |
634 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 635 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
636 | previous = list_entry(transfer->transfer_list.prev, |
637 | struct spi_transfer, transfer_list); | |
638 | if (previous->delay_usecs) | |
639 | udelay(previous->delay_usecs); | |
640 | } | |
641 | ||
642 | /* Setup the transfer state based on the type of transfer */ | |
138f97cd | 643 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
644 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
645 | message->status = -EIO; | |
138f97cd | 646 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
647 | return; |
648 | } | |
649 | ||
93b61bdd WM |
650 | if (transfer->len == 0) { |
651 | /* Move to next transfer of this msg */ | |
652 | message->state = bfin_spi_next_transfer(drv_data); | |
653 | /* Schedule next transfer tasklet */ | |
654 | tasklet_schedule(&drv_data->pump_transfers); | |
655 | } | |
656 | ||
a5f6abd4 WB |
657 | if (transfer->tx_buf != NULL) { |
658 | drv_data->tx = (void *)transfer->tx_buf; | |
659 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
660 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
661 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
662 | } else { |
663 | drv_data->tx = NULL; | |
664 | } | |
665 | ||
666 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 667 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
668 | drv_data->rx = transfer->rx_buf; |
669 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
670 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
671 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
672 | } else { |
673 | drv_data->rx = NULL; | |
674 | } | |
675 | ||
676 | drv_data->rx_dma = transfer->rx_dma; | |
677 | drv_data->tx_dma = transfer->tx_dma; | |
678 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 679 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 680 | |
092e1fda BW |
681 | /* Bits per word setup */ |
682 | switch (transfer->bits_per_word) { | |
683 | case 8: | |
684 | drv_data->n_bytes = 1; | |
685 | width = CFG_SPI_WORDSIZE8; | |
686 | drv_data->read = chip->cs_change_per_word ? | |
138f97cd | 687 | bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader; |
092e1fda | 688 | drv_data->write = chip->cs_change_per_word ? |
138f97cd | 689 | bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer; |
092e1fda | 690 | drv_data->duplex = chip->cs_change_per_word ? |
138f97cd | 691 | bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex; |
092e1fda BW |
692 | break; |
693 | ||
694 | case 16: | |
695 | drv_data->n_bytes = 2; | |
696 | width = CFG_SPI_WORDSIZE16; | |
697 | drv_data->read = chip->cs_change_per_word ? | |
138f97cd | 698 | bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader; |
092e1fda | 699 | drv_data->write = chip->cs_change_per_word ? |
138f97cd | 700 | bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer; |
092e1fda | 701 | drv_data->duplex = chip->cs_change_per_word ? |
138f97cd | 702 | bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex; |
092e1fda BW |
703 | break; |
704 | ||
705 | default: | |
706 | /* No change, the same as default setting */ | |
707 | drv_data->n_bytes = chip->n_bytes; | |
708 | width = chip->width; | |
138f97cd MF |
709 | drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer; |
710 | drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader; | |
711 | drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer; | |
092e1fda BW |
712 | break; |
713 | } | |
714 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
715 | cr |= (width << 8); | |
716 | write_CTRL(drv_data, cr); | |
717 | ||
a5f6abd4 WB |
718 | if (width == CFG_SPI_WORDSIZE16) { |
719 | drv_data->len = (transfer->len) >> 1; | |
720 | } else { | |
721 | drv_data->len = transfer->len; | |
722 | } | |
4fb98efa MF |
723 | dev_dbg(&drv_data->pdev->dev, |
724 | "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n", | |
138f97cd | 725 | drv_data->write, chip->write, bfin_spi_null_writer); |
a5f6abd4 WB |
726 | |
727 | /* speed and width has been set on per message */ | |
728 | message->state = RUNNING_STATE; | |
729 | dma_config = 0; | |
730 | ||
092e1fda BW |
731 | /* Speed setup (surely valid because already checked) */ |
732 | if (transfer->speed_hz) | |
733 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
734 | else | |
735 | write_BAUD(drv_data, chip->baud); | |
736 | ||
bb90eb00 BW |
737 | write_STAT(drv_data, BIT_STAT_CLR); |
738 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
b9b2a76a | 739 | if (drv_data->cs_change) |
138f97cd | 740 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 741 | |
88b40369 BW |
742 | dev_dbg(&drv_data->pdev->dev, |
743 | "now pumping a transfer: width is %d, len is %d\n", | |
744 | width, transfer->len); | |
a5f6abd4 WB |
745 | |
746 | /* | |
8cf5858c VM |
747 | * Try to map dma buffer and do a dma transfer. If successful use, |
748 | * different way to r/w according to the enable_dma settings and if | |
749 | * we are not doing a full duplex transfer (since the hardware does | |
750 | * not support full duplex DMA transfers). | |
a5f6abd4 | 751 | */ |
8eeb12e5 VM |
752 | if (!full_duplex && drv_data->cur_chip->enable_dma |
753 | && drv_data->len > 6) { | |
a5f6abd4 | 754 | |
11d6f599 | 755 | unsigned long dma_start_addr, flags; |
7aec3566 | 756 | |
bb90eb00 BW |
757 | disable_dma(drv_data->dma_channel); |
758 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
759 | |
760 | /* config dma channel */ | |
88b40369 | 761 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 762 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 | 763 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 | 764 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
765 | dma_width = WDSIZE_16; |
766 | } else { | |
bb90eb00 | 767 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
768 | dma_width = WDSIZE_8; |
769 | } | |
770 | ||
3f479a65 | 771 | /* poll for SPI completion before start */ |
bb90eb00 | 772 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 773 | cpu_relax(); |
3f479a65 | 774 | |
a5f6abd4 WB |
775 | /* dirty hack for autobuffer DMA mode */ |
776 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
777 | dev_dbg(&drv_data->pdev->dev, |
778 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
779 | |
780 | /* no irq in autobuffer mode */ | |
781 | dma_config = | |
782 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
783 | set_dma_config(drv_data->dma_channel, dma_config); |
784 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 785 | (unsigned long)drv_data->tx); |
bb90eb00 | 786 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 787 | |
07612e5f | 788 | /* start SPI transfer */ |
11d6f599 | 789 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
790 | |
791 | /* just return here, there can only be one transfer | |
792 | * in this mode | |
793 | */ | |
a5f6abd4 | 794 | message->status = 0; |
138f97cd | 795 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
796 | return; |
797 | } | |
798 | ||
799 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 800 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
801 | if (drv_data->rx != NULL) { |
802 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
803 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
804 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 805 | |
8cf5858c | 806 | /* invalidate caches, if needed */ |
67834fa9 | 807 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
808 | invalidate_dcache_range((unsigned long) drv_data->rx, |
809 | (unsigned long) (drv_data->rx + | |
ace32865 | 810 | drv_data->len_in_bytes)); |
8cf5858c | 811 | |
7aec3566 MF |
812 | dma_config |= WNR; |
813 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 814 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 815 | |
a5f6abd4 | 816 | } else if (drv_data->tx != NULL) { |
88b40369 | 817 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 818 | |
8cf5858c | 819 | /* flush caches, if needed */ |
67834fa9 | 820 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
821 | flush_dcache_range((unsigned long) drv_data->tx, |
822 | (unsigned long) (drv_data->tx + | |
ace32865 | 823 | drv_data->len_in_bytes)); |
8cf5858c | 824 | |
7aec3566 | 825 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 826 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
827 | |
828 | } else | |
829 | BUG(); | |
830 | ||
11d6f599 MF |
831 | /* oh man, here there be monsters ... and i dont mean the |
832 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
833 | * your data, kick your dog, and love it all. do *not* try | |
834 | * and change these lines unless you (1) heavily test DMA | |
835 | * with SPI flashes on a loaded system (e.g. ping floods), | |
836 | * (2) know just how broken the DMA engine interaction with | |
837 | * the SPI peripheral is, and (3) have someone else to blame | |
838 | * when you screw it all up anyways. | |
839 | */ | |
7aec3566 | 840 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
841 | set_dma_config(drv_data->dma_channel, dma_config); |
842 | local_irq_save(flags); | |
a963ea83 | 843 | SSYNC(); |
11d6f599 | 844 | write_CTRL(drv_data, cr); |
a963ea83 | 845 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
846 | dma_enable_irq(drv_data->dma_channel); |
847 | local_irq_restore(flags); | |
07612e5f | 848 | |
a5f6abd4 WB |
849 | } else { |
850 | /* IO mode write then read */ | |
88b40369 | 851 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
a5f6abd4 | 852 | |
93b61bdd WM |
853 | /* we always use SPI_WRITE mode. SPI_READ mode |
854 | seems to have problems with setting up the | |
855 | output value in TDBR prior to the transfer. */ | |
856 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); | |
857 | ||
8eeb12e5 | 858 | if (full_duplex) { |
a5f6abd4 WB |
859 | /* full duplex mode */ |
860 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
861 | (drv_data->rx_end - drv_data->rx)); | |
88b40369 BW |
862 | dev_dbg(&drv_data->pdev->dev, |
863 | "IO duplex: cr is 0x%x\n", cr); | |
a5f6abd4 | 864 | |
a5f6abd4 WB |
865 | drv_data->duplex(drv_data); |
866 | ||
867 | if (drv_data->tx != drv_data->tx_end) | |
868 | tranf_success = 0; | |
869 | } else if (drv_data->tx != NULL) { | |
870 | /* write only half duplex */ | |
131b17d4 | 871 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 872 | "IO write: cr is 0x%x\n", cr); |
a5f6abd4 | 873 | |
a5f6abd4 WB |
874 | drv_data->write(drv_data); |
875 | ||
876 | if (drv_data->tx != drv_data->tx_end) | |
877 | tranf_success = 0; | |
878 | } else if (drv_data->rx != NULL) { | |
879 | /* read only half duplex */ | |
131b17d4 | 880 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 881 | "IO read: cr is 0x%x\n", cr); |
a5f6abd4 | 882 | |
a5f6abd4 WB |
883 | drv_data->read(drv_data); |
884 | if (drv_data->rx != drv_data->rx_end) | |
885 | tranf_success = 0; | |
886 | } | |
887 | ||
888 | if (!tranf_success) { | |
131b17d4 | 889 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 890 | "IO write error!\n"); |
a5f6abd4 WB |
891 | message->state = ERROR_STATE; |
892 | } else { | |
893 | /* Update total byte transfered */ | |
ace32865 | 894 | message->actual_length += drv_data->len_in_bytes; |
a5f6abd4 | 895 | /* Move to next transfer of this msg */ |
138f97cd | 896 | message->state = bfin_spi_next_transfer(drv_data); |
b9b2a76a | 897 | if (drv_data->cs_change) |
138f97cd | 898 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 899 | } |
a5f6abd4 WB |
900 | /* Schedule next transfer tasklet */ |
901 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
902 | } |
903 | } | |
904 | ||
905 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 906 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 907 | { |
131b17d4 | 908 | struct driver_data *drv_data; |
a5f6abd4 WB |
909 | unsigned long flags; |
910 | ||
131b17d4 BW |
911 | drv_data = container_of(work, struct driver_data, pump_messages); |
912 | ||
a5f6abd4 WB |
913 | /* Lock queue and check for queue work */ |
914 | spin_lock_irqsave(&drv_data->lock, flags); | |
915 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
916 | /* pumper kicked off but no work to do */ | |
917 | drv_data->busy = 0; | |
918 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
919 | return; | |
920 | } | |
921 | ||
922 | /* Make sure we are not already running a message */ | |
923 | if (drv_data->cur_msg) { | |
924 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
925 | return; | |
926 | } | |
927 | ||
928 | /* Extract head of queue */ | |
929 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
930 | struct spi_message, queue); | |
5fec5b5a BW |
931 | |
932 | /* Setup the SSP using the per chip configuration */ | |
933 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 934 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 935 | |
a5f6abd4 WB |
936 | list_del_init(&drv_data->cur_msg->queue); |
937 | ||
938 | /* Initial message state */ | |
939 | drv_data->cur_msg->state = START_STATE; | |
940 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
941 | struct spi_transfer, transfer_list); | |
942 | ||
5fec5b5a BW |
943 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
944 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
945 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
946 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
947 | |
948 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
949 | "the first transfer len is %d\n", |
950 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
951 | |
952 | /* Mark as busy and launch transfers */ | |
953 | tasklet_schedule(&drv_data->pump_transfers); | |
954 | ||
955 | drv_data->busy = 1; | |
956 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
957 | } | |
958 | ||
959 | /* | |
960 | * got a msg to transfer, queue it in drv_data->queue. | |
961 | * And kick off message pumper | |
962 | */ | |
138f97cd | 963 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 WB |
964 | { |
965 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
966 | unsigned long flags; | |
967 | ||
968 | spin_lock_irqsave(&drv_data->lock, flags); | |
969 | ||
970 | if (drv_data->run == QUEUE_STOPPED) { | |
971 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
972 | return -ESHUTDOWN; | |
973 | } | |
974 | ||
975 | msg->actual_length = 0; | |
976 | msg->status = -EINPROGRESS; | |
977 | msg->state = START_STATE; | |
978 | ||
88b40369 | 979 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
980 | list_add_tail(&msg->queue, &drv_data->queue); |
981 | ||
982 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
983 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
984 | ||
985 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
986 | ||
987 | return 0; | |
988 | } | |
989 | ||
12e17c42 SZ |
990 | #define MAX_SPI_SSEL 7 |
991 | ||
4160bde2 | 992 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
993 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
994 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
995 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
996 | ||
997 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
998 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
999 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
1000 | ||
1001 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
1002 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
1003 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
1004 | }; | |
1005 | ||
a5f6abd4 | 1006 | /* first setup for new devices */ |
138f97cd | 1007 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 WB |
1008 | { |
1009 | struct bfin5xx_spi_chip *chip_info = NULL; | |
1010 | struct chip_data *chip; | |
1011 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
42c78b2b | 1012 | int ret; |
a5f6abd4 | 1013 | |
a5f6abd4 WB |
1014 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) |
1015 | return -EINVAL; | |
1016 | ||
1017 | /* Only alloc (or use chip_info) on first setup */ | |
1018 | chip = spi_get_ctldata(spi); | |
1019 | if (chip == NULL) { | |
1020 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1021 | if (!chip) | |
1022 | return -ENOMEM; | |
1023 | ||
1024 | chip->enable_dma = 0; | |
1025 | chip_info = spi->controller_data; | |
1026 | } | |
1027 | ||
1028 | /* chip_info isn't always needed */ | |
1029 | if (chip_info) { | |
2ed35516 MF |
1030 | /* Make sure people stop trying to set fields via ctl_reg |
1031 | * when they should actually be using common SPI framework. | |
1032 | * Currently we let through: WOM EMISO PSSE GM SZ TIMOD. | |
1033 | * Not sure if a user actually needs/uses any of these, | |
1034 | * but let's assume (for now) they do. | |
1035 | */ | |
1036 | if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) { | |
1037 | dev_err(&spi->dev, "do not set bits in ctl_reg " | |
1038 | "that the SPI framework manages\n"); | |
1039 | return -EINVAL; | |
1040 | } | |
1041 | ||
a5f6abd4 WB |
1042 | chip->enable_dma = chip_info->enable_dma != 0 |
1043 | && drv_data->master_info->enable_dma; | |
1044 | chip->ctl_reg = chip_info->ctl_reg; | |
1045 | chip->bits_per_word = chip_info->bits_per_word; | |
1046 | chip->cs_change_per_word = chip_info->cs_change_per_word; | |
1047 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
42c78b2b | 1048 | chip->cs_gpio = chip_info->cs_gpio; |
93b61bdd | 1049 | chip->idle_tx_val = chip_info->idle_tx_val; |
a5f6abd4 WB |
1050 | } |
1051 | ||
1052 | /* translate common spi framework into our register */ | |
1053 | if (spi->mode & SPI_CPOL) | |
1054 | chip->ctl_reg |= CPOL; | |
1055 | if (spi->mode & SPI_CPHA) | |
1056 | chip->ctl_reg |= CPHA; | |
1057 | if (spi->mode & SPI_LSB_FIRST) | |
1058 | chip->ctl_reg |= LSBF; | |
1059 | /* we dont support running in slave mode (yet?) */ | |
1060 | chip->ctl_reg |= MSTR; | |
1061 | ||
1062 | /* | |
1063 | * if any one SPI chip is registered and wants DMA, request the | |
1064 | * DMA channel for it | |
1065 | */ | |
bb90eb00 | 1066 | if (chip->enable_dma && !drv_data->dma_requested) { |
a5f6abd4 | 1067 | /* register dma irq handler */ |
59bfcc66 | 1068 | if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) { |
88b40369 BW |
1069 | dev_dbg(&spi->dev, |
1070 | "Unable to request BlackFin SPI DMA channel\n"); | |
a5f6abd4 WB |
1071 | return -ENODEV; |
1072 | } | |
bb90eb00 | 1073 | if (set_dma_callback(drv_data->dma_channel, |
138f97cd | 1074 | bfin_spi_dma_irq_handler, drv_data) < 0) { |
88b40369 | 1075 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
a5f6abd4 WB |
1076 | return -EPERM; |
1077 | } | |
bb90eb00 BW |
1078 | dma_disable_irq(drv_data->dma_channel); |
1079 | drv_data->dma_requested = 1; | |
a5f6abd4 WB |
1080 | } |
1081 | ||
1082 | /* | |
1083 | * Notice: for blackfin, the speed_hz is the value of register | |
1084 | * SPI_BAUD, not the real baudrate | |
1085 | */ | |
1086 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
2cf36834 | 1087 | chip->flag = 1 << (spi->chip_select); |
a5f6abd4 WB |
1088 | chip->chip_select_num = spi->chip_select; |
1089 | ||
42c78b2b MH |
1090 | if (chip->chip_select_num == 0) { |
1091 | ret = gpio_request(chip->cs_gpio, spi->modalias); | |
1092 | if (ret) { | |
1093 | if (drv_data->dma_requested) | |
1094 | free_dma(drv_data->dma_channel); | |
1095 | return ret; | |
1096 | } | |
1097 | gpio_direction_output(chip->cs_gpio, 1); | |
1098 | } | |
1099 | ||
a5f6abd4 WB |
1100 | switch (chip->bits_per_word) { |
1101 | case 8: | |
1102 | chip->n_bytes = 1; | |
1103 | chip->width = CFG_SPI_WORDSIZE8; | |
1104 | chip->read = chip->cs_change_per_word ? | |
138f97cd | 1105 | bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader; |
a5f6abd4 | 1106 | chip->write = chip->cs_change_per_word ? |
138f97cd | 1107 | bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer; |
a5f6abd4 | 1108 | chip->duplex = chip->cs_change_per_word ? |
138f97cd | 1109 | bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex; |
a5f6abd4 WB |
1110 | break; |
1111 | ||
1112 | case 16: | |
1113 | chip->n_bytes = 2; | |
1114 | chip->width = CFG_SPI_WORDSIZE16; | |
1115 | chip->read = chip->cs_change_per_word ? | |
138f97cd | 1116 | bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader; |
a5f6abd4 | 1117 | chip->write = chip->cs_change_per_word ? |
138f97cd | 1118 | bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer; |
a5f6abd4 | 1119 | chip->duplex = chip->cs_change_per_word ? |
138f97cd | 1120 | bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex; |
a5f6abd4 WB |
1121 | break; |
1122 | ||
1123 | default: | |
1124 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1125 | chip->bits_per_word); | |
138f97cd MF |
1126 | if (chip_info) |
1127 | kfree(chip); | |
a5f6abd4 WB |
1128 | return -ENODEV; |
1129 | } | |
1130 | ||
898eb71c | 1131 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1132 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1133 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1134 | chip->ctl_reg, chip->flag); |
1135 | ||
1136 | spi_set_ctldata(spi, chip); | |
1137 | ||
12e17c42 SZ |
1138 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
1139 | if ((chip->chip_select_num > 0) | |
1140 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1141 | peripheral_request(ssel[spi->master->bus_num] | |
aab0d83e | 1142 | [chip->chip_select_num-1], spi->modalias); |
12e17c42 | 1143 | |
138f97cd | 1144 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1145 | |
a5f6abd4 WB |
1146 | return 0; |
1147 | } | |
1148 | ||
1149 | /* | |
1150 | * callback for spi framework. | |
1151 | * clean driver specific data | |
1152 | */ | |
138f97cd | 1153 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1154 | { |
27bb9e79 | 1155 | struct chip_data *chip = spi_get_ctldata(spi); |
a5f6abd4 | 1156 | |
e7d02e3c MF |
1157 | if (!chip) |
1158 | return; | |
1159 | ||
12e17c42 SZ |
1160 | if ((chip->chip_select_num > 0) |
1161 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1162 | peripheral_free(ssel[spi->master->bus_num] | |
1163 | [chip->chip_select_num-1]); | |
1164 | ||
42c78b2b MH |
1165 | if (chip->chip_select_num == 0) |
1166 | gpio_free(chip->cs_gpio); | |
1167 | ||
a5f6abd4 WB |
1168 | kfree(chip); |
1169 | } | |
1170 | ||
138f97cd | 1171 | static inline int bfin_spi_init_queue(struct driver_data *drv_data) |
a5f6abd4 WB |
1172 | { |
1173 | INIT_LIST_HEAD(&drv_data->queue); | |
1174 | spin_lock_init(&drv_data->lock); | |
1175 | ||
1176 | drv_data->run = QUEUE_STOPPED; | |
1177 | drv_data->busy = 0; | |
1178 | ||
1179 | /* init transfer tasklet */ | |
1180 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1181 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1182 | |
1183 | /* init messages workqueue */ | |
138f97cd | 1184 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1185 | drv_data->workqueue = create_singlethread_workqueue( |
1186 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1187 | if (drv_data->workqueue == NULL) |
1188 | return -EBUSY; | |
1189 | ||
1190 | return 0; | |
1191 | } | |
1192 | ||
138f97cd | 1193 | static inline int bfin_spi_start_queue(struct driver_data *drv_data) |
a5f6abd4 WB |
1194 | { |
1195 | unsigned long flags; | |
1196 | ||
1197 | spin_lock_irqsave(&drv_data->lock, flags); | |
1198 | ||
1199 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1200 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1201 | return -EBUSY; | |
1202 | } | |
1203 | ||
1204 | drv_data->run = QUEUE_RUNNING; | |
1205 | drv_data->cur_msg = NULL; | |
1206 | drv_data->cur_transfer = NULL; | |
1207 | drv_data->cur_chip = NULL; | |
1208 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1209 | ||
1210 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1211 | ||
1212 | return 0; | |
1213 | } | |
1214 | ||
138f97cd | 1215 | static inline int bfin_spi_stop_queue(struct driver_data *drv_data) |
a5f6abd4 WB |
1216 | { |
1217 | unsigned long flags; | |
1218 | unsigned limit = 500; | |
1219 | int status = 0; | |
1220 | ||
1221 | spin_lock_irqsave(&drv_data->lock, flags); | |
1222 | ||
1223 | /* | |
1224 | * This is a bit lame, but is optimized for the common execution path. | |
1225 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1226 | * execution path (pump_messages) would be required to call wake_up or | |
1227 | * friends on every SPI message. Do this instead | |
1228 | */ | |
1229 | drv_data->run = QUEUE_STOPPED; | |
1230 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1231 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1232 | msleep(10); | |
1233 | spin_lock_irqsave(&drv_data->lock, flags); | |
1234 | } | |
1235 | ||
1236 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1237 | status = -EBUSY; | |
1238 | ||
1239 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1240 | ||
1241 | return status; | |
1242 | } | |
1243 | ||
138f97cd | 1244 | static inline int bfin_spi_destroy_queue(struct driver_data *drv_data) |
a5f6abd4 WB |
1245 | { |
1246 | int status; | |
1247 | ||
138f97cd | 1248 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1249 | if (status != 0) |
1250 | return status; | |
1251 | ||
1252 | destroy_workqueue(drv_data->workqueue); | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | ||
138f97cd | 1257 | static int __init bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1258 | { |
1259 | struct device *dev = &pdev->dev; | |
1260 | struct bfin5xx_spi_master *platform_info; | |
1261 | struct spi_master *master; | |
1262 | struct driver_data *drv_data = 0; | |
a32c691d | 1263 | struct resource *res; |
a5f6abd4 WB |
1264 | int status = 0; |
1265 | ||
1266 | platform_info = dev->platform_data; | |
1267 | ||
1268 | /* Allocate master with space for drv_data */ | |
1269 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1270 | if (!master) { | |
1271 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1272 | return -ENOMEM; | |
1273 | } | |
131b17d4 | 1274 | |
a5f6abd4 WB |
1275 | drv_data = spi_master_get_devdata(master); |
1276 | drv_data->master = master; | |
1277 | drv_data->master_info = platform_info; | |
1278 | drv_data->pdev = pdev; | |
003d9226 | 1279 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1280 | |
e7db06b5 DB |
1281 | /* the spi->mode bits supported by this driver: */ |
1282 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
1283 | ||
a5f6abd4 WB |
1284 | master->bus_num = pdev->id; |
1285 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1286 | master->cleanup = bfin_spi_cleanup; |
1287 | master->setup = bfin_spi_setup; | |
1288 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1289 | |
a32c691d BW |
1290 | /* Find and map our resources */ |
1291 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1292 | if (res == NULL) { | |
1293 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1294 | status = -ENOENT; | |
1295 | goto out_error_get_res; | |
1296 | } | |
1297 | ||
74947b89 | 1298 | drv_data->regs_base = ioremap(res->start, resource_size(res)); |
f452126c | 1299 | if (drv_data->regs_base == NULL) { |
a32c691d BW |
1300 | dev_err(dev, "Cannot map IO\n"); |
1301 | status = -ENXIO; | |
1302 | goto out_error_ioremap; | |
1303 | } | |
1304 | ||
bb90eb00 BW |
1305 | drv_data->dma_channel = platform_get_irq(pdev, 0); |
1306 | if (drv_data->dma_channel < 0) { | |
a32c691d BW |
1307 | dev_err(dev, "No DMA channel specified\n"); |
1308 | status = -ENOENT; | |
1309 | goto out_error_no_dma_ch; | |
1310 | } | |
1311 | ||
a5f6abd4 | 1312 | /* Initial and start queue */ |
138f97cd | 1313 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1314 | if (status != 0) { |
a32c691d | 1315 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1316 | goto out_error_queue_alloc; |
1317 | } | |
a32c691d | 1318 | |
138f97cd | 1319 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1320 | if (status != 0) { |
a32c691d | 1321 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1322 | goto out_error_queue_alloc; |
1323 | } | |
1324 | ||
f9e522ca VM |
1325 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1326 | if (status != 0) { | |
1327 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1328 | goto out_error_queue_alloc; | |
1329 | } | |
1330 | ||
a5f6abd4 WB |
1331 | /* Register with the SPI framework */ |
1332 | platform_set_drvdata(pdev, drv_data); | |
1333 | status = spi_register_master(master); | |
1334 | if (status != 0) { | |
a32c691d | 1335 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1336 | goto out_error_queue_alloc; |
1337 | } | |
a32c691d | 1338 | |
f452126c | 1339 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1340 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1341 | drv_data->dma_channel); | |
a5f6abd4 WB |
1342 | return status; |
1343 | ||
cc2f81a6 | 1344 | out_error_queue_alloc: |
138f97cd | 1345 | bfin_spi_destroy_queue(drv_data); |
a32c691d | 1346 | out_error_no_dma_ch: |
bb90eb00 | 1347 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1348 | out_error_ioremap: |
1349 | out_error_get_res: | |
a5f6abd4 | 1350 | spi_master_put(master); |
cc2f81a6 | 1351 | |
a5f6abd4 WB |
1352 | return status; |
1353 | } | |
1354 | ||
1355 | /* stop hardware and remove the driver */ | |
138f97cd | 1356 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 WB |
1357 | { |
1358 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1359 | int status = 0; | |
1360 | ||
1361 | if (!drv_data) | |
1362 | return 0; | |
1363 | ||
1364 | /* Remove the queue */ | |
138f97cd | 1365 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1366 | if (status != 0) |
1367 | return status; | |
1368 | ||
1369 | /* Disable the SSP at the peripheral and SOC level */ | |
1370 | bfin_spi_disable(drv_data); | |
1371 | ||
1372 | /* Release DMA */ | |
1373 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1374 | if (dma_channel_active(drv_data->dma_channel)) |
1375 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1376 | } |
1377 | ||
1378 | /* Disconnect from the SPI framework */ | |
1379 | spi_unregister_master(drv_data->master); | |
1380 | ||
003d9226 | 1381 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1382 | |
a5f6abd4 WB |
1383 | /* Prevent double remove */ |
1384 | platform_set_drvdata(pdev, NULL); | |
1385 | ||
1386 | return 0; | |
1387 | } | |
1388 | ||
1389 | #ifdef CONFIG_PM | |
138f97cd | 1390 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 WB |
1391 | { |
1392 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1393 | int status = 0; | |
1394 | ||
138f97cd | 1395 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1396 | if (status != 0) |
1397 | return status; | |
1398 | ||
1399 | /* stop hardware */ | |
1400 | bfin_spi_disable(drv_data); | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
138f97cd | 1405 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 WB |
1406 | { |
1407 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1408 | int status = 0; | |
1409 | ||
1410 | /* Enable the SPI interface */ | |
1411 | bfin_spi_enable(drv_data); | |
1412 | ||
1413 | /* Start the queue running */ | |
138f97cd | 1414 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1415 | if (status != 0) { |
1416 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1417 | return status; | |
1418 | } | |
1419 | ||
1420 | return 0; | |
1421 | } | |
1422 | #else | |
138f97cd MF |
1423 | #define bfin_spi_suspend NULL |
1424 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1425 | #endif /* CONFIG_PM */ |
1426 | ||
7e38c3c4 | 1427 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1428 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1429 | .driver = { |
a32c691d | 1430 | .name = DRV_NAME, |
88b40369 BW |
1431 | .owner = THIS_MODULE, |
1432 | }, | |
138f97cd MF |
1433 | .suspend = bfin_spi_suspend, |
1434 | .resume = bfin_spi_resume, | |
1435 | .remove = __devexit_p(bfin_spi_remove), | |
a5f6abd4 WB |
1436 | }; |
1437 | ||
138f97cd | 1438 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1439 | { |
138f97cd | 1440 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1441 | } |
138f97cd | 1442 | module_init(bfin_spi_init); |
a5f6abd4 | 1443 | |
138f97cd | 1444 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1445 | { |
138f97cd | 1446 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1447 | } |
138f97cd | 1448 | module_exit(bfin_spi_exit); |