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Commit | Line | Data |
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a5f6abd4 | 1 | /* |
131b17d4 BW |
2 | * File: drivers/spi/bfin5xx_spi.c |
3 | * Maintainer: | |
4 | * Bryan Wu <bryan.wu@analog.com> | |
5 | * Original Author: | |
6 | * Luke Yang (Analog Devices Inc.) | |
a5f6abd4 | 7 | * |
131b17d4 BW |
8 | * Created: March. 10th 2006 |
9 | * Description: SPI controller driver for Blackfin BF5xx | |
10 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
a5f6abd4 WB |
11 | * |
12 | * Modified: | |
13 | * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang) | |
14 | * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang) | |
131b17d4 | 15 | * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu) |
a32c691d BW |
16 | * July 30, 2007 add platfrom_resource interface to support multi-port |
17 | * SPI controller (Bryan Wu) | |
a5f6abd4 | 18 | * |
131b17d4 | 19 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 WB |
20 | * |
21 | * This program is free software ; you can redistribute it and/or modify | |
22 | * it under the terms of the GNU General Public License as published by | |
23 | * the Free Software Foundation ; either version 2, or (at your option) | |
24 | * any later version. | |
25 | * | |
26 | * This program is distributed in the hope that it will be useful, | |
27 | * but WITHOUT ANY WARRANTY ; without even the implied warranty of | |
28 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
29 | * GNU General Public License for more details. | |
30 | * | |
31 | * You should have received a copy of the GNU General Public License | |
32 | * along with this program ; see the file COPYING. | |
33 | * If not, write to the Free Software Foundation, | |
34 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
35 | */ | |
36 | ||
37 | #include <linux/init.h> | |
38 | #include <linux/module.h> | |
131b17d4 | 39 | #include <linux/delay.h> |
a5f6abd4 | 40 | #include <linux/device.h> |
131b17d4 | 41 | #include <linux/io.h> |
a5f6abd4 | 42 | #include <linux/ioport.h> |
131b17d4 | 43 | #include <linux/irq.h> |
a5f6abd4 WB |
44 | #include <linux/errno.h> |
45 | #include <linux/interrupt.h> | |
46 | #include <linux/platform_device.h> | |
47 | #include <linux/dma-mapping.h> | |
48 | #include <linux/spi/spi.h> | |
49 | #include <linux/workqueue.h> | |
a5f6abd4 | 50 | |
a5f6abd4 | 51 | #include <asm/dma.h> |
131b17d4 | 52 | #include <asm/portmux.h> |
a5f6abd4 WB |
53 | #include <asm/bfin5xx_spi.h> |
54 | ||
a32c691d BW |
55 | #define DRV_NAME "bfin-spi" |
56 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
57 | #define DRV_DESC "Blackfin BF5xx on-chip SPI Contoller Driver" | |
58 | #define DRV_VERSION "1.0" | |
59 | ||
60 | MODULE_AUTHOR(DRV_AUTHOR); | |
61 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
62 | MODULE_LICENSE("GPL"); |
63 | ||
64 | #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0) | |
65 | ||
a32c691d BW |
66 | static u32 spi_dma_ch; |
67 | static u32 spi_regs_base; | |
68 | ||
a5f6abd4 WB |
69 | #define DEFINE_SPI_REG(reg, off) \ |
70 | static inline u16 read_##reg(void) \ | |
a32c691d | 71 | { return bfin_read16(spi_regs_base + off); } \ |
a5f6abd4 | 72 | static inline void write_##reg(u16 v) \ |
a32c691d | 73 | {bfin_write16(spi_regs_base + off, v); } |
a5f6abd4 WB |
74 | |
75 | DEFINE_SPI_REG(CTRL, 0x00) | |
76 | DEFINE_SPI_REG(FLAG, 0x04) | |
77 | DEFINE_SPI_REG(STAT, 0x08) | |
78 | DEFINE_SPI_REG(TDBR, 0x0C) | |
79 | DEFINE_SPI_REG(RDBR, 0x10) | |
80 | DEFINE_SPI_REG(BAUD, 0x14) | |
81 | DEFINE_SPI_REG(SHAW, 0x18) | |
82 | #define START_STATE ((void*)0) | |
83 | #define RUNNING_STATE ((void*)1) | |
84 | #define DONE_STATE ((void*)2) | |
85 | #define ERROR_STATE ((void*)-1) | |
86 | #define QUEUE_RUNNING 0 | |
87 | #define QUEUE_STOPPED 1 | |
88 | int dma_requested; | |
89 | ||
90 | struct driver_data { | |
91 | /* Driver model hookup */ | |
92 | struct platform_device *pdev; | |
93 | ||
94 | /* SPI framework hookup */ | |
95 | struct spi_master *master; | |
96 | ||
97 | /* BFIN hookup */ | |
98 | struct bfin5xx_spi_master *master_info; | |
99 | ||
100 | /* Driver message queue */ | |
101 | struct workqueue_struct *workqueue; | |
102 | struct work_struct pump_messages; | |
103 | spinlock_t lock; | |
104 | struct list_head queue; | |
105 | int busy; | |
106 | int run; | |
107 | ||
108 | /* Message Transfer pump */ | |
109 | struct tasklet_struct pump_transfers; | |
110 | ||
111 | /* Current message transfer state info */ | |
112 | struct spi_message *cur_msg; | |
113 | struct spi_transfer *cur_transfer; | |
114 | struct chip_data *cur_chip; | |
115 | size_t len_in_bytes; | |
116 | size_t len; | |
117 | void *tx; | |
118 | void *tx_end; | |
119 | void *rx; | |
120 | void *rx_end; | |
121 | int dma_mapped; | |
122 | dma_addr_t rx_dma; | |
123 | dma_addr_t tx_dma; | |
124 | size_t rx_map_len; | |
125 | size_t tx_map_len; | |
126 | u8 n_bytes; | |
fad91c89 | 127 | int cs_change; |
a5f6abd4 WB |
128 | void (*write) (struct driver_data *); |
129 | void (*read) (struct driver_data *); | |
130 | void (*duplex) (struct driver_data *); | |
131 | }; | |
132 | ||
133 | struct chip_data { | |
134 | u16 ctl_reg; | |
135 | u16 baud; | |
136 | u16 flag; | |
137 | ||
138 | u8 chip_select_num; | |
139 | u8 n_bytes; | |
88b40369 | 140 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
141 | u8 enable_dma; |
142 | u8 bits_per_word; /* 8 or 16 */ | |
143 | u8 cs_change_per_word; | |
144 | u8 cs_chg_udelay; | |
145 | void (*write) (struct driver_data *); | |
146 | void (*read) (struct driver_data *); | |
147 | void (*duplex) (struct driver_data *); | |
148 | }; | |
149 | ||
88b40369 | 150 | static void bfin_spi_enable(struct driver_data *drv_data) |
a5f6abd4 WB |
151 | { |
152 | u16 cr; | |
153 | ||
154 | cr = read_CTRL(); | |
155 | write_CTRL(cr | BIT_CTL_ENABLE); | |
a5f6abd4 WB |
156 | } |
157 | ||
88b40369 | 158 | static void bfin_spi_disable(struct driver_data *drv_data) |
a5f6abd4 WB |
159 | { |
160 | u16 cr; | |
161 | ||
162 | cr = read_CTRL(); | |
163 | write_CTRL(cr & (~BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
164 | } |
165 | ||
166 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
167 | static u16 hz_to_spi_baud(u32 speed_hz) | |
168 | { | |
169 | u_long sclk = get_sclk(); | |
170 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
171 | ||
172 | if ((sclk % (2 * speed_hz)) > 0) | |
173 | spi_baud++; | |
174 | ||
a5f6abd4 WB |
175 | return spi_baud; |
176 | } | |
177 | ||
178 | static int flush(struct driver_data *drv_data) | |
179 | { | |
180 | unsigned long limit = loops_per_jiffy << 1; | |
181 | ||
182 | /* wait for stop and clear stat */ | |
183 | while (!(read_STAT() & BIT_STAT_SPIF) && limit--) | |
184 | continue; | |
185 | ||
186 | write_STAT(BIT_STAT_CLR); | |
187 | ||
188 | return limit; | |
189 | } | |
190 | ||
fad91c89 BW |
191 | /* Chip select operation functions for cs_change flag */ |
192 | static void cs_active(struct chip_data *chip) | |
193 | { | |
194 | u16 flag = read_FLAG(); | |
195 | ||
196 | flag |= chip->flag; | |
197 | flag &= ~(chip->flag << 8); | |
198 | ||
199 | write_FLAG(flag); | |
200 | } | |
201 | ||
202 | static void cs_deactive(struct chip_data *chip) | |
203 | { | |
204 | u16 flag = read_FLAG(); | |
205 | ||
206 | flag |= (chip->flag << 8); | |
207 | ||
208 | write_FLAG(flag); | |
209 | } | |
210 | ||
7c4ef094 | 211 | #define MAX_SPI_SSEL 7 |
5fec5b5a | 212 | |
a5f6abd4 | 213 | /* stop controller and re-config current chip*/ |
5fec5b5a | 214 | static int restore_state(struct driver_data *drv_data) |
a5f6abd4 WB |
215 | { |
216 | struct chip_data *chip = drv_data->cur_chip; | |
5fec5b5a | 217 | int ret = 0; |
12e17c42 | 218 | |
a5f6abd4 WB |
219 | /* Clear status and disable clock */ |
220 | write_STAT(BIT_STAT_CLR); | |
221 | bfin_spi_disable(drv_data); | |
88b40369 | 222 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 223 | |
5fec5b5a | 224 | /* Load the registers */ |
cc487e73 | 225 | cs_deactive(chip); |
5fec5b5a | 226 | write_BAUD(chip->baud); |
cc487e73 SZ |
227 | chip->ctl_reg &= (~BIT_CTL_TIMOD); |
228 | chip->ctl_reg |= (chip->width << 8); | |
229 | write_CTRL(chip->ctl_reg); | |
230 | ||
231 | bfin_spi_enable(drv_data); | |
5fec5b5a | 232 | |
5fec5b5a BW |
233 | if (ret) |
234 | dev_dbg(&drv_data->pdev->dev, | |
235 | ": request chip select number %d failed\n", | |
236 | chip->chip_select_num); | |
237 | ||
238 | return ret; | |
a5f6abd4 WB |
239 | } |
240 | ||
241 | /* used to kick off transfer in rx mode */ | |
242 | static unsigned short dummy_read(void) | |
243 | { | |
244 | unsigned short tmp; | |
245 | tmp = read_RDBR(); | |
246 | return tmp; | |
247 | } | |
248 | ||
249 | static void null_writer(struct driver_data *drv_data) | |
250 | { | |
251 | u8 n_bytes = drv_data->n_bytes; | |
252 | ||
253 | while (drv_data->tx < drv_data->tx_end) { | |
254 | write_TDBR(0); | |
255 | while ((read_STAT() & BIT_STAT_TXS)) | |
256 | continue; | |
257 | drv_data->tx += n_bytes; | |
258 | } | |
259 | } | |
260 | ||
261 | static void null_reader(struct driver_data *drv_data) | |
262 | { | |
263 | u8 n_bytes = drv_data->n_bytes; | |
264 | dummy_read(); | |
265 | ||
266 | while (drv_data->rx < drv_data->rx_end) { | |
267 | while (!(read_STAT() & BIT_STAT_RXS)) | |
268 | continue; | |
269 | dummy_read(); | |
270 | drv_data->rx += n_bytes; | |
271 | } | |
272 | } | |
273 | ||
274 | static void u8_writer(struct driver_data *drv_data) | |
275 | { | |
131b17d4 | 276 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 277 | "cr8-s is 0x%x\n", read_STAT()); |
cc487e73 | 278 | |
3f479a65 SZ |
279 | /* poll for SPI completion before start */ |
280 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
281 | continue; | |
282 | ||
a5f6abd4 WB |
283 | while (drv_data->tx < drv_data->tx_end) { |
284 | write_TDBR(*(u8 *) (drv_data->tx)); | |
285 | while (read_STAT() & BIT_STAT_TXS) | |
286 | continue; | |
287 | ++drv_data->tx; | |
288 | } | |
a5f6abd4 WB |
289 | } |
290 | ||
291 | static void u8_cs_chg_writer(struct driver_data *drv_data) | |
292 | { | |
293 | struct chip_data *chip = drv_data->cur_chip; | |
294 | ||
3f479a65 SZ |
295 | /* poll for SPI completion before start */ |
296 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
297 | continue; | |
298 | ||
a5f6abd4 | 299 | while (drv_data->tx < drv_data->tx_end) { |
fad91c89 | 300 | cs_active(chip); |
a5f6abd4 WB |
301 | |
302 | write_TDBR(*(u8 *) (drv_data->tx)); | |
303 | while (read_STAT() & BIT_STAT_TXS) | |
304 | continue; | |
fad91c89 | 305 | cs_deactive(chip); |
5fec5b5a | 306 | |
a5f6abd4 WB |
307 | if (chip->cs_chg_udelay) |
308 | udelay(chip->cs_chg_udelay); | |
309 | ++drv_data->tx; | |
310 | } | |
a5f6abd4 WB |
311 | } |
312 | ||
313 | static void u8_reader(struct driver_data *drv_data) | |
314 | { | |
131b17d4 | 315 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 316 | "cr-8 is 0x%x\n", read_STAT()); |
a5f6abd4 | 317 | |
3f479a65 SZ |
318 | /* poll for SPI completion before start */ |
319 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
320 | continue; | |
321 | ||
a5f6abd4 WB |
322 | /* clear TDBR buffer before read(else it will be shifted out) */ |
323 | write_TDBR(0xFFFF); | |
324 | ||
325 | dummy_read(); | |
cc487e73 | 326 | |
a5f6abd4 WB |
327 | while (drv_data->rx < drv_data->rx_end - 1) { |
328 | while (!(read_STAT() & BIT_STAT_RXS)) | |
329 | continue; | |
330 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
331 | ++drv_data->rx; | |
332 | } | |
333 | ||
334 | while (!(read_STAT() & BIT_STAT_RXS)) | |
335 | continue; | |
336 | *(u8 *) (drv_data->rx) = read_SHAW(); | |
337 | ++drv_data->rx; | |
338 | } | |
339 | ||
340 | static void u8_cs_chg_reader(struct driver_data *drv_data) | |
341 | { | |
342 | struct chip_data *chip = drv_data->cur_chip; | |
343 | ||
3f479a65 SZ |
344 | /* poll for SPI completion before start */ |
345 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
346 | continue; | |
347 | ||
cc487e73 SZ |
348 | /* clear TDBR buffer before read(else it will be shifted out) */ |
349 | write_TDBR(0xFFFF); | |
a5f6abd4 | 350 | |
cc487e73 SZ |
351 | cs_active(chip); |
352 | dummy_read(); | |
353 | ||
354 | while (drv_data->rx < drv_data->rx_end - 1) { | |
fad91c89 | 355 | cs_deactive(chip); |
5fec5b5a | 356 | |
a5f6abd4 WB |
357 | if (chip->cs_chg_udelay) |
358 | udelay(chip->cs_chg_udelay); | |
cc487e73 SZ |
359 | |
360 | while (!(read_STAT() & BIT_STAT_RXS)) | |
361 | continue; | |
362 | cs_active(chip); | |
363 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
a5f6abd4 WB |
364 | ++drv_data->rx; |
365 | } | |
fad91c89 | 366 | cs_deactive(chip); |
5fec5b5a | 367 | |
cc487e73 SZ |
368 | while (!(read_STAT() & BIT_STAT_RXS)) |
369 | continue; | |
370 | *(u8 *) (drv_data->rx) = read_SHAW(); | |
371 | ++drv_data->rx; | |
a5f6abd4 WB |
372 | } |
373 | ||
374 | static void u8_duplex(struct driver_data *drv_data) | |
375 | { | |
3f479a65 SZ |
376 | /* poll for SPI completion before start */ |
377 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
378 | continue; | |
379 | ||
a5f6abd4 WB |
380 | /* in duplex mode, clk is triggered by writing of TDBR */ |
381 | while (drv_data->rx < drv_data->rx_end) { | |
382 | write_TDBR(*(u8 *) (drv_data->tx)); | |
cc487e73 | 383 | while (read_STAT() & BIT_STAT_TXS) |
a5f6abd4 WB |
384 | continue; |
385 | while (!(read_STAT() & BIT_STAT_RXS)) | |
386 | continue; | |
387 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
388 | ++drv_data->rx; | |
389 | ++drv_data->tx; | |
390 | } | |
391 | } | |
392 | ||
393 | static void u8_cs_chg_duplex(struct driver_data *drv_data) | |
394 | { | |
395 | struct chip_data *chip = drv_data->cur_chip; | |
396 | ||
3f479a65 SZ |
397 | /* poll for SPI completion before start */ |
398 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
399 | continue; | |
400 | ||
a5f6abd4 | 401 | while (drv_data->rx < drv_data->rx_end) { |
fad91c89 | 402 | cs_active(chip); |
5fec5b5a | 403 | |
a5f6abd4 | 404 | write_TDBR(*(u8 *) (drv_data->tx)); |
cc487e73 | 405 | while (read_STAT() & BIT_STAT_TXS) |
a5f6abd4 WB |
406 | continue; |
407 | while (!(read_STAT() & BIT_STAT_RXS)) | |
408 | continue; | |
409 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
fad91c89 | 410 | cs_deactive(chip); |
5fec5b5a | 411 | |
a5f6abd4 WB |
412 | if (chip->cs_chg_udelay) |
413 | udelay(chip->cs_chg_udelay); | |
414 | ++drv_data->rx; | |
415 | ++drv_data->tx; | |
416 | } | |
a5f6abd4 WB |
417 | } |
418 | ||
419 | static void u16_writer(struct driver_data *drv_data) | |
420 | { | |
131b17d4 | 421 | dev_dbg(&drv_data->pdev->dev, |
88b40369 BW |
422 | "cr16 is 0x%x\n", read_STAT()); |
423 | ||
3f479a65 SZ |
424 | /* poll for SPI completion before start */ |
425 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
426 | continue; | |
427 | ||
a5f6abd4 WB |
428 | while (drv_data->tx < drv_data->tx_end) { |
429 | write_TDBR(*(u16 *) (drv_data->tx)); | |
430 | while ((read_STAT() & BIT_STAT_TXS)) | |
431 | continue; | |
432 | drv_data->tx += 2; | |
433 | } | |
a5f6abd4 WB |
434 | } |
435 | ||
436 | static void u16_cs_chg_writer(struct driver_data *drv_data) | |
437 | { | |
438 | struct chip_data *chip = drv_data->cur_chip; | |
439 | ||
3f479a65 SZ |
440 | /* poll for SPI completion before start */ |
441 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
442 | continue; | |
443 | ||
a5f6abd4 | 444 | while (drv_data->tx < drv_data->tx_end) { |
fad91c89 | 445 | cs_active(chip); |
a5f6abd4 WB |
446 | |
447 | write_TDBR(*(u16 *) (drv_data->tx)); | |
448 | while ((read_STAT() & BIT_STAT_TXS)) | |
449 | continue; | |
fad91c89 | 450 | cs_deactive(chip); |
5fec5b5a | 451 | |
a5f6abd4 WB |
452 | if (chip->cs_chg_udelay) |
453 | udelay(chip->cs_chg_udelay); | |
454 | drv_data->tx += 2; | |
455 | } | |
a5f6abd4 WB |
456 | } |
457 | ||
458 | static void u16_reader(struct driver_data *drv_data) | |
459 | { | |
88b40369 BW |
460 | dev_dbg(&drv_data->pdev->dev, |
461 | "cr-16 is 0x%x\n", read_STAT()); | |
cc487e73 | 462 | |
3f479a65 SZ |
463 | /* poll for SPI completion before start */ |
464 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
465 | continue; | |
466 | ||
cc487e73 SZ |
467 | /* clear TDBR buffer before read(else it will be shifted out) */ |
468 | write_TDBR(0xFFFF); | |
469 | ||
a5f6abd4 WB |
470 | dummy_read(); |
471 | ||
472 | while (drv_data->rx < (drv_data->rx_end - 2)) { | |
473 | while (!(read_STAT() & BIT_STAT_RXS)) | |
474 | continue; | |
475 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
476 | drv_data->rx += 2; | |
477 | } | |
478 | ||
479 | while (!(read_STAT() & BIT_STAT_RXS)) | |
480 | continue; | |
481 | *(u16 *) (drv_data->rx) = read_SHAW(); | |
482 | drv_data->rx += 2; | |
483 | } | |
484 | ||
485 | static void u16_cs_chg_reader(struct driver_data *drv_data) | |
486 | { | |
487 | struct chip_data *chip = drv_data->cur_chip; | |
488 | ||
3f479a65 SZ |
489 | /* poll for SPI completion before start */ |
490 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
491 | continue; | |
492 | ||
cc487e73 SZ |
493 | /* clear TDBR buffer before read(else it will be shifted out) */ |
494 | write_TDBR(0xFFFF); | |
a5f6abd4 | 495 | |
cc487e73 SZ |
496 | cs_active(chip); |
497 | dummy_read(); | |
498 | ||
499 | while (drv_data->rx < drv_data->rx_end) { | |
fad91c89 | 500 | cs_deactive(chip); |
5fec5b5a | 501 | |
a5f6abd4 WB |
502 | if (chip->cs_chg_udelay) |
503 | udelay(chip->cs_chg_udelay); | |
cc487e73 SZ |
504 | |
505 | while (!(read_STAT() & BIT_STAT_RXS)) | |
506 | continue; | |
507 | cs_active(chip); | |
508 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
a5f6abd4 WB |
509 | drv_data->rx += 2; |
510 | } | |
fad91c89 | 511 | cs_deactive(chip); |
cc487e73 SZ |
512 | |
513 | while (!(read_STAT() & BIT_STAT_RXS)) | |
514 | continue; | |
515 | *(u16 *) (drv_data->rx) = read_SHAW(); | |
516 | drv_data->rx += 2; | |
a5f6abd4 WB |
517 | } |
518 | ||
519 | static void u16_duplex(struct driver_data *drv_data) | |
520 | { | |
3f479a65 SZ |
521 | /* poll for SPI completion before start */ |
522 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
523 | continue; | |
524 | ||
a5f6abd4 WB |
525 | /* in duplex mode, clk is triggered by writing of TDBR */ |
526 | while (drv_data->tx < drv_data->tx_end) { | |
527 | write_TDBR(*(u16 *) (drv_data->tx)); | |
cc487e73 | 528 | while (read_STAT() & BIT_STAT_TXS) |
a5f6abd4 WB |
529 | continue; |
530 | while (!(read_STAT() & BIT_STAT_RXS)) | |
531 | continue; | |
532 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
533 | drv_data->rx += 2; | |
534 | drv_data->tx += 2; | |
535 | } | |
536 | } | |
537 | ||
538 | static void u16_cs_chg_duplex(struct driver_data *drv_data) | |
539 | { | |
540 | struct chip_data *chip = drv_data->cur_chip; | |
541 | ||
3f479a65 SZ |
542 | /* poll for SPI completion before start */ |
543 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
544 | continue; | |
545 | ||
a5f6abd4 | 546 | while (drv_data->tx < drv_data->tx_end) { |
fad91c89 | 547 | cs_active(chip); |
a5f6abd4 WB |
548 | |
549 | write_TDBR(*(u16 *) (drv_data->tx)); | |
cc487e73 | 550 | while (read_STAT() & BIT_STAT_TXS) |
a5f6abd4 WB |
551 | continue; |
552 | while (!(read_STAT() & BIT_STAT_RXS)) | |
553 | continue; | |
554 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
fad91c89 | 555 | cs_deactive(chip); |
5fec5b5a | 556 | |
a5f6abd4 WB |
557 | if (chip->cs_chg_udelay) |
558 | udelay(chip->cs_chg_udelay); | |
559 | drv_data->rx += 2; | |
560 | drv_data->tx += 2; | |
561 | } | |
a5f6abd4 WB |
562 | } |
563 | ||
564 | /* test if ther is more transfer to be done */ | |
565 | static void *next_transfer(struct driver_data *drv_data) | |
566 | { | |
567 | struct spi_message *msg = drv_data->cur_msg; | |
568 | struct spi_transfer *trans = drv_data->cur_transfer; | |
569 | ||
570 | /* Move to next transfer */ | |
571 | if (trans->transfer_list.next != &msg->transfers) { | |
572 | drv_data->cur_transfer = | |
573 | list_entry(trans->transfer_list.next, | |
574 | struct spi_transfer, transfer_list); | |
575 | return RUNNING_STATE; | |
576 | } else | |
577 | return DONE_STATE; | |
578 | } | |
579 | ||
580 | /* | |
581 | * caller already set message->status; | |
582 | * dma and pio irqs are blocked give finished message back | |
583 | */ | |
584 | static void giveback(struct driver_data *drv_data) | |
585 | { | |
fad91c89 | 586 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
587 | struct spi_transfer *last_transfer; |
588 | unsigned long flags; | |
589 | struct spi_message *msg; | |
590 | ||
591 | spin_lock_irqsave(&drv_data->lock, flags); | |
592 | msg = drv_data->cur_msg; | |
593 | drv_data->cur_msg = NULL; | |
594 | drv_data->cur_transfer = NULL; | |
595 | drv_data->cur_chip = NULL; | |
596 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
597 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
598 | ||
599 | last_transfer = list_entry(msg->transfers.prev, | |
600 | struct spi_transfer, transfer_list); | |
601 | ||
602 | msg->state = NULL; | |
603 | ||
604 | /* disable chip select signal. And not stop spi in autobuffer mode */ | |
605 | if (drv_data->tx_dma != 0xFFFF) { | |
fad91c89 | 606 | cs_deactive(chip); |
a5f6abd4 WB |
607 | bfin_spi_disable(drv_data); |
608 | } | |
609 | ||
fad91c89 BW |
610 | if (!drv_data->cs_change) |
611 | cs_deactive(chip); | |
612 | ||
a5f6abd4 WB |
613 | if (msg->complete) |
614 | msg->complete(msg->context); | |
615 | } | |
616 | ||
88b40369 | 617 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 WB |
618 | { |
619 | struct driver_data *drv_data = (struct driver_data *)dev_id; | |
620 | struct spi_message *msg = drv_data->cur_msg; | |
fad91c89 | 621 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 | 622 | |
88b40369 | 623 | dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); |
a32c691d | 624 | clear_dma_irqstat(spi_dma_ch); |
a5f6abd4 | 625 | |
d6fe89b0 | 626 | /* Wait for DMA to complete */ |
a32c691d | 627 | while (get_dma_curr_irqstat(spi_dma_ch) & DMA_RUN) |
d6fe89b0 BW |
628 | continue; |
629 | ||
a5f6abd4 | 630 | /* |
d6fe89b0 BW |
631 | * wait for the last transaction shifted out. HRM states: |
632 | * at this point there may still be data in the SPI DMA FIFO waiting | |
633 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
634 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
635 | */ |
636 | if (drv_data->tx != NULL) { | |
a32c691d BW |
637 | while ((read_STAT() & TXS) || |
638 | (read_STAT() & TXS)) | |
a5f6abd4 WB |
639 | continue; |
640 | } | |
641 | ||
a32c691d | 642 | while (!(read_STAT() & SPIF)) |
a5f6abd4 WB |
643 | continue; |
644 | ||
a5f6abd4 WB |
645 | msg->actual_length += drv_data->len_in_bytes; |
646 | ||
fad91c89 BW |
647 | if (drv_data->cs_change) |
648 | cs_deactive(chip); | |
649 | ||
a5f6abd4 WB |
650 | /* Move to next transfer */ |
651 | msg->state = next_transfer(drv_data); | |
652 | ||
653 | /* Schedule transfer tasklet */ | |
654 | tasklet_schedule(&drv_data->pump_transfers); | |
655 | ||
656 | /* free the irq handler before next transfer */ | |
88b40369 BW |
657 | dev_dbg(&drv_data->pdev->dev, |
658 | "disable dma channel irq%d\n", | |
a32c691d BW |
659 | spi_dma_ch); |
660 | dma_disable_irq(spi_dma_ch); | |
a5f6abd4 WB |
661 | |
662 | return IRQ_HANDLED; | |
663 | } | |
664 | ||
665 | static void pump_transfers(unsigned long data) | |
666 | { | |
667 | struct driver_data *drv_data = (struct driver_data *)data; | |
668 | struct spi_message *message = NULL; | |
669 | struct spi_transfer *transfer = NULL; | |
670 | struct spi_transfer *previous = NULL; | |
671 | struct chip_data *chip = NULL; | |
88b40369 BW |
672 | u8 width; |
673 | u16 cr, dma_width, dma_config; | |
a5f6abd4 WB |
674 | u32 tranf_success = 1; |
675 | ||
676 | /* Get current state information */ | |
677 | message = drv_data->cur_msg; | |
678 | transfer = drv_data->cur_transfer; | |
679 | chip = drv_data->cur_chip; | |
a5f6abd4 WB |
680 | /* |
681 | * if msg is error or done, report it back using complete() callback | |
682 | */ | |
683 | ||
684 | /* Handle for abort */ | |
685 | if (message->state == ERROR_STATE) { | |
686 | message->status = -EIO; | |
687 | giveback(drv_data); | |
688 | return; | |
689 | } | |
690 | ||
691 | /* Handle end of message */ | |
692 | if (message->state == DONE_STATE) { | |
693 | message->status = 0; | |
694 | giveback(drv_data); | |
695 | return; | |
696 | } | |
697 | ||
698 | /* Delay if requested at end of transfer */ | |
699 | if (message->state == RUNNING_STATE) { | |
700 | previous = list_entry(transfer->transfer_list.prev, | |
701 | struct spi_transfer, transfer_list); | |
702 | if (previous->delay_usecs) | |
703 | udelay(previous->delay_usecs); | |
704 | } | |
705 | ||
706 | /* Setup the transfer state based on the type of transfer */ | |
707 | if (flush(drv_data) == 0) { | |
708 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
709 | message->status = -EIO; | |
710 | giveback(drv_data); | |
711 | return; | |
712 | } | |
713 | ||
714 | if (transfer->tx_buf != NULL) { | |
715 | drv_data->tx = (void *)transfer->tx_buf; | |
716 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
717 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
718 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
719 | } else { |
720 | drv_data->tx = NULL; | |
721 | } | |
722 | ||
723 | if (transfer->rx_buf != NULL) { | |
724 | drv_data->rx = transfer->rx_buf; | |
725 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
726 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
727 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
728 | } else { |
729 | drv_data->rx = NULL; | |
730 | } | |
731 | ||
732 | drv_data->rx_dma = transfer->rx_dma; | |
733 | drv_data->tx_dma = transfer->tx_dma; | |
734 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 735 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 WB |
736 | |
737 | width = chip->width; | |
738 | if (width == CFG_SPI_WORDSIZE16) { | |
739 | drv_data->len = (transfer->len) >> 1; | |
740 | } else { | |
741 | drv_data->len = transfer->len; | |
742 | } | |
743 | drv_data->write = drv_data->tx ? chip->write : null_writer; | |
744 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
745 | drv_data->duplex = chip->duplex ? chip->duplex : null_writer; | |
131b17d4 BW |
746 | dev_dbg(&drv_data->pdev->dev, "transfer: ", |
747 | "drv_data->write is %p, chip->write is %p, null_wr is %p\n", | |
748 | drv_data->write, chip->write, null_writer); | |
a5f6abd4 WB |
749 | |
750 | /* speed and width has been set on per message */ | |
751 | message->state = RUNNING_STATE; | |
752 | dma_config = 0; | |
753 | ||
cc487e73 SZ |
754 | write_STAT(BIT_STAT_CLR); |
755 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); | |
fad91c89 | 756 | cs_active(chip); |
a5f6abd4 | 757 | |
88b40369 BW |
758 | dev_dbg(&drv_data->pdev->dev, |
759 | "now pumping a transfer: width is %d, len is %d\n", | |
760 | width, transfer->len); | |
a5f6abd4 WB |
761 | |
762 | /* | |
763 | * Try to map dma buffer and do a dma transfer if | |
764 | * successful use different way to r/w according to | |
765 | * drv_data->cur_chip->enable_dma | |
766 | */ | |
767 | if (drv_data->cur_chip->enable_dma && drv_data->len > 6) { | |
768 | ||
a32c691d BW |
769 | disable_dma(spi_dma_ch); |
770 | clear_dma_irqstat(spi_dma_ch); | |
a5f6abd4 WB |
771 | |
772 | /* config dma channel */ | |
88b40369 | 773 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
a5f6abd4 | 774 | if (width == CFG_SPI_WORDSIZE16) { |
a32c691d BW |
775 | set_dma_x_count(spi_dma_ch, drv_data->len); |
776 | set_dma_x_modify(spi_dma_ch, 2); | |
a5f6abd4 WB |
777 | dma_width = WDSIZE_16; |
778 | } else { | |
a32c691d BW |
779 | set_dma_x_count(spi_dma_ch, drv_data->len); |
780 | set_dma_x_modify(spi_dma_ch, 1); | |
a5f6abd4 WB |
781 | dma_width = WDSIZE_8; |
782 | } | |
783 | ||
3f479a65 SZ |
784 | /* poll for SPI completion before start */ |
785 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
786 | continue; | |
787 | ||
a5f6abd4 WB |
788 | /* dirty hack for autobuffer DMA mode */ |
789 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
790 | dev_dbg(&drv_data->pdev->dev, |
791 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 | 792 | |
cc487e73 SZ |
793 | /* set SPI transfer mode */ |
794 | write_CTRL(cr | CFG_SPI_DMAWRITE); | |
795 | ||
a5f6abd4 WB |
796 | /* no irq in autobuffer mode */ |
797 | dma_config = | |
798 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
a32c691d BW |
799 | set_dma_config(spi_dma_ch, dma_config); |
800 | set_dma_start_addr(spi_dma_ch, | |
801 | (unsigned long)drv_data->tx); | |
802 | enable_dma(spi_dma_ch); | |
a5f6abd4 WB |
803 | |
804 | /* just return here, there can only be one transfer in this mode */ | |
805 | message->status = 0; | |
806 | giveback(drv_data); | |
807 | return; | |
808 | } | |
809 | ||
810 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
811 | if (drv_data->rx != NULL) { | |
812 | /* set transfer mode, and enable SPI */ | |
88b40369 | 813 | dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n"); |
a5f6abd4 | 814 | |
cc487e73 SZ |
815 | /* set SPI transfer mode */ |
816 | write_CTRL(cr | CFG_SPI_DMAREAD); | |
a5f6abd4 WB |
817 | |
818 | /* clear tx reg soformer data is not shifted out */ | |
cc487e73 | 819 | write_TDBR(0xFFFF); |
a5f6abd4 | 820 | |
a32c691d | 821 | set_dma_x_count(spi_dma_ch, drv_data->len); |
a5f6abd4 WB |
822 | |
823 | /* start dma */ | |
a32c691d | 824 | dma_enable_irq(spi_dma_ch); |
a5f6abd4 | 825 | dma_config = (WNR | RESTART | dma_width | DI_EN); |
a32c691d BW |
826 | set_dma_config(spi_dma_ch, dma_config); |
827 | set_dma_start_addr(spi_dma_ch, | |
828 | (unsigned long)drv_data->rx); | |
829 | enable_dma(spi_dma_ch); | |
a5f6abd4 | 830 | |
a5f6abd4 | 831 | } else if (drv_data->tx != NULL) { |
88b40369 | 832 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 833 | |
cc487e73 SZ |
834 | /* set SPI transfer mode */ |
835 | write_CTRL(cr | CFG_SPI_DMAWRITE); | |
836 | ||
a5f6abd4 | 837 | /* start dma */ |
a32c691d | 838 | dma_enable_irq(spi_dma_ch); |
a5f6abd4 | 839 | dma_config = (RESTART | dma_width | DI_EN); |
a32c691d BW |
840 | set_dma_config(spi_dma_ch, dma_config); |
841 | set_dma_start_addr(spi_dma_ch, | |
842 | (unsigned long)drv_data->tx); | |
843 | enable_dma(spi_dma_ch); | |
a5f6abd4 WB |
844 | } |
845 | } else { | |
846 | /* IO mode write then read */ | |
88b40369 | 847 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
a5f6abd4 | 848 | |
a5f6abd4 WB |
849 | if (drv_data->tx != NULL && drv_data->rx != NULL) { |
850 | /* full duplex mode */ | |
851 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
852 | (drv_data->rx_end - drv_data->rx)); | |
88b40369 BW |
853 | dev_dbg(&drv_data->pdev->dev, |
854 | "IO duplex: cr is 0x%x\n", cr); | |
a5f6abd4 | 855 | |
cc487e73 SZ |
856 | /* set SPI transfer mode */ |
857 | write_CTRL(cr | CFG_SPI_WRITE); | |
a5f6abd4 WB |
858 | |
859 | drv_data->duplex(drv_data); | |
860 | ||
861 | if (drv_data->tx != drv_data->tx_end) | |
862 | tranf_success = 0; | |
863 | } else if (drv_data->tx != NULL) { | |
864 | /* write only half duplex */ | |
131b17d4 | 865 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 866 | "IO write: cr is 0x%x\n", cr); |
a5f6abd4 | 867 | |
cc487e73 SZ |
868 | /* set SPI transfer mode */ |
869 | write_CTRL(cr | CFG_SPI_WRITE); | |
a5f6abd4 WB |
870 | |
871 | drv_data->write(drv_data); | |
872 | ||
873 | if (drv_data->tx != drv_data->tx_end) | |
874 | tranf_success = 0; | |
875 | } else if (drv_data->rx != NULL) { | |
876 | /* read only half duplex */ | |
131b17d4 | 877 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 878 | "IO read: cr is 0x%x\n", cr); |
a5f6abd4 | 879 | |
cc487e73 SZ |
880 | /* set SPI transfer mode */ |
881 | write_CTRL(cr | CFG_SPI_READ); | |
a5f6abd4 WB |
882 | |
883 | drv_data->read(drv_data); | |
884 | if (drv_data->rx != drv_data->rx_end) | |
885 | tranf_success = 0; | |
886 | } | |
887 | ||
888 | if (!tranf_success) { | |
131b17d4 | 889 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 890 | "IO write error!\n"); |
a5f6abd4 WB |
891 | message->state = ERROR_STATE; |
892 | } else { | |
893 | /* Update total byte transfered */ | |
894 | message->actual_length += drv_data->len; | |
895 | ||
896 | /* Move to next transfer of this msg */ | |
897 | message->state = next_transfer(drv_data); | |
898 | } | |
899 | ||
900 | /* Schedule next transfer tasklet */ | |
901 | tasklet_schedule(&drv_data->pump_transfers); | |
902 | ||
903 | } | |
904 | } | |
905 | ||
906 | /* pop a msg from queue and kick off real transfer */ | |
907 | static void pump_messages(struct work_struct *work) | |
908 | { | |
131b17d4 | 909 | struct driver_data *drv_data; |
a5f6abd4 WB |
910 | unsigned long flags; |
911 | ||
131b17d4 BW |
912 | drv_data = container_of(work, struct driver_data, pump_messages); |
913 | ||
a5f6abd4 WB |
914 | /* Lock queue and check for queue work */ |
915 | spin_lock_irqsave(&drv_data->lock, flags); | |
916 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
917 | /* pumper kicked off but no work to do */ | |
918 | drv_data->busy = 0; | |
919 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
920 | return; | |
921 | } | |
922 | ||
923 | /* Make sure we are not already running a message */ | |
924 | if (drv_data->cur_msg) { | |
925 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
926 | return; | |
927 | } | |
928 | ||
929 | /* Extract head of queue */ | |
930 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
931 | struct spi_message, queue); | |
5fec5b5a BW |
932 | |
933 | /* Setup the SSP using the per chip configuration */ | |
934 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
935 | if (restore_state(drv_data)) { | |
936 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
937 | return; | |
938 | }; | |
939 | ||
a5f6abd4 WB |
940 | list_del_init(&drv_data->cur_msg->queue); |
941 | ||
942 | /* Initial message state */ | |
943 | drv_data->cur_msg->state = START_STATE; | |
944 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
945 | struct spi_transfer, transfer_list); | |
946 | ||
5fec5b5a BW |
947 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
948 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
949 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
950 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
951 | |
952 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
953 | "the first transfer len is %d\n", |
954 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
955 | |
956 | /* Mark as busy and launch transfers */ | |
957 | tasklet_schedule(&drv_data->pump_transfers); | |
958 | ||
959 | drv_data->busy = 1; | |
960 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
961 | } | |
962 | ||
963 | /* | |
964 | * got a msg to transfer, queue it in drv_data->queue. | |
965 | * And kick off message pumper | |
966 | */ | |
967 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
968 | { | |
969 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
970 | unsigned long flags; | |
971 | ||
972 | spin_lock_irqsave(&drv_data->lock, flags); | |
973 | ||
974 | if (drv_data->run == QUEUE_STOPPED) { | |
975 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
976 | return -ESHUTDOWN; | |
977 | } | |
978 | ||
979 | msg->actual_length = 0; | |
980 | msg->status = -EINPROGRESS; | |
981 | msg->state = START_STATE; | |
982 | ||
88b40369 | 983 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
984 | list_add_tail(&msg->queue, &drv_data->queue); |
985 | ||
986 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
987 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
988 | ||
989 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
990 | ||
991 | return 0; | |
992 | } | |
993 | ||
12e17c42 SZ |
994 | #define MAX_SPI_SSEL 7 |
995 | ||
996 | static u16 ssel[3][MAX_SPI_SSEL] = { | |
997 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, | |
998 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
999 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
1000 | ||
1001 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
1002 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
1003 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
1004 | ||
1005 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
1006 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
1007 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
1008 | }; | |
1009 | ||
a5f6abd4 WB |
1010 | /* first setup for new devices */ |
1011 | static int setup(struct spi_device *spi) | |
1012 | { | |
1013 | struct bfin5xx_spi_chip *chip_info = NULL; | |
1014 | struct chip_data *chip; | |
1015 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1016 | u8 spi_flg; | |
1017 | ||
1018 | /* Abort device setup if requested features are not supported */ | |
1019 | if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) { | |
1020 | dev_err(&spi->dev, "requested mode not fully supported\n"); | |
1021 | return -EINVAL; | |
1022 | } | |
1023 | ||
1024 | /* Zero (the default) here means 8 bits */ | |
1025 | if (!spi->bits_per_word) | |
1026 | spi->bits_per_word = 8; | |
1027 | ||
1028 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) | |
1029 | return -EINVAL; | |
1030 | ||
1031 | /* Only alloc (or use chip_info) on first setup */ | |
1032 | chip = spi_get_ctldata(spi); | |
1033 | if (chip == NULL) { | |
1034 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1035 | if (!chip) | |
1036 | return -ENOMEM; | |
1037 | ||
1038 | chip->enable_dma = 0; | |
1039 | chip_info = spi->controller_data; | |
1040 | } | |
1041 | ||
1042 | /* chip_info isn't always needed */ | |
1043 | if (chip_info) { | |
2ed35516 MF |
1044 | /* Make sure people stop trying to set fields via ctl_reg |
1045 | * when they should actually be using common SPI framework. | |
1046 | * Currently we let through: WOM EMISO PSSE GM SZ TIMOD. | |
1047 | * Not sure if a user actually needs/uses any of these, | |
1048 | * but let's assume (for now) they do. | |
1049 | */ | |
1050 | if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) { | |
1051 | dev_err(&spi->dev, "do not set bits in ctl_reg " | |
1052 | "that the SPI framework manages\n"); | |
1053 | return -EINVAL; | |
1054 | } | |
1055 | ||
a5f6abd4 WB |
1056 | chip->enable_dma = chip_info->enable_dma != 0 |
1057 | && drv_data->master_info->enable_dma; | |
1058 | chip->ctl_reg = chip_info->ctl_reg; | |
1059 | chip->bits_per_word = chip_info->bits_per_word; | |
1060 | chip->cs_change_per_word = chip_info->cs_change_per_word; | |
1061 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
1062 | } | |
1063 | ||
1064 | /* translate common spi framework into our register */ | |
1065 | if (spi->mode & SPI_CPOL) | |
1066 | chip->ctl_reg |= CPOL; | |
1067 | if (spi->mode & SPI_CPHA) | |
1068 | chip->ctl_reg |= CPHA; | |
1069 | if (spi->mode & SPI_LSB_FIRST) | |
1070 | chip->ctl_reg |= LSBF; | |
1071 | /* we dont support running in slave mode (yet?) */ | |
1072 | chip->ctl_reg |= MSTR; | |
1073 | ||
1074 | /* | |
1075 | * if any one SPI chip is registered and wants DMA, request the | |
1076 | * DMA channel for it | |
1077 | */ | |
1078 | if (chip->enable_dma && !dma_requested) { | |
1079 | /* register dma irq handler */ | |
a32c691d | 1080 | if (request_dma(spi_dma_ch, "BF53x_SPI_DMA") < 0) { |
88b40369 BW |
1081 | dev_dbg(&spi->dev, |
1082 | "Unable to request BlackFin SPI DMA channel\n"); | |
a5f6abd4 WB |
1083 | return -ENODEV; |
1084 | } | |
a32c691d BW |
1085 | if (set_dma_callback(spi_dma_ch, (void *)dma_irq_handler, |
1086 | drv_data) < 0) { | |
88b40369 | 1087 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
a5f6abd4 WB |
1088 | return -EPERM; |
1089 | } | |
a32c691d | 1090 | dma_disable_irq(spi_dma_ch); |
a5f6abd4 WB |
1091 | dma_requested = 1; |
1092 | } | |
1093 | ||
1094 | /* | |
1095 | * Notice: for blackfin, the speed_hz is the value of register | |
1096 | * SPI_BAUD, not the real baudrate | |
1097 | */ | |
1098 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
1099 | spi_flg = ~(1 << (spi->chip_select)); | |
1100 | chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select)); | |
1101 | chip->chip_select_num = spi->chip_select; | |
1102 | ||
1103 | switch (chip->bits_per_word) { | |
1104 | case 8: | |
1105 | chip->n_bytes = 1; | |
1106 | chip->width = CFG_SPI_WORDSIZE8; | |
1107 | chip->read = chip->cs_change_per_word ? | |
1108 | u8_cs_chg_reader : u8_reader; | |
1109 | chip->write = chip->cs_change_per_word ? | |
1110 | u8_cs_chg_writer : u8_writer; | |
1111 | chip->duplex = chip->cs_change_per_word ? | |
1112 | u8_cs_chg_duplex : u8_duplex; | |
1113 | break; | |
1114 | ||
1115 | case 16: | |
1116 | chip->n_bytes = 2; | |
1117 | chip->width = CFG_SPI_WORDSIZE16; | |
1118 | chip->read = chip->cs_change_per_word ? | |
1119 | u16_cs_chg_reader : u16_reader; | |
1120 | chip->write = chip->cs_change_per_word ? | |
1121 | u16_cs_chg_writer : u16_writer; | |
1122 | chip->duplex = chip->cs_change_per_word ? | |
1123 | u16_cs_chg_duplex : u16_duplex; | |
1124 | break; | |
1125 | ||
1126 | default: | |
1127 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1128 | chip->bits_per_word); | |
1129 | kfree(chip); | |
1130 | return -ENODEV; | |
1131 | } | |
1132 | ||
898eb71c | 1133 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1134 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1135 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1136 | chip->ctl_reg, chip->flag); |
1137 | ||
1138 | spi_set_ctldata(spi, chip); | |
1139 | ||
12e17c42 SZ |
1140 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
1141 | if ((chip->chip_select_num > 0) | |
1142 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1143 | peripheral_request(ssel[spi->master->bus_num] | |
1144 | [chip->chip_select_num-1], DRV_NAME); | |
1145 | ||
a5f6abd4 WB |
1146 | return 0; |
1147 | } | |
1148 | ||
1149 | /* | |
1150 | * callback for spi framework. | |
1151 | * clean driver specific data | |
1152 | */ | |
88b40369 | 1153 | static void cleanup(struct spi_device *spi) |
a5f6abd4 | 1154 | { |
27bb9e79 | 1155 | struct chip_data *chip = spi_get_ctldata(spi); |
a5f6abd4 | 1156 | |
12e17c42 SZ |
1157 | if ((chip->chip_select_num > 0) |
1158 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1159 | peripheral_free(ssel[spi->master->bus_num] | |
1160 | [chip->chip_select_num-1]); | |
1161 | ||
a5f6abd4 WB |
1162 | kfree(chip); |
1163 | } | |
1164 | ||
1165 | static inline int init_queue(struct driver_data *drv_data) | |
1166 | { | |
1167 | INIT_LIST_HEAD(&drv_data->queue); | |
1168 | spin_lock_init(&drv_data->lock); | |
1169 | ||
1170 | drv_data->run = QUEUE_STOPPED; | |
1171 | drv_data->busy = 0; | |
1172 | ||
1173 | /* init transfer tasklet */ | |
1174 | tasklet_init(&drv_data->pump_transfers, | |
1175 | pump_transfers, (unsigned long)drv_data); | |
1176 | ||
1177 | /* init messages workqueue */ | |
1178 | INIT_WORK(&drv_data->pump_messages, pump_messages); | |
1179 | drv_data->workqueue = | |
49dce689 | 1180 | create_singlethread_workqueue(drv_data->master->dev.parent->bus_id); |
a5f6abd4 WB |
1181 | if (drv_data->workqueue == NULL) |
1182 | return -EBUSY; | |
1183 | ||
1184 | return 0; | |
1185 | } | |
1186 | ||
1187 | static inline int start_queue(struct driver_data *drv_data) | |
1188 | { | |
1189 | unsigned long flags; | |
1190 | ||
1191 | spin_lock_irqsave(&drv_data->lock, flags); | |
1192 | ||
1193 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1194 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1195 | return -EBUSY; | |
1196 | } | |
1197 | ||
1198 | drv_data->run = QUEUE_RUNNING; | |
1199 | drv_data->cur_msg = NULL; | |
1200 | drv_data->cur_transfer = NULL; | |
1201 | drv_data->cur_chip = NULL; | |
1202 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1203 | ||
1204 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1205 | ||
1206 | return 0; | |
1207 | } | |
1208 | ||
1209 | static inline int stop_queue(struct driver_data *drv_data) | |
1210 | { | |
1211 | unsigned long flags; | |
1212 | unsigned limit = 500; | |
1213 | int status = 0; | |
1214 | ||
1215 | spin_lock_irqsave(&drv_data->lock, flags); | |
1216 | ||
1217 | /* | |
1218 | * This is a bit lame, but is optimized for the common execution path. | |
1219 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1220 | * execution path (pump_messages) would be required to call wake_up or | |
1221 | * friends on every SPI message. Do this instead | |
1222 | */ | |
1223 | drv_data->run = QUEUE_STOPPED; | |
1224 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1225 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1226 | msleep(10); | |
1227 | spin_lock_irqsave(&drv_data->lock, flags); | |
1228 | } | |
1229 | ||
1230 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1231 | status = -EBUSY; | |
1232 | ||
1233 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1234 | ||
1235 | return status; | |
1236 | } | |
1237 | ||
1238 | static inline int destroy_queue(struct driver_data *drv_data) | |
1239 | { | |
1240 | int status; | |
1241 | ||
1242 | status = stop_queue(drv_data); | |
1243 | if (status != 0) | |
1244 | return status; | |
1245 | ||
1246 | destroy_workqueue(drv_data->workqueue); | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
7c4ef094 | 1251 | static int setup_pin_mux(int action, int bus_num) |
cc2f81a6 MH |
1252 | { |
1253 | ||
7c4ef094 SZ |
1254 | u16 pin_req[3][4] = { |
1255 | {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | |
1256 | {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, | |
1257 | {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0}, | |
1258 | }; | |
cc2f81a6 MH |
1259 | |
1260 | if (action) { | |
7c4ef094 | 1261 | if (peripheral_request_list(pin_req[bus_num], DRV_NAME)) |
cc2f81a6 MH |
1262 | return -EFAULT; |
1263 | } else { | |
7c4ef094 | 1264 | peripheral_free_list(pin_req[bus_num]); |
cc2f81a6 MH |
1265 | } |
1266 | ||
1267 | return 0; | |
1268 | } | |
1269 | ||
a5f6abd4 WB |
1270 | static int __init bfin5xx_spi_probe(struct platform_device *pdev) |
1271 | { | |
1272 | struct device *dev = &pdev->dev; | |
1273 | struct bfin5xx_spi_master *platform_info; | |
1274 | struct spi_master *master; | |
1275 | struct driver_data *drv_data = 0; | |
a32c691d | 1276 | struct resource *res; |
a5f6abd4 WB |
1277 | int status = 0; |
1278 | ||
1279 | platform_info = dev->platform_data; | |
1280 | ||
1281 | /* Allocate master with space for drv_data */ | |
1282 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1283 | if (!master) { | |
1284 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1285 | return -ENOMEM; | |
1286 | } | |
131b17d4 | 1287 | |
a5f6abd4 WB |
1288 | drv_data = spi_master_get_devdata(master); |
1289 | drv_data->master = master; | |
1290 | drv_data->master_info = platform_info; | |
1291 | drv_data->pdev = pdev; | |
1292 | ||
1293 | master->bus_num = pdev->id; | |
1294 | master->num_chipselect = platform_info->num_chipselect; | |
1295 | master->cleanup = cleanup; | |
1296 | master->setup = setup; | |
1297 | master->transfer = transfer; | |
1298 | ||
a32c691d BW |
1299 | /* Find and map our resources */ |
1300 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1301 | if (res == NULL) { | |
1302 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1303 | status = -ENOENT; | |
1304 | goto out_error_get_res; | |
1305 | } | |
1306 | ||
1307 | spi_regs_base = (u32) ioremap(res->start, (res->end - res->start)+1); | |
1308 | if (!spi_regs_base) { | |
1309 | dev_err(dev, "Cannot map IO\n"); | |
1310 | status = -ENXIO; | |
1311 | goto out_error_ioremap; | |
1312 | } | |
1313 | ||
1314 | spi_dma_ch = platform_get_irq(pdev, 0); | |
1315 | if (spi_dma_ch < 0) { | |
1316 | dev_err(dev, "No DMA channel specified\n"); | |
1317 | status = -ENOENT; | |
1318 | goto out_error_no_dma_ch; | |
1319 | } | |
1320 | ||
a5f6abd4 WB |
1321 | /* Initial and start queue */ |
1322 | status = init_queue(drv_data); | |
1323 | if (status != 0) { | |
a32c691d | 1324 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1325 | goto out_error_queue_alloc; |
1326 | } | |
a32c691d | 1327 | |
a5f6abd4 WB |
1328 | status = start_queue(drv_data); |
1329 | if (status != 0) { | |
a32c691d | 1330 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1331 | goto out_error_queue_alloc; |
1332 | } | |
1333 | ||
1334 | /* Register with the SPI framework */ | |
1335 | platform_set_drvdata(pdev, drv_data); | |
1336 | status = spi_register_master(master); | |
1337 | if (status != 0) { | |
a32c691d | 1338 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1339 | goto out_error_queue_alloc; |
1340 | } | |
a32c691d | 1341 | |
7c4ef094 SZ |
1342 | if (setup_pin_mux(1, master->bus_num)) { |
1343 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1344 | goto out_error; | |
1345 | } | |
1346 | ||
a32c691d BW |
1347 | dev_info(dev, "%s, Version %s, regs_base @ 0x%08x\n", |
1348 | DRV_DESC, DRV_VERSION, spi_regs_base); | |
a5f6abd4 WB |
1349 | return status; |
1350 | ||
cc2f81a6 | 1351 | out_error_queue_alloc: |
a5f6abd4 | 1352 | destroy_queue(drv_data); |
a32c691d BW |
1353 | out_error_no_dma_ch: |
1354 | iounmap((void *) spi_regs_base); | |
1355 | out_error_ioremap: | |
1356 | out_error_get_res: | |
cc2f81a6 | 1357 | out_error: |
a5f6abd4 | 1358 | spi_master_put(master); |
cc2f81a6 | 1359 | |
a5f6abd4 WB |
1360 | return status; |
1361 | } | |
1362 | ||
1363 | /* stop hardware and remove the driver */ | |
1364 | static int __devexit bfin5xx_spi_remove(struct platform_device *pdev) | |
1365 | { | |
1366 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1367 | int status = 0; | |
1368 | ||
1369 | if (!drv_data) | |
1370 | return 0; | |
1371 | ||
1372 | /* Remove the queue */ | |
1373 | status = destroy_queue(drv_data); | |
1374 | if (status != 0) | |
1375 | return status; | |
1376 | ||
1377 | /* Disable the SSP at the peripheral and SOC level */ | |
1378 | bfin_spi_disable(drv_data); | |
1379 | ||
1380 | /* Release DMA */ | |
1381 | if (drv_data->master_info->enable_dma) { | |
a32c691d BW |
1382 | if (dma_channel_active(spi_dma_ch)) |
1383 | free_dma(spi_dma_ch); | |
a5f6abd4 WB |
1384 | } |
1385 | ||
1386 | /* Disconnect from the SPI framework */ | |
1387 | spi_unregister_master(drv_data->master); | |
1388 | ||
7c4ef094 | 1389 | setup_pin_mux(0, drv_data->master->bus_num); |
cc2f81a6 | 1390 | |
a5f6abd4 WB |
1391 | /* Prevent double remove */ |
1392 | platform_set_drvdata(pdev, NULL); | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | #ifdef CONFIG_PM | |
1398 | static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1399 | { | |
1400 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1401 | int status = 0; | |
1402 | ||
1403 | status = stop_queue(drv_data); | |
1404 | if (status != 0) | |
1405 | return status; | |
1406 | ||
1407 | /* stop hardware */ | |
1408 | bfin_spi_disable(drv_data); | |
1409 | ||
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | static int bfin5xx_spi_resume(struct platform_device *pdev) | |
1414 | { | |
1415 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1416 | int status = 0; | |
1417 | ||
1418 | /* Enable the SPI interface */ | |
1419 | bfin_spi_enable(drv_data); | |
1420 | ||
1421 | /* Start the queue running */ | |
1422 | status = start_queue(drv_data); | |
1423 | if (status != 0) { | |
1424 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1425 | return status; | |
1426 | } | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | #else | |
1431 | #define bfin5xx_spi_suspend NULL | |
1432 | #define bfin5xx_spi_resume NULL | |
1433 | #endif /* CONFIG_PM */ | |
1434 | ||
fc3ba952 | 1435 | MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */ |
a5f6abd4 | 1436 | static struct platform_driver bfin5xx_spi_driver = { |
fc3ba952 | 1437 | .driver = { |
a32c691d | 1438 | .name = DRV_NAME, |
88b40369 BW |
1439 | .owner = THIS_MODULE, |
1440 | }, | |
1441 | .suspend = bfin5xx_spi_suspend, | |
1442 | .resume = bfin5xx_spi_resume, | |
1443 | .remove = __devexit_p(bfin5xx_spi_remove), | |
a5f6abd4 WB |
1444 | }; |
1445 | ||
1446 | static int __init bfin5xx_spi_init(void) | |
1447 | { | |
88b40369 | 1448 | return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe); |
a5f6abd4 | 1449 | } |
a5f6abd4 WB |
1450 | module_init(bfin5xx_spi_init); |
1451 | ||
1452 | static void __exit bfin5xx_spi_exit(void) | |
1453 | { | |
1454 | platform_driver_unregister(&bfin5xx_spi_driver); | |
1455 | } | |
a5f6abd4 | 1456 | module_exit(bfin5xx_spi_exit); |