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Commit | Line | Data |
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a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
131b17d4 | 15 | #include <linux/io.h> |
a5f6abd4 | 16 | #include <linux/ioport.h> |
131b17d4 | 17 | #include <linux/irq.h> |
a5f6abd4 WB |
18 | #include <linux/errno.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/workqueue.h> | |
a5f6abd4 | 24 | |
a5f6abd4 | 25 | #include <asm/dma.h> |
131b17d4 | 26 | #include <asm/portmux.h> |
a5f6abd4 | 27 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
28 | #include <asm/cacheflush.h> |
29 | ||
a32c691d BW |
30 | #define DRV_NAME "bfin-spi" |
31 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
6b1a8028 | 32 | #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver" |
a32c691d BW |
33 | #define DRV_VERSION "1.0" |
34 | ||
35 | MODULE_AUTHOR(DRV_AUTHOR); | |
36 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
37 | MODULE_LICENSE("GPL"); |
38 | ||
bb90eb00 | 39 | #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0) |
a5f6abd4 | 40 | |
bb90eb00 BW |
41 | #define START_STATE ((void *)0) |
42 | #define RUNNING_STATE ((void *)1) | |
43 | #define DONE_STATE ((void *)2) | |
44 | #define ERROR_STATE ((void *)-1) | |
45 | #define QUEUE_RUNNING 0 | |
46 | #define QUEUE_STOPPED 1 | |
a5f6abd4 WB |
47 | |
48 | struct driver_data { | |
49 | /* Driver model hookup */ | |
50 | struct platform_device *pdev; | |
51 | ||
52 | /* SPI framework hookup */ | |
53 | struct spi_master *master; | |
54 | ||
bb90eb00 | 55 | /* Regs base of SPI controller */ |
f452126c | 56 | void __iomem *regs_base; |
bb90eb00 | 57 | |
003d9226 BW |
58 | /* Pin request list */ |
59 | u16 *pin_req; | |
60 | ||
a5f6abd4 WB |
61 | /* BFIN hookup */ |
62 | struct bfin5xx_spi_master *master_info; | |
63 | ||
64 | /* Driver message queue */ | |
65 | struct workqueue_struct *workqueue; | |
66 | struct work_struct pump_messages; | |
67 | spinlock_t lock; | |
68 | struct list_head queue; | |
69 | int busy; | |
70 | int run; | |
71 | ||
72 | /* Message Transfer pump */ | |
73 | struct tasklet_struct pump_transfers; | |
74 | ||
75 | /* Current message transfer state info */ | |
76 | struct spi_message *cur_msg; | |
77 | struct spi_transfer *cur_transfer; | |
78 | struct chip_data *cur_chip; | |
79 | size_t len_in_bytes; | |
80 | size_t len; | |
81 | void *tx; | |
82 | void *tx_end; | |
83 | void *rx; | |
84 | void *rx_end; | |
bb90eb00 BW |
85 | |
86 | /* DMA stuffs */ | |
87 | int dma_channel; | |
a5f6abd4 | 88 | int dma_mapped; |
bb90eb00 | 89 | int dma_requested; |
a5f6abd4 WB |
90 | dma_addr_t rx_dma; |
91 | dma_addr_t tx_dma; | |
bb90eb00 | 92 | |
a5f6abd4 WB |
93 | size_t rx_map_len; |
94 | size_t tx_map_len; | |
95 | u8 n_bytes; | |
fad91c89 | 96 | int cs_change; |
a5f6abd4 WB |
97 | void (*write) (struct driver_data *); |
98 | void (*read) (struct driver_data *); | |
99 | void (*duplex) (struct driver_data *); | |
100 | }; | |
101 | ||
102 | struct chip_data { | |
103 | u16 ctl_reg; | |
104 | u16 baud; | |
105 | u16 flag; | |
106 | ||
107 | u8 chip_select_num; | |
108 | u8 n_bytes; | |
88b40369 | 109 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
110 | u8 enable_dma; |
111 | u8 bits_per_word; /* 8 or 16 */ | |
112 | u8 cs_change_per_word; | |
62310e51 | 113 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
a5f6abd4 WB |
114 | void (*write) (struct driver_data *); |
115 | void (*read) (struct driver_data *); | |
116 | void (*duplex) (struct driver_data *); | |
117 | }; | |
118 | ||
bb90eb00 BW |
119 | #define DEFINE_SPI_REG(reg, off) \ |
120 | static inline u16 read_##reg(struct driver_data *drv_data) \ | |
121 | { return bfin_read16(drv_data->regs_base + off); } \ | |
122 | static inline void write_##reg(struct driver_data *drv_data, u16 v) \ | |
123 | { bfin_write16(drv_data->regs_base + off, v); } | |
124 | ||
125 | DEFINE_SPI_REG(CTRL, 0x00) | |
126 | DEFINE_SPI_REG(FLAG, 0x04) | |
127 | DEFINE_SPI_REG(STAT, 0x08) | |
128 | DEFINE_SPI_REG(TDBR, 0x0C) | |
129 | DEFINE_SPI_REG(RDBR, 0x10) | |
130 | DEFINE_SPI_REG(BAUD, 0x14) | |
131 | DEFINE_SPI_REG(SHAW, 0x18) | |
132 | ||
88b40369 | 133 | static void bfin_spi_enable(struct driver_data *drv_data) |
a5f6abd4 WB |
134 | { |
135 | u16 cr; | |
136 | ||
bb90eb00 BW |
137 | cr = read_CTRL(drv_data); |
138 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
139 | } |
140 | ||
88b40369 | 141 | static void bfin_spi_disable(struct driver_data *drv_data) |
a5f6abd4 WB |
142 | { |
143 | u16 cr; | |
144 | ||
bb90eb00 BW |
145 | cr = read_CTRL(drv_data); |
146 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
147 | } |
148 | ||
149 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
150 | static u16 hz_to_spi_baud(u32 speed_hz) | |
151 | { | |
152 | u_long sclk = get_sclk(); | |
153 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
154 | ||
155 | if ((sclk % (2 * speed_hz)) > 0) | |
156 | spi_baud++; | |
157 | ||
7513e006 MH |
158 | if (spi_baud < MIN_SPI_BAUD_VAL) |
159 | spi_baud = MIN_SPI_BAUD_VAL; | |
160 | ||
a5f6abd4 WB |
161 | return spi_baud; |
162 | } | |
163 | ||
164 | static int flush(struct driver_data *drv_data) | |
165 | { | |
166 | unsigned long limit = loops_per_jiffy << 1; | |
167 | ||
168 | /* wait for stop and clear stat */ | |
bb90eb00 | 169 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--) |
d8c05008 | 170 | cpu_relax(); |
a5f6abd4 | 171 | |
bb90eb00 | 172 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
173 | |
174 | return limit; | |
175 | } | |
176 | ||
fad91c89 | 177 | /* Chip select operation functions for cs_change flag */ |
bb90eb00 | 178 | static void cs_active(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 179 | { |
bb90eb00 | 180 | u16 flag = read_FLAG(drv_data); |
fad91c89 BW |
181 | |
182 | flag |= chip->flag; | |
183 | flag &= ~(chip->flag << 8); | |
184 | ||
bb90eb00 | 185 | write_FLAG(drv_data, flag); |
fad91c89 BW |
186 | } |
187 | ||
bb90eb00 | 188 | static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 189 | { |
bb90eb00 | 190 | u16 flag = read_FLAG(drv_data); |
fad91c89 BW |
191 | |
192 | flag |= (chip->flag << 8); | |
193 | ||
bb90eb00 | 194 | write_FLAG(drv_data, flag); |
62310e51 BW |
195 | |
196 | /* Move delay here for consistency */ | |
197 | if (chip->cs_chg_udelay) | |
198 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
199 | } |
200 | ||
7c4ef094 | 201 | #define MAX_SPI_SSEL 7 |
5fec5b5a | 202 | |
a5f6abd4 | 203 | /* stop controller and re-config current chip*/ |
8d20d0a7 | 204 | static void restore_state(struct driver_data *drv_data) |
a5f6abd4 WB |
205 | { |
206 | struct chip_data *chip = drv_data->cur_chip; | |
12e17c42 | 207 | |
a5f6abd4 | 208 | /* Clear status and disable clock */ |
bb90eb00 | 209 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 210 | bfin_spi_disable(drv_data); |
88b40369 | 211 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 212 | |
5fec5b5a | 213 | /* Load the registers */ |
bb90eb00 | 214 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 215 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
216 | |
217 | bfin_spi_enable(drv_data); | |
07612e5f | 218 | cs_active(drv_data, chip); |
a5f6abd4 WB |
219 | } |
220 | ||
221 | /* used to kick off transfer in rx mode */ | |
bb90eb00 | 222 | static unsigned short dummy_read(struct driver_data *drv_data) |
a5f6abd4 WB |
223 | { |
224 | unsigned short tmp; | |
bb90eb00 | 225 | tmp = read_RDBR(drv_data); |
a5f6abd4 WB |
226 | return tmp; |
227 | } | |
228 | ||
229 | static void null_writer(struct driver_data *drv_data) | |
230 | { | |
231 | u8 n_bytes = drv_data->n_bytes; | |
232 | ||
233 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 BW |
234 | write_TDBR(drv_data, 0); |
235 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 236 | cpu_relax(); |
a5f6abd4 WB |
237 | drv_data->tx += n_bytes; |
238 | } | |
239 | } | |
240 | ||
241 | static void null_reader(struct driver_data *drv_data) | |
242 | { | |
243 | u8 n_bytes = drv_data->n_bytes; | |
bb90eb00 | 244 | dummy_read(drv_data); |
a5f6abd4 WB |
245 | |
246 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 247 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 248 | cpu_relax(); |
bb90eb00 | 249 | dummy_read(drv_data); |
a5f6abd4 WB |
250 | drv_data->rx += n_bytes; |
251 | } | |
252 | } | |
253 | ||
254 | static void u8_writer(struct driver_data *drv_data) | |
255 | { | |
131b17d4 | 256 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 257 | "cr8-s is 0x%x\n", read_STAT(drv_data)); |
cc487e73 | 258 | |
a5f6abd4 | 259 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 BW |
260 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
261 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 262 | cpu_relax(); |
a5f6abd4 WB |
263 | ++drv_data->tx; |
264 | } | |
13f3e642 SZ |
265 | |
266 | /* poll for SPI completion before return */ | |
267 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | |
268 | cpu_relax(); | |
a5f6abd4 WB |
269 | } |
270 | ||
271 | static void u8_cs_chg_writer(struct driver_data *drv_data) | |
272 | { | |
273 | struct chip_data *chip = drv_data->cur_chip; | |
274 | ||
275 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 | 276 | cs_active(drv_data, chip); |
a5f6abd4 | 277 | |
bb90eb00 BW |
278 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
279 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 280 | cpu_relax(); |
e26aa015 BW |
281 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
282 | cpu_relax(); | |
62310e51 | 283 | |
bb90eb00 | 284 | cs_deactive(drv_data, chip); |
5fec5b5a | 285 | |
a5f6abd4 WB |
286 | ++drv_data->tx; |
287 | } | |
a5f6abd4 WB |
288 | } |
289 | ||
290 | static void u8_reader(struct driver_data *drv_data) | |
291 | { | |
131b17d4 | 292 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 293 | "cr-8 is 0x%x\n", read_STAT(drv_data)); |
a5f6abd4 | 294 | |
3f479a65 | 295 | /* poll for SPI completion before start */ |
bb90eb00 | 296 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 297 | cpu_relax(); |
3f479a65 | 298 | |
a5f6abd4 | 299 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 300 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 301 | |
bb90eb00 | 302 | dummy_read(drv_data); |
cc487e73 | 303 | |
a5f6abd4 | 304 | while (drv_data->rx < drv_data->rx_end - 1) { |
bb90eb00 | 305 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 306 | cpu_relax(); |
bb90eb00 | 307 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
308 | ++drv_data->rx; |
309 | } | |
310 | ||
bb90eb00 | 311 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 312 | cpu_relax(); |
bb90eb00 | 313 | *(u8 *) (drv_data->rx) = read_SHAW(drv_data); |
a5f6abd4 WB |
314 | ++drv_data->rx; |
315 | } | |
316 | ||
317 | static void u8_cs_chg_reader(struct driver_data *drv_data) | |
318 | { | |
319 | struct chip_data *chip = drv_data->cur_chip; | |
320 | ||
e26aa015 BW |
321 | while (drv_data->rx < drv_data->rx_end) { |
322 | cs_active(drv_data, chip); | |
323 | read_RDBR(drv_data); /* kick off */ | |
a5f6abd4 | 324 | |
e26aa015 BW |
325 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
326 | cpu_relax(); | |
327 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | |
328 | cpu_relax(); | |
cc487e73 | 329 | |
e26aa015 | 330 | *(u8 *) (drv_data->rx) = read_SHAW(drv_data); |
bb90eb00 | 331 | cs_deactive(drv_data, chip); |
5fec5b5a | 332 | |
a5f6abd4 WB |
333 | ++drv_data->rx; |
334 | } | |
a5f6abd4 WB |
335 | } |
336 | ||
337 | static void u8_duplex(struct driver_data *drv_data) | |
338 | { | |
339 | /* in duplex mode, clk is triggered by writing of TDBR */ | |
340 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 341 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
4fd432d9 | 342 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 343 | cpu_relax(); |
bb90eb00 | 344 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 345 | cpu_relax(); |
bb90eb00 | 346 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
347 | ++drv_data->rx; |
348 | ++drv_data->tx; | |
349 | } | |
350 | } | |
351 | ||
352 | static void u8_cs_chg_duplex(struct driver_data *drv_data) | |
353 | { | |
354 | struct chip_data *chip = drv_data->cur_chip; | |
355 | ||
356 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 357 | cs_active(drv_data, chip); |
5fec5b5a | 358 | |
bb90eb00 | 359 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
e26aa015 BW |
360 | |
361 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | |
d8c05008 | 362 | cpu_relax(); |
bb90eb00 | 363 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 364 | cpu_relax(); |
bb90eb00 | 365 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
62310e51 | 366 | |
bb90eb00 | 367 | cs_deactive(drv_data, chip); |
5fec5b5a | 368 | |
a5f6abd4 WB |
369 | ++drv_data->rx; |
370 | ++drv_data->tx; | |
371 | } | |
a5f6abd4 WB |
372 | } |
373 | ||
374 | static void u16_writer(struct driver_data *drv_data) | |
375 | { | |
131b17d4 | 376 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 377 | "cr16 is 0x%x\n", read_STAT(drv_data)); |
88b40369 | 378 | |
a5f6abd4 | 379 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 BW |
380 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
381 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 382 | cpu_relax(); |
a5f6abd4 WB |
383 | drv_data->tx += 2; |
384 | } | |
13f3e642 SZ |
385 | |
386 | /* poll for SPI completion before return */ | |
387 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | |
388 | cpu_relax(); | |
a5f6abd4 WB |
389 | } |
390 | ||
391 | static void u16_cs_chg_writer(struct driver_data *drv_data) | |
392 | { | |
393 | struct chip_data *chip = drv_data->cur_chip; | |
394 | ||
395 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 | 396 | cs_active(drv_data, chip); |
a5f6abd4 | 397 | |
bb90eb00 BW |
398 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
399 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 400 | cpu_relax(); |
13f3e642 SZ |
401 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
402 | cpu_relax(); | |
62310e51 | 403 | |
bb90eb00 | 404 | cs_deactive(drv_data, chip); |
5fec5b5a | 405 | |
a5f6abd4 WB |
406 | drv_data->tx += 2; |
407 | } | |
a5f6abd4 WB |
408 | } |
409 | ||
410 | static void u16_reader(struct driver_data *drv_data) | |
411 | { | |
88b40369 | 412 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 413 | "cr-16 is 0x%x\n", read_STAT(drv_data)); |
cc487e73 | 414 | |
3f479a65 | 415 | /* poll for SPI completion before start */ |
bb90eb00 | 416 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 417 | cpu_relax(); |
3f479a65 | 418 | |
cc487e73 | 419 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 420 | write_TDBR(drv_data, 0xFFFF); |
cc487e73 | 421 | |
bb90eb00 | 422 | dummy_read(drv_data); |
a5f6abd4 WB |
423 | |
424 | while (drv_data->rx < (drv_data->rx_end - 2)) { | |
bb90eb00 | 425 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 426 | cpu_relax(); |
bb90eb00 | 427 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
428 | drv_data->rx += 2; |
429 | } | |
430 | ||
bb90eb00 | 431 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 432 | cpu_relax(); |
bb90eb00 | 433 | *(u16 *) (drv_data->rx) = read_SHAW(drv_data); |
a5f6abd4 WB |
434 | drv_data->rx += 2; |
435 | } | |
436 | ||
437 | static void u16_cs_chg_reader(struct driver_data *drv_data) | |
438 | { | |
439 | struct chip_data *chip = drv_data->cur_chip; | |
440 | ||
3f479a65 | 441 | /* poll for SPI completion before start */ |
bb90eb00 | 442 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 443 | cpu_relax(); |
3f479a65 | 444 | |
cc487e73 | 445 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 446 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 447 | |
bb90eb00 BW |
448 | cs_active(drv_data, chip); |
449 | dummy_read(drv_data); | |
cc487e73 | 450 | |
c3061abb | 451 | while (drv_data->rx < drv_data->rx_end - 2) { |
bb90eb00 | 452 | cs_deactive(drv_data, chip); |
5fec5b5a | 453 | |
bb90eb00 | 454 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 455 | cpu_relax(); |
bb90eb00 BW |
456 | cs_active(drv_data, chip); |
457 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
a5f6abd4 WB |
458 | drv_data->rx += 2; |
459 | } | |
bb90eb00 | 460 | cs_deactive(drv_data, chip); |
cc487e73 | 461 | |
bb90eb00 | 462 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 463 | cpu_relax(); |
bb90eb00 | 464 | *(u16 *) (drv_data->rx) = read_SHAW(drv_data); |
cc487e73 | 465 | drv_data->rx += 2; |
a5f6abd4 WB |
466 | } |
467 | ||
468 | static void u16_duplex(struct driver_data *drv_data) | |
469 | { | |
470 | /* in duplex mode, clk is triggered by writing of TDBR */ | |
471 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 | 472 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
4fd432d9 | 473 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 474 | cpu_relax(); |
bb90eb00 | 475 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 476 | cpu_relax(); |
bb90eb00 | 477 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
478 | drv_data->rx += 2; |
479 | drv_data->tx += 2; | |
480 | } | |
481 | } | |
482 | ||
483 | static void u16_cs_chg_duplex(struct driver_data *drv_data) | |
484 | { | |
485 | struct chip_data *chip = drv_data->cur_chip; | |
486 | ||
487 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 | 488 | cs_active(drv_data, chip); |
a5f6abd4 | 489 | |
bb90eb00 | 490 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
4fd432d9 | 491 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 492 | cpu_relax(); |
bb90eb00 | 493 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 494 | cpu_relax(); |
bb90eb00 | 495 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
62310e51 | 496 | |
bb90eb00 | 497 | cs_deactive(drv_data, chip); |
5fec5b5a | 498 | |
a5f6abd4 WB |
499 | drv_data->rx += 2; |
500 | drv_data->tx += 2; | |
501 | } | |
a5f6abd4 WB |
502 | } |
503 | ||
504 | /* test if ther is more transfer to be done */ | |
505 | static void *next_transfer(struct driver_data *drv_data) | |
506 | { | |
507 | struct spi_message *msg = drv_data->cur_msg; | |
508 | struct spi_transfer *trans = drv_data->cur_transfer; | |
509 | ||
510 | /* Move to next transfer */ | |
511 | if (trans->transfer_list.next != &msg->transfers) { | |
512 | drv_data->cur_transfer = | |
513 | list_entry(trans->transfer_list.next, | |
514 | struct spi_transfer, transfer_list); | |
515 | return RUNNING_STATE; | |
516 | } else | |
517 | return DONE_STATE; | |
518 | } | |
519 | ||
520 | /* | |
521 | * caller already set message->status; | |
522 | * dma and pio irqs are blocked give finished message back | |
523 | */ | |
524 | static void giveback(struct driver_data *drv_data) | |
525 | { | |
fad91c89 | 526 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
527 | struct spi_transfer *last_transfer; |
528 | unsigned long flags; | |
529 | struct spi_message *msg; | |
530 | ||
531 | spin_lock_irqsave(&drv_data->lock, flags); | |
532 | msg = drv_data->cur_msg; | |
533 | drv_data->cur_msg = NULL; | |
534 | drv_data->cur_transfer = NULL; | |
535 | drv_data->cur_chip = NULL; | |
536 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
537 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
538 | ||
539 | last_transfer = list_entry(msg->transfers.prev, | |
540 | struct spi_transfer, transfer_list); | |
541 | ||
542 | msg->state = NULL; | |
543 | ||
544 | /* disable chip select signal. And not stop spi in autobuffer mode */ | |
545 | if (drv_data->tx_dma != 0xFFFF) { | |
bb90eb00 | 546 | cs_deactive(drv_data, chip); |
a5f6abd4 WB |
547 | bfin_spi_disable(drv_data); |
548 | } | |
549 | ||
fad91c89 | 550 | if (!drv_data->cs_change) |
bb90eb00 | 551 | cs_deactive(drv_data, chip); |
fad91c89 | 552 | |
a5f6abd4 WB |
553 | if (msg->complete) |
554 | msg->complete(msg->context); | |
555 | } | |
556 | ||
88b40369 | 557 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 558 | { |
15aafa2f | 559 | struct driver_data *drv_data = dev_id; |
fad91c89 | 560 | struct chip_data *chip = drv_data->cur_chip; |
bb90eb00 | 561 | struct spi_message *msg = drv_data->cur_msg; |
a5f6abd4 | 562 | |
88b40369 | 563 | dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); |
bb90eb00 | 564 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 | 565 | |
d6fe89b0 | 566 | /* Wait for DMA to complete */ |
bb90eb00 | 567 | while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN) |
d8c05008 | 568 | cpu_relax(); |
d6fe89b0 | 569 | |
a5f6abd4 | 570 | /* |
d6fe89b0 BW |
571 | * wait for the last transaction shifted out. HRM states: |
572 | * at this point there may still be data in the SPI DMA FIFO waiting | |
573 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
574 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
575 | */ |
576 | if (drv_data->tx != NULL) { | |
bb90eb00 BW |
577 | while ((read_STAT(drv_data) & TXS) || |
578 | (read_STAT(drv_data) & TXS)) | |
d8c05008 | 579 | cpu_relax(); |
a5f6abd4 WB |
580 | } |
581 | ||
bb90eb00 | 582 | while (!(read_STAT(drv_data) & SPIF)) |
d8c05008 | 583 | cpu_relax(); |
a5f6abd4 | 584 | |
a5f6abd4 WB |
585 | msg->actual_length += drv_data->len_in_bytes; |
586 | ||
fad91c89 | 587 | if (drv_data->cs_change) |
bb90eb00 | 588 | cs_deactive(drv_data, chip); |
fad91c89 | 589 | |
a5f6abd4 WB |
590 | /* Move to next transfer */ |
591 | msg->state = next_transfer(drv_data); | |
592 | ||
593 | /* Schedule transfer tasklet */ | |
594 | tasklet_schedule(&drv_data->pump_transfers); | |
595 | ||
596 | /* free the irq handler before next transfer */ | |
88b40369 BW |
597 | dev_dbg(&drv_data->pdev->dev, |
598 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
599 | drv_data->dma_channel); |
600 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
601 | |
602 | return IRQ_HANDLED; | |
603 | } | |
604 | ||
605 | static void pump_transfers(unsigned long data) | |
606 | { | |
607 | struct driver_data *drv_data = (struct driver_data *)data; | |
608 | struct spi_message *message = NULL; | |
609 | struct spi_transfer *transfer = NULL; | |
610 | struct spi_transfer *previous = NULL; | |
611 | struct chip_data *chip = NULL; | |
88b40369 BW |
612 | u8 width; |
613 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 614 | u32 tranf_success = 1; |
8eeb12e5 | 615 | u8 full_duplex = 0; |
a5f6abd4 WB |
616 | |
617 | /* Get current state information */ | |
618 | message = drv_data->cur_msg; | |
619 | transfer = drv_data->cur_transfer; | |
620 | chip = drv_data->cur_chip; | |
092e1fda | 621 | |
a5f6abd4 WB |
622 | /* |
623 | * if msg is error or done, report it back using complete() callback | |
624 | */ | |
625 | ||
626 | /* Handle for abort */ | |
627 | if (message->state == ERROR_STATE) { | |
628 | message->status = -EIO; | |
629 | giveback(drv_data); | |
630 | return; | |
631 | } | |
632 | ||
633 | /* Handle end of message */ | |
634 | if (message->state == DONE_STATE) { | |
635 | message->status = 0; | |
636 | giveback(drv_data); | |
637 | return; | |
638 | } | |
639 | ||
640 | /* Delay if requested at end of transfer */ | |
641 | if (message->state == RUNNING_STATE) { | |
642 | previous = list_entry(transfer->transfer_list.prev, | |
643 | struct spi_transfer, transfer_list); | |
644 | if (previous->delay_usecs) | |
645 | udelay(previous->delay_usecs); | |
646 | } | |
647 | ||
648 | /* Setup the transfer state based on the type of transfer */ | |
649 | if (flush(drv_data) == 0) { | |
650 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
651 | message->status = -EIO; | |
652 | giveback(drv_data); | |
653 | return; | |
654 | } | |
655 | ||
656 | if (transfer->tx_buf != NULL) { | |
657 | drv_data->tx = (void *)transfer->tx_buf; | |
658 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
659 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
660 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
661 | } else { |
662 | drv_data->tx = NULL; | |
663 | } | |
664 | ||
665 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 666 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
667 | drv_data->rx = transfer->rx_buf; |
668 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
669 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
670 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
671 | } else { |
672 | drv_data->rx = NULL; | |
673 | } | |
674 | ||
675 | drv_data->rx_dma = transfer->rx_dma; | |
676 | drv_data->tx_dma = transfer->tx_dma; | |
677 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 678 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 679 | |
092e1fda BW |
680 | /* Bits per word setup */ |
681 | switch (transfer->bits_per_word) { | |
682 | case 8: | |
683 | drv_data->n_bytes = 1; | |
684 | width = CFG_SPI_WORDSIZE8; | |
685 | drv_data->read = chip->cs_change_per_word ? | |
686 | u8_cs_chg_reader : u8_reader; | |
687 | drv_data->write = chip->cs_change_per_word ? | |
688 | u8_cs_chg_writer : u8_writer; | |
689 | drv_data->duplex = chip->cs_change_per_word ? | |
690 | u8_cs_chg_duplex : u8_duplex; | |
691 | break; | |
692 | ||
693 | case 16: | |
694 | drv_data->n_bytes = 2; | |
695 | width = CFG_SPI_WORDSIZE16; | |
696 | drv_data->read = chip->cs_change_per_word ? | |
697 | u16_cs_chg_reader : u16_reader; | |
698 | drv_data->write = chip->cs_change_per_word ? | |
699 | u16_cs_chg_writer : u16_writer; | |
700 | drv_data->duplex = chip->cs_change_per_word ? | |
701 | u16_cs_chg_duplex : u16_duplex; | |
702 | break; | |
703 | ||
704 | default: | |
705 | /* No change, the same as default setting */ | |
706 | drv_data->n_bytes = chip->n_bytes; | |
707 | width = chip->width; | |
708 | drv_data->write = drv_data->tx ? chip->write : null_writer; | |
709 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
710 | drv_data->duplex = chip->duplex ? chip->duplex : null_writer; | |
711 | break; | |
712 | } | |
713 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
714 | cr |= (width << 8); | |
715 | write_CTRL(drv_data, cr); | |
716 | ||
a5f6abd4 WB |
717 | if (width == CFG_SPI_WORDSIZE16) { |
718 | drv_data->len = (transfer->len) >> 1; | |
719 | } else { | |
720 | drv_data->len = transfer->len; | |
721 | } | |
4fb98efa MF |
722 | dev_dbg(&drv_data->pdev->dev, |
723 | "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n", | |
131b17d4 | 724 | drv_data->write, chip->write, null_writer); |
a5f6abd4 WB |
725 | |
726 | /* speed and width has been set on per message */ | |
727 | message->state = RUNNING_STATE; | |
728 | dma_config = 0; | |
729 | ||
092e1fda BW |
730 | /* Speed setup (surely valid because already checked) */ |
731 | if (transfer->speed_hz) | |
732 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
733 | else | |
734 | write_BAUD(drv_data, chip->baud); | |
735 | ||
bb90eb00 BW |
736 | write_STAT(drv_data, BIT_STAT_CLR); |
737 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
738 | cs_active(drv_data, chip); | |
a5f6abd4 | 739 | |
88b40369 BW |
740 | dev_dbg(&drv_data->pdev->dev, |
741 | "now pumping a transfer: width is %d, len is %d\n", | |
742 | width, transfer->len); | |
a5f6abd4 WB |
743 | |
744 | /* | |
8cf5858c VM |
745 | * Try to map dma buffer and do a dma transfer. If successful use, |
746 | * different way to r/w according to the enable_dma settings and if | |
747 | * we are not doing a full duplex transfer (since the hardware does | |
748 | * not support full duplex DMA transfers). | |
a5f6abd4 | 749 | */ |
8eeb12e5 VM |
750 | if (!full_duplex && drv_data->cur_chip->enable_dma |
751 | && drv_data->len > 6) { | |
a5f6abd4 | 752 | |
bb90eb00 BW |
753 | disable_dma(drv_data->dma_channel); |
754 | clear_dma_irqstat(drv_data->dma_channel); | |
07612e5f | 755 | bfin_spi_disable(drv_data); |
a5f6abd4 WB |
756 | |
757 | /* config dma channel */ | |
88b40369 | 758 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
a5f6abd4 | 759 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 BW |
760 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
761 | set_dma_x_modify(drv_data->dma_channel, 2); | |
a5f6abd4 WB |
762 | dma_width = WDSIZE_16; |
763 | } else { | |
bb90eb00 BW |
764 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
765 | set_dma_x_modify(drv_data->dma_channel, 1); | |
a5f6abd4 WB |
766 | dma_width = WDSIZE_8; |
767 | } | |
768 | ||
3f479a65 | 769 | /* poll for SPI completion before start */ |
bb90eb00 | 770 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 771 | cpu_relax(); |
3f479a65 | 772 | |
a5f6abd4 WB |
773 | /* dirty hack for autobuffer DMA mode */ |
774 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
775 | dev_dbg(&drv_data->pdev->dev, |
776 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
777 | |
778 | /* no irq in autobuffer mode */ | |
779 | dma_config = | |
780 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
781 | set_dma_config(drv_data->dma_channel, dma_config); |
782 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 783 | (unsigned long)drv_data->tx); |
bb90eb00 | 784 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 785 | |
07612e5f SZ |
786 | /* start SPI transfer */ |
787 | write_CTRL(drv_data, | |
788 | (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE)); | |
789 | ||
790 | /* just return here, there can only be one transfer | |
791 | * in this mode | |
792 | */ | |
a5f6abd4 WB |
793 | message->status = 0; |
794 | giveback(drv_data); | |
795 | return; | |
796 | } | |
797 | ||
798 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
799 | if (drv_data->rx != NULL) { | |
800 | /* set transfer mode, and enable SPI */ | |
88b40369 | 801 | dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n"); |
a5f6abd4 | 802 | |
8cf5858c VM |
803 | /* invalidate caches, if needed */ |
804 | if (bfin_addr_dcachable((unsigned long) drv_data->rx)) | |
805 | invalidate_dcache_range((unsigned long) drv_data->rx, | |
806 | (unsigned long) (drv_data->rx + | |
807 | drv_data->len)); | |
808 | ||
a5f6abd4 | 809 | /* clear tx reg soformer data is not shifted out */ |
bb90eb00 | 810 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 811 | |
bb90eb00 | 812 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 WB |
813 | |
814 | /* start dma */ | |
bb90eb00 | 815 | dma_enable_irq(drv_data->dma_channel); |
a5f6abd4 | 816 | dma_config = (WNR | RESTART | dma_width | DI_EN); |
bb90eb00 BW |
817 | set_dma_config(drv_data->dma_channel, dma_config); |
818 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 819 | (unsigned long)drv_data->rx); |
bb90eb00 | 820 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 821 | |
07612e5f SZ |
822 | /* start SPI transfer */ |
823 | write_CTRL(drv_data, | |
824 | (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE)); | |
825 | ||
a5f6abd4 | 826 | } else if (drv_data->tx != NULL) { |
88b40369 | 827 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 828 | |
8cf5858c VM |
829 | /* flush caches, if needed */ |
830 | if (bfin_addr_dcachable((unsigned long) drv_data->tx)) | |
831 | flush_dcache_range((unsigned long) drv_data->tx, | |
832 | (unsigned long) (drv_data->tx + | |
833 | drv_data->len)); | |
834 | ||
a5f6abd4 | 835 | /* start dma */ |
bb90eb00 | 836 | dma_enable_irq(drv_data->dma_channel); |
a5f6abd4 | 837 | dma_config = (RESTART | dma_width | DI_EN); |
bb90eb00 BW |
838 | set_dma_config(drv_data->dma_channel, dma_config); |
839 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 840 | (unsigned long)drv_data->tx); |
bb90eb00 | 841 | enable_dma(drv_data->dma_channel); |
07612e5f SZ |
842 | |
843 | /* start SPI transfer */ | |
844 | write_CTRL(drv_data, | |
845 | (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
846 | } |
847 | } else { | |
848 | /* IO mode write then read */ | |
88b40369 | 849 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
a5f6abd4 | 850 | |
8eeb12e5 | 851 | if (full_duplex) { |
a5f6abd4 WB |
852 | /* full duplex mode */ |
853 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
854 | (drv_data->rx_end - drv_data->rx)); | |
88b40369 BW |
855 | dev_dbg(&drv_data->pdev->dev, |
856 | "IO duplex: cr is 0x%x\n", cr); | |
a5f6abd4 | 857 | |
cc487e73 | 858 | /* set SPI transfer mode */ |
bb90eb00 | 859 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
a5f6abd4 WB |
860 | |
861 | drv_data->duplex(drv_data); | |
862 | ||
863 | if (drv_data->tx != drv_data->tx_end) | |
864 | tranf_success = 0; | |
865 | } else if (drv_data->tx != NULL) { | |
866 | /* write only half duplex */ | |
131b17d4 | 867 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 868 | "IO write: cr is 0x%x\n", cr); |
a5f6abd4 | 869 | |
cc487e73 | 870 | /* set SPI transfer mode */ |
bb90eb00 | 871 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
a5f6abd4 WB |
872 | |
873 | drv_data->write(drv_data); | |
874 | ||
875 | if (drv_data->tx != drv_data->tx_end) | |
876 | tranf_success = 0; | |
877 | } else if (drv_data->rx != NULL) { | |
878 | /* read only half duplex */ | |
131b17d4 | 879 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 880 | "IO read: cr is 0x%x\n", cr); |
a5f6abd4 | 881 | |
cc487e73 | 882 | /* set SPI transfer mode */ |
bb90eb00 | 883 | write_CTRL(drv_data, (cr | CFG_SPI_READ)); |
a5f6abd4 WB |
884 | |
885 | drv_data->read(drv_data); | |
886 | if (drv_data->rx != drv_data->rx_end) | |
887 | tranf_success = 0; | |
888 | } | |
889 | ||
890 | if (!tranf_success) { | |
131b17d4 | 891 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 892 | "IO write error!\n"); |
a5f6abd4 WB |
893 | message->state = ERROR_STATE; |
894 | } else { | |
895 | /* Update total byte transfered */ | |
896 | message->actual_length += drv_data->len; | |
897 | ||
898 | /* Move to next transfer of this msg */ | |
899 | message->state = next_transfer(drv_data); | |
900 | } | |
901 | ||
902 | /* Schedule next transfer tasklet */ | |
903 | tasklet_schedule(&drv_data->pump_transfers); | |
904 | ||
905 | } | |
906 | } | |
907 | ||
908 | /* pop a msg from queue and kick off real transfer */ | |
909 | static void pump_messages(struct work_struct *work) | |
910 | { | |
131b17d4 | 911 | struct driver_data *drv_data; |
a5f6abd4 WB |
912 | unsigned long flags; |
913 | ||
131b17d4 BW |
914 | drv_data = container_of(work, struct driver_data, pump_messages); |
915 | ||
a5f6abd4 WB |
916 | /* Lock queue and check for queue work */ |
917 | spin_lock_irqsave(&drv_data->lock, flags); | |
918 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
919 | /* pumper kicked off but no work to do */ | |
920 | drv_data->busy = 0; | |
921 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
922 | return; | |
923 | } | |
924 | ||
925 | /* Make sure we are not already running a message */ | |
926 | if (drv_data->cur_msg) { | |
927 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
928 | return; | |
929 | } | |
930 | ||
931 | /* Extract head of queue */ | |
932 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
933 | struct spi_message, queue); | |
5fec5b5a BW |
934 | |
935 | /* Setup the SSP using the per chip configuration */ | |
936 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
8d20d0a7 | 937 | restore_state(drv_data); |
5fec5b5a | 938 | |
a5f6abd4 WB |
939 | list_del_init(&drv_data->cur_msg->queue); |
940 | ||
941 | /* Initial message state */ | |
942 | drv_data->cur_msg->state = START_STATE; | |
943 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
944 | struct spi_transfer, transfer_list); | |
945 | ||
5fec5b5a BW |
946 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
947 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
948 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
949 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
950 | |
951 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
952 | "the first transfer len is %d\n", |
953 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
954 | |
955 | /* Mark as busy and launch transfers */ | |
956 | tasklet_schedule(&drv_data->pump_transfers); | |
957 | ||
958 | drv_data->busy = 1; | |
959 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
960 | } | |
961 | ||
962 | /* | |
963 | * got a msg to transfer, queue it in drv_data->queue. | |
964 | * And kick off message pumper | |
965 | */ | |
966 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
967 | { | |
968 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
969 | unsigned long flags; | |
970 | ||
971 | spin_lock_irqsave(&drv_data->lock, flags); | |
972 | ||
973 | if (drv_data->run == QUEUE_STOPPED) { | |
974 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
975 | return -ESHUTDOWN; | |
976 | } | |
977 | ||
978 | msg->actual_length = 0; | |
979 | msg->status = -EINPROGRESS; | |
980 | msg->state = START_STATE; | |
981 | ||
88b40369 | 982 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
983 | list_add_tail(&msg->queue, &drv_data->queue); |
984 | ||
985 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
986 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
987 | ||
988 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
12e17c42 SZ |
993 | #define MAX_SPI_SSEL 7 |
994 | ||
995 | static u16 ssel[3][MAX_SPI_SSEL] = { | |
996 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, | |
997 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
998 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
999 | ||
1000 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
1001 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
1002 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
1003 | ||
1004 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
1005 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
1006 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
1007 | }; | |
1008 | ||
a5f6abd4 WB |
1009 | /* first setup for new devices */ |
1010 | static int setup(struct spi_device *spi) | |
1011 | { | |
1012 | struct bfin5xx_spi_chip *chip_info = NULL; | |
1013 | struct chip_data *chip; | |
1014 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1015 | u8 spi_flg; | |
1016 | ||
1017 | /* Abort device setup if requested features are not supported */ | |
1018 | if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) { | |
1019 | dev_err(&spi->dev, "requested mode not fully supported\n"); | |
1020 | return -EINVAL; | |
1021 | } | |
1022 | ||
1023 | /* Zero (the default) here means 8 bits */ | |
1024 | if (!spi->bits_per_word) | |
1025 | spi->bits_per_word = 8; | |
1026 | ||
1027 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) | |
1028 | return -EINVAL; | |
1029 | ||
1030 | /* Only alloc (or use chip_info) on first setup */ | |
1031 | chip = spi_get_ctldata(spi); | |
1032 | if (chip == NULL) { | |
1033 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1034 | if (!chip) | |
1035 | return -ENOMEM; | |
1036 | ||
1037 | chip->enable_dma = 0; | |
1038 | chip_info = spi->controller_data; | |
1039 | } | |
1040 | ||
1041 | /* chip_info isn't always needed */ | |
1042 | if (chip_info) { | |
2ed35516 MF |
1043 | /* Make sure people stop trying to set fields via ctl_reg |
1044 | * when they should actually be using common SPI framework. | |
1045 | * Currently we let through: WOM EMISO PSSE GM SZ TIMOD. | |
1046 | * Not sure if a user actually needs/uses any of these, | |
1047 | * but let's assume (for now) they do. | |
1048 | */ | |
1049 | if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) { | |
1050 | dev_err(&spi->dev, "do not set bits in ctl_reg " | |
1051 | "that the SPI framework manages\n"); | |
1052 | return -EINVAL; | |
1053 | } | |
1054 | ||
a5f6abd4 WB |
1055 | chip->enable_dma = chip_info->enable_dma != 0 |
1056 | && drv_data->master_info->enable_dma; | |
1057 | chip->ctl_reg = chip_info->ctl_reg; | |
1058 | chip->bits_per_word = chip_info->bits_per_word; | |
1059 | chip->cs_change_per_word = chip_info->cs_change_per_word; | |
1060 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
1061 | } | |
1062 | ||
1063 | /* translate common spi framework into our register */ | |
1064 | if (spi->mode & SPI_CPOL) | |
1065 | chip->ctl_reg |= CPOL; | |
1066 | if (spi->mode & SPI_CPHA) | |
1067 | chip->ctl_reg |= CPHA; | |
1068 | if (spi->mode & SPI_LSB_FIRST) | |
1069 | chip->ctl_reg |= LSBF; | |
1070 | /* we dont support running in slave mode (yet?) */ | |
1071 | chip->ctl_reg |= MSTR; | |
1072 | ||
1073 | /* | |
1074 | * if any one SPI chip is registered and wants DMA, request the | |
1075 | * DMA channel for it | |
1076 | */ | |
bb90eb00 | 1077 | if (chip->enable_dma && !drv_data->dma_requested) { |
a5f6abd4 | 1078 | /* register dma irq handler */ |
bb90eb00 | 1079 | if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) { |
88b40369 BW |
1080 | dev_dbg(&spi->dev, |
1081 | "Unable to request BlackFin SPI DMA channel\n"); | |
a5f6abd4 WB |
1082 | return -ENODEV; |
1083 | } | |
bb90eb00 BW |
1084 | if (set_dma_callback(drv_data->dma_channel, |
1085 | (void *)dma_irq_handler, drv_data) < 0) { | |
88b40369 | 1086 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
a5f6abd4 WB |
1087 | return -EPERM; |
1088 | } | |
bb90eb00 BW |
1089 | dma_disable_irq(drv_data->dma_channel); |
1090 | drv_data->dma_requested = 1; | |
a5f6abd4 WB |
1091 | } |
1092 | ||
1093 | /* | |
1094 | * Notice: for blackfin, the speed_hz is the value of register | |
1095 | * SPI_BAUD, not the real baudrate | |
1096 | */ | |
1097 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
1098 | spi_flg = ~(1 << (spi->chip_select)); | |
1099 | chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select)); | |
1100 | chip->chip_select_num = spi->chip_select; | |
1101 | ||
1102 | switch (chip->bits_per_word) { | |
1103 | case 8: | |
1104 | chip->n_bytes = 1; | |
1105 | chip->width = CFG_SPI_WORDSIZE8; | |
1106 | chip->read = chip->cs_change_per_word ? | |
1107 | u8_cs_chg_reader : u8_reader; | |
1108 | chip->write = chip->cs_change_per_word ? | |
1109 | u8_cs_chg_writer : u8_writer; | |
1110 | chip->duplex = chip->cs_change_per_word ? | |
1111 | u8_cs_chg_duplex : u8_duplex; | |
1112 | break; | |
1113 | ||
1114 | case 16: | |
1115 | chip->n_bytes = 2; | |
1116 | chip->width = CFG_SPI_WORDSIZE16; | |
1117 | chip->read = chip->cs_change_per_word ? | |
1118 | u16_cs_chg_reader : u16_reader; | |
1119 | chip->write = chip->cs_change_per_word ? | |
1120 | u16_cs_chg_writer : u16_writer; | |
1121 | chip->duplex = chip->cs_change_per_word ? | |
1122 | u16_cs_chg_duplex : u16_duplex; | |
1123 | break; | |
1124 | ||
1125 | default: | |
1126 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1127 | chip->bits_per_word); | |
1128 | kfree(chip); | |
1129 | return -ENODEV; | |
1130 | } | |
1131 | ||
898eb71c | 1132 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1133 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1134 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1135 | chip->ctl_reg, chip->flag); |
1136 | ||
1137 | spi_set_ctldata(spi, chip); | |
1138 | ||
12e17c42 SZ |
1139 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
1140 | if ((chip->chip_select_num > 0) | |
1141 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1142 | peripheral_request(ssel[spi->master->bus_num] | |
aab0d83e | 1143 | [chip->chip_select_num-1], spi->modalias); |
12e17c42 | 1144 | |
07612e5f SZ |
1145 | cs_deactive(drv_data, chip); |
1146 | ||
a5f6abd4 WB |
1147 | return 0; |
1148 | } | |
1149 | ||
1150 | /* | |
1151 | * callback for spi framework. | |
1152 | * clean driver specific data | |
1153 | */ | |
88b40369 | 1154 | static void cleanup(struct spi_device *spi) |
a5f6abd4 | 1155 | { |
27bb9e79 | 1156 | struct chip_data *chip = spi_get_ctldata(spi); |
a5f6abd4 | 1157 | |
12e17c42 SZ |
1158 | if ((chip->chip_select_num > 0) |
1159 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1160 | peripheral_free(ssel[spi->master->bus_num] | |
1161 | [chip->chip_select_num-1]); | |
1162 | ||
a5f6abd4 WB |
1163 | kfree(chip); |
1164 | } | |
1165 | ||
1166 | static inline int init_queue(struct driver_data *drv_data) | |
1167 | { | |
1168 | INIT_LIST_HEAD(&drv_data->queue); | |
1169 | spin_lock_init(&drv_data->lock); | |
1170 | ||
1171 | drv_data->run = QUEUE_STOPPED; | |
1172 | drv_data->busy = 0; | |
1173 | ||
1174 | /* init transfer tasklet */ | |
1175 | tasklet_init(&drv_data->pump_transfers, | |
1176 | pump_transfers, (unsigned long)drv_data); | |
1177 | ||
1178 | /* init messages workqueue */ | |
1179 | INIT_WORK(&drv_data->pump_messages, pump_messages); | |
6c7377ab KS |
1180 | drv_data->workqueue = create_singlethread_workqueue( |
1181 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1182 | if (drv_data->workqueue == NULL) |
1183 | return -EBUSY; | |
1184 | ||
1185 | return 0; | |
1186 | } | |
1187 | ||
1188 | static inline int start_queue(struct driver_data *drv_data) | |
1189 | { | |
1190 | unsigned long flags; | |
1191 | ||
1192 | spin_lock_irqsave(&drv_data->lock, flags); | |
1193 | ||
1194 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1195 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1196 | return -EBUSY; | |
1197 | } | |
1198 | ||
1199 | drv_data->run = QUEUE_RUNNING; | |
1200 | drv_data->cur_msg = NULL; | |
1201 | drv_data->cur_transfer = NULL; | |
1202 | drv_data->cur_chip = NULL; | |
1203 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1204 | ||
1205 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1206 | ||
1207 | return 0; | |
1208 | } | |
1209 | ||
1210 | static inline int stop_queue(struct driver_data *drv_data) | |
1211 | { | |
1212 | unsigned long flags; | |
1213 | unsigned limit = 500; | |
1214 | int status = 0; | |
1215 | ||
1216 | spin_lock_irqsave(&drv_data->lock, flags); | |
1217 | ||
1218 | /* | |
1219 | * This is a bit lame, but is optimized for the common execution path. | |
1220 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1221 | * execution path (pump_messages) would be required to call wake_up or | |
1222 | * friends on every SPI message. Do this instead | |
1223 | */ | |
1224 | drv_data->run = QUEUE_STOPPED; | |
1225 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1226 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1227 | msleep(10); | |
1228 | spin_lock_irqsave(&drv_data->lock, flags); | |
1229 | } | |
1230 | ||
1231 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1232 | status = -EBUSY; | |
1233 | ||
1234 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1235 | ||
1236 | return status; | |
1237 | } | |
1238 | ||
1239 | static inline int destroy_queue(struct driver_data *drv_data) | |
1240 | { | |
1241 | int status; | |
1242 | ||
1243 | status = stop_queue(drv_data); | |
1244 | if (status != 0) | |
1245 | return status; | |
1246 | ||
1247 | destroy_workqueue(drv_data->workqueue); | |
1248 | ||
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static int __init bfin5xx_spi_probe(struct platform_device *pdev) | |
1253 | { | |
1254 | struct device *dev = &pdev->dev; | |
1255 | struct bfin5xx_spi_master *platform_info; | |
1256 | struct spi_master *master; | |
1257 | struct driver_data *drv_data = 0; | |
a32c691d | 1258 | struct resource *res; |
a5f6abd4 WB |
1259 | int status = 0; |
1260 | ||
1261 | platform_info = dev->platform_data; | |
1262 | ||
1263 | /* Allocate master with space for drv_data */ | |
1264 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1265 | if (!master) { | |
1266 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1267 | return -ENOMEM; | |
1268 | } | |
131b17d4 | 1269 | |
a5f6abd4 WB |
1270 | drv_data = spi_master_get_devdata(master); |
1271 | drv_data->master = master; | |
1272 | drv_data->master_info = platform_info; | |
1273 | drv_data->pdev = pdev; | |
003d9226 | 1274 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 WB |
1275 | |
1276 | master->bus_num = pdev->id; | |
1277 | master->num_chipselect = platform_info->num_chipselect; | |
1278 | master->cleanup = cleanup; | |
1279 | master->setup = setup; | |
1280 | master->transfer = transfer; | |
1281 | ||
a32c691d BW |
1282 | /* Find and map our resources */ |
1283 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1284 | if (res == NULL) { | |
1285 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1286 | status = -ENOENT; | |
1287 | goto out_error_get_res; | |
1288 | } | |
1289 | ||
f452126c BW |
1290 | drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1)); |
1291 | if (drv_data->regs_base == NULL) { | |
a32c691d BW |
1292 | dev_err(dev, "Cannot map IO\n"); |
1293 | status = -ENXIO; | |
1294 | goto out_error_ioremap; | |
1295 | } | |
1296 | ||
bb90eb00 BW |
1297 | drv_data->dma_channel = platform_get_irq(pdev, 0); |
1298 | if (drv_data->dma_channel < 0) { | |
a32c691d BW |
1299 | dev_err(dev, "No DMA channel specified\n"); |
1300 | status = -ENOENT; | |
1301 | goto out_error_no_dma_ch; | |
1302 | } | |
1303 | ||
a5f6abd4 WB |
1304 | /* Initial and start queue */ |
1305 | status = init_queue(drv_data); | |
1306 | if (status != 0) { | |
a32c691d | 1307 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1308 | goto out_error_queue_alloc; |
1309 | } | |
a32c691d | 1310 | |
a5f6abd4 WB |
1311 | status = start_queue(drv_data); |
1312 | if (status != 0) { | |
a32c691d | 1313 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1314 | goto out_error_queue_alloc; |
1315 | } | |
1316 | ||
f9e522ca VM |
1317 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1318 | if (status != 0) { | |
1319 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1320 | goto out_error_queue_alloc; | |
1321 | } | |
1322 | ||
a5f6abd4 WB |
1323 | /* Register with the SPI framework */ |
1324 | platform_set_drvdata(pdev, drv_data); | |
1325 | status = spi_register_master(master); | |
1326 | if (status != 0) { | |
a32c691d | 1327 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1328 | goto out_error_queue_alloc; |
1329 | } | |
a32c691d | 1330 | |
f452126c | 1331 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1332 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1333 | drv_data->dma_channel); | |
a5f6abd4 WB |
1334 | return status; |
1335 | ||
cc2f81a6 | 1336 | out_error_queue_alloc: |
a5f6abd4 | 1337 | destroy_queue(drv_data); |
a32c691d | 1338 | out_error_no_dma_ch: |
bb90eb00 | 1339 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1340 | out_error_ioremap: |
1341 | out_error_get_res: | |
a5f6abd4 | 1342 | spi_master_put(master); |
cc2f81a6 | 1343 | |
a5f6abd4 WB |
1344 | return status; |
1345 | } | |
1346 | ||
1347 | /* stop hardware and remove the driver */ | |
1348 | static int __devexit bfin5xx_spi_remove(struct platform_device *pdev) | |
1349 | { | |
1350 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1351 | int status = 0; | |
1352 | ||
1353 | if (!drv_data) | |
1354 | return 0; | |
1355 | ||
1356 | /* Remove the queue */ | |
1357 | status = destroy_queue(drv_data); | |
1358 | if (status != 0) | |
1359 | return status; | |
1360 | ||
1361 | /* Disable the SSP at the peripheral and SOC level */ | |
1362 | bfin_spi_disable(drv_data); | |
1363 | ||
1364 | /* Release DMA */ | |
1365 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1366 | if (dma_channel_active(drv_data->dma_channel)) |
1367 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1368 | } |
1369 | ||
1370 | /* Disconnect from the SPI framework */ | |
1371 | spi_unregister_master(drv_data->master); | |
1372 | ||
003d9226 | 1373 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1374 | |
a5f6abd4 WB |
1375 | /* Prevent double remove */ |
1376 | platform_set_drvdata(pdev, NULL); | |
1377 | ||
1378 | return 0; | |
1379 | } | |
1380 | ||
1381 | #ifdef CONFIG_PM | |
1382 | static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1383 | { | |
1384 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1385 | int status = 0; | |
1386 | ||
1387 | status = stop_queue(drv_data); | |
1388 | if (status != 0) | |
1389 | return status; | |
1390 | ||
1391 | /* stop hardware */ | |
1392 | bfin_spi_disable(drv_data); | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | static int bfin5xx_spi_resume(struct platform_device *pdev) | |
1398 | { | |
1399 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1400 | int status = 0; | |
1401 | ||
1402 | /* Enable the SPI interface */ | |
1403 | bfin_spi_enable(drv_data); | |
1404 | ||
1405 | /* Start the queue running */ | |
1406 | status = start_queue(drv_data); | |
1407 | if (status != 0) { | |
1408 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1409 | return status; | |
1410 | } | |
1411 | ||
1412 | return 0; | |
1413 | } | |
1414 | #else | |
1415 | #define bfin5xx_spi_suspend NULL | |
1416 | #define bfin5xx_spi_resume NULL | |
1417 | #endif /* CONFIG_PM */ | |
1418 | ||
7e38c3c4 | 1419 | MODULE_ALIAS("platform:bfin-spi"); |
a5f6abd4 | 1420 | static struct platform_driver bfin5xx_spi_driver = { |
fc3ba952 | 1421 | .driver = { |
a32c691d | 1422 | .name = DRV_NAME, |
88b40369 BW |
1423 | .owner = THIS_MODULE, |
1424 | }, | |
1425 | .suspend = bfin5xx_spi_suspend, | |
1426 | .resume = bfin5xx_spi_resume, | |
1427 | .remove = __devexit_p(bfin5xx_spi_remove), | |
a5f6abd4 WB |
1428 | }; |
1429 | ||
1430 | static int __init bfin5xx_spi_init(void) | |
1431 | { | |
88b40369 | 1432 | return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe); |
a5f6abd4 | 1433 | } |
a5f6abd4 WB |
1434 | module_init(bfin5xx_spi_init); |
1435 | ||
1436 | static void __exit bfin5xx_spi_exit(void) | |
1437 | { | |
1438 | platform_driver_unregister(&bfin5xx_spi_driver); | |
1439 | } | |
a5f6abd4 | 1440 | module_exit(bfin5xx_spi_exit); |