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Commit | Line | Data |
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a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
131b17d4 | 15 | #include <linux/io.h> |
a5f6abd4 | 16 | #include <linux/ioport.h> |
131b17d4 | 17 | #include <linux/irq.h> |
a5f6abd4 WB |
18 | #include <linux/errno.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/workqueue.h> | |
a5f6abd4 | 24 | |
a5f6abd4 | 25 | #include <asm/dma.h> |
131b17d4 | 26 | #include <asm/portmux.h> |
a5f6abd4 | 27 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
28 | #include <asm/cacheflush.h> |
29 | ||
a32c691d BW |
30 | #define DRV_NAME "bfin-spi" |
31 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
6b1a8028 | 32 | #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver" |
a32c691d BW |
33 | #define DRV_VERSION "1.0" |
34 | ||
35 | MODULE_AUTHOR(DRV_AUTHOR); | |
36 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
37 | MODULE_LICENSE("GPL"); |
38 | ||
bb90eb00 | 39 | #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0) |
a5f6abd4 | 40 | |
bb90eb00 BW |
41 | #define START_STATE ((void *)0) |
42 | #define RUNNING_STATE ((void *)1) | |
43 | #define DONE_STATE ((void *)2) | |
44 | #define ERROR_STATE ((void *)-1) | |
45 | #define QUEUE_RUNNING 0 | |
46 | #define QUEUE_STOPPED 1 | |
a5f6abd4 WB |
47 | |
48 | struct driver_data { | |
49 | /* Driver model hookup */ | |
50 | struct platform_device *pdev; | |
51 | ||
52 | /* SPI framework hookup */ | |
53 | struct spi_master *master; | |
54 | ||
bb90eb00 | 55 | /* Regs base of SPI controller */ |
f452126c | 56 | void __iomem *regs_base; |
bb90eb00 | 57 | |
003d9226 BW |
58 | /* Pin request list */ |
59 | u16 *pin_req; | |
60 | ||
a5f6abd4 WB |
61 | /* BFIN hookup */ |
62 | struct bfin5xx_spi_master *master_info; | |
63 | ||
64 | /* Driver message queue */ | |
65 | struct workqueue_struct *workqueue; | |
66 | struct work_struct pump_messages; | |
67 | spinlock_t lock; | |
68 | struct list_head queue; | |
69 | int busy; | |
70 | int run; | |
71 | ||
72 | /* Message Transfer pump */ | |
73 | struct tasklet_struct pump_transfers; | |
74 | ||
75 | /* Current message transfer state info */ | |
76 | struct spi_message *cur_msg; | |
77 | struct spi_transfer *cur_transfer; | |
78 | struct chip_data *cur_chip; | |
79 | size_t len_in_bytes; | |
80 | size_t len; | |
81 | void *tx; | |
82 | void *tx_end; | |
83 | void *rx; | |
84 | void *rx_end; | |
bb90eb00 BW |
85 | |
86 | /* DMA stuffs */ | |
87 | int dma_channel; | |
a5f6abd4 | 88 | int dma_mapped; |
bb90eb00 | 89 | int dma_requested; |
a5f6abd4 WB |
90 | dma_addr_t rx_dma; |
91 | dma_addr_t tx_dma; | |
bb90eb00 | 92 | |
a5f6abd4 WB |
93 | size_t rx_map_len; |
94 | size_t tx_map_len; | |
95 | u8 n_bytes; | |
fad91c89 | 96 | int cs_change; |
a5f6abd4 WB |
97 | void (*write) (struct driver_data *); |
98 | void (*read) (struct driver_data *); | |
99 | void (*duplex) (struct driver_data *); | |
100 | }; | |
101 | ||
102 | struct chip_data { | |
103 | u16 ctl_reg; | |
104 | u16 baud; | |
105 | u16 flag; | |
106 | ||
107 | u8 chip_select_num; | |
108 | u8 n_bytes; | |
88b40369 | 109 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
110 | u8 enable_dma; |
111 | u8 bits_per_word; /* 8 or 16 */ | |
112 | u8 cs_change_per_word; | |
62310e51 | 113 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
a5f6abd4 WB |
114 | void (*write) (struct driver_data *); |
115 | void (*read) (struct driver_data *); | |
116 | void (*duplex) (struct driver_data *); | |
117 | }; | |
118 | ||
bb90eb00 BW |
119 | #define DEFINE_SPI_REG(reg, off) \ |
120 | static inline u16 read_##reg(struct driver_data *drv_data) \ | |
121 | { return bfin_read16(drv_data->regs_base + off); } \ | |
122 | static inline void write_##reg(struct driver_data *drv_data, u16 v) \ | |
123 | { bfin_write16(drv_data->regs_base + off, v); } | |
124 | ||
125 | DEFINE_SPI_REG(CTRL, 0x00) | |
126 | DEFINE_SPI_REG(FLAG, 0x04) | |
127 | DEFINE_SPI_REG(STAT, 0x08) | |
128 | DEFINE_SPI_REG(TDBR, 0x0C) | |
129 | DEFINE_SPI_REG(RDBR, 0x10) | |
130 | DEFINE_SPI_REG(BAUD, 0x14) | |
131 | DEFINE_SPI_REG(SHAW, 0x18) | |
132 | ||
88b40369 | 133 | static void bfin_spi_enable(struct driver_data *drv_data) |
a5f6abd4 WB |
134 | { |
135 | u16 cr; | |
136 | ||
bb90eb00 BW |
137 | cr = read_CTRL(drv_data); |
138 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
139 | } |
140 | ||
88b40369 | 141 | static void bfin_spi_disable(struct driver_data *drv_data) |
a5f6abd4 WB |
142 | { |
143 | u16 cr; | |
144 | ||
bb90eb00 BW |
145 | cr = read_CTRL(drv_data); |
146 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
147 | } |
148 | ||
149 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
150 | static u16 hz_to_spi_baud(u32 speed_hz) | |
151 | { | |
152 | u_long sclk = get_sclk(); | |
153 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
154 | ||
155 | if ((sclk % (2 * speed_hz)) > 0) | |
156 | spi_baud++; | |
157 | ||
7513e006 MH |
158 | if (spi_baud < MIN_SPI_BAUD_VAL) |
159 | spi_baud = MIN_SPI_BAUD_VAL; | |
160 | ||
a5f6abd4 WB |
161 | return spi_baud; |
162 | } | |
163 | ||
164 | static int flush(struct driver_data *drv_data) | |
165 | { | |
166 | unsigned long limit = loops_per_jiffy << 1; | |
167 | ||
168 | /* wait for stop and clear stat */ | |
bb90eb00 | 169 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--) |
d8c05008 | 170 | cpu_relax(); |
a5f6abd4 | 171 | |
bb90eb00 | 172 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
173 | |
174 | return limit; | |
175 | } | |
176 | ||
fad91c89 | 177 | /* Chip select operation functions for cs_change flag */ |
bb90eb00 | 178 | static void cs_active(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 179 | { |
bb90eb00 | 180 | u16 flag = read_FLAG(drv_data); |
fad91c89 BW |
181 | |
182 | flag |= chip->flag; | |
183 | flag &= ~(chip->flag << 8); | |
184 | ||
bb90eb00 | 185 | write_FLAG(drv_data, flag); |
fad91c89 BW |
186 | } |
187 | ||
bb90eb00 | 188 | static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 189 | { |
bb90eb00 | 190 | u16 flag = read_FLAG(drv_data); |
fad91c89 BW |
191 | |
192 | flag |= (chip->flag << 8); | |
193 | ||
bb90eb00 | 194 | write_FLAG(drv_data, flag); |
62310e51 BW |
195 | |
196 | /* Move delay here for consistency */ | |
197 | if (chip->cs_chg_udelay) | |
198 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
199 | } |
200 | ||
a5f6abd4 | 201 | /* stop controller and re-config current chip*/ |
8d20d0a7 | 202 | static void restore_state(struct driver_data *drv_data) |
a5f6abd4 WB |
203 | { |
204 | struct chip_data *chip = drv_data->cur_chip; | |
12e17c42 | 205 | |
a5f6abd4 | 206 | /* Clear status and disable clock */ |
bb90eb00 | 207 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 208 | bfin_spi_disable(drv_data); |
88b40369 | 209 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 210 | |
5fec5b5a | 211 | /* Load the registers */ |
bb90eb00 | 212 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 213 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
214 | |
215 | bfin_spi_enable(drv_data); | |
07612e5f | 216 | cs_active(drv_data, chip); |
a5f6abd4 WB |
217 | } |
218 | ||
219 | /* used to kick off transfer in rx mode */ | |
bb90eb00 | 220 | static unsigned short dummy_read(struct driver_data *drv_data) |
a5f6abd4 WB |
221 | { |
222 | unsigned short tmp; | |
bb90eb00 | 223 | tmp = read_RDBR(drv_data); |
a5f6abd4 WB |
224 | return tmp; |
225 | } | |
226 | ||
227 | static void null_writer(struct driver_data *drv_data) | |
228 | { | |
229 | u8 n_bytes = drv_data->n_bytes; | |
230 | ||
231 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 BW |
232 | write_TDBR(drv_data, 0); |
233 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 234 | cpu_relax(); |
a5f6abd4 WB |
235 | drv_data->tx += n_bytes; |
236 | } | |
237 | } | |
238 | ||
239 | static void null_reader(struct driver_data *drv_data) | |
240 | { | |
241 | u8 n_bytes = drv_data->n_bytes; | |
bb90eb00 | 242 | dummy_read(drv_data); |
a5f6abd4 WB |
243 | |
244 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 245 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 246 | cpu_relax(); |
bb90eb00 | 247 | dummy_read(drv_data); |
a5f6abd4 WB |
248 | drv_data->rx += n_bytes; |
249 | } | |
250 | } | |
251 | ||
252 | static void u8_writer(struct driver_data *drv_data) | |
253 | { | |
131b17d4 | 254 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 255 | "cr8-s is 0x%x\n", read_STAT(drv_data)); |
cc487e73 | 256 | |
a5f6abd4 | 257 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 BW |
258 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
259 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 260 | cpu_relax(); |
a5f6abd4 WB |
261 | ++drv_data->tx; |
262 | } | |
13f3e642 SZ |
263 | |
264 | /* poll for SPI completion before return */ | |
265 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | |
266 | cpu_relax(); | |
a5f6abd4 WB |
267 | } |
268 | ||
269 | static void u8_cs_chg_writer(struct driver_data *drv_data) | |
270 | { | |
271 | struct chip_data *chip = drv_data->cur_chip; | |
272 | ||
273 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 | 274 | cs_active(drv_data, chip); |
a5f6abd4 | 275 | |
bb90eb00 BW |
276 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
277 | while (read_STAT(drv_data) & BIT_STAT_TXS) | |
d8c05008 | 278 | cpu_relax(); |
e26aa015 BW |
279 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
280 | cpu_relax(); | |
62310e51 | 281 | |
bb90eb00 | 282 | cs_deactive(drv_data, chip); |
5fec5b5a | 283 | |
a5f6abd4 WB |
284 | ++drv_data->tx; |
285 | } | |
a5f6abd4 WB |
286 | } |
287 | ||
288 | static void u8_reader(struct driver_data *drv_data) | |
289 | { | |
131b17d4 | 290 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 291 | "cr-8 is 0x%x\n", read_STAT(drv_data)); |
a5f6abd4 | 292 | |
3f479a65 | 293 | /* poll for SPI completion before start */ |
bb90eb00 | 294 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 295 | cpu_relax(); |
3f479a65 | 296 | |
a5f6abd4 | 297 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 298 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 299 | |
bb90eb00 | 300 | dummy_read(drv_data); |
cc487e73 | 301 | |
a5f6abd4 | 302 | while (drv_data->rx < drv_data->rx_end - 1) { |
bb90eb00 | 303 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 304 | cpu_relax(); |
bb90eb00 | 305 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
306 | ++drv_data->rx; |
307 | } | |
308 | ||
bb90eb00 | 309 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 310 | cpu_relax(); |
bb90eb00 | 311 | *(u8 *) (drv_data->rx) = read_SHAW(drv_data); |
a5f6abd4 WB |
312 | ++drv_data->rx; |
313 | } | |
314 | ||
315 | static void u8_cs_chg_reader(struct driver_data *drv_data) | |
316 | { | |
317 | struct chip_data *chip = drv_data->cur_chip; | |
318 | ||
e26aa015 BW |
319 | while (drv_data->rx < drv_data->rx_end) { |
320 | cs_active(drv_data, chip); | |
321 | read_RDBR(drv_data); /* kick off */ | |
a5f6abd4 | 322 | |
e26aa015 BW |
323 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
324 | cpu_relax(); | |
325 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | |
326 | cpu_relax(); | |
cc487e73 | 327 | |
e26aa015 | 328 | *(u8 *) (drv_data->rx) = read_SHAW(drv_data); |
bb90eb00 | 329 | cs_deactive(drv_data, chip); |
5fec5b5a | 330 | |
a5f6abd4 WB |
331 | ++drv_data->rx; |
332 | } | |
a5f6abd4 WB |
333 | } |
334 | ||
335 | static void u8_duplex(struct driver_data *drv_data) | |
336 | { | |
337 | /* in duplex mode, clk is triggered by writing of TDBR */ | |
338 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 339 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
4fd432d9 | 340 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 341 | cpu_relax(); |
bb90eb00 | 342 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 343 | cpu_relax(); |
bb90eb00 | 344 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
345 | ++drv_data->rx; |
346 | ++drv_data->tx; | |
347 | } | |
348 | } | |
349 | ||
350 | static void u8_cs_chg_duplex(struct driver_data *drv_data) | |
351 | { | |
352 | struct chip_data *chip = drv_data->cur_chip; | |
353 | ||
354 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 355 | cs_active(drv_data, chip); |
5fec5b5a | 356 | |
bb90eb00 | 357 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); |
e26aa015 BW |
358 | |
359 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | |
d8c05008 | 360 | cpu_relax(); |
bb90eb00 | 361 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 362 | cpu_relax(); |
bb90eb00 | 363 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); |
62310e51 | 364 | |
bb90eb00 | 365 | cs_deactive(drv_data, chip); |
5fec5b5a | 366 | |
a5f6abd4 WB |
367 | ++drv_data->rx; |
368 | ++drv_data->tx; | |
369 | } | |
a5f6abd4 WB |
370 | } |
371 | ||
372 | static void u16_writer(struct driver_data *drv_data) | |
373 | { | |
131b17d4 | 374 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 375 | "cr16 is 0x%x\n", read_STAT(drv_data)); |
88b40369 | 376 | |
a5f6abd4 | 377 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 BW |
378 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
379 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 380 | cpu_relax(); |
a5f6abd4 WB |
381 | drv_data->tx += 2; |
382 | } | |
13f3e642 SZ |
383 | |
384 | /* poll for SPI completion before return */ | |
385 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) | |
386 | cpu_relax(); | |
a5f6abd4 WB |
387 | } |
388 | ||
389 | static void u16_cs_chg_writer(struct driver_data *drv_data) | |
390 | { | |
391 | struct chip_data *chip = drv_data->cur_chip; | |
392 | ||
393 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 | 394 | cs_active(drv_data, chip); |
a5f6abd4 | 395 | |
bb90eb00 BW |
396 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
397 | while ((read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 398 | cpu_relax(); |
13f3e642 SZ |
399 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
400 | cpu_relax(); | |
62310e51 | 401 | |
bb90eb00 | 402 | cs_deactive(drv_data, chip); |
5fec5b5a | 403 | |
a5f6abd4 WB |
404 | drv_data->tx += 2; |
405 | } | |
a5f6abd4 WB |
406 | } |
407 | ||
408 | static void u16_reader(struct driver_data *drv_data) | |
409 | { | |
88b40369 | 410 | dev_dbg(&drv_data->pdev->dev, |
bb90eb00 | 411 | "cr-16 is 0x%x\n", read_STAT(drv_data)); |
cc487e73 | 412 | |
3f479a65 | 413 | /* poll for SPI completion before start */ |
bb90eb00 | 414 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 415 | cpu_relax(); |
3f479a65 | 416 | |
cc487e73 | 417 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 418 | write_TDBR(drv_data, 0xFFFF); |
cc487e73 | 419 | |
bb90eb00 | 420 | dummy_read(drv_data); |
a5f6abd4 WB |
421 | |
422 | while (drv_data->rx < (drv_data->rx_end - 2)) { | |
bb90eb00 | 423 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 424 | cpu_relax(); |
bb90eb00 | 425 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
426 | drv_data->rx += 2; |
427 | } | |
428 | ||
bb90eb00 | 429 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 430 | cpu_relax(); |
bb90eb00 | 431 | *(u16 *) (drv_data->rx) = read_SHAW(drv_data); |
a5f6abd4 WB |
432 | drv_data->rx += 2; |
433 | } | |
434 | ||
435 | static void u16_cs_chg_reader(struct driver_data *drv_data) | |
436 | { | |
437 | struct chip_data *chip = drv_data->cur_chip; | |
438 | ||
3f479a65 | 439 | /* poll for SPI completion before start */ |
bb90eb00 | 440 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 441 | cpu_relax(); |
3f479a65 | 442 | |
cc487e73 | 443 | /* clear TDBR buffer before read(else it will be shifted out) */ |
bb90eb00 | 444 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 445 | |
bb90eb00 BW |
446 | cs_active(drv_data, chip); |
447 | dummy_read(drv_data); | |
cc487e73 | 448 | |
c3061abb | 449 | while (drv_data->rx < drv_data->rx_end - 2) { |
bb90eb00 | 450 | cs_deactive(drv_data, chip); |
5fec5b5a | 451 | |
bb90eb00 | 452 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 453 | cpu_relax(); |
bb90eb00 BW |
454 | cs_active(drv_data, chip); |
455 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
a5f6abd4 WB |
456 | drv_data->rx += 2; |
457 | } | |
bb90eb00 | 458 | cs_deactive(drv_data, chip); |
cc487e73 | 459 | |
bb90eb00 | 460 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 461 | cpu_relax(); |
bb90eb00 | 462 | *(u16 *) (drv_data->rx) = read_SHAW(drv_data); |
cc487e73 | 463 | drv_data->rx += 2; |
a5f6abd4 WB |
464 | } |
465 | ||
466 | static void u16_duplex(struct driver_data *drv_data) | |
467 | { | |
468 | /* in duplex mode, clk is triggered by writing of TDBR */ | |
469 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 | 470 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
4fd432d9 | 471 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 472 | cpu_relax(); |
bb90eb00 | 473 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 474 | cpu_relax(); |
bb90eb00 | 475 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
476 | drv_data->rx += 2; |
477 | drv_data->tx += 2; | |
478 | } | |
479 | } | |
480 | ||
481 | static void u16_cs_chg_duplex(struct driver_data *drv_data) | |
482 | { | |
483 | struct chip_data *chip = drv_data->cur_chip; | |
484 | ||
485 | while (drv_data->tx < drv_data->tx_end) { | |
bb90eb00 | 486 | cs_active(drv_data, chip); |
a5f6abd4 | 487 | |
bb90eb00 | 488 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
4fd432d9 | 489 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 490 | cpu_relax(); |
bb90eb00 | 491 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 492 | cpu_relax(); |
bb90eb00 | 493 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
62310e51 | 494 | |
bb90eb00 | 495 | cs_deactive(drv_data, chip); |
5fec5b5a | 496 | |
a5f6abd4 WB |
497 | drv_data->rx += 2; |
498 | drv_data->tx += 2; | |
499 | } | |
a5f6abd4 WB |
500 | } |
501 | ||
502 | /* test if ther is more transfer to be done */ | |
503 | static void *next_transfer(struct driver_data *drv_data) | |
504 | { | |
505 | struct spi_message *msg = drv_data->cur_msg; | |
506 | struct spi_transfer *trans = drv_data->cur_transfer; | |
507 | ||
508 | /* Move to next transfer */ | |
509 | if (trans->transfer_list.next != &msg->transfers) { | |
510 | drv_data->cur_transfer = | |
511 | list_entry(trans->transfer_list.next, | |
512 | struct spi_transfer, transfer_list); | |
513 | return RUNNING_STATE; | |
514 | } else | |
515 | return DONE_STATE; | |
516 | } | |
517 | ||
518 | /* | |
519 | * caller already set message->status; | |
520 | * dma and pio irqs are blocked give finished message back | |
521 | */ | |
522 | static void giveback(struct driver_data *drv_data) | |
523 | { | |
fad91c89 | 524 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
525 | struct spi_transfer *last_transfer; |
526 | unsigned long flags; | |
527 | struct spi_message *msg; | |
528 | ||
529 | spin_lock_irqsave(&drv_data->lock, flags); | |
530 | msg = drv_data->cur_msg; | |
531 | drv_data->cur_msg = NULL; | |
532 | drv_data->cur_transfer = NULL; | |
533 | drv_data->cur_chip = NULL; | |
534 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
535 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
536 | ||
537 | last_transfer = list_entry(msg->transfers.prev, | |
538 | struct spi_transfer, transfer_list); | |
539 | ||
540 | msg->state = NULL; | |
541 | ||
542 | /* disable chip select signal. And not stop spi in autobuffer mode */ | |
543 | if (drv_data->tx_dma != 0xFFFF) { | |
bb90eb00 | 544 | cs_deactive(drv_data, chip); |
a5f6abd4 WB |
545 | bfin_spi_disable(drv_data); |
546 | } | |
547 | ||
fad91c89 | 548 | if (!drv_data->cs_change) |
bb90eb00 | 549 | cs_deactive(drv_data, chip); |
fad91c89 | 550 | |
a5f6abd4 WB |
551 | if (msg->complete) |
552 | msg->complete(msg->context); | |
553 | } | |
554 | ||
88b40369 | 555 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 556 | { |
15aafa2f | 557 | struct driver_data *drv_data = dev_id; |
fad91c89 | 558 | struct chip_data *chip = drv_data->cur_chip; |
bb90eb00 | 559 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 560 | unsigned long timeout; |
d24bd1d0 | 561 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 562 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 563 | |
d24bd1d0 MF |
564 | dev_dbg(&drv_data->pdev->dev, |
565 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
566 | dmastat, spistat); | |
567 | ||
bb90eb00 | 568 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 | 569 | |
d6fe89b0 | 570 | /* Wait for DMA to complete */ |
bb90eb00 | 571 | while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN) |
d8c05008 | 572 | cpu_relax(); |
d6fe89b0 | 573 | |
a5f6abd4 | 574 | /* |
d6fe89b0 BW |
575 | * wait for the last transaction shifted out. HRM states: |
576 | * at this point there may still be data in the SPI DMA FIFO waiting | |
577 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
578 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
579 | */ |
580 | if (drv_data->tx != NULL) { | |
bb90eb00 BW |
581 | while ((read_STAT(drv_data) & TXS) || |
582 | (read_STAT(drv_data) & TXS)) | |
d8c05008 | 583 | cpu_relax(); |
a5f6abd4 WB |
584 | } |
585 | ||
aaaf939c MF |
586 | dev_dbg(&drv_data->pdev->dev, |
587 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
588 | dmastat, read_STAT(drv_data)); | |
589 | ||
590 | timeout = jiffies + HZ; | |
bb90eb00 | 591 | while (!(read_STAT(drv_data) & SPIF)) |
aaaf939c MF |
592 | if (!time_before(jiffies, timeout)) { |
593 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
594 | break; | |
595 | } else | |
596 | cpu_relax(); | |
a5f6abd4 | 597 | |
40a2945b | 598 | if ((dmastat & DMA_ERR) && (spistat & RBSY)) { |
04b95d2f MF |
599 | msg->state = ERROR_STATE; |
600 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
601 | } else { | |
602 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 603 | |
04b95d2f MF |
604 | if (drv_data->cs_change) |
605 | cs_deactive(drv_data, chip); | |
fad91c89 | 606 | |
04b95d2f MF |
607 | /* Move to next transfer */ |
608 | msg->state = next_transfer(drv_data); | |
609 | } | |
a5f6abd4 WB |
610 | |
611 | /* Schedule transfer tasklet */ | |
612 | tasklet_schedule(&drv_data->pump_transfers); | |
613 | ||
614 | /* free the irq handler before next transfer */ | |
88b40369 BW |
615 | dev_dbg(&drv_data->pdev->dev, |
616 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
617 | drv_data->dma_channel); |
618 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
619 | |
620 | return IRQ_HANDLED; | |
621 | } | |
622 | ||
623 | static void pump_transfers(unsigned long data) | |
624 | { | |
625 | struct driver_data *drv_data = (struct driver_data *)data; | |
626 | struct spi_message *message = NULL; | |
627 | struct spi_transfer *transfer = NULL; | |
628 | struct spi_transfer *previous = NULL; | |
629 | struct chip_data *chip = NULL; | |
88b40369 BW |
630 | u8 width; |
631 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 632 | u32 tranf_success = 1; |
8eeb12e5 | 633 | u8 full_duplex = 0; |
a5f6abd4 WB |
634 | |
635 | /* Get current state information */ | |
636 | message = drv_data->cur_msg; | |
637 | transfer = drv_data->cur_transfer; | |
638 | chip = drv_data->cur_chip; | |
092e1fda | 639 | |
a5f6abd4 WB |
640 | /* |
641 | * if msg is error or done, report it back using complete() callback | |
642 | */ | |
643 | ||
644 | /* Handle for abort */ | |
645 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 646 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 WB |
647 | message->status = -EIO; |
648 | giveback(drv_data); | |
649 | return; | |
650 | } | |
651 | ||
652 | /* Handle end of message */ | |
653 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 654 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 WB |
655 | message->status = 0; |
656 | giveback(drv_data); | |
657 | return; | |
658 | } | |
659 | ||
660 | /* Delay if requested at end of transfer */ | |
661 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 662 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
663 | previous = list_entry(transfer->transfer_list.prev, |
664 | struct spi_transfer, transfer_list); | |
665 | if (previous->delay_usecs) | |
666 | udelay(previous->delay_usecs); | |
667 | } | |
668 | ||
669 | /* Setup the transfer state based on the type of transfer */ | |
670 | if (flush(drv_data) == 0) { | |
671 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
672 | message->status = -EIO; | |
673 | giveback(drv_data); | |
674 | return; | |
675 | } | |
676 | ||
677 | if (transfer->tx_buf != NULL) { | |
678 | drv_data->tx = (void *)transfer->tx_buf; | |
679 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
680 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
681 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
682 | } else { |
683 | drv_data->tx = NULL; | |
684 | } | |
685 | ||
686 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 687 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
688 | drv_data->rx = transfer->rx_buf; |
689 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
690 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
691 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
692 | } else { |
693 | drv_data->rx = NULL; | |
694 | } | |
695 | ||
696 | drv_data->rx_dma = transfer->rx_dma; | |
697 | drv_data->tx_dma = transfer->tx_dma; | |
698 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 699 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 700 | |
092e1fda BW |
701 | /* Bits per word setup */ |
702 | switch (transfer->bits_per_word) { | |
703 | case 8: | |
704 | drv_data->n_bytes = 1; | |
705 | width = CFG_SPI_WORDSIZE8; | |
706 | drv_data->read = chip->cs_change_per_word ? | |
707 | u8_cs_chg_reader : u8_reader; | |
708 | drv_data->write = chip->cs_change_per_word ? | |
709 | u8_cs_chg_writer : u8_writer; | |
710 | drv_data->duplex = chip->cs_change_per_word ? | |
711 | u8_cs_chg_duplex : u8_duplex; | |
712 | break; | |
713 | ||
714 | case 16: | |
715 | drv_data->n_bytes = 2; | |
716 | width = CFG_SPI_WORDSIZE16; | |
717 | drv_data->read = chip->cs_change_per_word ? | |
718 | u16_cs_chg_reader : u16_reader; | |
719 | drv_data->write = chip->cs_change_per_word ? | |
720 | u16_cs_chg_writer : u16_writer; | |
721 | drv_data->duplex = chip->cs_change_per_word ? | |
722 | u16_cs_chg_duplex : u16_duplex; | |
723 | break; | |
724 | ||
725 | default: | |
726 | /* No change, the same as default setting */ | |
727 | drv_data->n_bytes = chip->n_bytes; | |
728 | width = chip->width; | |
729 | drv_data->write = drv_data->tx ? chip->write : null_writer; | |
730 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
731 | drv_data->duplex = chip->duplex ? chip->duplex : null_writer; | |
732 | break; | |
733 | } | |
734 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
735 | cr |= (width << 8); | |
736 | write_CTRL(drv_data, cr); | |
737 | ||
a5f6abd4 WB |
738 | if (width == CFG_SPI_WORDSIZE16) { |
739 | drv_data->len = (transfer->len) >> 1; | |
740 | } else { | |
741 | drv_data->len = transfer->len; | |
742 | } | |
4fb98efa MF |
743 | dev_dbg(&drv_data->pdev->dev, |
744 | "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n", | |
131b17d4 | 745 | drv_data->write, chip->write, null_writer); |
a5f6abd4 WB |
746 | |
747 | /* speed and width has been set on per message */ | |
748 | message->state = RUNNING_STATE; | |
749 | dma_config = 0; | |
750 | ||
092e1fda BW |
751 | /* Speed setup (surely valid because already checked) */ |
752 | if (transfer->speed_hz) | |
753 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
754 | else | |
755 | write_BAUD(drv_data, chip->baud); | |
756 | ||
bb90eb00 BW |
757 | write_STAT(drv_data, BIT_STAT_CLR); |
758 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
759 | cs_active(drv_data, chip); | |
a5f6abd4 | 760 | |
88b40369 BW |
761 | dev_dbg(&drv_data->pdev->dev, |
762 | "now pumping a transfer: width is %d, len is %d\n", | |
763 | width, transfer->len); | |
a5f6abd4 WB |
764 | |
765 | /* | |
8cf5858c VM |
766 | * Try to map dma buffer and do a dma transfer. If successful use, |
767 | * different way to r/w according to the enable_dma settings and if | |
768 | * we are not doing a full duplex transfer (since the hardware does | |
769 | * not support full duplex DMA transfers). | |
a5f6abd4 | 770 | */ |
8eeb12e5 VM |
771 | if (!full_duplex && drv_data->cur_chip->enable_dma |
772 | && drv_data->len > 6) { | |
a5f6abd4 | 773 | |
11d6f599 | 774 | unsigned long dma_start_addr, flags; |
7aec3566 | 775 | |
bb90eb00 BW |
776 | disable_dma(drv_data->dma_channel); |
777 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
778 | |
779 | /* config dma channel */ | |
88b40369 | 780 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 781 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 | 782 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 | 783 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
784 | dma_width = WDSIZE_16; |
785 | } else { | |
bb90eb00 | 786 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
787 | dma_width = WDSIZE_8; |
788 | } | |
789 | ||
3f479a65 | 790 | /* poll for SPI completion before start */ |
bb90eb00 | 791 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 792 | cpu_relax(); |
3f479a65 | 793 | |
a5f6abd4 WB |
794 | /* dirty hack for autobuffer DMA mode */ |
795 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
796 | dev_dbg(&drv_data->pdev->dev, |
797 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
798 | |
799 | /* no irq in autobuffer mode */ | |
800 | dma_config = | |
801 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
802 | set_dma_config(drv_data->dma_channel, dma_config); |
803 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 804 | (unsigned long)drv_data->tx); |
bb90eb00 | 805 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 806 | |
07612e5f | 807 | /* start SPI transfer */ |
11d6f599 | 808 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
809 | |
810 | /* just return here, there can only be one transfer | |
811 | * in this mode | |
812 | */ | |
a5f6abd4 WB |
813 | message->status = 0; |
814 | giveback(drv_data); | |
815 | return; | |
816 | } | |
817 | ||
818 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 819 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
820 | if (drv_data->rx != NULL) { |
821 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
822 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
823 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 824 | |
8cf5858c VM |
825 | /* invalidate caches, if needed */ |
826 | if (bfin_addr_dcachable((unsigned long) drv_data->rx)) | |
827 | invalidate_dcache_range((unsigned long) drv_data->rx, | |
828 | (unsigned long) (drv_data->rx + | |
ace32865 | 829 | drv_data->len_in_bytes)); |
8cf5858c | 830 | |
a5f6abd4 | 831 | /* clear tx reg soformer data is not shifted out */ |
bb90eb00 | 832 | write_TDBR(drv_data, 0xFFFF); |
a5f6abd4 | 833 | |
7aec3566 MF |
834 | dma_config |= WNR; |
835 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 836 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 837 | |
a5f6abd4 | 838 | } else if (drv_data->tx != NULL) { |
88b40369 | 839 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 840 | |
8cf5858c VM |
841 | /* flush caches, if needed */ |
842 | if (bfin_addr_dcachable((unsigned long) drv_data->tx)) | |
843 | flush_dcache_range((unsigned long) drv_data->tx, | |
844 | (unsigned long) (drv_data->tx + | |
ace32865 | 845 | drv_data->len_in_bytes)); |
8cf5858c | 846 | |
7aec3566 | 847 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 848 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
849 | |
850 | } else | |
851 | BUG(); | |
852 | ||
11d6f599 MF |
853 | /* oh man, here there be monsters ... and i dont mean the |
854 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
855 | * your data, kick your dog, and love it all. do *not* try | |
856 | * and change these lines unless you (1) heavily test DMA | |
857 | * with SPI flashes on a loaded system (e.g. ping floods), | |
858 | * (2) know just how broken the DMA engine interaction with | |
859 | * the SPI peripheral is, and (3) have someone else to blame | |
860 | * when you screw it all up anyways. | |
861 | */ | |
7aec3566 | 862 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
863 | set_dma_config(drv_data->dma_channel, dma_config); |
864 | local_irq_save(flags); | |
7aec3566 | 865 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
866 | write_CTRL(drv_data, cr); |
867 | dma_enable_irq(drv_data->dma_channel); | |
868 | local_irq_restore(flags); | |
07612e5f | 869 | |
a5f6abd4 WB |
870 | } else { |
871 | /* IO mode write then read */ | |
88b40369 | 872 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
a5f6abd4 | 873 | |
8eeb12e5 | 874 | if (full_duplex) { |
a5f6abd4 WB |
875 | /* full duplex mode */ |
876 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
877 | (drv_data->rx_end - drv_data->rx)); | |
88b40369 BW |
878 | dev_dbg(&drv_data->pdev->dev, |
879 | "IO duplex: cr is 0x%x\n", cr); | |
a5f6abd4 | 880 | |
cc487e73 | 881 | /* set SPI transfer mode */ |
bb90eb00 | 882 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
a5f6abd4 WB |
883 | |
884 | drv_data->duplex(drv_data); | |
885 | ||
886 | if (drv_data->tx != drv_data->tx_end) | |
887 | tranf_success = 0; | |
888 | } else if (drv_data->tx != NULL) { | |
889 | /* write only half duplex */ | |
131b17d4 | 890 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 891 | "IO write: cr is 0x%x\n", cr); |
a5f6abd4 | 892 | |
cc487e73 | 893 | /* set SPI transfer mode */ |
bb90eb00 | 894 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
a5f6abd4 WB |
895 | |
896 | drv_data->write(drv_data); | |
897 | ||
898 | if (drv_data->tx != drv_data->tx_end) | |
899 | tranf_success = 0; | |
900 | } else if (drv_data->rx != NULL) { | |
901 | /* read only half duplex */ | |
131b17d4 | 902 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 903 | "IO read: cr is 0x%x\n", cr); |
a5f6abd4 | 904 | |
cc487e73 | 905 | /* set SPI transfer mode */ |
bb90eb00 | 906 | write_CTRL(drv_data, (cr | CFG_SPI_READ)); |
a5f6abd4 WB |
907 | |
908 | drv_data->read(drv_data); | |
909 | if (drv_data->rx != drv_data->rx_end) | |
910 | tranf_success = 0; | |
911 | } | |
912 | ||
913 | if (!tranf_success) { | |
131b17d4 | 914 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 915 | "IO write error!\n"); |
a5f6abd4 WB |
916 | message->state = ERROR_STATE; |
917 | } else { | |
918 | /* Update total byte transfered */ | |
ace32865 | 919 | message->actual_length += drv_data->len_in_bytes; |
a5f6abd4 WB |
920 | |
921 | /* Move to next transfer of this msg */ | |
922 | message->state = next_transfer(drv_data); | |
923 | } | |
924 | ||
925 | /* Schedule next transfer tasklet */ | |
926 | tasklet_schedule(&drv_data->pump_transfers); | |
927 | ||
928 | } | |
929 | } | |
930 | ||
931 | /* pop a msg from queue and kick off real transfer */ | |
932 | static void pump_messages(struct work_struct *work) | |
933 | { | |
131b17d4 | 934 | struct driver_data *drv_data; |
a5f6abd4 WB |
935 | unsigned long flags; |
936 | ||
131b17d4 BW |
937 | drv_data = container_of(work, struct driver_data, pump_messages); |
938 | ||
a5f6abd4 WB |
939 | /* Lock queue and check for queue work */ |
940 | spin_lock_irqsave(&drv_data->lock, flags); | |
941 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
942 | /* pumper kicked off but no work to do */ | |
943 | drv_data->busy = 0; | |
944 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
945 | return; | |
946 | } | |
947 | ||
948 | /* Make sure we are not already running a message */ | |
949 | if (drv_data->cur_msg) { | |
950 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
951 | return; | |
952 | } | |
953 | ||
954 | /* Extract head of queue */ | |
955 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
956 | struct spi_message, queue); | |
5fec5b5a BW |
957 | |
958 | /* Setup the SSP using the per chip configuration */ | |
959 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
8d20d0a7 | 960 | restore_state(drv_data); |
5fec5b5a | 961 | |
a5f6abd4 WB |
962 | list_del_init(&drv_data->cur_msg->queue); |
963 | ||
964 | /* Initial message state */ | |
965 | drv_data->cur_msg->state = START_STATE; | |
966 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
967 | struct spi_transfer, transfer_list); | |
968 | ||
5fec5b5a BW |
969 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
970 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
971 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
972 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
973 | |
974 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
975 | "the first transfer len is %d\n", |
976 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
977 | |
978 | /* Mark as busy and launch transfers */ | |
979 | tasklet_schedule(&drv_data->pump_transfers); | |
980 | ||
981 | drv_data->busy = 1; | |
982 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
983 | } | |
984 | ||
985 | /* | |
986 | * got a msg to transfer, queue it in drv_data->queue. | |
987 | * And kick off message pumper | |
988 | */ | |
989 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
990 | { | |
991 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
992 | unsigned long flags; | |
993 | ||
994 | spin_lock_irqsave(&drv_data->lock, flags); | |
995 | ||
996 | if (drv_data->run == QUEUE_STOPPED) { | |
997 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
998 | return -ESHUTDOWN; | |
999 | } | |
1000 | ||
1001 | msg->actual_length = 0; | |
1002 | msg->status = -EINPROGRESS; | |
1003 | msg->state = START_STATE; | |
1004 | ||
88b40369 | 1005 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
1006 | list_add_tail(&msg->queue, &drv_data->queue); |
1007 | ||
1008 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
1009 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1010 | ||
1011 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1012 | ||
1013 | return 0; | |
1014 | } | |
1015 | ||
12e17c42 SZ |
1016 | #define MAX_SPI_SSEL 7 |
1017 | ||
4160bde2 | 1018 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
1019 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
1020 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
1021 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
1022 | ||
1023 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
1024 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
1025 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
1026 | ||
1027 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
1028 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
1029 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
1030 | }; | |
1031 | ||
a5f6abd4 WB |
1032 | /* first setup for new devices */ |
1033 | static int setup(struct spi_device *spi) | |
1034 | { | |
1035 | struct bfin5xx_spi_chip *chip_info = NULL; | |
1036 | struct chip_data *chip; | |
1037 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
1038 | u8 spi_flg; | |
1039 | ||
1040 | /* Abort device setup if requested features are not supported */ | |
1041 | if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) { | |
1042 | dev_err(&spi->dev, "requested mode not fully supported\n"); | |
1043 | return -EINVAL; | |
1044 | } | |
1045 | ||
1046 | /* Zero (the default) here means 8 bits */ | |
1047 | if (!spi->bits_per_word) | |
1048 | spi->bits_per_word = 8; | |
1049 | ||
1050 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) | |
1051 | return -EINVAL; | |
1052 | ||
1053 | /* Only alloc (or use chip_info) on first setup */ | |
1054 | chip = spi_get_ctldata(spi); | |
1055 | if (chip == NULL) { | |
1056 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1057 | if (!chip) | |
1058 | return -ENOMEM; | |
1059 | ||
1060 | chip->enable_dma = 0; | |
1061 | chip_info = spi->controller_data; | |
1062 | } | |
1063 | ||
1064 | /* chip_info isn't always needed */ | |
1065 | if (chip_info) { | |
2ed35516 MF |
1066 | /* Make sure people stop trying to set fields via ctl_reg |
1067 | * when they should actually be using common SPI framework. | |
1068 | * Currently we let through: WOM EMISO PSSE GM SZ TIMOD. | |
1069 | * Not sure if a user actually needs/uses any of these, | |
1070 | * but let's assume (for now) they do. | |
1071 | */ | |
1072 | if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) { | |
1073 | dev_err(&spi->dev, "do not set bits in ctl_reg " | |
1074 | "that the SPI framework manages\n"); | |
1075 | return -EINVAL; | |
1076 | } | |
1077 | ||
a5f6abd4 WB |
1078 | chip->enable_dma = chip_info->enable_dma != 0 |
1079 | && drv_data->master_info->enable_dma; | |
1080 | chip->ctl_reg = chip_info->ctl_reg; | |
1081 | chip->bits_per_word = chip_info->bits_per_word; | |
1082 | chip->cs_change_per_word = chip_info->cs_change_per_word; | |
1083 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
1084 | } | |
1085 | ||
1086 | /* translate common spi framework into our register */ | |
1087 | if (spi->mode & SPI_CPOL) | |
1088 | chip->ctl_reg |= CPOL; | |
1089 | if (spi->mode & SPI_CPHA) | |
1090 | chip->ctl_reg |= CPHA; | |
1091 | if (spi->mode & SPI_LSB_FIRST) | |
1092 | chip->ctl_reg |= LSBF; | |
1093 | /* we dont support running in slave mode (yet?) */ | |
1094 | chip->ctl_reg |= MSTR; | |
1095 | ||
1096 | /* | |
1097 | * if any one SPI chip is registered and wants DMA, request the | |
1098 | * DMA channel for it | |
1099 | */ | |
bb90eb00 | 1100 | if (chip->enable_dma && !drv_data->dma_requested) { |
a5f6abd4 | 1101 | /* register dma irq handler */ |
59bfcc66 | 1102 | if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) { |
88b40369 BW |
1103 | dev_dbg(&spi->dev, |
1104 | "Unable to request BlackFin SPI DMA channel\n"); | |
a5f6abd4 WB |
1105 | return -ENODEV; |
1106 | } | |
bb90eb00 | 1107 | if (set_dma_callback(drv_data->dma_channel, |
59bfcc66 | 1108 | dma_irq_handler, drv_data) < 0) { |
88b40369 | 1109 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
a5f6abd4 WB |
1110 | return -EPERM; |
1111 | } | |
bb90eb00 BW |
1112 | dma_disable_irq(drv_data->dma_channel); |
1113 | drv_data->dma_requested = 1; | |
a5f6abd4 WB |
1114 | } |
1115 | ||
1116 | /* | |
1117 | * Notice: for blackfin, the speed_hz is the value of register | |
1118 | * SPI_BAUD, not the real baudrate | |
1119 | */ | |
1120 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
1121 | spi_flg = ~(1 << (spi->chip_select)); | |
1122 | chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select)); | |
1123 | chip->chip_select_num = spi->chip_select; | |
1124 | ||
1125 | switch (chip->bits_per_word) { | |
1126 | case 8: | |
1127 | chip->n_bytes = 1; | |
1128 | chip->width = CFG_SPI_WORDSIZE8; | |
1129 | chip->read = chip->cs_change_per_word ? | |
1130 | u8_cs_chg_reader : u8_reader; | |
1131 | chip->write = chip->cs_change_per_word ? | |
1132 | u8_cs_chg_writer : u8_writer; | |
1133 | chip->duplex = chip->cs_change_per_word ? | |
1134 | u8_cs_chg_duplex : u8_duplex; | |
1135 | break; | |
1136 | ||
1137 | case 16: | |
1138 | chip->n_bytes = 2; | |
1139 | chip->width = CFG_SPI_WORDSIZE16; | |
1140 | chip->read = chip->cs_change_per_word ? | |
1141 | u16_cs_chg_reader : u16_reader; | |
1142 | chip->write = chip->cs_change_per_word ? | |
1143 | u16_cs_chg_writer : u16_writer; | |
1144 | chip->duplex = chip->cs_change_per_word ? | |
1145 | u16_cs_chg_duplex : u16_duplex; | |
1146 | break; | |
1147 | ||
1148 | default: | |
1149 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1150 | chip->bits_per_word); | |
1151 | kfree(chip); | |
1152 | return -ENODEV; | |
1153 | } | |
1154 | ||
898eb71c | 1155 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1156 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1157 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1158 | chip->ctl_reg, chip->flag); |
1159 | ||
1160 | spi_set_ctldata(spi, chip); | |
1161 | ||
12e17c42 SZ |
1162 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
1163 | if ((chip->chip_select_num > 0) | |
1164 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1165 | peripheral_request(ssel[spi->master->bus_num] | |
aab0d83e | 1166 | [chip->chip_select_num-1], spi->modalias); |
12e17c42 | 1167 | |
07612e5f SZ |
1168 | cs_deactive(drv_data, chip); |
1169 | ||
a5f6abd4 WB |
1170 | return 0; |
1171 | } | |
1172 | ||
1173 | /* | |
1174 | * callback for spi framework. | |
1175 | * clean driver specific data | |
1176 | */ | |
88b40369 | 1177 | static void cleanup(struct spi_device *spi) |
a5f6abd4 | 1178 | { |
27bb9e79 | 1179 | struct chip_data *chip = spi_get_ctldata(spi); |
a5f6abd4 | 1180 | |
12e17c42 SZ |
1181 | if ((chip->chip_select_num > 0) |
1182 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1183 | peripheral_free(ssel[spi->master->bus_num] | |
1184 | [chip->chip_select_num-1]); | |
1185 | ||
a5f6abd4 WB |
1186 | kfree(chip); |
1187 | } | |
1188 | ||
1189 | static inline int init_queue(struct driver_data *drv_data) | |
1190 | { | |
1191 | INIT_LIST_HEAD(&drv_data->queue); | |
1192 | spin_lock_init(&drv_data->lock); | |
1193 | ||
1194 | drv_data->run = QUEUE_STOPPED; | |
1195 | drv_data->busy = 0; | |
1196 | ||
1197 | /* init transfer tasklet */ | |
1198 | tasklet_init(&drv_data->pump_transfers, | |
1199 | pump_transfers, (unsigned long)drv_data); | |
1200 | ||
1201 | /* init messages workqueue */ | |
1202 | INIT_WORK(&drv_data->pump_messages, pump_messages); | |
6c7377ab KS |
1203 | drv_data->workqueue = create_singlethread_workqueue( |
1204 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1205 | if (drv_data->workqueue == NULL) |
1206 | return -EBUSY; | |
1207 | ||
1208 | return 0; | |
1209 | } | |
1210 | ||
1211 | static inline int start_queue(struct driver_data *drv_data) | |
1212 | { | |
1213 | unsigned long flags; | |
1214 | ||
1215 | spin_lock_irqsave(&drv_data->lock, flags); | |
1216 | ||
1217 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1218 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1219 | return -EBUSY; | |
1220 | } | |
1221 | ||
1222 | drv_data->run = QUEUE_RUNNING; | |
1223 | drv_data->cur_msg = NULL; | |
1224 | drv_data->cur_transfer = NULL; | |
1225 | drv_data->cur_chip = NULL; | |
1226 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1227 | ||
1228 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1229 | ||
1230 | return 0; | |
1231 | } | |
1232 | ||
1233 | static inline int stop_queue(struct driver_data *drv_data) | |
1234 | { | |
1235 | unsigned long flags; | |
1236 | unsigned limit = 500; | |
1237 | int status = 0; | |
1238 | ||
1239 | spin_lock_irqsave(&drv_data->lock, flags); | |
1240 | ||
1241 | /* | |
1242 | * This is a bit lame, but is optimized for the common execution path. | |
1243 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1244 | * execution path (pump_messages) would be required to call wake_up or | |
1245 | * friends on every SPI message. Do this instead | |
1246 | */ | |
1247 | drv_data->run = QUEUE_STOPPED; | |
1248 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1249 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1250 | msleep(10); | |
1251 | spin_lock_irqsave(&drv_data->lock, flags); | |
1252 | } | |
1253 | ||
1254 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1255 | status = -EBUSY; | |
1256 | ||
1257 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1258 | ||
1259 | return status; | |
1260 | } | |
1261 | ||
1262 | static inline int destroy_queue(struct driver_data *drv_data) | |
1263 | { | |
1264 | int status; | |
1265 | ||
1266 | status = stop_queue(drv_data); | |
1267 | if (status != 0) | |
1268 | return status; | |
1269 | ||
1270 | destroy_workqueue(drv_data->workqueue); | |
1271 | ||
1272 | return 0; | |
1273 | } | |
1274 | ||
1275 | static int __init bfin5xx_spi_probe(struct platform_device *pdev) | |
1276 | { | |
1277 | struct device *dev = &pdev->dev; | |
1278 | struct bfin5xx_spi_master *platform_info; | |
1279 | struct spi_master *master; | |
1280 | struct driver_data *drv_data = 0; | |
a32c691d | 1281 | struct resource *res; |
a5f6abd4 WB |
1282 | int status = 0; |
1283 | ||
1284 | platform_info = dev->platform_data; | |
1285 | ||
1286 | /* Allocate master with space for drv_data */ | |
1287 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1288 | if (!master) { | |
1289 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1290 | return -ENOMEM; | |
1291 | } | |
131b17d4 | 1292 | |
a5f6abd4 WB |
1293 | drv_data = spi_master_get_devdata(master); |
1294 | drv_data->master = master; | |
1295 | drv_data->master_info = platform_info; | |
1296 | drv_data->pdev = pdev; | |
003d9226 | 1297 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 WB |
1298 | |
1299 | master->bus_num = pdev->id; | |
1300 | master->num_chipselect = platform_info->num_chipselect; | |
1301 | master->cleanup = cleanup; | |
1302 | master->setup = setup; | |
1303 | master->transfer = transfer; | |
1304 | ||
a32c691d BW |
1305 | /* Find and map our resources */ |
1306 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1307 | if (res == NULL) { | |
1308 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1309 | status = -ENOENT; | |
1310 | goto out_error_get_res; | |
1311 | } | |
1312 | ||
f452126c BW |
1313 | drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1)); |
1314 | if (drv_data->regs_base == NULL) { | |
a32c691d BW |
1315 | dev_err(dev, "Cannot map IO\n"); |
1316 | status = -ENXIO; | |
1317 | goto out_error_ioremap; | |
1318 | } | |
1319 | ||
bb90eb00 BW |
1320 | drv_data->dma_channel = platform_get_irq(pdev, 0); |
1321 | if (drv_data->dma_channel < 0) { | |
a32c691d BW |
1322 | dev_err(dev, "No DMA channel specified\n"); |
1323 | status = -ENOENT; | |
1324 | goto out_error_no_dma_ch; | |
1325 | } | |
1326 | ||
a5f6abd4 WB |
1327 | /* Initial and start queue */ |
1328 | status = init_queue(drv_data); | |
1329 | if (status != 0) { | |
a32c691d | 1330 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1331 | goto out_error_queue_alloc; |
1332 | } | |
a32c691d | 1333 | |
a5f6abd4 WB |
1334 | status = start_queue(drv_data); |
1335 | if (status != 0) { | |
a32c691d | 1336 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1337 | goto out_error_queue_alloc; |
1338 | } | |
1339 | ||
f9e522ca VM |
1340 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1341 | if (status != 0) { | |
1342 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1343 | goto out_error_queue_alloc; | |
1344 | } | |
1345 | ||
a5f6abd4 WB |
1346 | /* Register with the SPI framework */ |
1347 | platform_set_drvdata(pdev, drv_data); | |
1348 | status = spi_register_master(master); | |
1349 | if (status != 0) { | |
a32c691d | 1350 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1351 | goto out_error_queue_alloc; |
1352 | } | |
a32c691d | 1353 | |
f452126c | 1354 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1355 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1356 | drv_data->dma_channel); | |
a5f6abd4 WB |
1357 | return status; |
1358 | ||
cc2f81a6 | 1359 | out_error_queue_alloc: |
a5f6abd4 | 1360 | destroy_queue(drv_data); |
a32c691d | 1361 | out_error_no_dma_ch: |
bb90eb00 | 1362 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1363 | out_error_ioremap: |
1364 | out_error_get_res: | |
a5f6abd4 | 1365 | spi_master_put(master); |
cc2f81a6 | 1366 | |
a5f6abd4 WB |
1367 | return status; |
1368 | } | |
1369 | ||
1370 | /* stop hardware and remove the driver */ | |
1371 | static int __devexit bfin5xx_spi_remove(struct platform_device *pdev) | |
1372 | { | |
1373 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1374 | int status = 0; | |
1375 | ||
1376 | if (!drv_data) | |
1377 | return 0; | |
1378 | ||
1379 | /* Remove the queue */ | |
1380 | status = destroy_queue(drv_data); | |
1381 | if (status != 0) | |
1382 | return status; | |
1383 | ||
1384 | /* Disable the SSP at the peripheral and SOC level */ | |
1385 | bfin_spi_disable(drv_data); | |
1386 | ||
1387 | /* Release DMA */ | |
1388 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1389 | if (dma_channel_active(drv_data->dma_channel)) |
1390 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1391 | } |
1392 | ||
1393 | /* Disconnect from the SPI framework */ | |
1394 | spi_unregister_master(drv_data->master); | |
1395 | ||
003d9226 | 1396 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1397 | |
a5f6abd4 WB |
1398 | /* Prevent double remove */ |
1399 | platform_set_drvdata(pdev, NULL); | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
1404 | #ifdef CONFIG_PM | |
1405 | static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1406 | { | |
1407 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1408 | int status = 0; | |
1409 | ||
1410 | status = stop_queue(drv_data); | |
1411 | if (status != 0) | |
1412 | return status; | |
1413 | ||
1414 | /* stop hardware */ | |
1415 | bfin_spi_disable(drv_data); | |
1416 | ||
1417 | return 0; | |
1418 | } | |
1419 | ||
1420 | static int bfin5xx_spi_resume(struct platform_device *pdev) | |
1421 | { | |
1422 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1423 | int status = 0; | |
1424 | ||
1425 | /* Enable the SPI interface */ | |
1426 | bfin_spi_enable(drv_data); | |
1427 | ||
1428 | /* Start the queue running */ | |
1429 | status = start_queue(drv_data); | |
1430 | if (status != 0) { | |
1431 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1432 | return status; | |
1433 | } | |
1434 | ||
1435 | return 0; | |
1436 | } | |
1437 | #else | |
1438 | #define bfin5xx_spi_suspend NULL | |
1439 | #define bfin5xx_spi_resume NULL | |
1440 | #endif /* CONFIG_PM */ | |
1441 | ||
7e38c3c4 | 1442 | MODULE_ALIAS("platform:bfin-spi"); |
a5f6abd4 | 1443 | static struct platform_driver bfin5xx_spi_driver = { |
fc3ba952 | 1444 | .driver = { |
a32c691d | 1445 | .name = DRV_NAME, |
88b40369 BW |
1446 | .owner = THIS_MODULE, |
1447 | }, | |
1448 | .suspend = bfin5xx_spi_suspend, | |
1449 | .resume = bfin5xx_spi_resume, | |
1450 | .remove = __devexit_p(bfin5xx_spi_remove), | |
a5f6abd4 WB |
1451 | }; |
1452 | ||
1453 | static int __init bfin5xx_spi_init(void) | |
1454 | { | |
88b40369 | 1455 | return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe); |
a5f6abd4 | 1456 | } |
a5f6abd4 WB |
1457 | module_init(bfin5xx_spi_init); |
1458 | ||
1459 | static void __exit bfin5xx_spi_exit(void) | |
1460 | { | |
1461 | platform_driver_unregister(&bfin5xx_spi_driver); | |
1462 | } | |
a5f6abd4 | 1463 | module_exit(bfin5xx_spi_exit); |