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Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
5a0e3ad6 | 15 | #include <linux/slab.h> |
131b17d4 | 16 | #include <linux/io.h> |
a5f6abd4 | 17 | #include <linux/ioport.h> |
131b17d4 | 18 | #include <linux/irq.h> |
a5f6abd4 WB |
19 | #include <linux/errno.h> |
20 | #include <linux/interrupt.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/dma-mapping.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/workqueue.h> | |
a5f6abd4 | 25 | |
a5f6abd4 | 26 | #include <asm/dma.h> |
131b17d4 | 27 | #include <asm/portmux.h> |
a5f6abd4 | 28 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
29 | #include <asm/cacheflush.h> |
30 | ||
a32c691d BW |
31 | #define DRV_NAME "bfin-spi" |
32 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 33 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
34 | #define DRV_VERSION "1.0" |
35 | ||
36 | MODULE_AUTHOR(DRV_AUTHOR); | |
37 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
38 | MODULE_LICENSE("GPL"); |
39 | ||
bb90eb00 BW |
40 | #define START_STATE ((void *)0) |
41 | #define RUNNING_STATE ((void *)1) | |
42 | #define DONE_STATE ((void *)2) | |
43 | #define ERROR_STATE ((void *)-1) | |
a5f6abd4 | 44 | |
b9f139a7 | 45 | struct master_data; |
9c4542c7 MF |
46 | |
47 | struct transfer_ops { | |
b9f139a7 MF |
48 | void (*write) (struct master_data *); |
49 | void (*read) (struct master_data *); | |
50 | void (*duplex) (struct master_data *); | |
9c4542c7 MF |
51 | }; |
52 | ||
b9f139a7 | 53 | struct master_data { |
a5f6abd4 WB |
54 | /* Driver model hookup */ |
55 | struct platform_device *pdev; | |
56 | ||
57 | /* SPI framework hookup */ | |
58 | struct spi_master *master; | |
59 | ||
bb90eb00 | 60 | /* Regs base of SPI controller */ |
f452126c | 61 | void __iomem *regs_base; |
bb90eb00 | 62 | |
003d9226 BW |
63 | /* Pin request list */ |
64 | u16 *pin_req; | |
65 | ||
a5f6abd4 WB |
66 | /* BFIN hookup */ |
67 | struct bfin5xx_spi_master *master_info; | |
68 | ||
69 | /* Driver message queue */ | |
70 | struct workqueue_struct *workqueue; | |
71 | struct work_struct pump_messages; | |
72 | spinlock_t lock; | |
73 | struct list_head queue; | |
74 | int busy; | |
f4f50c3f | 75 | bool running; |
a5f6abd4 WB |
76 | |
77 | /* Message Transfer pump */ | |
78 | struct tasklet_struct pump_transfers; | |
79 | ||
80 | /* Current message transfer state info */ | |
81 | struct spi_message *cur_msg; | |
82 | struct spi_transfer *cur_transfer; | |
b9f139a7 | 83 | struct slave_data *cur_chip; |
a5f6abd4 WB |
84 | size_t len_in_bytes; |
85 | size_t len; | |
86 | void *tx; | |
87 | void *tx_end; | |
88 | void *rx; | |
89 | void *rx_end; | |
bb90eb00 BW |
90 | |
91 | /* DMA stuffs */ | |
92 | int dma_channel; | |
a5f6abd4 | 93 | int dma_mapped; |
bb90eb00 | 94 | int dma_requested; |
a5f6abd4 WB |
95 | dma_addr_t rx_dma; |
96 | dma_addr_t tx_dma; | |
bb90eb00 | 97 | |
f6a6d966 YL |
98 | int irq_requested; |
99 | int spi_irq; | |
100 | ||
a5f6abd4 WB |
101 | size_t rx_map_len; |
102 | size_t tx_map_len; | |
103 | u8 n_bytes; | |
fad91c89 | 104 | int cs_change; |
9c4542c7 | 105 | const struct transfer_ops *ops; |
a5f6abd4 WB |
106 | }; |
107 | ||
b9f139a7 | 108 | struct slave_data { |
a5f6abd4 WB |
109 | u16 ctl_reg; |
110 | u16 baud; | |
111 | u16 flag; | |
112 | ||
113 | u8 chip_select_num; | |
114 | u8 n_bytes; | |
88b40369 | 115 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
116 | u8 enable_dma; |
117 | u8 bits_per_word; /* 8 or 16 */ | |
62310e51 | 118 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 119 | u32 cs_gpio; |
93b61bdd | 120 | u16 idle_tx_val; |
f6a6d966 | 121 | u8 pio_interrupt; /* use spi data irq */ |
9c4542c7 | 122 | const struct transfer_ops *ops; |
a5f6abd4 WB |
123 | }; |
124 | ||
bb90eb00 | 125 | #define DEFINE_SPI_REG(reg, off) \ |
b9f139a7 | 126 | static inline u16 read_##reg(struct master_data *drv_data) \ |
bb90eb00 | 127 | { return bfin_read16(drv_data->regs_base + off); } \ |
b9f139a7 | 128 | static inline void write_##reg(struct master_data *drv_data, u16 v) \ |
bb90eb00 BW |
129 | { bfin_write16(drv_data->regs_base + off, v); } |
130 | ||
131 | DEFINE_SPI_REG(CTRL, 0x00) | |
132 | DEFINE_SPI_REG(FLAG, 0x04) | |
133 | DEFINE_SPI_REG(STAT, 0x08) | |
134 | DEFINE_SPI_REG(TDBR, 0x0C) | |
135 | DEFINE_SPI_REG(RDBR, 0x10) | |
136 | DEFINE_SPI_REG(BAUD, 0x14) | |
137 | DEFINE_SPI_REG(SHAW, 0x18) | |
138 | ||
b9f139a7 | 139 | static void bfin_spi_enable(struct master_data *drv_data) |
a5f6abd4 WB |
140 | { |
141 | u16 cr; | |
142 | ||
bb90eb00 BW |
143 | cr = read_CTRL(drv_data); |
144 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
145 | } |
146 | ||
b9f139a7 | 147 | static void bfin_spi_disable(struct master_data *drv_data) |
a5f6abd4 WB |
148 | { |
149 | u16 cr; | |
150 | ||
bb90eb00 BW |
151 | cr = read_CTRL(drv_data); |
152 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
153 | } |
154 | ||
155 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
156 | static u16 hz_to_spi_baud(u32 speed_hz) | |
157 | { | |
158 | u_long sclk = get_sclk(); | |
159 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
160 | ||
161 | if ((sclk % (2 * speed_hz)) > 0) | |
162 | spi_baud++; | |
163 | ||
7513e006 MH |
164 | if (spi_baud < MIN_SPI_BAUD_VAL) |
165 | spi_baud = MIN_SPI_BAUD_VAL; | |
166 | ||
a5f6abd4 WB |
167 | return spi_baud; |
168 | } | |
169 | ||
b9f139a7 | 170 | static int bfin_spi_flush(struct master_data *drv_data) |
a5f6abd4 WB |
171 | { |
172 | unsigned long limit = loops_per_jiffy << 1; | |
173 | ||
174 | /* wait for stop and clear stat */ | |
b4bd2aba | 175 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 176 | cpu_relax(); |
a5f6abd4 | 177 | |
bb90eb00 | 178 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
179 | |
180 | return limit; | |
181 | } | |
182 | ||
fad91c89 | 183 | /* Chip select operation functions for cs_change flag */ |
b9f139a7 | 184 | static void bfin_spi_cs_active(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 185 | { |
d3cc71f7 | 186 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 187 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 188 | |
8221610e | 189 | flag &= ~chip->flag; |
fad91c89 | 190 | |
42c78b2b MH |
191 | write_FLAG(drv_data, flag); |
192 | } else { | |
193 | gpio_set_value(chip->cs_gpio, 0); | |
194 | } | |
fad91c89 BW |
195 | } |
196 | ||
b9f139a7 | 197 | static void bfin_spi_cs_deactive(struct master_data *drv_data, struct slave_data *chip) |
fad91c89 | 198 | { |
d3cc71f7 | 199 | if (likely(chip->chip_select_num < MAX_CTRL_CS)) { |
42c78b2b | 200 | u16 flag = read_FLAG(drv_data); |
fad91c89 | 201 | |
8221610e | 202 | flag |= chip->flag; |
fad91c89 | 203 | |
42c78b2b MH |
204 | write_FLAG(drv_data, flag); |
205 | } else { | |
206 | gpio_set_value(chip->cs_gpio, 1); | |
207 | } | |
62310e51 BW |
208 | |
209 | /* Move delay here for consistency */ | |
210 | if (chip->cs_chg_udelay) | |
211 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
212 | } |
213 | ||
8221610e | 214 | /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ |
b9f139a7 | 215 | static inline void bfin_spi_cs_enable(struct master_data *drv_data, struct slave_data *chip) |
8221610e | 216 | { |
d3cc71f7 BS |
217 | if (chip->chip_select_num < MAX_CTRL_CS) { |
218 | u16 flag = read_FLAG(drv_data); | |
8221610e | 219 | |
d3cc71f7 | 220 | flag |= (chip->flag >> 8); |
8221610e | 221 | |
d3cc71f7 BS |
222 | write_FLAG(drv_data, flag); |
223 | } | |
8221610e BS |
224 | } |
225 | ||
b9f139a7 | 226 | static inline void bfin_spi_cs_disable(struct master_data *drv_data, struct slave_data *chip) |
8221610e | 227 | { |
d3cc71f7 BS |
228 | if (chip->chip_select_num < MAX_CTRL_CS) { |
229 | u16 flag = read_FLAG(drv_data); | |
8221610e | 230 | |
d3cc71f7 | 231 | flag &= ~(chip->flag >> 8); |
8221610e | 232 | |
d3cc71f7 BS |
233 | write_FLAG(drv_data, flag); |
234 | } | |
8221610e BS |
235 | } |
236 | ||
a5f6abd4 | 237 | /* stop controller and re-config current chip*/ |
b9f139a7 | 238 | static void bfin_spi_restore_state(struct master_data *drv_data) |
a5f6abd4 | 239 | { |
b9f139a7 | 240 | struct slave_data *chip = drv_data->cur_chip; |
12e17c42 | 241 | |
a5f6abd4 | 242 | /* Clear status and disable clock */ |
bb90eb00 | 243 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 244 | bfin_spi_disable(drv_data); |
88b40369 | 245 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 246 | |
5fec5b5a | 247 | /* Load the registers */ |
bb90eb00 | 248 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 249 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
250 | |
251 | bfin_spi_enable(drv_data); | |
138f97cd | 252 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
253 | } |
254 | ||
93b61bdd | 255 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
b9f139a7 | 256 | static inline void bfin_spi_dummy_read(struct master_data *drv_data) |
a5f6abd4 | 257 | { |
93b61bdd | 258 | (void) read_RDBR(drv_data); |
a5f6abd4 WB |
259 | } |
260 | ||
b9f139a7 | 261 | static void bfin_spi_u8_writer(struct master_data *drv_data) |
a5f6abd4 | 262 | { |
93b61bdd WM |
263 | /* clear RXS (we check for RXS inside the loop) */ |
264 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 265 | |
a5f6abd4 | 266 | while (drv_data->tx < drv_data->tx_end) { |
93b61bdd WM |
267 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
268 | /* wait until transfer finished. | |
269 | checking SPIF or TXS may not guarantee transfer completion */ | |
270 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
d8c05008 | 271 | cpu_relax(); |
93b61bdd WM |
272 | /* discard RX data and clear RXS */ |
273 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 274 | } |
a5f6abd4 WB |
275 | } |
276 | ||
b9f139a7 | 277 | static void bfin_spi_u8_reader(struct master_data *drv_data) |
a5f6abd4 | 278 | { |
93b61bdd | 279 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 280 | |
93b61bdd | 281 | /* discard old RX data and clear RXS */ |
138f97cd | 282 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 283 | |
93b61bdd WM |
284 | while (drv_data->rx < drv_data->rx_end) { |
285 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 286 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 287 | cpu_relax(); |
93b61bdd | 288 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 | 289 | } |
a5f6abd4 WB |
290 | } |
291 | ||
b9f139a7 | 292 | static void bfin_spi_u8_duplex(struct master_data *drv_data) |
a5f6abd4 | 293 | { |
93b61bdd WM |
294 | /* discard old RX data and clear RXS */ |
295 | bfin_spi_dummy_read(drv_data); | |
296 | ||
a5f6abd4 | 297 | while (drv_data->rx < drv_data->rx_end) { |
93b61bdd | 298 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 299 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 300 | cpu_relax(); |
93b61bdd | 301 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 WB |
302 | } |
303 | } | |
304 | ||
9c4542c7 MF |
305 | static const struct transfer_ops bfin_transfer_ops_u8 = { |
306 | .write = bfin_spi_u8_writer, | |
307 | .read = bfin_spi_u8_reader, | |
308 | .duplex = bfin_spi_u8_duplex, | |
309 | }; | |
310 | ||
b9f139a7 | 311 | static void bfin_spi_u16_writer(struct master_data *drv_data) |
a5f6abd4 | 312 | { |
93b61bdd WM |
313 | /* clear RXS (we check for RXS inside the loop) */ |
314 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 315 | |
a5f6abd4 | 316 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 317 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 318 | drv_data->tx += 2; |
93b61bdd WM |
319 | /* wait until transfer finished. |
320 | checking SPIF or TXS may not guarantee transfer completion */ | |
321 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
322 | cpu_relax(); | |
323 | /* discard RX data and clear RXS */ | |
324 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 325 | } |
a5f6abd4 WB |
326 | } |
327 | ||
b9f139a7 | 328 | static void bfin_spi_u16_reader(struct master_data *drv_data) |
a5f6abd4 | 329 | { |
93b61bdd | 330 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 331 | |
93b61bdd | 332 | /* discard old RX data and clear RXS */ |
138f97cd | 333 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 334 | |
93b61bdd WM |
335 | while (drv_data->rx < drv_data->rx_end) { |
336 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 337 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 338 | cpu_relax(); |
bb90eb00 | 339 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
340 | drv_data->rx += 2; |
341 | } | |
a5f6abd4 WB |
342 | } |
343 | ||
b9f139a7 | 344 | static void bfin_spi_u16_duplex(struct master_data *drv_data) |
a5f6abd4 | 345 | { |
93b61bdd WM |
346 | /* discard old RX data and clear RXS */ |
347 | bfin_spi_dummy_read(drv_data); | |
348 | ||
349 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 350 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 351 | drv_data->tx += 2; |
bb90eb00 | 352 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 353 | cpu_relax(); |
bb90eb00 | 354 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 355 | drv_data->rx += 2; |
a5f6abd4 WB |
356 | } |
357 | } | |
358 | ||
9c4542c7 MF |
359 | static const struct transfer_ops bfin_transfer_ops_u16 = { |
360 | .write = bfin_spi_u16_writer, | |
361 | .read = bfin_spi_u16_reader, | |
362 | .duplex = bfin_spi_u16_duplex, | |
363 | }; | |
364 | ||
a5f6abd4 | 365 | /* test if ther is more transfer to be done */ |
b9f139a7 | 366 | static void *bfin_spi_next_transfer(struct master_data *drv_data) |
a5f6abd4 WB |
367 | { |
368 | struct spi_message *msg = drv_data->cur_msg; | |
369 | struct spi_transfer *trans = drv_data->cur_transfer; | |
370 | ||
371 | /* Move to next transfer */ | |
372 | if (trans->transfer_list.next != &msg->transfers) { | |
373 | drv_data->cur_transfer = | |
374 | list_entry(trans->transfer_list.next, | |
375 | struct spi_transfer, transfer_list); | |
376 | return RUNNING_STATE; | |
377 | } else | |
378 | return DONE_STATE; | |
379 | } | |
380 | ||
381 | /* | |
382 | * caller already set message->status; | |
383 | * dma and pio irqs are blocked give finished message back | |
384 | */ | |
b9f139a7 | 385 | static void bfin_spi_giveback(struct master_data *drv_data) |
a5f6abd4 | 386 | { |
b9f139a7 | 387 | struct slave_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
388 | struct spi_transfer *last_transfer; |
389 | unsigned long flags; | |
390 | struct spi_message *msg; | |
391 | ||
392 | spin_lock_irqsave(&drv_data->lock, flags); | |
393 | msg = drv_data->cur_msg; | |
394 | drv_data->cur_msg = NULL; | |
395 | drv_data->cur_transfer = NULL; | |
396 | drv_data->cur_chip = NULL; | |
397 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
398 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
399 | ||
400 | last_transfer = list_entry(msg->transfers.prev, | |
401 | struct spi_transfer, transfer_list); | |
402 | ||
403 | msg->state = NULL; | |
404 | ||
fad91c89 | 405 | if (!drv_data->cs_change) |
138f97cd | 406 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 407 | |
b9b2a76a YL |
408 | /* Not stop spi in autobuffer mode */ |
409 | if (drv_data->tx_dma != 0xFFFF) | |
410 | bfin_spi_disable(drv_data); | |
411 | ||
a5f6abd4 WB |
412 | if (msg->complete) |
413 | msg->complete(msg->context); | |
414 | } | |
415 | ||
f6a6d966 YL |
416 | /* spi data irq handler */ |
417 | static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id) | |
418 | { | |
b9f139a7 MF |
419 | struct master_data *drv_data = dev_id; |
420 | struct slave_data *chip = drv_data->cur_chip; | |
f6a6d966 YL |
421 | struct spi_message *msg = drv_data->cur_msg; |
422 | int n_bytes = drv_data->n_bytes; | |
423 | ||
424 | /* wait until transfer finished. */ | |
425 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
426 | cpu_relax(); | |
427 | ||
428 | if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) || | |
429 | (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) { | |
430 | /* last read */ | |
431 | if (drv_data->rx) { | |
432 | dev_dbg(&drv_data->pdev->dev, "last read\n"); | |
433 | if (n_bytes == 2) | |
434 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
435 | else if (n_bytes == 1) | |
436 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
437 | drv_data->rx += n_bytes; | |
438 | } | |
439 | ||
440 | msg->actual_length += drv_data->len_in_bytes; | |
441 | if (drv_data->cs_change) | |
442 | bfin_spi_cs_deactive(drv_data, chip); | |
443 | /* Move to next transfer */ | |
444 | msg->state = bfin_spi_next_transfer(drv_data); | |
445 | ||
446 | disable_irq(drv_data->spi_irq); | |
447 | ||
448 | /* Schedule transfer tasklet */ | |
449 | tasklet_schedule(&drv_data->pump_transfers); | |
450 | return IRQ_HANDLED; | |
451 | } | |
452 | ||
453 | if (drv_data->rx && drv_data->tx) { | |
454 | /* duplex */ | |
455 | dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n"); | |
456 | if (drv_data->n_bytes == 2) { | |
457 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
458 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
459 | } else if (drv_data->n_bytes == 1) { | |
460 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
461 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
462 | } | |
463 | } else if (drv_data->rx) { | |
464 | /* read */ | |
465 | dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n"); | |
466 | if (drv_data->n_bytes == 2) | |
467 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); | |
468 | else if (drv_data->n_bytes == 1) | |
469 | *(u8 *) (drv_data->rx) = read_RDBR(drv_data); | |
470 | write_TDBR(drv_data, chip->idle_tx_val); | |
471 | } else if (drv_data->tx) { | |
472 | /* write */ | |
473 | dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n"); | |
474 | bfin_spi_dummy_read(drv_data); | |
475 | if (drv_data->n_bytes == 2) | |
476 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
477 | else if (drv_data->n_bytes == 1) | |
478 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
479 | } | |
480 | ||
481 | if (drv_data->tx) | |
482 | drv_data->tx += n_bytes; | |
483 | if (drv_data->rx) | |
484 | drv_data->rx += n_bytes; | |
485 | ||
486 | return IRQ_HANDLED; | |
487 | } | |
488 | ||
138f97cd | 489 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 490 | { |
b9f139a7 MF |
491 | struct master_data *drv_data = dev_id; |
492 | struct slave_data *chip = drv_data->cur_chip; | |
bb90eb00 | 493 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 494 | unsigned long timeout; |
d24bd1d0 | 495 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 496 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 497 | |
d24bd1d0 MF |
498 | dev_dbg(&drv_data->pdev->dev, |
499 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
500 | dmastat, spistat); | |
501 | ||
bb90eb00 | 502 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 WB |
503 | |
504 | /* | |
d6fe89b0 BW |
505 | * wait for the last transaction shifted out. HRM states: |
506 | * at this point there may still be data in the SPI DMA FIFO waiting | |
507 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
508 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
509 | */ |
510 | if (drv_data->tx != NULL) { | |
90008a64 MF |
511 | while ((read_STAT(drv_data) & BIT_STAT_TXS) || |
512 | (read_STAT(drv_data) & BIT_STAT_TXS)) | |
d8c05008 | 513 | cpu_relax(); |
a5f6abd4 WB |
514 | } |
515 | ||
aaaf939c MF |
516 | dev_dbg(&drv_data->pdev->dev, |
517 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
518 | dmastat, read_STAT(drv_data)); | |
519 | ||
520 | timeout = jiffies + HZ; | |
90008a64 | 521 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
aaaf939c MF |
522 | if (!time_before(jiffies, timeout)) { |
523 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
524 | break; | |
525 | } else | |
526 | cpu_relax(); | |
a5f6abd4 | 527 | |
90008a64 | 528 | if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) { |
04b95d2f MF |
529 | msg->state = ERROR_STATE; |
530 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
531 | } else { | |
532 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 533 | |
04b95d2f | 534 | if (drv_data->cs_change) |
138f97cd | 535 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 536 | |
04b95d2f | 537 | /* Move to next transfer */ |
138f97cd | 538 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 539 | } |
a5f6abd4 WB |
540 | |
541 | /* Schedule transfer tasklet */ | |
542 | tasklet_schedule(&drv_data->pump_transfers); | |
543 | ||
544 | /* free the irq handler before next transfer */ | |
88b40369 BW |
545 | dev_dbg(&drv_data->pdev->dev, |
546 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
547 | drv_data->dma_channel); |
548 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
549 | |
550 | return IRQ_HANDLED; | |
551 | } | |
552 | ||
138f97cd | 553 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 | 554 | { |
b9f139a7 | 555 | struct master_data *drv_data = (struct master_data *)data; |
a5f6abd4 WB |
556 | struct spi_message *message = NULL; |
557 | struct spi_transfer *transfer = NULL; | |
558 | struct spi_transfer *previous = NULL; | |
b9f139a7 | 559 | struct slave_data *chip = NULL; |
88b40369 BW |
560 | u8 width; |
561 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 562 | u32 tranf_success = 1; |
8eeb12e5 | 563 | u8 full_duplex = 0; |
a5f6abd4 WB |
564 | |
565 | /* Get current state information */ | |
566 | message = drv_data->cur_msg; | |
567 | transfer = drv_data->cur_transfer; | |
568 | chip = drv_data->cur_chip; | |
092e1fda | 569 | |
a5f6abd4 WB |
570 | /* |
571 | * if msg is error or done, report it back using complete() callback | |
572 | */ | |
573 | ||
574 | /* Handle for abort */ | |
575 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 576 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 577 | message->status = -EIO; |
138f97cd | 578 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
579 | return; |
580 | } | |
581 | ||
582 | /* Handle end of message */ | |
583 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 584 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 585 | message->status = 0; |
138f97cd | 586 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
587 | return; |
588 | } | |
589 | ||
590 | /* Delay if requested at end of transfer */ | |
591 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 592 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
593 | previous = list_entry(transfer->transfer_list.prev, |
594 | struct spi_transfer, transfer_list); | |
595 | if (previous->delay_usecs) | |
596 | udelay(previous->delay_usecs); | |
597 | } | |
598 | ||
ab09e040 | 599 | /* Flush any existing transfers that may be sitting in the hardware */ |
138f97cd | 600 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
601 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
602 | message->status = -EIO; | |
138f97cd | 603 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
604 | return; |
605 | } | |
606 | ||
93b61bdd WM |
607 | if (transfer->len == 0) { |
608 | /* Move to next transfer of this msg */ | |
609 | message->state = bfin_spi_next_transfer(drv_data); | |
610 | /* Schedule next transfer tasklet */ | |
611 | tasklet_schedule(&drv_data->pump_transfers); | |
612 | } | |
613 | ||
a5f6abd4 WB |
614 | if (transfer->tx_buf != NULL) { |
615 | drv_data->tx = (void *)transfer->tx_buf; | |
616 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
617 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
618 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
619 | } else { |
620 | drv_data->tx = NULL; | |
621 | } | |
622 | ||
623 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 624 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
625 | drv_data->rx = transfer->rx_buf; |
626 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
627 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
628 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
629 | } else { |
630 | drv_data->rx = NULL; | |
631 | } | |
632 | ||
633 | drv_data->rx_dma = transfer->rx_dma; | |
634 | drv_data->tx_dma = transfer->tx_dma; | |
635 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 636 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 637 | |
092e1fda BW |
638 | /* Bits per word setup */ |
639 | switch (transfer->bits_per_word) { | |
640 | case 8: | |
641 | drv_data->n_bytes = 1; | |
642 | width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 643 | drv_data->ops = &bfin_transfer_ops_u8; |
092e1fda BW |
644 | break; |
645 | ||
646 | case 16: | |
647 | drv_data->n_bytes = 2; | |
648 | width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 649 | drv_data->ops = &bfin_transfer_ops_u16; |
092e1fda BW |
650 | break; |
651 | ||
652 | default: | |
653 | /* No change, the same as default setting */ | |
f6a6d966 | 654 | transfer->bits_per_word = chip->bits_per_word; |
092e1fda BW |
655 | drv_data->n_bytes = chip->n_bytes; |
656 | width = chip->width; | |
9c4542c7 | 657 | drv_data->ops = chip->ops; |
092e1fda BW |
658 | break; |
659 | } | |
660 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
661 | cr |= (width << 8); | |
662 | write_CTRL(drv_data, cr); | |
663 | ||
a5f6abd4 WB |
664 | if (width == CFG_SPI_WORDSIZE16) { |
665 | drv_data->len = (transfer->len) >> 1; | |
666 | } else { | |
667 | drv_data->len = transfer->len; | |
668 | } | |
4fb98efa | 669 | dev_dbg(&drv_data->pdev->dev, |
9c4542c7 MF |
670 | "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n", |
671 | drv_data->ops, chip->ops, &bfin_transfer_ops_u8); | |
a5f6abd4 | 672 | |
a5f6abd4 WB |
673 | message->state = RUNNING_STATE; |
674 | dma_config = 0; | |
675 | ||
092e1fda BW |
676 | /* Speed setup (surely valid because already checked) */ |
677 | if (transfer->speed_hz) | |
678 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
679 | else | |
680 | write_BAUD(drv_data, chip->baud); | |
681 | ||
bb90eb00 BW |
682 | write_STAT(drv_data, BIT_STAT_CLR); |
683 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
b9b2a76a | 684 | if (drv_data->cs_change) |
138f97cd | 685 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 686 | |
88b40369 BW |
687 | dev_dbg(&drv_data->pdev->dev, |
688 | "now pumping a transfer: width is %d, len is %d\n", | |
689 | width, transfer->len); | |
a5f6abd4 WB |
690 | |
691 | /* | |
8cf5858c VM |
692 | * Try to map dma buffer and do a dma transfer. If successful use, |
693 | * different way to r/w according to the enable_dma settings and if | |
694 | * we are not doing a full duplex transfer (since the hardware does | |
695 | * not support full duplex DMA transfers). | |
a5f6abd4 | 696 | */ |
8eeb12e5 VM |
697 | if (!full_duplex && drv_data->cur_chip->enable_dma |
698 | && drv_data->len > 6) { | |
a5f6abd4 | 699 | |
11d6f599 | 700 | unsigned long dma_start_addr, flags; |
7aec3566 | 701 | |
bb90eb00 BW |
702 | disable_dma(drv_data->dma_channel); |
703 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
704 | |
705 | /* config dma channel */ | |
88b40369 | 706 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 707 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 | 708 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 | 709 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
710 | dma_width = WDSIZE_16; |
711 | } else { | |
bb90eb00 | 712 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
713 | dma_width = WDSIZE_8; |
714 | } | |
715 | ||
3f479a65 | 716 | /* poll for SPI completion before start */ |
bb90eb00 | 717 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 718 | cpu_relax(); |
3f479a65 | 719 | |
a5f6abd4 WB |
720 | /* dirty hack for autobuffer DMA mode */ |
721 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
722 | dev_dbg(&drv_data->pdev->dev, |
723 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
724 | |
725 | /* no irq in autobuffer mode */ | |
726 | dma_config = | |
727 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
728 | set_dma_config(drv_data->dma_channel, dma_config); |
729 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 730 | (unsigned long)drv_data->tx); |
bb90eb00 | 731 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 732 | |
07612e5f | 733 | /* start SPI transfer */ |
11d6f599 | 734 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
735 | |
736 | /* just return here, there can only be one transfer | |
737 | * in this mode | |
738 | */ | |
a5f6abd4 | 739 | message->status = 0; |
138f97cd | 740 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
741 | return; |
742 | } | |
743 | ||
744 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 745 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
746 | if (drv_data->rx != NULL) { |
747 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
748 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
749 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 750 | |
8cf5858c | 751 | /* invalidate caches, if needed */ |
67834fa9 | 752 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
753 | invalidate_dcache_range((unsigned long) drv_data->rx, |
754 | (unsigned long) (drv_data->rx + | |
ace32865 | 755 | drv_data->len_in_bytes)); |
8cf5858c | 756 | |
7aec3566 MF |
757 | dma_config |= WNR; |
758 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 759 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 760 | |
a5f6abd4 | 761 | } else if (drv_data->tx != NULL) { |
88b40369 | 762 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 763 | |
8cf5858c | 764 | /* flush caches, if needed */ |
67834fa9 | 765 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
766 | flush_dcache_range((unsigned long) drv_data->tx, |
767 | (unsigned long) (drv_data->tx + | |
ace32865 | 768 | drv_data->len_in_bytes)); |
8cf5858c | 769 | |
7aec3566 | 770 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 771 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
772 | |
773 | } else | |
774 | BUG(); | |
775 | ||
11d6f599 MF |
776 | /* oh man, here there be monsters ... and i dont mean the |
777 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
778 | * your data, kick your dog, and love it all. do *not* try | |
779 | * and change these lines unless you (1) heavily test DMA | |
780 | * with SPI flashes on a loaded system (e.g. ping floods), | |
781 | * (2) know just how broken the DMA engine interaction with | |
782 | * the SPI peripheral is, and (3) have someone else to blame | |
783 | * when you screw it all up anyways. | |
784 | */ | |
7aec3566 | 785 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
786 | set_dma_config(drv_data->dma_channel, dma_config); |
787 | local_irq_save(flags); | |
a963ea83 | 788 | SSYNC(); |
11d6f599 | 789 | write_CTRL(drv_data, cr); |
a963ea83 | 790 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
791 | dma_enable_irq(drv_data->dma_channel); |
792 | local_irq_restore(flags); | |
07612e5f | 793 | |
f6a6d966 YL |
794 | return; |
795 | } | |
a5f6abd4 | 796 | |
f6a6d966 YL |
797 | if (chip->pio_interrupt) { |
798 | /* use write mode. spi irq should have been disabled */ | |
799 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
93b61bdd WM |
800 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); |
801 | ||
f6a6d966 YL |
802 | /* discard old RX data and clear RXS */ |
803 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 804 | |
f6a6d966 YL |
805 | /* start transfer */ |
806 | if (drv_data->tx == NULL) | |
807 | write_TDBR(drv_data, chip->idle_tx_val); | |
808 | else { | |
809 | if (transfer->bits_per_word == 8) | |
810 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx))); | |
811 | else if (transfer->bits_per_word == 16) | |
812 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); | |
813 | drv_data->tx += drv_data->n_bytes; | |
814 | } | |
a5f6abd4 | 815 | |
f6a6d966 YL |
816 | /* once TDBR is empty, interrupt is triggered */ |
817 | enable_irq(drv_data->spi_irq); | |
818 | return; | |
819 | } | |
a5f6abd4 | 820 | |
f6a6d966 YL |
821 | /* IO mode */ |
822 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); | |
823 | ||
824 | /* we always use SPI_WRITE mode. SPI_READ mode | |
825 | seems to have problems with setting up the | |
826 | output value in TDBR prior to the transfer. */ | |
827 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); | |
828 | ||
829 | if (full_duplex) { | |
830 | /* full duplex mode */ | |
831 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
832 | (drv_data->rx_end - drv_data->rx)); | |
833 | dev_dbg(&drv_data->pdev->dev, | |
834 | "IO duplex: cr is 0x%x\n", cr); | |
835 | ||
9c4542c7 | 836 | drv_data->ops->duplex(drv_data); |
f6a6d966 YL |
837 | |
838 | if (drv_data->tx != drv_data->tx_end) | |
839 | tranf_success = 0; | |
840 | } else if (drv_data->tx != NULL) { | |
841 | /* write only half duplex */ | |
842 | dev_dbg(&drv_data->pdev->dev, | |
843 | "IO write: cr is 0x%x\n", cr); | |
844 | ||
9c4542c7 | 845 | drv_data->ops->write(drv_data); |
f6a6d966 YL |
846 | |
847 | if (drv_data->tx != drv_data->tx_end) | |
848 | tranf_success = 0; | |
849 | } else if (drv_data->rx != NULL) { | |
850 | /* read only half duplex */ | |
851 | dev_dbg(&drv_data->pdev->dev, | |
852 | "IO read: cr is 0x%x\n", cr); | |
853 | ||
9c4542c7 | 854 | drv_data->ops->read(drv_data); |
f6a6d966 YL |
855 | if (drv_data->rx != drv_data->rx_end) |
856 | tranf_success = 0; | |
857 | } | |
a5f6abd4 | 858 | |
f6a6d966 YL |
859 | if (!tranf_success) { |
860 | dev_dbg(&drv_data->pdev->dev, | |
861 | "IO write error!\n"); | |
862 | message->state = ERROR_STATE; | |
863 | } else { | |
864 | /* Update total byte transfered */ | |
865 | message->actual_length += drv_data->len_in_bytes; | |
866 | /* Move to next transfer of this msg */ | |
867 | message->state = bfin_spi_next_transfer(drv_data); | |
868 | if (drv_data->cs_change) | |
869 | bfin_spi_cs_deactive(drv_data, chip); | |
a5f6abd4 | 870 | } |
f6a6d966 YL |
871 | |
872 | /* Schedule next transfer tasklet */ | |
873 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
874 | } |
875 | ||
876 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 877 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 878 | { |
b9f139a7 | 879 | struct master_data *drv_data; |
a5f6abd4 WB |
880 | unsigned long flags; |
881 | ||
b9f139a7 | 882 | drv_data = container_of(work, struct master_data, pump_messages); |
131b17d4 | 883 | |
a5f6abd4 WB |
884 | /* Lock queue and check for queue work */ |
885 | spin_lock_irqsave(&drv_data->lock, flags); | |
f4f50c3f | 886 | if (list_empty(&drv_data->queue) || !drv_data->running) { |
a5f6abd4 WB |
887 | /* pumper kicked off but no work to do */ |
888 | drv_data->busy = 0; | |
889 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
890 | return; | |
891 | } | |
892 | ||
893 | /* Make sure we are not already running a message */ | |
894 | if (drv_data->cur_msg) { | |
895 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
896 | return; | |
897 | } | |
898 | ||
899 | /* Extract head of queue */ | |
900 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
901 | struct spi_message, queue); | |
5fec5b5a BW |
902 | |
903 | /* Setup the SSP using the per chip configuration */ | |
904 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 905 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 906 | |
a5f6abd4 WB |
907 | list_del_init(&drv_data->cur_msg->queue); |
908 | ||
909 | /* Initial message state */ | |
910 | drv_data->cur_msg->state = START_STATE; | |
911 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
912 | struct spi_transfer, transfer_list); | |
913 | ||
5fec5b5a BW |
914 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
915 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
916 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
917 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
918 | |
919 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
920 | "the first transfer len is %d\n", |
921 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
922 | |
923 | /* Mark as busy and launch transfers */ | |
924 | tasklet_schedule(&drv_data->pump_transfers); | |
925 | ||
926 | drv_data->busy = 1; | |
927 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
928 | } | |
929 | ||
930 | /* | |
931 | * got a msg to transfer, queue it in drv_data->queue. | |
932 | * And kick off message pumper | |
933 | */ | |
138f97cd | 934 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 | 935 | { |
b9f139a7 | 936 | struct master_data *drv_data = spi_master_get_devdata(spi->master); |
a5f6abd4 WB |
937 | unsigned long flags; |
938 | ||
939 | spin_lock_irqsave(&drv_data->lock, flags); | |
940 | ||
f4f50c3f | 941 | if (!drv_data->running) { |
a5f6abd4 WB |
942 | spin_unlock_irqrestore(&drv_data->lock, flags); |
943 | return -ESHUTDOWN; | |
944 | } | |
945 | ||
946 | msg->actual_length = 0; | |
947 | msg->status = -EINPROGRESS; | |
948 | msg->state = START_STATE; | |
949 | ||
88b40369 | 950 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
951 | list_add_tail(&msg->queue, &drv_data->queue); |
952 | ||
f4f50c3f | 953 | if (drv_data->running && !drv_data->busy) |
a5f6abd4 WB |
954 | queue_work(drv_data->workqueue, &drv_data->pump_messages); |
955 | ||
956 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
12e17c42 SZ |
961 | #define MAX_SPI_SSEL 7 |
962 | ||
4160bde2 | 963 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
964 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
965 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
966 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
967 | ||
968 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
969 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
970 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
971 | ||
972 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
973 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
974 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
975 | }; | |
976 | ||
ab09e040 | 977 | /* setup for devices (may be called multiple times -- not just first setup) */ |
138f97cd | 978 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 | 979 | { |
ac01e97d | 980 | struct bfin5xx_spi_chip *chip_info; |
b9f139a7 MF |
981 | struct slave_data *chip = NULL; |
982 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
ac01e97d | 983 | int ret = -EINVAL; |
a5f6abd4 | 984 | |
a5f6abd4 | 985 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) |
ac01e97d | 986 | goto error; |
a5f6abd4 WB |
987 | |
988 | /* Only alloc (or use chip_info) on first setup */ | |
ac01e97d | 989 | chip_info = NULL; |
a5f6abd4 WB |
990 | chip = spi_get_ctldata(spi); |
991 | if (chip == NULL) { | |
ac01e97d DM |
992 | chip = kzalloc(sizeof(*chip), GFP_KERNEL); |
993 | if (!chip) { | |
994 | dev_err(&spi->dev, "cannot allocate chip data\n"); | |
995 | ret = -ENOMEM; | |
996 | goto error; | |
997 | } | |
a5f6abd4 WB |
998 | |
999 | chip->enable_dma = 0; | |
1000 | chip_info = spi->controller_data; | |
1001 | } | |
1002 | ||
1003 | /* chip_info isn't always needed */ | |
1004 | if (chip_info) { | |
2ed35516 MF |
1005 | /* Make sure people stop trying to set fields via ctl_reg |
1006 | * when they should actually be using common SPI framework. | |
90008a64 | 1007 | * Currently we let through: WOM EMISO PSSE GM SZ. |
2ed35516 MF |
1008 | * Not sure if a user actually needs/uses any of these, |
1009 | * but let's assume (for now) they do. | |
1010 | */ | |
90008a64 MF |
1011 | if (chip_info->ctl_reg & ~(BIT_CTL_OPENDRAIN | BIT_CTL_EMISO | \ |
1012 | BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ)) { | |
2ed35516 MF |
1013 | dev_err(&spi->dev, "do not set bits in ctl_reg " |
1014 | "that the SPI framework manages\n"); | |
ac01e97d | 1015 | goto error; |
2ed35516 MF |
1016 | } |
1017 | ||
a5f6abd4 WB |
1018 | chip->enable_dma = chip_info->enable_dma != 0 |
1019 | && drv_data->master_info->enable_dma; | |
1020 | chip->ctl_reg = chip_info->ctl_reg; | |
1021 | chip->bits_per_word = chip_info->bits_per_word; | |
a5f6abd4 | 1022 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; |
93b61bdd | 1023 | chip->idle_tx_val = chip_info->idle_tx_val; |
f6a6d966 | 1024 | chip->pio_interrupt = chip_info->pio_interrupt; |
a5f6abd4 WB |
1025 | } |
1026 | ||
1027 | /* translate common spi framework into our register */ | |
1028 | if (spi->mode & SPI_CPOL) | |
90008a64 | 1029 | chip->ctl_reg |= BIT_CTL_CPOL; |
a5f6abd4 | 1030 | if (spi->mode & SPI_CPHA) |
90008a64 | 1031 | chip->ctl_reg |= BIT_CTL_CPHA; |
a5f6abd4 | 1032 | if (spi->mode & SPI_LSB_FIRST) |
90008a64 | 1033 | chip->ctl_reg |= BIT_CTL_LSBF; |
a5f6abd4 | 1034 | /* we dont support running in slave mode (yet?) */ |
90008a64 | 1035 | chip->ctl_reg |= BIT_CTL_MASTER; |
a5f6abd4 | 1036 | |
a5f6abd4 WB |
1037 | /* |
1038 | * Notice: for blackfin, the speed_hz is the value of register | |
1039 | * SPI_BAUD, not the real baudrate | |
1040 | */ | |
1041 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
a5f6abd4 | 1042 | chip->chip_select_num = spi->chip_select; |
d3cc71f7 BS |
1043 | if (chip->chip_select_num < MAX_CTRL_CS) |
1044 | chip->flag = (1 << spi->chip_select) << 8; | |
1045 | else | |
1046 | chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS; | |
a5f6abd4 WB |
1047 | |
1048 | switch (chip->bits_per_word) { | |
1049 | case 8: | |
1050 | chip->n_bytes = 1; | |
1051 | chip->width = CFG_SPI_WORDSIZE8; | |
9c4542c7 | 1052 | chip->ops = &bfin_transfer_ops_u8; |
a5f6abd4 WB |
1053 | break; |
1054 | ||
1055 | case 16: | |
1056 | chip->n_bytes = 2; | |
1057 | chip->width = CFG_SPI_WORDSIZE16; | |
9c4542c7 | 1058 | chip->ops = &bfin_transfer_ops_u16; |
a5f6abd4 WB |
1059 | break; |
1060 | ||
1061 | default: | |
1062 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1063 | chip->bits_per_word); | |
ac01e97d DM |
1064 | goto error; |
1065 | } | |
1066 | ||
f6a6d966 YL |
1067 | if (chip->enable_dma && chip->pio_interrupt) { |
1068 | dev_err(&spi->dev, "enable_dma is set, " | |
1069 | "do not set pio_interrupt\n"); | |
1070 | goto error; | |
1071 | } | |
ac01e97d DM |
1072 | /* |
1073 | * if any one SPI chip is registered and wants DMA, request the | |
1074 | * DMA channel for it | |
1075 | */ | |
1076 | if (chip->enable_dma && !drv_data->dma_requested) { | |
1077 | /* register dma irq handler */ | |
1078 | ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA"); | |
1079 | if (ret) { | |
1080 | dev_err(&spi->dev, | |
1081 | "Unable to request BlackFin SPI DMA channel\n"); | |
1082 | goto error; | |
1083 | } | |
1084 | drv_data->dma_requested = 1; | |
1085 | ||
1086 | ret = set_dma_callback(drv_data->dma_channel, | |
1087 | bfin_spi_dma_irq_handler, drv_data); | |
1088 | if (ret) { | |
1089 | dev_err(&spi->dev, "Unable to set dma callback\n"); | |
1090 | goto error; | |
1091 | } | |
1092 | dma_disable_irq(drv_data->dma_channel); | |
1093 | } | |
1094 | ||
f6a6d966 YL |
1095 | if (chip->pio_interrupt && !drv_data->irq_requested) { |
1096 | ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler, | |
1097 | IRQF_DISABLED, "BFIN_SPI", drv_data); | |
1098 | if (ret) { | |
1099 | dev_err(&spi->dev, "Unable to register spi IRQ\n"); | |
1100 | goto error; | |
1101 | } | |
1102 | drv_data->irq_requested = 1; | |
1103 | /* we use write mode, spi irq has to be disabled here */ | |
1104 | disable_irq(drv_data->spi_irq); | |
1105 | } | |
1106 | ||
d3cc71f7 | 1107 | if (chip->chip_select_num >= MAX_CTRL_CS) { |
ac01e97d DM |
1108 | ret = gpio_request(chip->cs_gpio, spi->modalias); |
1109 | if (ret) { | |
1110 | dev_err(&spi->dev, "gpio_request() error\n"); | |
1111 | goto pin_error; | |
1112 | } | |
1113 | gpio_direction_output(chip->cs_gpio, 1); | |
a5f6abd4 WB |
1114 | } |
1115 | ||
898eb71c | 1116 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1117 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1118 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1119 | chip->ctl_reg, chip->flag); |
1120 | ||
1121 | spi_set_ctldata(spi, chip); | |
1122 | ||
12e17c42 | 1123 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
d3cc71f7 | 1124 | if (chip->chip_select_num < MAX_CTRL_CS) { |
ac01e97d DM |
1125 | ret = peripheral_request(ssel[spi->master->bus_num] |
1126 | [chip->chip_select_num-1], spi->modalias); | |
1127 | if (ret) { | |
1128 | dev_err(&spi->dev, "peripheral_request() error\n"); | |
1129 | goto pin_error; | |
1130 | } | |
1131 | } | |
12e17c42 | 1132 | |
8221610e | 1133 | bfin_spi_cs_enable(drv_data, chip); |
138f97cd | 1134 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1135 | |
a5f6abd4 | 1136 | return 0; |
ac01e97d DM |
1137 | |
1138 | pin_error: | |
d3cc71f7 | 1139 | if (chip->chip_select_num >= MAX_CTRL_CS) |
ac01e97d DM |
1140 | gpio_free(chip->cs_gpio); |
1141 | else | |
1142 | peripheral_free(ssel[spi->master->bus_num] | |
1143 | [chip->chip_select_num - 1]); | |
1144 | error: | |
1145 | if (chip) { | |
1146 | if (drv_data->dma_requested) | |
1147 | free_dma(drv_data->dma_channel); | |
1148 | drv_data->dma_requested = 0; | |
1149 | ||
1150 | kfree(chip); | |
1151 | /* prevent free 'chip' twice */ | |
1152 | spi_set_ctldata(spi, NULL); | |
1153 | } | |
1154 | ||
1155 | return ret; | |
a5f6abd4 WB |
1156 | } |
1157 | ||
1158 | /* | |
1159 | * callback for spi framework. | |
1160 | * clean driver specific data | |
1161 | */ | |
138f97cd | 1162 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1163 | { |
b9f139a7 MF |
1164 | struct slave_data *chip = spi_get_ctldata(spi); |
1165 | struct master_data *drv_data = spi_master_get_devdata(spi->master); | |
a5f6abd4 | 1166 | |
e7d02e3c MF |
1167 | if (!chip) |
1168 | return; | |
1169 | ||
d3cc71f7 | 1170 | if (chip->chip_select_num < MAX_CTRL_CS) { |
12e17c42 SZ |
1171 | peripheral_free(ssel[spi->master->bus_num] |
1172 | [chip->chip_select_num-1]); | |
8221610e | 1173 | bfin_spi_cs_disable(drv_data, chip); |
d3cc71f7 | 1174 | } else |
42c78b2b MH |
1175 | gpio_free(chip->cs_gpio); |
1176 | ||
a5f6abd4 | 1177 | kfree(chip); |
ac01e97d DM |
1178 | /* prevent free 'chip' twice */ |
1179 | spi_set_ctldata(spi, NULL); | |
a5f6abd4 WB |
1180 | } |
1181 | ||
b9f139a7 | 1182 | static inline int bfin_spi_init_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1183 | { |
1184 | INIT_LIST_HEAD(&drv_data->queue); | |
1185 | spin_lock_init(&drv_data->lock); | |
1186 | ||
f4f50c3f | 1187 | drv_data->running = false; |
a5f6abd4 WB |
1188 | drv_data->busy = 0; |
1189 | ||
1190 | /* init transfer tasklet */ | |
1191 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1192 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1193 | |
1194 | /* init messages workqueue */ | |
138f97cd | 1195 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1196 | drv_data->workqueue = create_singlethread_workqueue( |
1197 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1198 | if (drv_data->workqueue == NULL) |
1199 | return -EBUSY; | |
1200 | ||
1201 | return 0; | |
1202 | } | |
1203 | ||
b9f139a7 | 1204 | static inline int bfin_spi_start_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1205 | { |
1206 | unsigned long flags; | |
1207 | ||
1208 | spin_lock_irqsave(&drv_data->lock, flags); | |
1209 | ||
f4f50c3f | 1210 | if (drv_data->running || drv_data->busy) { |
a5f6abd4 WB |
1211 | spin_unlock_irqrestore(&drv_data->lock, flags); |
1212 | return -EBUSY; | |
1213 | } | |
1214 | ||
f4f50c3f | 1215 | drv_data->running = true; |
a5f6abd4 WB |
1216 | drv_data->cur_msg = NULL; |
1217 | drv_data->cur_transfer = NULL; | |
1218 | drv_data->cur_chip = NULL; | |
1219 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1220 | ||
1221 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1222 | ||
1223 | return 0; | |
1224 | } | |
1225 | ||
b9f139a7 | 1226 | static inline int bfin_spi_stop_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1227 | { |
1228 | unsigned long flags; | |
1229 | unsigned limit = 500; | |
1230 | int status = 0; | |
1231 | ||
1232 | spin_lock_irqsave(&drv_data->lock, flags); | |
1233 | ||
1234 | /* | |
1235 | * This is a bit lame, but is optimized for the common execution path. | |
1236 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1237 | * execution path (pump_messages) would be required to call wake_up or | |
1238 | * friends on every SPI message. Do this instead | |
1239 | */ | |
f4f50c3f | 1240 | drv_data->running = false; |
a5f6abd4 WB |
1241 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { |
1242 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1243 | msleep(10); | |
1244 | spin_lock_irqsave(&drv_data->lock, flags); | |
1245 | } | |
1246 | ||
1247 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1248 | status = -EBUSY; | |
1249 | ||
1250 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1251 | ||
1252 | return status; | |
1253 | } | |
1254 | ||
b9f139a7 | 1255 | static inline int bfin_spi_destroy_queue(struct master_data *drv_data) |
a5f6abd4 WB |
1256 | { |
1257 | int status; | |
1258 | ||
138f97cd | 1259 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1260 | if (status != 0) |
1261 | return status; | |
1262 | ||
1263 | destroy_workqueue(drv_data->workqueue); | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
138f97cd | 1268 | static int __init bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1269 | { |
1270 | struct device *dev = &pdev->dev; | |
1271 | struct bfin5xx_spi_master *platform_info; | |
1272 | struct spi_master *master; | |
2a045131 | 1273 | struct master_data *drv_data; |
a32c691d | 1274 | struct resource *res; |
a5f6abd4 WB |
1275 | int status = 0; |
1276 | ||
1277 | platform_info = dev->platform_data; | |
1278 | ||
1279 | /* Allocate master with space for drv_data */ | |
2a045131 | 1280 | master = spi_alloc_master(dev, sizeof(*drv_data)); |
a5f6abd4 WB |
1281 | if (!master) { |
1282 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1283 | return -ENOMEM; | |
1284 | } | |
131b17d4 | 1285 | |
a5f6abd4 WB |
1286 | drv_data = spi_master_get_devdata(master); |
1287 | drv_data->master = master; | |
1288 | drv_data->master_info = platform_info; | |
1289 | drv_data->pdev = pdev; | |
003d9226 | 1290 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1291 | |
e7db06b5 DB |
1292 | /* the spi->mode bits supported by this driver: */ |
1293 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
1294 | ||
a5f6abd4 WB |
1295 | master->bus_num = pdev->id; |
1296 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1297 | master->cleanup = bfin_spi_cleanup; |
1298 | master->setup = bfin_spi_setup; | |
1299 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1300 | |
a32c691d BW |
1301 | /* Find and map our resources */ |
1302 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1303 | if (res == NULL) { | |
1304 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1305 | status = -ENOENT; | |
1306 | goto out_error_get_res; | |
1307 | } | |
1308 | ||
74947b89 | 1309 | drv_data->regs_base = ioremap(res->start, resource_size(res)); |
f452126c | 1310 | if (drv_data->regs_base == NULL) { |
a32c691d BW |
1311 | dev_err(dev, "Cannot map IO\n"); |
1312 | status = -ENXIO; | |
1313 | goto out_error_ioremap; | |
1314 | } | |
1315 | ||
f6a6d966 YL |
1316 | res = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
1317 | if (res == NULL) { | |
a32c691d BW |
1318 | dev_err(dev, "No DMA channel specified\n"); |
1319 | status = -ENOENT; | |
f6a6d966 YL |
1320 | goto out_error_free_io; |
1321 | } | |
1322 | drv_data->dma_channel = res->start; | |
1323 | ||
1324 | drv_data->spi_irq = platform_get_irq(pdev, 0); | |
1325 | if (drv_data->spi_irq < 0) { | |
1326 | dev_err(dev, "No spi pio irq specified\n"); | |
1327 | status = -ENOENT; | |
1328 | goto out_error_free_io; | |
a32c691d BW |
1329 | } |
1330 | ||
a5f6abd4 | 1331 | /* Initial and start queue */ |
138f97cd | 1332 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1333 | if (status != 0) { |
a32c691d | 1334 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1335 | goto out_error_queue_alloc; |
1336 | } | |
a32c691d | 1337 | |
138f97cd | 1338 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1339 | if (status != 0) { |
a32c691d | 1340 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1341 | goto out_error_queue_alloc; |
1342 | } | |
1343 | ||
f9e522ca VM |
1344 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1345 | if (status != 0) { | |
1346 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1347 | goto out_error_queue_alloc; | |
1348 | } | |
1349 | ||
bb8beecd WM |
1350 | /* Reset SPI registers. If these registers were used by the boot loader, |
1351 | * the sky may fall on your head if you enable the dma controller. | |
1352 | */ | |
1353 | write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER); | |
1354 | write_FLAG(drv_data, 0xFF00); | |
1355 | ||
a5f6abd4 WB |
1356 | /* Register with the SPI framework */ |
1357 | platform_set_drvdata(pdev, drv_data); | |
1358 | status = spi_register_master(master); | |
1359 | if (status != 0) { | |
a32c691d | 1360 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1361 | goto out_error_queue_alloc; |
1362 | } | |
a32c691d | 1363 | |
f452126c | 1364 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1365 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1366 | drv_data->dma_channel); | |
a5f6abd4 WB |
1367 | return status; |
1368 | ||
cc2f81a6 | 1369 | out_error_queue_alloc: |
138f97cd | 1370 | bfin_spi_destroy_queue(drv_data); |
f6a6d966 | 1371 | out_error_free_io: |
bb90eb00 | 1372 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1373 | out_error_ioremap: |
1374 | out_error_get_res: | |
a5f6abd4 | 1375 | spi_master_put(master); |
cc2f81a6 | 1376 | |
a5f6abd4 WB |
1377 | return status; |
1378 | } | |
1379 | ||
1380 | /* stop hardware and remove the driver */ | |
138f97cd | 1381 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 | 1382 | { |
b9f139a7 | 1383 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1384 | int status = 0; |
1385 | ||
1386 | if (!drv_data) | |
1387 | return 0; | |
1388 | ||
1389 | /* Remove the queue */ | |
138f97cd | 1390 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1391 | if (status != 0) |
1392 | return status; | |
1393 | ||
1394 | /* Disable the SSP at the peripheral and SOC level */ | |
1395 | bfin_spi_disable(drv_data); | |
1396 | ||
1397 | /* Release DMA */ | |
1398 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1399 | if (dma_channel_active(drv_data->dma_channel)) |
1400 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1401 | } |
1402 | ||
f6a6d966 YL |
1403 | if (drv_data->irq_requested) { |
1404 | free_irq(drv_data->spi_irq, drv_data); | |
1405 | drv_data->irq_requested = 0; | |
1406 | } | |
1407 | ||
a5f6abd4 WB |
1408 | /* Disconnect from the SPI framework */ |
1409 | spi_unregister_master(drv_data->master); | |
1410 | ||
003d9226 | 1411 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1412 | |
a5f6abd4 WB |
1413 | /* Prevent double remove */ |
1414 | platform_set_drvdata(pdev, NULL); | |
1415 | ||
1416 | return 0; | |
1417 | } | |
1418 | ||
1419 | #ifdef CONFIG_PM | |
138f97cd | 1420 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 | 1421 | { |
b9f139a7 | 1422 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1423 | int status = 0; |
1424 | ||
138f97cd | 1425 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1426 | if (status != 0) |
1427 | return status; | |
1428 | ||
1429 | /* stop hardware */ | |
1430 | bfin_spi_disable(drv_data); | |
1431 | ||
1432 | return 0; | |
1433 | } | |
1434 | ||
138f97cd | 1435 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 | 1436 | { |
b9f139a7 | 1437 | struct master_data *drv_data = platform_get_drvdata(pdev); |
a5f6abd4 WB |
1438 | int status = 0; |
1439 | ||
1440 | /* Enable the SPI interface */ | |
1441 | bfin_spi_enable(drv_data); | |
1442 | ||
1443 | /* Start the queue running */ | |
138f97cd | 1444 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1445 | if (status != 0) { |
1446 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1447 | return status; | |
1448 | } | |
1449 | ||
1450 | return 0; | |
1451 | } | |
1452 | #else | |
138f97cd MF |
1453 | #define bfin_spi_suspend NULL |
1454 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1455 | #endif /* CONFIG_PM */ |
1456 | ||
7e38c3c4 | 1457 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1458 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1459 | .driver = { |
a32c691d | 1460 | .name = DRV_NAME, |
88b40369 BW |
1461 | .owner = THIS_MODULE, |
1462 | }, | |
138f97cd MF |
1463 | .suspend = bfin_spi_suspend, |
1464 | .resume = bfin_spi_resume, | |
1465 | .remove = __devexit_p(bfin_spi_remove), | |
a5f6abd4 WB |
1466 | }; |
1467 | ||
138f97cd | 1468 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1469 | { |
138f97cd | 1470 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1471 | } |
138f97cd | 1472 | module_init(bfin_spi_init); |
a5f6abd4 | 1473 | |
138f97cd | 1474 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1475 | { |
138f97cd | 1476 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1477 | } |
138f97cd | 1478 | module_exit(bfin_spi_exit); |