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a5f6abd4 WB |
1 | /* |
2 | * File: drivers/spi/bfin5xx_spi.c | |
3 | * Based on: N/A | |
4 | * Author: Luke Yang (Analog Devices Inc.) | |
5 | * | |
6 | * Created: March. 10th 2006 | |
7 | * Description: SPI controller driver for Blackfin 5xx | |
8 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | |
9 | * | |
10 | * Modified: | |
11 | * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang) | |
12 | * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang) | |
13 | * | |
14 | * Copyright 2004-2006 Analog Devices Inc. | |
15 | * | |
16 | * This program is free software ; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License as published by | |
18 | * the Free Software Foundation ; either version 2, or (at your option) | |
19 | * any later version. | |
20 | * | |
21 | * This program is distributed in the hope that it will be useful, | |
22 | * but WITHOUT ANY WARRANTY ; without even the implied warranty of | |
23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
24 | * GNU General Public License for more details. | |
25 | * | |
26 | * You should have received a copy of the GNU General Public License | |
27 | * along with this program ; see the file COPYING. | |
28 | * If not, write to the Free Software Foundation, | |
29 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
30 | */ | |
31 | ||
32 | #include <linux/init.h> | |
33 | #include <linux/module.h> | |
34 | #include <linux/device.h> | |
35 | #include <linux/ioport.h> | |
36 | #include <linux/errno.h> | |
37 | #include <linux/interrupt.h> | |
38 | #include <linux/platform_device.h> | |
39 | #include <linux/dma-mapping.h> | |
40 | #include <linux/spi/spi.h> | |
41 | #include <linux/workqueue.h> | |
42 | #include <linux/errno.h> | |
43 | #include <linux/delay.h> | |
44 | ||
45 | #include <asm/io.h> | |
46 | #include <asm/irq.h> | |
47 | #include <asm/delay.h> | |
48 | #include <asm/dma.h> | |
49 | ||
50 | #include <asm/bfin5xx_spi.h> | |
51 | ||
52 | MODULE_AUTHOR("Luke Yang"); | |
53 | MODULE_DESCRIPTION("Blackfin 5xx SPI Contoller"); | |
54 | MODULE_LICENSE("GPL"); | |
55 | ||
56 | #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0) | |
57 | ||
58 | #define DEFINE_SPI_REG(reg, off) \ | |
59 | static inline u16 read_##reg(void) \ | |
60 | { return *(volatile unsigned short*)(SPI0_REGBASE + off); } \ | |
61 | static inline void write_##reg(u16 v) \ | |
62 | {*(volatile unsigned short*)(SPI0_REGBASE + off) = v;\ | |
63 | SSYNC();} | |
64 | ||
65 | DEFINE_SPI_REG(CTRL, 0x00) | |
66 | DEFINE_SPI_REG(FLAG, 0x04) | |
67 | DEFINE_SPI_REG(STAT, 0x08) | |
68 | DEFINE_SPI_REG(TDBR, 0x0C) | |
69 | DEFINE_SPI_REG(RDBR, 0x10) | |
70 | DEFINE_SPI_REG(BAUD, 0x14) | |
71 | DEFINE_SPI_REG(SHAW, 0x18) | |
72 | #define START_STATE ((void*)0) | |
73 | #define RUNNING_STATE ((void*)1) | |
74 | #define DONE_STATE ((void*)2) | |
75 | #define ERROR_STATE ((void*)-1) | |
76 | #define QUEUE_RUNNING 0 | |
77 | #define QUEUE_STOPPED 1 | |
78 | int dma_requested; | |
79 | ||
80 | struct driver_data { | |
81 | /* Driver model hookup */ | |
82 | struct platform_device *pdev; | |
83 | ||
84 | /* SPI framework hookup */ | |
85 | struct spi_master *master; | |
86 | ||
87 | /* BFIN hookup */ | |
88 | struct bfin5xx_spi_master *master_info; | |
89 | ||
90 | /* Driver message queue */ | |
91 | struct workqueue_struct *workqueue; | |
92 | struct work_struct pump_messages; | |
93 | spinlock_t lock; | |
94 | struct list_head queue; | |
95 | int busy; | |
96 | int run; | |
97 | ||
98 | /* Message Transfer pump */ | |
99 | struct tasklet_struct pump_transfers; | |
100 | ||
101 | /* Current message transfer state info */ | |
102 | struct spi_message *cur_msg; | |
103 | struct spi_transfer *cur_transfer; | |
104 | struct chip_data *cur_chip; | |
105 | size_t len_in_bytes; | |
106 | size_t len; | |
107 | void *tx; | |
108 | void *tx_end; | |
109 | void *rx; | |
110 | void *rx_end; | |
111 | int dma_mapped; | |
112 | dma_addr_t rx_dma; | |
113 | dma_addr_t tx_dma; | |
114 | size_t rx_map_len; | |
115 | size_t tx_map_len; | |
116 | u8 n_bytes; | |
117 | void (*write) (struct driver_data *); | |
118 | void (*read) (struct driver_data *); | |
119 | void (*duplex) (struct driver_data *); | |
120 | }; | |
121 | ||
122 | struct chip_data { | |
123 | u16 ctl_reg; | |
124 | u16 baud; | |
125 | u16 flag; | |
126 | ||
127 | u8 chip_select_num; | |
128 | u8 n_bytes; | |
88b40369 | 129 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
130 | u8 enable_dma; |
131 | u8 bits_per_word; /* 8 or 16 */ | |
132 | u8 cs_change_per_word; | |
133 | u8 cs_chg_udelay; | |
134 | void (*write) (struct driver_data *); | |
135 | void (*read) (struct driver_data *); | |
136 | void (*duplex) (struct driver_data *); | |
137 | }; | |
138 | ||
88b40369 | 139 | static void bfin_spi_enable(struct driver_data *drv_data) |
a5f6abd4 WB |
140 | { |
141 | u16 cr; | |
142 | ||
143 | cr = read_CTRL(); | |
144 | write_CTRL(cr | BIT_CTL_ENABLE); | |
145 | SSYNC(); | |
146 | } | |
147 | ||
88b40369 | 148 | static void bfin_spi_disable(struct driver_data *drv_data) |
a5f6abd4 WB |
149 | { |
150 | u16 cr; | |
151 | ||
152 | cr = read_CTRL(); | |
153 | write_CTRL(cr & (~BIT_CTL_ENABLE)); | |
154 | SSYNC(); | |
155 | } | |
156 | ||
157 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
158 | static u16 hz_to_spi_baud(u32 speed_hz) | |
159 | { | |
160 | u_long sclk = get_sclk(); | |
161 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
162 | ||
163 | if ((sclk % (2 * speed_hz)) > 0) | |
164 | spi_baud++; | |
165 | ||
a5f6abd4 WB |
166 | return spi_baud; |
167 | } | |
168 | ||
169 | static int flush(struct driver_data *drv_data) | |
170 | { | |
171 | unsigned long limit = loops_per_jiffy << 1; | |
172 | ||
173 | /* wait for stop and clear stat */ | |
174 | while (!(read_STAT() & BIT_STAT_SPIF) && limit--) | |
175 | continue; | |
176 | ||
177 | write_STAT(BIT_STAT_CLR); | |
178 | ||
179 | return limit; | |
180 | } | |
181 | ||
182 | /* stop controller and re-config current chip*/ | |
183 | static void restore_state(struct driver_data *drv_data) | |
184 | { | |
185 | struct chip_data *chip = drv_data->cur_chip; | |
186 | ||
187 | /* Clear status and disable clock */ | |
188 | write_STAT(BIT_STAT_CLR); | |
189 | bfin_spi_disable(drv_data); | |
88b40369 | 190 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 WB |
191 | |
192 | #if defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) | |
88b40369 BW |
193 | dev_dbg(&drv_data->pdev->dev, |
194 | "chip select number is %d\n", chip->chip_select_num); | |
195 | ||
a5f6abd4 WB |
196 | switch (chip->chip_select_num) { |
197 | case 1: | |
198 | bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3c00); | |
199 | SSYNC(); | |
200 | break; | |
201 | ||
202 | case 2: | |
203 | case 3: | |
204 | bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJSE_SPI); | |
205 | SSYNC(); | |
206 | bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800); | |
207 | SSYNC(); | |
208 | break; | |
209 | ||
210 | case 4: | |
211 | bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS4E_SPI); | |
212 | SSYNC(); | |
213 | bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3840); | |
214 | SSYNC(); | |
215 | break; | |
216 | ||
217 | case 5: | |
218 | bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS5E_SPI); | |
219 | SSYNC(); | |
220 | bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3820); | |
221 | SSYNC(); | |
222 | break; | |
223 | ||
224 | case 6: | |
225 | bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PFS6E_SPI); | |
226 | SSYNC(); | |
227 | bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3810); | |
228 | SSYNC(); | |
229 | break; | |
230 | ||
231 | case 7: | |
232 | bfin_write_PORT_MUX(bfin_read_PORT_MUX() | PJCE_SPI); | |
233 | SSYNC(); | |
234 | bfin_write_PORTF_FER(bfin_read_PORTF_FER() | 0x3800); | |
235 | SSYNC(); | |
236 | break; | |
237 | } | |
238 | #endif | |
239 | ||
240 | /* Load the registers */ | |
241 | write_CTRL(chip->ctl_reg); | |
242 | write_BAUD(chip->baud); | |
243 | write_FLAG(chip->flag); | |
244 | } | |
245 | ||
246 | /* used to kick off transfer in rx mode */ | |
247 | static unsigned short dummy_read(void) | |
248 | { | |
249 | unsigned short tmp; | |
250 | tmp = read_RDBR(); | |
251 | return tmp; | |
252 | } | |
253 | ||
254 | static void null_writer(struct driver_data *drv_data) | |
255 | { | |
256 | u8 n_bytes = drv_data->n_bytes; | |
257 | ||
258 | while (drv_data->tx < drv_data->tx_end) { | |
259 | write_TDBR(0); | |
260 | while ((read_STAT() & BIT_STAT_TXS)) | |
261 | continue; | |
262 | drv_data->tx += n_bytes; | |
263 | } | |
264 | } | |
265 | ||
266 | static void null_reader(struct driver_data *drv_data) | |
267 | { | |
268 | u8 n_bytes = drv_data->n_bytes; | |
269 | dummy_read(); | |
270 | ||
271 | while (drv_data->rx < drv_data->rx_end) { | |
272 | while (!(read_STAT() & BIT_STAT_RXS)) | |
273 | continue; | |
274 | dummy_read(); | |
275 | drv_data->rx += n_bytes; | |
276 | } | |
277 | } | |
278 | ||
279 | static void u8_writer(struct driver_data *drv_data) | |
280 | { | |
88b40369 BW |
281 | dev_dbg(&drv_data->pdev->dev, |
282 | "cr8-s is 0x%x\n", read_STAT()); | |
a5f6abd4 WB |
283 | while (drv_data->tx < drv_data->tx_end) { |
284 | write_TDBR(*(u8 *) (drv_data->tx)); | |
285 | while (read_STAT() & BIT_STAT_TXS) | |
286 | continue; | |
287 | ++drv_data->tx; | |
288 | } | |
289 | ||
290 | /* poll for SPI completion before returning */ | |
291 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
292 | continue; | |
293 | } | |
294 | ||
295 | static void u8_cs_chg_writer(struct driver_data *drv_data) | |
296 | { | |
297 | struct chip_data *chip = drv_data->cur_chip; | |
298 | ||
299 | while (drv_data->tx < drv_data->tx_end) { | |
300 | write_FLAG(chip->flag); | |
301 | SSYNC(); | |
302 | ||
303 | write_TDBR(*(u8 *) (drv_data->tx)); | |
304 | while (read_STAT() & BIT_STAT_TXS) | |
305 | continue; | |
306 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
307 | continue; | |
308 | write_FLAG(0xFF00 | chip->flag); | |
309 | SSYNC(); | |
310 | if (chip->cs_chg_udelay) | |
311 | udelay(chip->cs_chg_udelay); | |
312 | ++drv_data->tx; | |
313 | } | |
314 | write_FLAG(0xFF00); | |
315 | SSYNC(); | |
316 | } | |
317 | ||
318 | static void u8_reader(struct driver_data *drv_data) | |
319 | { | |
88b40369 BW |
320 | dev_dbg(&drv_data->pdev->dev, |
321 | "cr-8 is 0x%x\n", read_STAT()); | |
a5f6abd4 WB |
322 | |
323 | /* clear TDBR buffer before read(else it will be shifted out) */ | |
324 | write_TDBR(0xFFFF); | |
325 | ||
326 | dummy_read(); | |
327 | ||
328 | while (drv_data->rx < drv_data->rx_end - 1) { | |
329 | while (!(read_STAT() & BIT_STAT_RXS)) | |
330 | continue; | |
331 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
332 | ++drv_data->rx; | |
333 | } | |
334 | ||
335 | while (!(read_STAT() & BIT_STAT_RXS)) | |
336 | continue; | |
337 | *(u8 *) (drv_data->rx) = read_SHAW(); | |
338 | ++drv_data->rx; | |
339 | } | |
340 | ||
341 | static void u8_cs_chg_reader(struct driver_data *drv_data) | |
342 | { | |
343 | struct chip_data *chip = drv_data->cur_chip; | |
344 | ||
345 | while (drv_data->rx < drv_data->rx_end) { | |
346 | write_FLAG(chip->flag); | |
347 | SSYNC(); | |
348 | ||
349 | read_RDBR(); /* kick off */ | |
350 | while (!(read_STAT() & BIT_STAT_RXS)) | |
351 | continue; | |
352 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
353 | continue; | |
354 | *(u8 *) (drv_data->rx) = read_SHAW(); | |
355 | write_FLAG(0xFF00 | chip->flag); | |
356 | SSYNC(); | |
357 | if (chip->cs_chg_udelay) | |
358 | udelay(chip->cs_chg_udelay); | |
359 | ++drv_data->rx; | |
360 | } | |
361 | write_FLAG(0xFF00); | |
362 | SSYNC(); | |
363 | } | |
364 | ||
365 | static void u8_duplex(struct driver_data *drv_data) | |
366 | { | |
367 | /* in duplex mode, clk is triggered by writing of TDBR */ | |
368 | while (drv_data->rx < drv_data->rx_end) { | |
369 | write_TDBR(*(u8 *) (drv_data->tx)); | |
370 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
371 | continue; | |
372 | while (!(read_STAT() & BIT_STAT_RXS)) | |
373 | continue; | |
374 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
375 | ++drv_data->rx; | |
376 | ++drv_data->tx; | |
377 | } | |
378 | } | |
379 | ||
380 | static void u8_cs_chg_duplex(struct driver_data *drv_data) | |
381 | { | |
382 | struct chip_data *chip = drv_data->cur_chip; | |
383 | ||
384 | while (drv_data->rx < drv_data->rx_end) { | |
385 | write_FLAG(chip->flag); | |
386 | SSYNC(); | |
387 | ||
388 | write_TDBR(*(u8 *) (drv_data->tx)); | |
389 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
390 | continue; | |
391 | while (!(read_STAT() & BIT_STAT_RXS)) | |
392 | continue; | |
393 | *(u8 *) (drv_data->rx) = read_RDBR(); | |
394 | write_FLAG(0xFF00 | chip->flag); | |
395 | SSYNC(); | |
396 | if (chip->cs_chg_udelay) | |
397 | udelay(chip->cs_chg_udelay); | |
398 | ++drv_data->rx; | |
399 | ++drv_data->tx; | |
400 | } | |
401 | write_FLAG(0xFF00); | |
402 | SSYNC(); | |
403 | } | |
404 | ||
405 | static void u16_writer(struct driver_data *drv_data) | |
406 | { | |
88b40369 BW |
407 | dev_dbg(&drv_data->pdev->dev, |
408 | "cr16 is 0x%x\n", read_STAT()); | |
409 | ||
a5f6abd4 WB |
410 | while (drv_data->tx < drv_data->tx_end) { |
411 | write_TDBR(*(u16 *) (drv_data->tx)); | |
412 | while ((read_STAT() & BIT_STAT_TXS)) | |
413 | continue; | |
414 | drv_data->tx += 2; | |
415 | } | |
416 | ||
417 | /* poll for SPI completion before returning */ | |
418 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
419 | continue; | |
420 | } | |
421 | ||
422 | static void u16_cs_chg_writer(struct driver_data *drv_data) | |
423 | { | |
424 | struct chip_data *chip = drv_data->cur_chip; | |
425 | ||
426 | while (drv_data->tx < drv_data->tx_end) { | |
427 | write_FLAG(chip->flag); | |
428 | SSYNC(); | |
429 | ||
430 | write_TDBR(*(u16 *) (drv_data->tx)); | |
431 | while ((read_STAT() & BIT_STAT_TXS)) | |
432 | continue; | |
433 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
434 | continue; | |
435 | write_FLAG(0xFF00 | chip->flag); | |
436 | SSYNC(); | |
437 | if (chip->cs_chg_udelay) | |
438 | udelay(chip->cs_chg_udelay); | |
439 | drv_data->tx += 2; | |
440 | } | |
441 | write_FLAG(0xFF00); | |
442 | SSYNC(); | |
443 | } | |
444 | ||
445 | static void u16_reader(struct driver_data *drv_data) | |
446 | { | |
88b40369 BW |
447 | dev_dbg(&drv_data->pdev->dev, |
448 | "cr-16 is 0x%x\n", read_STAT()); | |
a5f6abd4 WB |
449 | dummy_read(); |
450 | ||
451 | while (drv_data->rx < (drv_data->rx_end - 2)) { | |
452 | while (!(read_STAT() & BIT_STAT_RXS)) | |
453 | continue; | |
454 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
455 | drv_data->rx += 2; | |
456 | } | |
457 | ||
458 | while (!(read_STAT() & BIT_STAT_RXS)) | |
459 | continue; | |
460 | *(u16 *) (drv_data->rx) = read_SHAW(); | |
461 | drv_data->rx += 2; | |
462 | } | |
463 | ||
464 | static void u16_cs_chg_reader(struct driver_data *drv_data) | |
465 | { | |
466 | struct chip_data *chip = drv_data->cur_chip; | |
467 | ||
468 | while (drv_data->rx < drv_data->rx_end) { | |
469 | write_FLAG(chip->flag); | |
470 | SSYNC(); | |
471 | ||
472 | read_RDBR(); /* kick off */ | |
473 | while (!(read_STAT() & BIT_STAT_RXS)) | |
474 | continue; | |
475 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
476 | continue; | |
477 | *(u16 *) (drv_data->rx) = read_SHAW(); | |
478 | write_FLAG(0xFF00 | chip->flag); | |
479 | SSYNC(); | |
480 | if (chip->cs_chg_udelay) | |
481 | udelay(chip->cs_chg_udelay); | |
482 | drv_data->rx += 2; | |
483 | } | |
484 | write_FLAG(0xFF00); | |
485 | SSYNC(); | |
486 | } | |
487 | ||
488 | static void u16_duplex(struct driver_data *drv_data) | |
489 | { | |
490 | /* in duplex mode, clk is triggered by writing of TDBR */ | |
491 | while (drv_data->tx < drv_data->tx_end) { | |
492 | write_TDBR(*(u16 *) (drv_data->tx)); | |
493 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
494 | continue; | |
495 | while (!(read_STAT() & BIT_STAT_RXS)) | |
496 | continue; | |
497 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
498 | drv_data->rx += 2; | |
499 | drv_data->tx += 2; | |
500 | } | |
501 | } | |
502 | ||
503 | static void u16_cs_chg_duplex(struct driver_data *drv_data) | |
504 | { | |
505 | struct chip_data *chip = drv_data->cur_chip; | |
506 | ||
507 | while (drv_data->tx < drv_data->tx_end) { | |
508 | write_FLAG(chip->flag); | |
509 | SSYNC(); | |
510 | ||
511 | write_TDBR(*(u16 *) (drv_data->tx)); | |
512 | while (!(read_STAT() & BIT_STAT_SPIF)) | |
513 | continue; | |
514 | while (!(read_STAT() & BIT_STAT_RXS)) | |
515 | continue; | |
516 | *(u16 *) (drv_data->rx) = read_RDBR(); | |
517 | write_FLAG(0xFF00 | chip->flag); | |
518 | SSYNC(); | |
519 | if (chip->cs_chg_udelay) | |
520 | udelay(chip->cs_chg_udelay); | |
521 | drv_data->rx += 2; | |
522 | drv_data->tx += 2; | |
523 | } | |
524 | write_FLAG(0xFF00); | |
525 | SSYNC(); | |
526 | } | |
527 | ||
528 | /* test if ther is more transfer to be done */ | |
529 | static void *next_transfer(struct driver_data *drv_data) | |
530 | { | |
531 | struct spi_message *msg = drv_data->cur_msg; | |
532 | struct spi_transfer *trans = drv_data->cur_transfer; | |
533 | ||
534 | /* Move to next transfer */ | |
535 | if (trans->transfer_list.next != &msg->transfers) { | |
536 | drv_data->cur_transfer = | |
537 | list_entry(trans->transfer_list.next, | |
538 | struct spi_transfer, transfer_list); | |
539 | return RUNNING_STATE; | |
540 | } else | |
541 | return DONE_STATE; | |
542 | } | |
543 | ||
544 | /* | |
545 | * caller already set message->status; | |
546 | * dma and pio irqs are blocked give finished message back | |
547 | */ | |
548 | static void giveback(struct driver_data *drv_data) | |
549 | { | |
550 | struct spi_transfer *last_transfer; | |
551 | unsigned long flags; | |
552 | struct spi_message *msg; | |
553 | ||
554 | spin_lock_irqsave(&drv_data->lock, flags); | |
555 | msg = drv_data->cur_msg; | |
556 | drv_data->cur_msg = NULL; | |
557 | drv_data->cur_transfer = NULL; | |
558 | drv_data->cur_chip = NULL; | |
559 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
560 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
561 | ||
562 | last_transfer = list_entry(msg->transfers.prev, | |
563 | struct spi_transfer, transfer_list); | |
564 | ||
565 | msg->state = NULL; | |
566 | ||
567 | /* disable chip select signal. And not stop spi in autobuffer mode */ | |
568 | if (drv_data->tx_dma != 0xFFFF) { | |
569 | write_FLAG(0xFF00); | |
570 | bfin_spi_disable(drv_data); | |
571 | } | |
572 | ||
573 | if (msg->complete) | |
574 | msg->complete(msg->context); | |
575 | } | |
576 | ||
88b40369 | 577 | static irqreturn_t dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 WB |
578 | { |
579 | struct driver_data *drv_data = (struct driver_data *)dev_id; | |
580 | struct spi_message *msg = drv_data->cur_msg; | |
581 | ||
88b40369 | 582 | dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n"); |
a5f6abd4 WB |
583 | clear_dma_irqstat(CH_SPI); |
584 | ||
d6fe89b0 BW |
585 | /* Wait for DMA to complete */ |
586 | while (get_dma_curr_irqstat(CH_SPI) & DMA_RUN) | |
587 | continue; | |
588 | ||
a5f6abd4 | 589 | /* |
d6fe89b0 BW |
590 | * wait for the last transaction shifted out. HRM states: |
591 | * at this point there may still be data in the SPI DMA FIFO waiting | |
592 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
593 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
594 | */ |
595 | if (drv_data->tx != NULL) { | |
d6fe89b0 BW |
596 | while ((bfin_read_SPI_STAT() & TXS) || |
597 | (bfin_read_SPI_STAT() & TXS)) | |
a5f6abd4 WB |
598 | continue; |
599 | } | |
600 | ||
601 | while (!(bfin_read_SPI_STAT() & SPIF)) | |
602 | continue; | |
603 | ||
604 | bfin_spi_disable(drv_data); | |
605 | ||
606 | msg->actual_length += drv_data->len_in_bytes; | |
607 | ||
608 | /* Move to next transfer */ | |
609 | msg->state = next_transfer(drv_data); | |
610 | ||
611 | /* Schedule transfer tasklet */ | |
612 | tasklet_schedule(&drv_data->pump_transfers); | |
613 | ||
614 | /* free the irq handler before next transfer */ | |
88b40369 BW |
615 | dev_dbg(&drv_data->pdev->dev, |
616 | "disable dma channel irq%d\n", | |
617 | CH_SPI); | |
a5f6abd4 WB |
618 | dma_disable_irq(CH_SPI); |
619 | ||
620 | return IRQ_HANDLED; | |
621 | } | |
622 | ||
623 | static void pump_transfers(unsigned long data) | |
624 | { | |
625 | struct driver_data *drv_data = (struct driver_data *)data; | |
626 | struct spi_message *message = NULL; | |
627 | struct spi_transfer *transfer = NULL; | |
628 | struct spi_transfer *previous = NULL; | |
629 | struct chip_data *chip = NULL; | |
88b40369 BW |
630 | u8 width; |
631 | u16 cr, dma_width, dma_config; | |
a5f6abd4 WB |
632 | u32 tranf_success = 1; |
633 | ||
634 | /* Get current state information */ | |
635 | message = drv_data->cur_msg; | |
636 | transfer = drv_data->cur_transfer; | |
637 | chip = drv_data->cur_chip; | |
638 | ||
639 | /* | |
640 | * if msg is error or done, report it back using complete() callback | |
641 | */ | |
642 | ||
643 | /* Handle for abort */ | |
644 | if (message->state == ERROR_STATE) { | |
645 | message->status = -EIO; | |
646 | giveback(drv_data); | |
647 | return; | |
648 | } | |
649 | ||
650 | /* Handle end of message */ | |
651 | if (message->state == DONE_STATE) { | |
652 | message->status = 0; | |
653 | giveback(drv_data); | |
654 | return; | |
655 | } | |
656 | ||
657 | /* Delay if requested at end of transfer */ | |
658 | if (message->state == RUNNING_STATE) { | |
659 | previous = list_entry(transfer->transfer_list.prev, | |
660 | struct spi_transfer, transfer_list); | |
661 | if (previous->delay_usecs) | |
662 | udelay(previous->delay_usecs); | |
663 | } | |
664 | ||
665 | /* Setup the transfer state based on the type of transfer */ | |
666 | if (flush(drv_data) == 0) { | |
667 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); | |
668 | message->status = -EIO; | |
669 | giveback(drv_data); | |
670 | return; | |
671 | } | |
672 | ||
673 | if (transfer->tx_buf != NULL) { | |
674 | drv_data->tx = (void *)transfer->tx_buf; | |
675 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
676 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
677 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
678 | } else { |
679 | drv_data->tx = NULL; | |
680 | } | |
681 | ||
682 | if (transfer->rx_buf != NULL) { | |
683 | drv_data->rx = transfer->rx_buf; | |
684 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
685 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
686 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
687 | } else { |
688 | drv_data->rx = NULL; | |
689 | } | |
690 | ||
691 | drv_data->rx_dma = transfer->rx_dma; | |
692 | drv_data->tx_dma = transfer->tx_dma; | |
693 | drv_data->len_in_bytes = transfer->len; | |
694 | ||
695 | width = chip->width; | |
696 | if (width == CFG_SPI_WORDSIZE16) { | |
697 | drv_data->len = (transfer->len) >> 1; | |
698 | } else { | |
699 | drv_data->len = transfer->len; | |
700 | } | |
701 | drv_data->write = drv_data->tx ? chip->write : null_writer; | |
702 | drv_data->read = drv_data->rx ? chip->read : null_reader; | |
703 | drv_data->duplex = chip->duplex ? chip->duplex : null_writer; | |
88b40369 BW |
704 | dev_dbg(&drv_data->pdev->dev, |
705 | "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n", | |
706 | drv_data->write, chip->write, null_writer); | |
a5f6abd4 WB |
707 | |
708 | /* speed and width has been set on per message */ | |
709 | message->state = RUNNING_STATE; | |
710 | dma_config = 0; | |
711 | ||
712 | /* restore spi status for each spi transfer */ | |
713 | if (transfer->speed_hz) { | |
714 | write_BAUD(hz_to_spi_baud(transfer->speed_hz)); | |
715 | } else { | |
716 | write_BAUD(chip->baud); | |
717 | } | |
718 | write_FLAG(chip->flag); | |
719 | ||
88b40369 BW |
720 | dev_dbg(&drv_data->pdev->dev, |
721 | "now pumping a transfer: width is %d, len is %d\n", | |
722 | width, transfer->len); | |
a5f6abd4 WB |
723 | |
724 | /* | |
725 | * Try to map dma buffer and do a dma transfer if | |
726 | * successful use different way to r/w according to | |
727 | * drv_data->cur_chip->enable_dma | |
728 | */ | |
729 | if (drv_data->cur_chip->enable_dma && drv_data->len > 6) { | |
730 | ||
731 | write_STAT(BIT_STAT_CLR); | |
732 | disable_dma(CH_SPI); | |
733 | clear_dma_irqstat(CH_SPI); | |
734 | bfin_spi_disable(drv_data); | |
735 | ||
736 | /* config dma channel */ | |
88b40369 | 737 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
a5f6abd4 WB |
738 | if (width == CFG_SPI_WORDSIZE16) { |
739 | set_dma_x_count(CH_SPI, drv_data->len); | |
740 | set_dma_x_modify(CH_SPI, 2); | |
741 | dma_width = WDSIZE_16; | |
742 | } else { | |
743 | set_dma_x_count(CH_SPI, drv_data->len); | |
744 | set_dma_x_modify(CH_SPI, 1); | |
745 | dma_width = WDSIZE_8; | |
746 | } | |
747 | ||
748 | /* set transfer width,direction. And enable spi */ | |
749 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); | |
750 | ||
751 | /* dirty hack for autobuffer DMA mode */ | |
752 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
753 | dev_dbg(&drv_data->pdev->dev, |
754 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
755 | |
756 | /* no irq in autobuffer mode */ | |
757 | dma_config = | |
758 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
759 | set_dma_config(CH_SPI, dma_config); | |
760 | set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx); | |
761 | enable_dma(CH_SPI); | |
762 | write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) | | |
763 | (CFG_SPI_ENABLE << 14)); | |
764 | ||
765 | /* just return here, there can only be one transfer in this mode */ | |
766 | message->status = 0; | |
767 | giveback(drv_data); | |
768 | return; | |
769 | } | |
770 | ||
771 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
772 | if (drv_data->rx != NULL) { | |
773 | /* set transfer mode, and enable SPI */ | |
88b40369 | 774 | dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n"); |
a5f6abd4 WB |
775 | |
776 | /* disable SPI before write to TDBR */ | |
777 | write_CTRL(cr & ~BIT_CTL_ENABLE); | |
778 | ||
779 | /* clear tx reg soformer data is not shifted out */ | |
780 | write_TDBR(0xFF); | |
781 | ||
782 | set_dma_x_count(CH_SPI, drv_data->len); | |
783 | ||
784 | /* start dma */ | |
785 | dma_enable_irq(CH_SPI); | |
786 | dma_config = (WNR | RESTART | dma_width | DI_EN); | |
787 | set_dma_config(CH_SPI, dma_config); | |
788 | set_dma_start_addr(CH_SPI, (unsigned long)drv_data->rx); | |
789 | enable_dma(CH_SPI); | |
790 | ||
791 | cr |= | |
792 | CFG_SPI_DMAREAD | (width << 8) | (CFG_SPI_ENABLE << | |
793 | 14); | |
794 | /* set transfer mode, and enable SPI */ | |
795 | write_CTRL(cr); | |
796 | } else if (drv_data->tx != NULL) { | |
88b40369 | 797 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 WB |
798 | |
799 | /* start dma */ | |
800 | dma_enable_irq(CH_SPI); | |
801 | dma_config = (RESTART | dma_width | DI_EN); | |
802 | set_dma_config(CH_SPI, dma_config); | |
803 | set_dma_start_addr(CH_SPI, (unsigned long)drv_data->tx); | |
804 | enable_dma(CH_SPI); | |
805 | ||
806 | write_CTRL(cr | CFG_SPI_DMAWRITE | (width << 8) | | |
807 | (CFG_SPI_ENABLE << 14)); | |
808 | ||
809 | } | |
810 | } else { | |
811 | /* IO mode write then read */ | |
88b40369 | 812 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
a5f6abd4 WB |
813 | |
814 | write_STAT(BIT_STAT_CLR); | |
815 | ||
816 | if (drv_data->tx != NULL && drv_data->rx != NULL) { | |
817 | /* full duplex mode */ | |
818 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
819 | (drv_data->rx_end - drv_data->rx)); | |
88b40369 BW |
820 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); |
821 | cr |= CFG_SPI_WRITE | (width << 8) | | |
822 | (CFG_SPI_ENABLE << 14); | |
823 | dev_dbg(&drv_data->pdev->dev, | |
824 | "IO duplex: cr is 0x%x\n", cr); | |
a5f6abd4 WB |
825 | |
826 | write_CTRL(cr); | |
827 | SSYNC(); | |
828 | ||
829 | drv_data->duplex(drv_data); | |
830 | ||
831 | if (drv_data->tx != drv_data->tx_end) | |
832 | tranf_success = 0; | |
833 | } else if (drv_data->tx != NULL) { | |
834 | /* write only half duplex */ | |
88b40369 BW |
835 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); |
836 | cr |= CFG_SPI_WRITE | (width << 8) | | |
837 | (CFG_SPI_ENABLE << 14); | |
838 | dev_dbg(&drv_data->pdev->dev, | |
839 | "IO write: cr is 0x%x\n", cr); | |
a5f6abd4 WB |
840 | |
841 | write_CTRL(cr); | |
842 | SSYNC(); | |
843 | ||
844 | drv_data->write(drv_data); | |
845 | ||
846 | if (drv_data->tx != drv_data->tx_end) | |
847 | tranf_success = 0; | |
848 | } else if (drv_data->rx != NULL) { | |
849 | /* read only half duplex */ | |
88b40369 BW |
850 | cr = (read_CTRL() & (~BIT_CTL_TIMOD)); |
851 | cr |= CFG_SPI_READ | (width << 8) | | |
852 | (CFG_SPI_ENABLE << 14); | |
853 | dev_dbg(&drv_data->pdev->dev, | |
854 | "IO read: cr is 0x%x\n", cr); | |
a5f6abd4 WB |
855 | |
856 | write_CTRL(cr); | |
857 | SSYNC(); | |
858 | ||
859 | drv_data->read(drv_data); | |
860 | if (drv_data->rx != drv_data->rx_end) | |
861 | tranf_success = 0; | |
862 | } | |
863 | ||
864 | if (!tranf_success) { | |
88b40369 BW |
865 | dev_dbg(&drv_data->pdev->dev, |
866 | "IO write error!\n"); | |
a5f6abd4 WB |
867 | message->state = ERROR_STATE; |
868 | } else { | |
869 | /* Update total byte transfered */ | |
870 | message->actual_length += drv_data->len; | |
871 | ||
872 | /* Move to next transfer of this msg */ | |
873 | message->state = next_transfer(drv_data); | |
874 | } | |
875 | ||
876 | /* Schedule next transfer tasklet */ | |
877 | tasklet_schedule(&drv_data->pump_transfers); | |
878 | ||
879 | } | |
880 | } | |
881 | ||
882 | /* pop a msg from queue and kick off real transfer */ | |
883 | static void pump_messages(struct work_struct *work) | |
884 | { | |
885 | struct driver_data *drv_data = container_of(work, struct driver_data, pump_messages); | |
886 | unsigned long flags; | |
887 | ||
888 | /* Lock queue and check for queue work */ | |
889 | spin_lock_irqsave(&drv_data->lock, flags); | |
890 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
891 | /* pumper kicked off but no work to do */ | |
892 | drv_data->busy = 0; | |
893 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
894 | return; | |
895 | } | |
896 | ||
897 | /* Make sure we are not already running a message */ | |
898 | if (drv_data->cur_msg) { | |
899 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
900 | return; | |
901 | } | |
902 | ||
903 | /* Extract head of queue */ | |
904 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
905 | struct spi_message, queue); | |
906 | list_del_init(&drv_data->cur_msg->queue); | |
907 | ||
908 | /* Initial message state */ | |
909 | drv_data->cur_msg->state = START_STATE; | |
910 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
911 | struct spi_transfer, transfer_list); | |
912 | ||
913 | /* Setup the SSP using the per chip configuration */ | |
914 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
915 | restore_state(drv_data); | |
88b40369 BW |
916 | dev_dbg(&drv_data->pdev->dev, |
917 | "got a message to pump, state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
918 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
919 | drv_data->cur_chip->ctl_reg); | |
920 | ||
921 | dev_dbg(&drv_data->pdev->dev, | |
922 | "the first transfer len is %d\n", | |
923 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
924 | |
925 | /* Mark as busy and launch transfers */ | |
926 | tasklet_schedule(&drv_data->pump_transfers); | |
927 | ||
928 | drv_data->busy = 1; | |
929 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
930 | } | |
931 | ||
932 | /* | |
933 | * got a msg to transfer, queue it in drv_data->queue. | |
934 | * And kick off message pumper | |
935 | */ | |
936 | static int transfer(struct spi_device *spi, struct spi_message *msg) | |
937 | { | |
938 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
939 | unsigned long flags; | |
940 | ||
941 | spin_lock_irqsave(&drv_data->lock, flags); | |
942 | ||
943 | if (drv_data->run == QUEUE_STOPPED) { | |
944 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
945 | return -ESHUTDOWN; | |
946 | } | |
947 | ||
948 | msg->actual_length = 0; | |
949 | msg->status = -EINPROGRESS; | |
950 | msg->state = START_STATE; | |
951 | ||
88b40369 | 952 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
953 | list_add_tail(&msg->queue, &drv_data->queue); |
954 | ||
955 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
956 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
957 | ||
958 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
963 | /* first setup for new devices */ | |
964 | static int setup(struct spi_device *spi) | |
965 | { | |
966 | struct bfin5xx_spi_chip *chip_info = NULL; | |
967 | struct chip_data *chip; | |
968 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
969 | u8 spi_flg; | |
970 | ||
971 | /* Abort device setup if requested features are not supported */ | |
972 | if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) { | |
973 | dev_err(&spi->dev, "requested mode not fully supported\n"); | |
974 | return -EINVAL; | |
975 | } | |
976 | ||
977 | /* Zero (the default) here means 8 bits */ | |
978 | if (!spi->bits_per_word) | |
979 | spi->bits_per_word = 8; | |
980 | ||
981 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) | |
982 | return -EINVAL; | |
983 | ||
984 | /* Only alloc (or use chip_info) on first setup */ | |
985 | chip = spi_get_ctldata(spi); | |
986 | if (chip == NULL) { | |
987 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
988 | if (!chip) | |
989 | return -ENOMEM; | |
990 | ||
991 | chip->enable_dma = 0; | |
992 | chip_info = spi->controller_data; | |
993 | } | |
994 | ||
995 | /* chip_info isn't always needed */ | |
996 | if (chip_info) { | |
997 | chip->enable_dma = chip_info->enable_dma != 0 | |
998 | && drv_data->master_info->enable_dma; | |
999 | chip->ctl_reg = chip_info->ctl_reg; | |
1000 | chip->bits_per_word = chip_info->bits_per_word; | |
1001 | chip->cs_change_per_word = chip_info->cs_change_per_word; | |
1002 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
1003 | } | |
1004 | ||
1005 | /* translate common spi framework into our register */ | |
1006 | if (spi->mode & SPI_CPOL) | |
1007 | chip->ctl_reg |= CPOL; | |
1008 | if (spi->mode & SPI_CPHA) | |
1009 | chip->ctl_reg |= CPHA; | |
1010 | if (spi->mode & SPI_LSB_FIRST) | |
1011 | chip->ctl_reg |= LSBF; | |
1012 | /* we dont support running in slave mode (yet?) */ | |
1013 | chip->ctl_reg |= MSTR; | |
1014 | ||
1015 | /* | |
1016 | * if any one SPI chip is registered and wants DMA, request the | |
1017 | * DMA channel for it | |
1018 | */ | |
1019 | if (chip->enable_dma && !dma_requested) { | |
1020 | /* register dma irq handler */ | |
1021 | if (request_dma(CH_SPI, "BF53x_SPI_DMA") < 0) { | |
88b40369 BW |
1022 | dev_dbg(&spi->dev, |
1023 | "Unable to request BlackFin SPI DMA channel\n"); | |
a5f6abd4 WB |
1024 | return -ENODEV; |
1025 | } | |
1026 | if (set_dma_callback(CH_SPI, (void *)dma_irq_handler, drv_data) | |
1027 | < 0) { | |
88b40369 | 1028 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
a5f6abd4 WB |
1029 | return -EPERM; |
1030 | } | |
1031 | dma_disable_irq(CH_SPI); | |
1032 | dma_requested = 1; | |
1033 | } | |
1034 | ||
1035 | /* | |
1036 | * Notice: for blackfin, the speed_hz is the value of register | |
1037 | * SPI_BAUD, not the real baudrate | |
1038 | */ | |
1039 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
1040 | spi_flg = ~(1 << (spi->chip_select)); | |
1041 | chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select)); | |
1042 | chip->chip_select_num = spi->chip_select; | |
1043 | ||
1044 | switch (chip->bits_per_word) { | |
1045 | case 8: | |
1046 | chip->n_bytes = 1; | |
1047 | chip->width = CFG_SPI_WORDSIZE8; | |
1048 | chip->read = chip->cs_change_per_word ? | |
1049 | u8_cs_chg_reader : u8_reader; | |
1050 | chip->write = chip->cs_change_per_word ? | |
1051 | u8_cs_chg_writer : u8_writer; | |
1052 | chip->duplex = chip->cs_change_per_word ? | |
1053 | u8_cs_chg_duplex : u8_duplex; | |
1054 | break; | |
1055 | ||
1056 | case 16: | |
1057 | chip->n_bytes = 2; | |
1058 | chip->width = CFG_SPI_WORDSIZE16; | |
1059 | chip->read = chip->cs_change_per_word ? | |
1060 | u16_cs_chg_reader : u16_reader; | |
1061 | chip->write = chip->cs_change_per_word ? | |
1062 | u16_cs_chg_writer : u16_writer; | |
1063 | chip->duplex = chip->cs_change_per_word ? | |
1064 | u16_cs_chg_duplex : u16_duplex; | |
1065 | break; | |
1066 | ||
1067 | default: | |
1068 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1069 | chip->bits_per_word); | |
1070 | kfree(chip); | |
1071 | return -ENODEV; | |
1072 | } | |
1073 | ||
88b40369 | 1074 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d,", |
a5f6abd4 | 1075 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1076 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1077 | chip->ctl_reg, chip->flag); |
1078 | ||
1079 | spi_set_ctldata(spi, chip); | |
1080 | ||
1081 | return 0; | |
1082 | } | |
1083 | ||
1084 | /* | |
1085 | * callback for spi framework. | |
1086 | * clean driver specific data | |
1087 | */ | |
88b40369 | 1088 | static void cleanup(struct spi_device *spi) |
a5f6abd4 | 1089 | { |
27bb9e79 | 1090 | struct chip_data *chip = spi_get_ctldata(spi); |
a5f6abd4 WB |
1091 | |
1092 | kfree(chip); | |
1093 | } | |
1094 | ||
1095 | static inline int init_queue(struct driver_data *drv_data) | |
1096 | { | |
1097 | INIT_LIST_HEAD(&drv_data->queue); | |
1098 | spin_lock_init(&drv_data->lock); | |
1099 | ||
1100 | drv_data->run = QUEUE_STOPPED; | |
1101 | drv_data->busy = 0; | |
1102 | ||
1103 | /* init transfer tasklet */ | |
1104 | tasklet_init(&drv_data->pump_transfers, | |
1105 | pump_transfers, (unsigned long)drv_data); | |
1106 | ||
1107 | /* init messages workqueue */ | |
1108 | INIT_WORK(&drv_data->pump_messages, pump_messages); | |
1109 | drv_data->workqueue = | |
1110 | create_singlethread_workqueue(drv_data->master->cdev.dev->bus_id); | |
1111 | if (drv_data->workqueue == NULL) | |
1112 | return -EBUSY; | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static inline int start_queue(struct driver_data *drv_data) | |
1118 | { | |
1119 | unsigned long flags; | |
1120 | ||
1121 | spin_lock_irqsave(&drv_data->lock, flags); | |
1122 | ||
1123 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1124 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1125 | return -EBUSY; | |
1126 | } | |
1127 | ||
1128 | drv_data->run = QUEUE_RUNNING; | |
1129 | drv_data->cur_msg = NULL; | |
1130 | drv_data->cur_transfer = NULL; | |
1131 | drv_data->cur_chip = NULL; | |
1132 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1133 | ||
1134 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | static inline int stop_queue(struct driver_data *drv_data) | |
1140 | { | |
1141 | unsigned long flags; | |
1142 | unsigned limit = 500; | |
1143 | int status = 0; | |
1144 | ||
1145 | spin_lock_irqsave(&drv_data->lock, flags); | |
1146 | ||
1147 | /* | |
1148 | * This is a bit lame, but is optimized for the common execution path. | |
1149 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1150 | * execution path (pump_messages) would be required to call wake_up or | |
1151 | * friends on every SPI message. Do this instead | |
1152 | */ | |
1153 | drv_data->run = QUEUE_STOPPED; | |
1154 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1155 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1156 | msleep(10); | |
1157 | spin_lock_irqsave(&drv_data->lock, flags); | |
1158 | } | |
1159 | ||
1160 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1161 | status = -EBUSY; | |
1162 | ||
1163 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1164 | ||
1165 | return status; | |
1166 | } | |
1167 | ||
1168 | static inline int destroy_queue(struct driver_data *drv_data) | |
1169 | { | |
1170 | int status; | |
1171 | ||
1172 | status = stop_queue(drv_data); | |
1173 | if (status != 0) | |
1174 | return status; | |
1175 | ||
1176 | destroy_workqueue(drv_data->workqueue); | |
1177 | ||
1178 | return 0; | |
1179 | } | |
1180 | ||
1181 | static int __init bfin5xx_spi_probe(struct platform_device *pdev) | |
1182 | { | |
1183 | struct device *dev = &pdev->dev; | |
1184 | struct bfin5xx_spi_master *platform_info; | |
1185 | struct spi_master *master; | |
1186 | struct driver_data *drv_data = 0; | |
1187 | int status = 0; | |
1188 | ||
1189 | platform_info = dev->platform_data; | |
1190 | ||
1191 | /* Allocate master with space for drv_data */ | |
1192 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1193 | if (!master) { | |
1194 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1195 | return -ENOMEM; | |
1196 | } | |
1197 | drv_data = spi_master_get_devdata(master); | |
1198 | drv_data->master = master; | |
1199 | drv_data->master_info = platform_info; | |
1200 | drv_data->pdev = pdev; | |
1201 | ||
1202 | master->bus_num = pdev->id; | |
1203 | master->num_chipselect = platform_info->num_chipselect; | |
1204 | master->cleanup = cleanup; | |
1205 | master->setup = setup; | |
1206 | master->transfer = transfer; | |
1207 | ||
1208 | /* Initial and start queue */ | |
1209 | status = init_queue(drv_data); | |
1210 | if (status != 0) { | |
1211 | dev_err(&pdev->dev, "problem initializing queue\n"); | |
1212 | goto out_error_queue_alloc; | |
1213 | } | |
1214 | status = start_queue(drv_data); | |
1215 | if (status != 0) { | |
1216 | dev_err(&pdev->dev, "problem starting queue\n"); | |
1217 | goto out_error_queue_alloc; | |
1218 | } | |
1219 | ||
1220 | /* Register with the SPI framework */ | |
1221 | platform_set_drvdata(pdev, drv_data); | |
1222 | status = spi_register_master(master); | |
1223 | if (status != 0) { | |
1224 | dev_err(&pdev->dev, "problem registering spi master\n"); | |
1225 | goto out_error_queue_alloc; | |
1226 | } | |
88b40369 | 1227 | dev_dbg(&pdev->dev, "controller probe successfully\n"); |
a5f6abd4 WB |
1228 | return status; |
1229 | ||
1230 | out_error_queue_alloc: | |
1231 | destroy_queue(drv_data); | |
1232 | spi_master_put(master); | |
1233 | return status; | |
1234 | } | |
1235 | ||
1236 | /* stop hardware and remove the driver */ | |
1237 | static int __devexit bfin5xx_spi_remove(struct platform_device *pdev) | |
1238 | { | |
1239 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1240 | int status = 0; | |
1241 | ||
1242 | if (!drv_data) | |
1243 | return 0; | |
1244 | ||
1245 | /* Remove the queue */ | |
1246 | status = destroy_queue(drv_data); | |
1247 | if (status != 0) | |
1248 | return status; | |
1249 | ||
1250 | /* Disable the SSP at the peripheral and SOC level */ | |
1251 | bfin_spi_disable(drv_data); | |
1252 | ||
1253 | /* Release DMA */ | |
1254 | if (drv_data->master_info->enable_dma) { | |
1255 | if (dma_channel_active(CH_SPI)) | |
1256 | free_dma(CH_SPI); | |
1257 | } | |
1258 | ||
1259 | /* Disconnect from the SPI framework */ | |
1260 | spi_unregister_master(drv_data->master); | |
1261 | ||
1262 | /* Prevent double remove */ | |
1263 | platform_set_drvdata(pdev, NULL); | |
1264 | ||
1265 | return 0; | |
1266 | } | |
1267 | ||
1268 | #ifdef CONFIG_PM | |
1269 | static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state) | |
1270 | { | |
1271 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1272 | int status = 0; | |
1273 | ||
1274 | status = stop_queue(drv_data); | |
1275 | if (status != 0) | |
1276 | return status; | |
1277 | ||
1278 | /* stop hardware */ | |
1279 | bfin_spi_disable(drv_data); | |
1280 | ||
1281 | return 0; | |
1282 | } | |
1283 | ||
1284 | static int bfin5xx_spi_resume(struct platform_device *pdev) | |
1285 | { | |
1286 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1287 | int status = 0; | |
1288 | ||
1289 | /* Enable the SPI interface */ | |
1290 | bfin_spi_enable(drv_data); | |
1291 | ||
1292 | /* Start the queue running */ | |
1293 | status = start_queue(drv_data); | |
1294 | if (status != 0) { | |
1295 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1296 | return status; | |
1297 | } | |
1298 | ||
1299 | return 0; | |
1300 | } | |
1301 | #else | |
1302 | #define bfin5xx_spi_suspend NULL | |
1303 | #define bfin5xx_spi_resume NULL | |
1304 | #endif /* CONFIG_PM */ | |
1305 | ||
1306 | static struct platform_driver bfin5xx_spi_driver = { | |
88b40369 BW |
1307 | .driver = { |
1308 | .name = "bfin-spi-master", | |
1309 | .owner = THIS_MODULE, | |
1310 | }, | |
1311 | .suspend = bfin5xx_spi_suspend, | |
1312 | .resume = bfin5xx_spi_resume, | |
1313 | .remove = __devexit_p(bfin5xx_spi_remove), | |
a5f6abd4 WB |
1314 | }; |
1315 | ||
1316 | static int __init bfin5xx_spi_init(void) | |
1317 | { | |
88b40369 | 1318 | return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe); |
a5f6abd4 | 1319 | } |
a5f6abd4 WB |
1320 | module_init(bfin5xx_spi_init); |
1321 | ||
1322 | static void __exit bfin5xx_spi_exit(void) | |
1323 | { | |
1324 | platform_driver_unregister(&bfin5xx_spi_driver); | |
1325 | } | |
a5f6abd4 | 1326 | module_exit(bfin5xx_spi_exit); |