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Commit | Line | Data |
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9904f22a DB |
1 | /* |
2 | * spi_bitbang.c - polling/bitbanging SPI master controller driver utilities | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
9904f22a DB |
19 | #include <linux/init.h> |
20 | #include <linux/spinlock.h> | |
21 | #include <linux/workqueue.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/delay.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/platform_device.h> | |
26 | ||
27 | #include <linux/spi/spi.h> | |
28 | #include <linux/spi/spi_bitbang.h> | |
29 | ||
30 | ||
31 | /*----------------------------------------------------------------------*/ | |
32 | ||
33 | /* | |
34 | * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support. | |
35 | * Use this for GPIO or shift-register level hardware APIs. | |
36 | * | |
37 | * spi_bitbang_cs is in spi_device->controller_state, which is unavailable | |
38 | * to glue code. These bitbang setup() and cleanup() routines are always | |
39 | * used, though maybe they're called from controller-aware code. | |
40 | * | |
41 | * chipselect() and friends may use use spi_device->controller_data and | |
42 | * controller registers as appropriate. | |
43 | * | |
44 | * | |
45 | * NOTE: SPI controller pins can often be used as GPIO pins instead, | |
46 | * which means you could use a bitbang driver either to get hardware | |
47 | * working quickly, or testing for differences that aren't speed related. | |
48 | */ | |
49 | ||
50 | struct spi_bitbang_cs { | |
51 | unsigned nsecs; /* (clock cycle time)/2 */ | |
52 | u32 (*txrx_word)(struct spi_device *spi, unsigned nsecs, | |
53 | u32 word, u8 bits); | |
54 | unsigned (*txrx_bufs)(struct spi_device *, | |
55 | u32 (*txrx_word)( | |
56 | struct spi_device *spi, | |
57 | unsigned nsecs, | |
58 | u32 word, u8 bits), | |
59 | unsigned, struct spi_transfer *); | |
60 | }; | |
61 | ||
62 | static unsigned bitbang_txrx_8( | |
63 | struct spi_device *spi, | |
64 | u32 (*txrx_word)(struct spi_device *spi, | |
65 | unsigned nsecs, | |
66 | u32 word, u8 bits), | |
67 | unsigned ns, | |
68 | struct spi_transfer *t | |
69 | ) { | |
70 | unsigned bits = spi->bits_per_word; | |
71 | unsigned count = t->len; | |
72 | const u8 *tx = t->tx_buf; | |
73 | u8 *rx = t->rx_buf; | |
74 | ||
75 | while (likely(count > 0)) { | |
76 | u8 word = 0; | |
77 | ||
78 | if (tx) | |
79 | word = *tx++; | |
80 | word = txrx_word(spi, ns, word, bits); | |
81 | if (rx) | |
82 | *rx++ = word; | |
83 | count -= 1; | |
84 | } | |
85 | return t->len - count; | |
86 | } | |
87 | ||
88 | static unsigned bitbang_txrx_16( | |
89 | struct spi_device *spi, | |
90 | u32 (*txrx_word)(struct spi_device *spi, | |
91 | unsigned nsecs, | |
92 | u32 word, u8 bits), | |
93 | unsigned ns, | |
94 | struct spi_transfer *t | |
95 | ) { | |
96 | unsigned bits = spi->bits_per_word; | |
97 | unsigned count = t->len; | |
98 | const u16 *tx = t->tx_buf; | |
99 | u16 *rx = t->rx_buf; | |
100 | ||
101 | while (likely(count > 1)) { | |
102 | u16 word = 0; | |
103 | ||
104 | if (tx) | |
105 | word = *tx++; | |
106 | word = txrx_word(spi, ns, word, bits); | |
107 | if (rx) | |
108 | *rx++ = word; | |
109 | count -= 2; | |
110 | } | |
111 | return t->len - count; | |
112 | } | |
113 | ||
114 | static unsigned bitbang_txrx_32( | |
115 | struct spi_device *spi, | |
116 | u32 (*txrx_word)(struct spi_device *spi, | |
117 | unsigned nsecs, | |
118 | u32 word, u8 bits), | |
119 | unsigned ns, | |
120 | struct spi_transfer *t | |
121 | ) { | |
122 | unsigned bits = spi->bits_per_word; | |
123 | unsigned count = t->len; | |
124 | const u32 *tx = t->tx_buf; | |
125 | u32 *rx = t->rx_buf; | |
126 | ||
127 | while (likely(count > 3)) { | |
128 | u32 word = 0; | |
129 | ||
130 | if (tx) | |
131 | word = *tx++; | |
132 | word = txrx_word(spi, ns, word, bits); | |
133 | if (rx) | |
134 | *rx++ = word; | |
135 | count -= 4; | |
136 | } | |
137 | return t->len - count; | |
138 | } | |
139 | ||
ff9f4771 | 140 | int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
4cff33f9 ID |
141 | { |
142 | struct spi_bitbang_cs *cs = spi->controller_state; | |
143 | u8 bits_per_word; | |
144 | u32 hz; | |
145 | ||
146 | if (t) { | |
147 | bits_per_word = t->bits_per_word; | |
148 | hz = t->speed_hz; | |
149 | } else { | |
150 | bits_per_word = 0; | |
151 | hz = 0; | |
152 | } | |
153 | ||
154 | /* spi_transfer level calls that work per-word */ | |
155 | if (!bits_per_word) | |
156 | bits_per_word = spi->bits_per_word; | |
157 | if (bits_per_word <= 8) | |
158 | cs->txrx_bufs = bitbang_txrx_8; | |
159 | else if (bits_per_word <= 16) | |
160 | cs->txrx_bufs = bitbang_txrx_16; | |
161 | else if (bits_per_word <= 32) | |
162 | cs->txrx_bufs = bitbang_txrx_32; | |
163 | else | |
164 | return -EINVAL; | |
165 | ||
166 | /* nsecs = (clock period)/2 */ | |
167 | if (!hz) | |
168 | hz = spi->max_speed_hz; | |
1e316d75 DB |
169 | if (hz) { |
170 | cs->nsecs = (1000000000/2) / hz; | |
171 | if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000)) | |
172 | return -EINVAL; | |
173 | } | |
4cff33f9 ID |
174 | |
175 | return 0; | |
176 | } | |
ff9f4771 | 177 | EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer); |
4cff33f9 | 178 | |
9904f22a DB |
179 | /** |
180 | * spi_bitbang_setup - default setup for per-word I/O loops | |
181 | */ | |
182 | int spi_bitbang_setup(struct spi_device *spi) | |
183 | { | |
184 | struct spi_bitbang_cs *cs = spi->controller_state; | |
185 | struct spi_bitbang *bitbang; | |
4cff33f9 | 186 | int retval; |
d52df2e2 | 187 | unsigned long flags; |
9904f22a | 188 | |
ccf77cc4 DB |
189 | bitbang = spi_master_get_devdata(spi->master); |
190 | ||
dccd573b DB |
191 | /* Bitbangers can support SPI_CS_HIGH, SPI_3WIRE, and so on; |
192 | * add those to master->flags, and provide the other support. | |
ccf77cc4 | 193 | */ |
dccd573b | 194 | if ((spi->mode & ~(SPI_CPOL|SPI_CPHA|bitbang->flags)) != 0) |
ccf77cc4 DB |
195 | return -EINVAL; |
196 | ||
9904f22a | 197 | if (!cs) { |
e94b1766 | 198 | cs = kzalloc(sizeof *cs, GFP_KERNEL); |
9904f22a DB |
199 | if (!cs) |
200 | return -ENOMEM; | |
201 | spi->controller_state = cs; | |
202 | } | |
9904f22a DB |
203 | |
204 | if (!spi->bits_per_word) | |
205 | spi->bits_per_word = 8; | |
206 | ||
9904f22a DB |
207 | /* per-word shift register access, in hardware or bitbanging */ |
208 | cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)]; | |
209 | if (!cs->txrx_word) | |
210 | return -EINVAL; | |
211 | ||
7f8c7619 | 212 | retval = bitbang->setup_transfer(spi, NULL); |
4cff33f9 ID |
213 | if (retval < 0) |
214 | return retval; | |
9904f22a | 215 | |
1e316d75 | 216 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n", |
9904f22a DB |
217 | __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA), |
218 | spi->bits_per_word, 2 * cs->nsecs); | |
219 | ||
220 | /* NOTE we _need_ to call chipselect() early, ideally with adapter | |
221 | * setup, unless the hardware defaults cooperate to avoid confusion | |
222 | * between normal (active low) and inverted chipselects. | |
223 | */ | |
224 | ||
225 | /* deselect chip (low or high) */ | |
d52df2e2 | 226 | spin_lock_irqsave(&bitbang->lock, flags); |
9904f22a | 227 | if (!bitbang->busy) { |
8275c642 | 228 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); |
9904f22a DB |
229 | ndelay(cs->nsecs); |
230 | } | |
d52df2e2 | 231 | spin_unlock_irqrestore(&bitbang->lock, flags); |
9904f22a DB |
232 | |
233 | return 0; | |
234 | } | |
235 | EXPORT_SYMBOL_GPL(spi_bitbang_setup); | |
236 | ||
237 | /** | |
238 | * spi_bitbang_cleanup - default cleanup for per-word I/O loops | |
239 | */ | |
0ffa0285 | 240 | void spi_bitbang_cleanup(struct spi_device *spi) |
9904f22a DB |
241 | { |
242 | kfree(spi->controller_state); | |
243 | } | |
244 | EXPORT_SYMBOL_GPL(spi_bitbang_cleanup); | |
245 | ||
246 | static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t) | |
247 | { | |
248 | struct spi_bitbang_cs *cs = spi->controller_state; | |
249 | unsigned nsecs = cs->nsecs; | |
250 | ||
251 | return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t); | |
252 | } | |
253 | ||
254 | /*----------------------------------------------------------------------*/ | |
255 | ||
256 | /* | |
257 | * SECOND PART ... simple transfer queue runner. | |
258 | * | |
259 | * This costs a task context per controller, running the queue by | |
260 | * performing each transfer in sequence. Smarter hardware can queue | |
261 | * several DMA transfers at once, and process several controller queues | |
262 | * in parallel; this driver doesn't match such hardware very well. | |
263 | * | |
264 | * Drivers can provide word-at-a-time i/o primitives, or provide | |
265 | * transfer-at-a-time ones to leverage dma or fifo hardware. | |
266 | */ | |
c4028958 | 267 | static void bitbang_work(struct work_struct *work) |
9904f22a | 268 | { |
c4028958 DH |
269 | struct spi_bitbang *bitbang = |
270 | container_of(work, struct spi_bitbang, work); | |
9904f22a DB |
271 | unsigned long flags; |
272 | ||
273 | spin_lock_irqsave(&bitbang->lock, flags); | |
274 | bitbang->busy = 1; | |
275 | while (!list_empty(&bitbang->queue)) { | |
276 | struct spi_message *m; | |
277 | struct spi_device *spi; | |
278 | unsigned nsecs; | |
8275c642 | 279 | struct spi_transfer *t = NULL; |
9904f22a | 280 | unsigned tmp; |
8275c642 | 281 | unsigned cs_change; |
9904f22a | 282 | int status; |
4cff33f9 ID |
283 | int (*setup_transfer)(struct spi_device *, |
284 | struct spi_transfer *); | |
9904f22a DB |
285 | |
286 | m = container_of(bitbang->queue.next, struct spi_message, | |
287 | queue); | |
288 | list_del_init(&m->queue); | |
289 | spin_unlock_irqrestore(&bitbang->lock, flags); | |
290 | ||
8275c642 VW |
291 | /* FIXME this is made-up ... the correct value is known to |
292 | * word-at-a-time bitbang code, and presumably chipselect() | |
293 | * should enforce these requirements too? | |
294 | */ | |
295 | nsecs = 100; | |
9904f22a DB |
296 | |
297 | spi = m->spi; | |
9904f22a | 298 | tmp = 0; |
8275c642 | 299 | cs_change = 1; |
9904f22a | 300 | status = 0; |
4cff33f9 | 301 | setup_transfer = NULL; |
9904f22a | 302 | |
8275c642 | 303 | list_for_each_entry (t, &m->transfers, transfer_list) { |
9904f22a | 304 | |
4cff33f9 ID |
305 | /* override or restore speed and wordsize */ |
306 | if (t->speed_hz || t->bits_per_word) { | |
307 | setup_transfer = bitbang->setup_transfer; | |
308 | if (!setup_transfer) { | |
309 | status = -ENOPROTOOPT; | |
310 | break; | |
311 | } | |
312 | } | |
313 | if (setup_transfer) { | |
314 | status = setup_transfer(spi, t); | |
315 | if (status < 0) | |
316 | break; | |
317 | } | |
318 | ||
8275c642 VW |
319 | /* set up default clock polarity, and activate chip; |
320 | * this implicitly updates clock and spi modes as | |
321 | * previously recorded for this device via setup(). | |
322 | * (and also deselects any other chip that might be | |
323 | * selected ...) | |
324 | */ | |
325 | if (cs_change) { | |
326 | bitbang->chipselect(spi, BITBANG_CS_ACTIVE); | |
9904f22a DB |
327 | ndelay(nsecs); |
328 | } | |
8275c642 | 329 | cs_change = t->cs_change; |
9904f22a DB |
330 | if (!t->tx_buf && !t->rx_buf && t->len) { |
331 | status = -EINVAL; | |
332 | break; | |
333 | } | |
334 | ||
8275c642 VW |
335 | /* transfer data. the lower level code handles any |
336 | * new dma mappings it needs. our caller always gave | |
337 | * us dma-safe buffers. | |
338 | */ | |
9904f22a | 339 | if (t->len) { |
8275c642 VW |
340 | /* REVISIT dma API still needs a designated |
341 | * DMA_ADDR_INVALID; ~0 might be better. | |
9904f22a | 342 | */ |
8275c642 VW |
343 | if (!m->is_dma_mapped) |
344 | t->rx_dma = t->tx_dma = 0; | |
9904f22a DB |
345 | status = bitbang->txrx_bufs(spi, t); |
346 | } | |
347 | if (status != t->len) { | |
348 | if (status > 0) | |
349 | status = -EMSGSIZE; | |
350 | break; | |
351 | } | |
352 | m->actual_length += status; | |
353 | status = 0; | |
354 | ||
355 | /* protocol tweaks before next transfer */ | |
356 | if (t->delay_usecs) | |
357 | udelay(t->delay_usecs); | |
358 | ||
8275c642 | 359 | if (!cs_change) |
9904f22a | 360 | continue; |
8275c642 VW |
361 | if (t->transfer_list.next == &m->transfers) |
362 | break; | |
9904f22a | 363 | |
8275c642 VW |
364 | /* sometimes a short mid-message deselect of the chip |
365 | * may be needed to terminate a mode or command | |
366 | */ | |
367 | ndelay(nsecs); | |
368 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | |
369 | ndelay(nsecs); | |
9904f22a DB |
370 | } |
371 | ||
9904f22a DB |
372 | m->status = status; |
373 | m->complete(m->context); | |
374 | ||
4cff33f9 ID |
375 | /* restore speed and wordsize */ |
376 | if (setup_transfer) | |
377 | setup_transfer(spi, NULL); | |
378 | ||
8275c642 VW |
379 | /* normally deactivate chipselect ... unless no error and |
380 | * cs_change has hinted that the next message will probably | |
381 | * be for this chip too. | |
382 | */ | |
383 | if (!(status == 0 && cs_change)) { | |
384 | ndelay(nsecs); | |
385 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | |
386 | ndelay(nsecs); | |
387 | } | |
9904f22a DB |
388 | |
389 | spin_lock_irqsave(&bitbang->lock, flags); | |
390 | } | |
391 | bitbang->busy = 0; | |
392 | spin_unlock_irqrestore(&bitbang->lock, flags); | |
393 | } | |
394 | ||
395 | /** | |
396 | * spi_bitbang_transfer - default submit to transfer queue | |
397 | */ | |
398 | int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m) | |
399 | { | |
400 | struct spi_bitbang *bitbang; | |
401 | unsigned long flags; | |
1e316d75 | 402 | int status = 0; |
9904f22a DB |
403 | |
404 | m->actual_length = 0; | |
405 | m->status = -EINPROGRESS; | |
406 | ||
407 | bitbang = spi_master_get_devdata(spi->master); | |
9904f22a DB |
408 | |
409 | spin_lock_irqsave(&bitbang->lock, flags); | |
1e316d75 DB |
410 | if (!spi->max_speed_hz) |
411 | status = -ENETDOWN; | |
412 | else { | |
413 | list_add_tail(&m->queue, &bitbang->queue); | |
414 | queue_work(bitbang->workqueue, &bitbang->work); | |
415 | } | |
9904f22a DB |
416 | spin_unlock_irqrestore(&bitbang->lock, flags); |
417 | ||
1e316d75 | 418 | return status; |
9904f22a DB |
419 | } |
420 | EXPORT_SYMBOL_GPL(spi_bitbang_transfer); | |
421 | ||
422 | /*----------------------------------------------------------------------*/ | |
423 | ||
424 | /** | |
425 | * spi_bitbang_start - start up a polled/bitbanging SPI master driver | |
426 | * @bitbang: driver handle | |
427 | * | |
428 | * Caller should have zero-initialized all parts of the structure, and then | |
429 | * provided callbacks for chip selection and I/O loops. If the master has | |
430 | * a transfer method, its final step should call spi_bitbang_transfer; or, | |
431 | * that's the default if the transfer routine is not initialized. It should | |
432 | * also set up the bus number and number of chipselects. | |
433 | * | |
434 | * For i/o loops, provide callbacks either per-word (for bitbanging, or for | |
435 | * hardware that basically exposes a shift register) or per-spi_transfer | |
436 | * (which takes better advantage of hardware like fifos or DMA engines). | |
437 | * | |
7f8c7619 HPN |
438 | * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup, |
439 | * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi | |
440 | * master methods. Those methods are the defaults if the bitbang->txrx_bufs | |
441 | * routine isn't initialized. | |
9904f22a DB |
442 | * |
443 | * This routine registers the spi_master, which will process requests in a | |
444 | * dedicated task, keeping IRQs unblocked most of the time. To stop | |
445 | * processing those requests, call spi_bitbang_stop(). | |
446 | */ | |
447 | int spi_bitbang_start(struct spi_bitbang *bitbang) | |
448 | { | |
449 | int status; | |
450 | ||
451 | if (!bitbang->master || !bitbang->chipselect) | |
452 | return -EINVAL; | |
453 | ||
c4028958 | 454 | INIT_WORK(&bitbang->work, bitbang_work); |
9904f22a DB |
455 | spin_lock_init(&bitbang->lock); |
456 | INIT_LIST_HEAD(&bitbang->queue); | |
457 | ||
458 | if (!bitbang->master->transfer) | |
459 | bitbang->master->transfer = spi_bitbang_transfer; | |
460 | if (!bitbang->txrx_bufs) { | |
461 | bitbang->use_dma = 0; | |
462 | bitbang->txrx_bufs = spi_bitbang_bufs; | |
463 | if (!bitbang->master->setup) { | |
ff9f4771 KG |
464 | if (!bitbang->setup_transfer) |
465 | bitbang->setup_transfer = | |
466 | spi_bitbang_setup_transfer; | |
9904f22a DB |
467 | bitbang->master->setup = spi_bitbang_setup; |
468 | bitbang->master->cleanup = spi_bitbang_cleanup; | |
469 | } | |
470 | } else if (!bitbang->master->setup) | |
471 | return -EINVAL; | |
472 | ||
473 | /* this task is the only thing to touch the SPI bits */ | |
474 | bitbang->busy = 0; | |
475 | bitbang->workqueue = create_singlethread_workqueue( | |
49dce689 | 476 | bitbang->master->dev.parent->bus_id); |
9904f22a DB |
477 | if (bitbang->workqueue == NULL) { |
478 | status = -EBUSY; | |
479 | goto err1; | |
480 | } | |
481 | ||
482 | /* driver may get busy before register() returns, especially | |
483 | * if someone registered boardinfo for devices | |
484 | */ | |
485 | status = spi_register_master(bitbang->master); | |
486 | if (status < 0) | |
487 | goto err2; | |
488 | ||
489 | return status; | |
490 | ||
491 | err2: | |
492 | destroy_workqueue(bitbang->workqueue); | |
493 | err1: | |
494 | return status; | |
495 | } | |
496 | EXPORT_SYMBOL_GPL(spi_bitbang_start); | |
497 | ||
498 | /** | |
499 | * spi_bitbang_stop - stops the task providing spi communication | |
500 | */ | |
501 | int spi_bitbang_stop(struct spi_bitbang *bitbang) | |
502 | { | |
a836f585 | 503 | spi_unregister_master(bitbang->master); |
9904f22a | 504 | |
a836f585 | 505 | WARN_ON(!list_empty(&bitbang->queue)); |
9904f22a DB |
506 | |
507 | destroy_workqueue(bitbang->workqueue); | |
508 | ||
9904f22a DB |
509 | return 0; |
510 | } | |
511 | EXPORT_SYMBOL_GPL(spi_bitbang_stop); | |
512 | ||
513 | MODULE_LICENSE("GPL"); | |
514 |