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Commit | Line | Data |
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ccf06998 KG |
1 | /* |
2 | * MPC83xx SPI controller driver. | |
3 | * | |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | */ | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/completion.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/irq.h> | |
21 | #include <linux/device.h> | |
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/spi/spi_bitbang.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/fsl_devices.h> | |
26 | ||
27 | #include <asm/irq.h> | |
28 | #include <asm/io.h> | |
29 | ||
30 | /* SPI Controller registers */ | |
31 | struct mpc83xx_spi_reg { | |
32 | u8 res1[0x20]; | |
33 | __be32 mode; | |
34 | __be32 event; | |
35 | __be32 mask; | |
36 | __be32 command; | |
37 | __be32 transmit; | |
38 | __be32 receive; | |
39 | }; | |
40 | ||
41 | /* SPI Controller mode register definitions */ | |
2a485d7a | 42 | #define SPMODE_LOOP (1 << 30) |
ccf06998 KG |
43 | #define SPMODE_CI_INACTIVEHIGH (1 << 29) |
44 | #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) | |
45 | #define SPMODE_DIV16 (1 << 27) | |
46 | #define SPMODE_REV (1 << 26) | |
47 | #define SPMODE_MS (1 << 25) | |
48 | #define SPMODE_ENABLE (1 << 24) | |
49 | #define SPMODE_LEN(x) ((x) << 20) | |
50 | #define SPMODE_PM(x) ((x) << 16) | |
f29ba280 | 51 | #define SPMODE_OP (1 << 14) |
ccf06998 KG |
52 | |
53 | /* | |
54 | * Default for SPI Mode: | |
55 | * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk | |
56 | */ | |
57 | #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ | |
58 | SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) | |
59 | ||
60 | /* SPIE register values */ | |
61 | #define SPIE_NE 0x00000200 /* Not empty */ | |
62 | #define SPIE_NF 0x00000100 /* Not full */ | |
63 | ||
64 | /* SPIM register values */ | |
65 | #define SPIM_NE 0x00000200 /* Not empty */ | |
66 | #define SPIM_NF 0x00000100 /* Not full */ | |
67 | ||
68 | /* SPI Controller driver's private data. */ | |
69 | struct mpc83xx_spi { | |
70 | /* bitbang has to be first */ | |
71 | struct spi_bitbang bitbang; | |
72 | struct completion done; | |
73 | ||
74 | struct mpc83xx_spi_reg __iomem *base; | |
75 | ||
76 | /* rx & tx bufs from the spi_transfer */ | |
77 | const void *tx; | |
78 | void *rx; | |
79 | ||
80 | /* functions to deal with different sized buffers */ | |
81 | void (*get_rx) (u32 rx_data, struct mpc83xx_spi *); | |
82 | u32(*get_tx) (struct mpc83xx_spi *); | |
83 | ||
84 | unsigned int count; | |
85 | u32 irq; | |
86 | ||
87 | unsigned nsecs; /* (clock cycle time)/2 */ | |
88 | ||
e24a4d1e | 89 | u32 spibrg; /* SPIBRG input clock */ |
f29ba280 JT |
90 | u32 rx_shift; /* RX data reg shift when in qe mode */ |
91 | u32 tx_shift; /* TX data reg shift when in qe mode */ | |
92 | ||
93 | bool qe_mode; | |
94 | ||
ccf06998 KG |
95 | void (*activate_cs) (u8 cs, u8 polarity); |
96 | void (*deactivate_cs) (u8 cs, u8 polarity); | |
97 | }; | |
98 | ||
99 | static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val) | |
100 | { | |
101 | out_be32(reg, val); | |
102 | } | |
103 | ||
104 | static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg) | |
105 | { | |
106 | return in_be32(reg); | |
107 | } | |
108 | ||
109 | #define MPC83XX_SPI_RX_BUF(type) \ | |
110 | void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \ | |
111 | { \ | |
112 | type * rx = mpc83xx_spi->rx; \ | |
f29ba280 | 113 | *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \ |
ccf06998 KG |
114 | mpc83xx_spi->rx = rx; \ |
115 | } | |
116 | ||
117 | #define MPC83XX_SPI_TX_BUF(type) \ | |
118 | u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \ | |
119 | { \ | |
120 | u32 data; \ | |
121 | const type * tx = mpc83xx_spi->tx; \ | |
4b1badf5 DB |
122 | if (!tx) \ |
123 | return 0; \ | |
f29ba280 | 124 | data = *tx++ << mpc83xx_spi->tx_shift; \ |
ccf06998 KG |
125 | mpc83xx_spi->tx = tx; \ |
126 | return data; \ | |
127 | } | |
128 | ||
129 | MPC83XX_SPI_RX_BUF(u8) | |
130 | MPC83XX_SPI_RX_BUF(u16) | |
131 | MPC83XX_SPI_RX_BUF(u32) | |
132 | MPC83XX_SPI_TX_BUF(u8) | |
133 | MPC83XX_SPI_TX_BUF(u16) | |
134 | MPC83XX_SPI_TX_BUF(u32) | |
135 | ||
136 | static void mpc83xx_spi_chipselect(struct spi_device *spi, int value) | |
137 | { | |
138 | struct mpc83xx_spi *mpc83xx_spi; | |
139 | u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
140 | ||
141 | mpc83xx_spi = spi_master_get_devdata(spi->master); | |
142 | ||
143 | if (value == BITBANG_CS_INACTIVE) { | |
144 | if (mpc83xx_spi->deactivate_cs) | |
145 | mpc83xx_spi->deactivate_cs(spi->chip_select, pol); | |
146 | } | |
147 | ||
148 | if (value == BITBANG_CS_ACTIVE) { | |
149 | u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); | |
150 | u32 len = spi->bits_per_word; | |
a44648b0 AV |
151 | u8 pm; |
152 | ||
ccf06998 KG |
153 | if (len == 32) |
154 | len = 0; | |
155 | else | |
156 | len = len - 1; | |
157 | ||
158 | /* mask out bits we are going to set */ | |
32421daa AV |
159 | regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH |
160 | | SPMODE_LEN(0xF) | SPMODE_DIV16 | |
2a485d7a | 161 | | SPMODE_PM(0xF) | SPMODE_REV | SPMODE_LOOP); |
ccf06998 KG |
162 | |
163 | if (spi->mode & SPI_CPHA) | |
164 | regval |= SPMODE_CP_BEGIN_EDGECLK; | |
165 | if (spi->mode & SPI_CPOL) | |
166 | regval |= SPMODE_CI_INACTIVEHIGH; | |
32421daa AV |
167 | if (!(spi->mode & SPI_LSB_FIRST)) |
168 | regval |= SPMODE_REV; | |
2a485d7a AV |
169 | if (spi->mode & SPI_LOOP) |
170 | regval |= SPMODE_LOOP; | |
ccf06998 KG |
171 | |
172 | regval |= SPMODE_LEN(len); | |
173 | ||
e24a4d1e | 174 | if ((mpc83xx_spi->spibrg / spi->max_speed_hz) >= 64) { |
a44648b0 | 175 | pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 64) - 1; |
698ca47e | 176 | if (pm > 0x0f) { |
e24a4d1e AV |
177 | dev_err(&spi->dev, "Requested speed is too " |
178 | "low: %d Hz. Will use %d Hz instead.\n", | |
179 | spi->max_speed_hz, | |
180 | mpc83xx_spi->spibrg / 1024); | |
698ca47e CW |
181 | pm = 0x0f; |
182 | } | |
ccf06998 KG |
183 | regval |= SPMODE_PM(pm) | SPMODE_DIV16; |
184 | } else { | |
a44648b0 AV |
185 | pm = mpc83xx_spi->spibrg / (spi->max_speed_hz * 4); |
186 | if (pm) | |
187 | pm--; | |
ccf06998 KG |
188 | regval |= SPMODE_PM(pm); |
189 | } | |
190 | ||
49bb2300 AV |
191 | /* Turn off SPI unit prior changing mode */ |
192 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0); | |
ccf06998 KG |
193 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); |
194 | if (mpc83xx_spi->activate_cs) | |
195 | mpc83xx_spi->activate_cs(spi->chip_select, pol); | |
196 | } | |
197 | } | |
198 | ||
199 | static | |
200 | int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) | |
201 | { | |
202 | struct mpc83xx_spi *mpc83xx_spi; | |
203 | u32 regval; | |
204 | u8 bits_per_word; | |
205 | u32 hz; | |
206 | ||
207 | mpc83xx_spi = spi_master_get_devdata(spi->master); | |
208 | ||
209 | if (t) { | |
210 | bits_per_word = t->bits_per_word; | |
211 | hz = t->speed_hz; | |
212 | } else { | |
213 | bits_per_word = 0; | |
214 | hz = 0; | |
215 | } | |
216 | ||
217 | /* spi_transfer level calls that work per-word */ | |
218 | if (!bits_per_word) | |
219 | bits_per_word = spi->bits_per_word; | |
220 | ||
221 | /* Make sure its a bit width we support [4..16, 32] */ | |
222 | if ((bits_per_word < 4) | |
223 | || ((bits_per_word > 16) && (bits_per_word != 32))) | |
224 | return -EINVAL; | |
225 | ||
f29ba280 JT |
226 | mpc83xx_spi->rx_shift = 0; |
227 | mpc83xx_spi->tx_shift = 0; | |
ccf06998 KG |
228 | if (bits_per_word <= 8) { |
229 | mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8; | |
230 | mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8; | |
f29ba280 JT |
231 | if (mpc83xx_spi->qe_mode) { |
232 | mpc83xx_spi->rx_shift = 16; | |
233 | mpc83xx_spi->tx_shift = 24; | |
234 | } | |
ccf06998 KG |
235 | } else if (bits_per_word <= 16) { |
236 | mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16; | |
237 | mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16; | |
f29ba280 JT |
238 | if (mpc83xx_spi->qe_mode) { |
239 | mpc83xx_spi->rx_shift = 16; | |
240 | mpc83xx_spi->tx_shift = 16; | |
241 | } | |
ccf06998 KG |
242 | } else if (bits_per_word <= 32) { |
243 | mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32; | |
244 | mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32; | |
245 | } else | |
246 | return -EINVAL; | |
247 | ||
35cc0b97 AV |
248 | if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) { |
249 | mpc83xx_spi->tx_shift = 0; | |
250 | if (bits_per_word <= 8) | |
251 | mpc83xx_spi->rx_shift = 8; | |
252 | else | |
253 | mpc83xx_spi->rx_shift = 0; | |
254 | } | |
255 | ||
ccf06998 KG |
256 | /* nsecs = (clock period)/2 */ |
257 | if (!hz) | |
258 | hz = spi->max_speed_hz; | |
259 | mpc83xx_spi->nsecs = (1000000000 / 2) / hz; | |
260 | if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000) | |
261 | return -EINVAL; | |
262 | ||
263 | if (bits_per_word == 32) | |
264 | bits_per_word = 0; | |
265 | else | |
266 | bits_per_word = bits_per_word - 1; | |
267 | ||
268 | regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode); | |
269 | ||
32421daa AV |
270 | /* mask out bits we are going to set */ |
271 | regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV); | |
ccf06998 | 272 | regval |= SPMODE_LEN(bits_per_word); |
32421daa AV |
273 | if (!(spi->mode & SPI_LSB_FIRST)) |
274 | regval |= SPMODE_REV; | |
ccf06998 | 275 | |
49bb2300 AV |
276 | /* Turn off SPI unit prior changing mode */ |
277 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0); | |
ccf06998 KG |
278 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); |
279 | ||
280 | return 0; | |
281 | } | |
282 | ||
dccd573b | 283 | /* the spi->mode bits understood by this driver: */ |
2a485d7a AV |
284 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \ |
285 | | SPI_LSB_FIRST | SPI_LOOP) | |
dccd573b | 286 | |
ccf06998 KG |
287 | static int mpc83xx_spi_setup(struct spi_device *spi) |
288 | { | |
289 | struct spi_bitbang *bitbang; | |
290 | struct mpc83xx_spi *mpc83xx_spi; | |
291 | int retval; | |
292 | ||
dccd573b DB |
293 | if (spi->mode & ~MODEBITS) { |
294 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
295 | spi->mode & ~MODEBITS); | |
296 | return -EINVAL; | |
297 | } | |
298 | ||
ccf06998 KG |
299 | if (!spi->max_speed_hz) |
300 | return -EINVAL; | |
301 | ||
302 | bitbang = spi_master_get_devdata(spi->master); | |
303 | mpc83xx_spi = spi_master_get_devdata(spi->master); | |
304 | ||
305 | if (!spi->bits_per_word) | |
306 | spi->bits_per_word = 8; | |
307 | ||
308 | retval = mpc83xx_spi_setup_transfer(spi, NULL); | |
309 | if (retval < 0) | |
310 | return retval; | |
311 | ||
312 | dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n", | |
313 | __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA), | |
314 | spi->bits_per_word, 2 * mpc83xx_spi->nsecs); | |
315 | ||
316 | /* NOTE we _need_ to call chipselect() early, ideally with adapter | |
317 | * setup, unless the hardware defaults cooperate to avoid confusion | |
318 | * between normal (active low) and inverted chipselects. | |
319 | */ | |
320 | ||
321 | /* deselect chip (low or high) */ | |
322 | spin_lock(&bitbang->lock); | |
323 | if (!bitbang->busy) { | |
324 | bitbang->chipselect(spi, BITBANG_CS_INACTIVE); | |
325 | ndelay(mpc83xx_spi->nsecs); | |
326 | } | |
327 | spin_unlock(&bitbang->lock); | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t) | |
333 | { | |
334 | struct mpc83xx_spi *mpc83xx_spi; | |
335 | u32 word; | |
336 | ||
337 | mpc83xx_spi = spi_master_get_devdata(spi->master); | |
338 | ||
339 | mpc83xx_spi->tx = t->tx_buf; | |
340 | mpc83xx_spi->rx = t->rx_buf; | |
341 | mpc83xx_spi->count = t->len; | |
342 | INIT_COMPLETION(mpc83xx_spi->done); | |
343 | ||
344 | /* enable rx ints */ | |
345 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE); | |
346 | ||
347 | /* transmit word */ | |
348 | word = mpc83xx_spi->get_tx(mpc83xx_spi); | |
349 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word); | |
350 | ||
351 | wait_for_completion(&mpc83xx_spi->done); | |
352 | ||
353 | /* disable rx ints */ | |
354 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0); | |
355 | ||
356 | return t->len - mpc83xx_spi->count; | |
357 | } | |
358 | ||
7d12e780 | 359 | irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data) |
ccf06998 KG |
360 | { |
361 | struct mpc83xx_spi *mpc83xx_spi = context_data; | |
362 | u32 event; | |
363 | irqreturn_t ret = IRQ_NONE; | |
364 | ||
365 | /* Get interrupt events(tx/rx) */ | |
366 | event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event); | |
367 | ||
368 | /* We need handle RX first */ | |
369 | if (event & SPIE_NE) { | |
370 | u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive); | |
371 | ||
372 | if (mpc83xx_spi->rx) | |
373 | mpc83xx_spi->get_rx(rx_data, mpc83xx_spi); | |
374 | ||
375 | ret = IRQ_HANDLED; | |
376 | } | |
377 | ||
378 | if ((event & SPIE_NF) == 0) | |
379 | /* spin until TX is done */ | |
380 | while (((event = | |
381 | mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) & | |
382 | SPIE_NF) == 0) | |
383 | cpu_relax(); | |
384 | ||
385 | mpc83xx_spi->count -= 1; | |
386 | if (mpc83xx_spi->count) { | |
65e213cd JA |
387 | u32 word = mpc83xx_spi->get_tx(mpc83xx_spi); |
388 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word); | |
ccf06998 KG |
389 | } else { |
390 | complete(&mpc83xx_spi->done); | |
391 | } | |
392 | ||
393 | /* Clear the events */ | |
394 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event); | |
395 | ||
396 | return ret; | |
397 | } | |
398 | ||
399 | static int __init mpc83xx_spi_probe(struct platform_device *dev) | |
400 | { | |
401 | struct spi_master *master; | |
402 | struct mpc83xx_spi *mpc83xx_spi; | |
403 | struct fsl_spi_platform_data *pdata; | |
404 | struct resource *r; | |
405 | u32 regval; | |
406 | int ret = 0; | |
407 | ||
408 | /* Get resources(memory, IRQ) associated with the device */ | |
409 | master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi)); | |
410 | ||
411 | if (master == NULL) { | |
412 | ret = -ENOMEM; | |
413 | goto err; | |
414 | } | |
415 | ||
416 | platform_set_drvdata(dev, master); | |
417 | pdata = dev->dev.platform_data; | |
418 | ||
419 | if (pdata == NULL) { | |
420 | ret = -ENODEV; | |
421 | goto free_master; | |
422 | } | |
423 | ||
424 | r = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
425 | if (r == NULL) { | |
426 | ret = -ENODEV; | |
427 | goto free_master; | |
428 | } | |
ccf06998 KG |
429 | mpc83xx_spi = spi_master_get_devdata(master); |
430 | mpc83xx_spi->bitbang.master = spi_master_get(master); | |
431 | mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect; | |
432 | mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer; | |
433 | mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs; | |
ccf06998 KG |
434 | mpc83xx_spi->activate_cs = pdata->activate_cs; |
435 | mpc83xx_spi->deactivate_cs = pdata->deactivate_cs; | |
f29ba280 | 436 | mpc83xx_spi->qe_mode = pdata->qe_mode; |
ccf06998 KG |
437 | mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8; |
438 | mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8; | |
59a0ea50 | 439 | mpc83xx_spi->spibrg = pdata->sysclk; |
e24a4d1e | 440 | |
f29ba280 JT |
441 | mpc83xx_spi->rx_shift = 0; |
442 | mpc83xx_spi->tx_shift = 0; | |
443 | if (mpc83xx_spi->qe_mode) { | |
444 | mpc83xx_spi->rx_shift = 16; | |
445 | mpc83xx_spi->tx_shift = 24; | |
446 | } | |
447 | ||
ccf06998 KG |
448 | mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup; |
449 | init_completion(&mpc83xx_spi->done); | |
450 | ||
451 | mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1); | |
452 | if (mpc83xx_spi->base == NULL) { | |
453 | ret = -ENOMEM; | |
454 | goto put_master; | |
455 | } | |
456 | ||
457 | mpc83xx_spi->irq = platform_get_irq(dev, 0); | |
458 | ||
459 | if (mpc83xx_spi->irq < 0) { | |
460 | ret = -ENXIO; | |
461 | goto unmap_io; | |
462 | } | |
463 | ||
464 | /* Register for SPI Interrupt */ | |
465 | ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq, | |
466 | 0, "mpc83xx_spi", mpc83xx_spi); | |
467 | ||
468 | if (ret != 0) | |
469 | goto unmap_io; | |
470 | ||
471 | master->bus_num = pdata->bus_num; | |
472 | master->num_chipselect = pdata->max_chipselect; | |
473 | ||
474 | /* SPI controller initializations */ | |
475 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0); | |
476 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0); | |
477 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0); | |
478 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff); | |
479 | ||
480 | /* Enable SPI interface */ | |
481 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
f29ba280 JT |
482 | if (pdata->qe_mode) |
483 | regval |= SPMODE_OP; | |
484 | ||
ccf06998 KG |
485 | mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval); |
486 | ||
487 | ret = spi_bitbang_start(&mpc83xx_spi->bitbang); | |
488 | ||
489 | if (ret != 0) | |
490 | goto free_irq; | |
491 | ||
492 | printk(KERN_INFO | |
493 | "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n", | |
494 | dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq); | |
495 | ||
496 | return ret; | |
497 | ||
498 | free_irq: | |
499 | free_irq(mpc83xx_spi->irq, mpc83xx_spi); | |
500 | unmap_io: | |
501 | iounmap(mpc83xx_spi->base); | |
502 | put_master: | |
503 | spi_master_put(master); | |
504 | free_master: | |
505 | kfree(master); | |
506 | err: | |
507 | return ret; | |
508 | } | |
509 | ||
d1e44d9c | 510 | static int __exit mpc83xx_spi_remove(struct platform_device *dev) |
ccf06998 KG |
511 | { |
512 | struct mpc83xx_spi *mpc83xx_spi; | |
513 | struct spi_master *master; | |
514 | ||
515 | master = platform_get_drvdata(dev); | |
516 | mpc83xx_spi = spi_master_get_devdata(master); | |
517 | ||
518 | spi_bitbang_stop(&mpc83xx_spi->bitbang); | |
519 | free_irq(mpc83xx_spi->irq, mpc83xx_spi); | |
520 | iounmap(mpc83xx_spi->base); | |
521 | spi_master_put(mpc83xx_spi->bitbang.master); | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
fc3ba952 | 526 | MODULE_ALIAS("mpc83xx_spi"); /* for platform bus hotplug */ |
ccf06998 | 527 | static struct platform_driver mpc83xx_spi_driver = { |
d1e44d9c | 528 | .remove = __exit_p(mpc83xx_spi_remove), |
ccf06998 KG |
529 | .driver = { |
530 | .name = "mpc83xx_spi", | |
531 | }, | |
532 | }; | |
533 | ||
534 | static int __init mpc83xx_spi_init(void) | |
535 | { | |
d1e44d9c | 536 | return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe); |
ccf06998 KG |
537 | } |
538 | ||
539 | static void __exit mpc83xx_spi_exit(void) | |
540 | { | |
541 | platform_driver_unregister(&mpc83xx_spi_driver); | |
542 | } | |
543 | ||
544 | module_init(mpc83xx_spi_init); | |
545 | module_exit(mpc83xx_spi_exit); | |
546 | ||
547 | MODULE_AUTHOR("Kumar Gala"); | |
548 | MODULE_DESCRIPTION("Simple MPC83xx SPI Driver"); | |
549 | MODULE_LICENSE("GPL"); |