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7fba5340 BD |
1 | /* linux/drivers/spi/spi_s3c24xx.c |
2 | * | |
3 | * Copyright (c) 2006 Ben Dooks | |
4 | * Copyright (c) 2006 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | */ | |
12 | ||
7fba5340 BD |
13 | #include <linux/init.h> |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/workqueue.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/platform_device.h> | |
ee9c1fbf | 22 | #include <linux/gpio.h> |
1a0c220f | 23 | #include <linux/io.h> |
7fba5340 BD |
24 | |
25 | #include <linux/spi/spi.h> | |
26 | #include <linux/spi/spi_bitbang.h> | |
27 | ||
13622708 | 28 | #include <plat/regs-spi.h> |
a09e64fb | 29 | #include <mach/spi.h> |
7fba5340 BD |
30 | |
31 | struct s3c24xx_spi { | |
32 | /* bitbang has to be first */ | |
33 | struct spi_bitbang bitbang; | |
34 | struct completion done; | |
35 | ||
36 | void __iomem *regs; | |
37 | int irq; | |
38 | int len; | |
39 | int count; | |
40 | ||
6c912a3d | 41 | void (*set_cs)(struct s3c2410_spi_info *spi, |
8736b927 BD |
42 | int cs, int pol); |
43 | ||
7fba5340 BD |
44 | /* data buffers */ |
45 | const unsigned char *tx; | |
46 | unsigned char *rx; | |
47 | ||
48 | struct clk *clk; | |
49 | struct resource *ioarea; | |
50 | struct spi_master *master; | |
51 | struct spi_device *curdev; | |
52 | struct device *dev; | |
53 | struct s3c2410_spi_info *pdata; | |
54 | }; | |
55 | ||
56 | #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) | |
57 | #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) | |
58 | ||
59 | static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) | |
60 | { | |
61 | return spi_master_get_devdata(sdev->master); | |
62 | } | |
63 | ||
8736b927 BD |
64 | static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) |
65 | { | |
ee9c1fbf | 66 | gpio_set_value(spi->pin_cs, pol); |
8736b927 BD |
67 | } |
68 | ||
7fba5340 BD |
69 | static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) |
70 | { | |
71 | struct s3c24xx_spi *hw = to_hw(spi); | |
72 | unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
73 | unsigned int spcon; | |
74 | ||
75 | switch (value) { | |
76 | case BITBANG_CS_INACTIVE: | |
3d2c5b41 | 77 | hw->set_cs(hw->pdata, spi->chip_select, cspol^1); |
7fba5340 BD |
78 | break; |
79 | ||
80 | case BITBANG_CS_ACTIVE: | |
81 | spcon = readb(hw->regs + S3C2410_SPCON); | |
82 | ||
83 | if (spi->mode & SPI_CPHA) | |
84 | spcon |= S3C2410_SPCON_CPHA_FMTB; | |
85 | else | |
86 | spcon &= ~S3C2410_SPCON_CPHA_FMTB; | |
87 | ||
88 | if (spi->mode & SPI_CPOL) | |
89 | spcon |= S3C2410_SPCON_CPOL_HIGH; | |
90 | else | |
91 | spcon &= ~S3C2410_SPCON_CPOL_HIGH; | |
92 | ||
93 | spcon |= S3C2410_SPCON_ENSCK; | |
94 | ||
95 | /* write new configration */ | |
96 | ||
97 | writeb(spcon, hw->regs + S3C2410_SPCON); | |
3d2c5b41 | 98 | hw->set_cs(hw->pdata, spi->chip_select, cspol); |
7fba5340 BD |
99 | |
100 | break; | |
7fba5340 BD |
101 | } |
102 | } | |
103 | ||
104 | static int s3c24xx_spi_setupxfer(struct spi_device *spi, | |
105 | struct spi_transfer *t) | |
106 | { | |
107 | struct s3c24xx_spi *hw = to_hw(spi); | |
108 | unsigned int bpw; | |
109 | unsigned int hz; | |
110 | unsigned int div; | |
b8978784 | 111 | unsigned long clk; |
7fba5340 BD |
112 | |
113 | bpw = t ? t->bits_per_word : spi->bits_per_word; | |
114 | hz = t ? t->speed_hz : spi->max_speed_hz; | |
115 | ||
19152975 BD |
116 | if (!bpw) |
117 | bpw = 8; | |
118 | ||
119 | if (!hz) | |
120 | hz = spi->max_speed_hz; | |
121 | ||
7fba5340 BD |
122 | if (bpw != 8) { |
123 | dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw); | |
124 | return -EINVAL; | |
125 | } | |
126 | ||
b8978784 BD |
127 | clk = clk_get_rate(hw->clk); |
128 | div = DIV_ROUND_UP(clk, hz * 2) - 1; | |
7fba5340 BD |
129 | |
130 | if (div > 255) | |
131 | div = 255; | |
132 | ||
b8978784 BD |
133 | dev_dbg(&spi->dev, "setting pre-scaler to %d (wanted %d, got %ld)\n", |
134 | div, hz, clk / (2 * (div + 1))); | |
135 | ||
136 | ||
7fba5340 BD |
137 | writeb(div, hw->regs + S3C2410_SPPRE); |
138 | ||
139 | spin_lock(&hw->bitbang.lock); | |
140 | if (!hw->bitbang.busy) { | |
141 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
142 | /* need to ndelay for 0.5 clocktick ? */ | |
143 | } | |
144 | spin_unlock(&hw->bitbang.lock); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | static int s3c24xx_spi_setup(struct spi_device *spi) | |
150 | { | |
151 | int ret; | |
152 | ||
7fba5340 BD |
153 | ret = s3c24xx_spi_setupxfer(spi, NULL); |
154 | if (ret < 0) { | |
155 | dev_err(&spi->dev, "setupxfer returned %d\n", ret); | |
156 | return ret; | |
157 | } | |
158 | ||
7fba5340 BD |
159 | return 0; |
160 | } | |
161 | ||
162 | static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) | |
163 | { | |
4b1badf5 | 164 | return hw->tx ? hw->tx[count] : 0; |
7fba5340 BD |
165 | } |
166 | ||
167 | static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
168 | { | |
169 | struct s3c24xx_spi *hw = to_hw(spi); | |
170 | ||
171 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", | |
172 | t->tx_buf, t->rx_buf, t->len); | |
173 | ||
174 | hw->tx = t->tx_buf; | |
175 | hw->rx = t->rx_buf; | |
176 | hw->len = t->len; | |
177 | hw->count = 0; | |
178 | ||
4bb5eba0 BD |
179 | init_completion(&hw->done); |
180 | ||
7fba5340 BD |
181 | /* send the first byte */ |
182 | writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); | |
4bb5eba0 | 183 | |
7fba5340 BD |
184 | wait_for_completion(&hw->done); |
185 | ||
186 | return hw->count; | |
187 | } | |
188 | ||
7d12e780 | 189 | static irqreturn_t s3c24xx_spi_irq(int irq, void *dev) |
7fba5340 BD |
190 | { |
191 | struct s3c24xx_spi *hw = dev; | |
192 | unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); | |
193 | unsigned int count = hw->count; | |
194 | ||
195 | if (spsta & S3C2410_SPSTA_DCOL) { | |
196 | dev_dbg(hw->dev, "data-collision\n"); | |
197 | complete(&hw->done); | |
198 | goto irq_done; | |
199 | } | |
200 | ||
201 | if (!(spsta & S3C2410_SPSTA_READY)) { | |
202 | dev_dbg(hw->dev, "spi not ready for tx?\n"); | |
203 | complete(&hw->done); | |
204 | goto irq_done; | |
205 | } | |
206 | ||
207 | hw->count++; | |
208 | ||
209 | if (hw->rx) | |
210 | hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); | |
211 | ||
212 | count++; | |
213 | ||
214 | if (count < hw->len) | |
215 | writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); | |
216 | else | |
217 | complete(&hw->done); | |
218 | ||
219 | irq_done: | |
220 | return IRQ_HANDLED; | |
221 | } | |
222 | ||
5aa6cf30 BD |
223 | static void s3c24xx_spi_initialsetup(struct s3c24xx_spi *hw) |
224 | { | |
225 | /* for the moment, permanently enable the clock */ | |
226 | ||
227 | clk_enable(hw->clk); | |
228 | ||
229 | /* program defaults into the registers */ | |
230 | ||
231 | writeb(0xff, hw->regs + S3C2410_SPPRE); | |
232 | writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); | |
233 | writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); | |
cf46b973 | 234 | |
ee9c1fbf BD |
235 | if (hw->pdata) { |
236 | if (hw->set_cs == s3c24xx_spi_gpiocs) | |
237 | gpio_direction_output(hw->pdata->pin_cs, 1); | |
238 | ||
239 | if (hw->pdata->gpio_setup) | |
240 | hw->pdata->gpio_setup(hw->pdata, 1); | |
241 | } | |
5aa6cf30 BD |
242 | } |
243 | ||
d1e44d9c | 244 | static int __init s3c24xx_spi_probe(struct platform_device *pdev) |
7fba5340 | 245 | { |
50f426b5 | 246 | struct s3c2410_spi_info *pdata; |
7fba5340 BD |
247 | struct s3c24xx_spi *hw; |
248 | struct spi_master *master; | |
7fba5340 BD |
249 | struct resource *res; |
250 | int err = 0; | |
7fba5340 BD |
251 | |
252 | master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); | |
253 | if (master == NULL) { | |
254 | dev_err(&pdev->dev, "No memory for spi_master\n"); | |
255 | err = -ENOMEM; | |
256 | goto err_nomem; | |
257 | } | |
258 | ||
259 | hw = spi_master_get_devdata(master); | |
260 | memset(hw, 0, sizeof(struct s3c24xx_spi)); | |
261 | ||
262 | hw->master = spi_master_get(master); | |
50f426b5 | 263 | hw->pdata = pdata = pdev->dev.platform_data; |
7fba5340 BD |
264 | hw->dev = &pdev->dev; |
265 | ||
50f426b5 | 266 | if (pdata == NULL) { |
7fba5340 BD |
267 | dev_err(&pdev->dev, "No platform data supplied\n"); |
268 | err = -ENOENT; | |
269 | goto err_no_pdata; | |
270 | } | |
271 | ||
272 | platform_set_drvdata(pdev, hw); | |
273 | init_completion(&hw->done); | |
274 | ||
d1e77806 BD |
275 | /* setup the master state. */ |
276 | ||
e7db06b5 DB |
277 | /* the spi->mode bits understood by this driver: */ |
278 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; | |
279 | ||
d1e77806 | 280 | master->num_chipselect = hw->pdata->num_cs; |
cb1d0a7a | 281 | master->bus_num = pdata->bus_num; |
d1e77806 | 282 | |
7fba5340 BD |
283 | /* setup the state for the bitbang driver */ |
284 | ||
285 | hw->bitbang.master = hw->master; | |
286 | hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; | |
287 | hw->bitbang.chipselect = s3c24xx_spi_chipsel; | |
288 | hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; | |
289 | hw->bitbang.master->setup = s3c24xx_spi_setup; | |
290 | ||
291 | dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); | |
292 | ||
293 | /* find and map our resources */ | |
294 | ||
295 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
296 | if (res == NULL) { | |
297 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
298 | err = -ENOENT; | |
299 | goto err_no_iores; | |
300 | } | |
301 | ||
302 | hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1, | |
303 | pdev->name); | |
304 | ||
305 | if (hw->ioarea == NULL) { | |
306 | dev_err(&pdev->dev, "Cannot reserve region\n"); | |
307 | err = -ENXIO; | |
308 | goto err_no_iores; | |
309 | } | |
310 | ||
311 | hw->regs = ioremap(res->start, (res->end - res->start)+1); | |
312 | if (hw->regs == NULL) { | |
313 | dev_err(&pdev->dev, "Cannot map IO\n"); | |
314 | err = -ENXIO; | |
315 | goto err_no_iomap; | |
316 | } | |
317 | ||
318 | hw->irq = platform_get_irq(pdev, 0); | |
319 | if (hw->irq < 0) { | |
320 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
321 | err = -ENOENT; | |
322 | goto err_no_irq; | |
323 | } | |
324 | ||
325 | err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw); | |
326 | if (err) { | |
327 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
328 | goto err_no_irq; | |
329 | } | |
330 | ||
331 | hw->clk = clk_get(&pdev->dev, "spi"); | |
332 | if (IS_ERR(hw->clk)) { | |
333 | dev_err(&pdev->dev, "No clock for device\n"); | |
334 | err = PTR_ERR(hw->clk); | |
335 | goto err_no_clk; | |
336 | } | |
337 | ||
7fba5340 BD |
338 | /* setup any gpio we can */ |
339 | ||
50f426b5 | 340 | if (!pdata->set_cs) { |
ee9c1fbf BD |
341 | if (pdata->pin_cs < 0) { |
342 | dev_err(&pdev->dev, "No chipselect pin\n"); | |
343 | goto err_register; | |
344 | } | |
8736b927 | 345 | |
ee9c1fbf BD |
346 | err = gpio_request(pdata->pin_cs, dev_name(&pdev->dev)); |
347 | if (err) { | |
348 | dev_err(&pdev->dev, "Failed to get gpio for cs\n"); | |
349 | goto err_register; | |
350 | } | |
351 | ||
352 | hw->set_cs = s3c24xx_spi_gpiocs; | |
353 | gpio_direction_output(pdata->pin_cs, 1); | |
8736b927 | 354 | } else |
50f426b5 | 355 | hw->set_cs = pdata->set_cs; |
7fba5340 | 356 | |
ee9c1fbf BD |
357 | s3c24xx_spi_initialsetup(hw); |
358 | ||
7fba5340 BD |
359 | /* register our spi controller */ |
360 | ||
361 | err = spi_bitbang_start(&hw->bitbang); | |
362 | if (err) { | |
363 | dev_err(&pdev->dev, "Failed to register SPI master\n"); | |
364 | goto err_register; | |
365 | } | |
366 | ||
7fba5340 BD |
367 | return 0; |
368 | ||
369 | err_register: | |
ee9c1fbf BD |
370 | if (hw->set_cs == s3c24xx_spi_gpiocs) |
371 | gpio_free(pdata->pin_cs); | |
372 | ||
7fba5340 BD |
373 | clk_disable(hw->clk); |
374 | clk_put(hw->clk); | |
375 | ||
376 | err_no_clk: | |
377 | free_irq(hw->irq, hw); | |
378 | ||
379 | err_no_irq: | |
380 | iounmap(hw->regs); | |
381 | ||
382 | err_no_iomap: | |
383 | release_resource(hw->ioarea); | |
384 | kfree(hw->ioarea); | |
385 | ||
386 | err_no_iores: | |
387 | err_no_pdata: | |
a419aef8 | 388 | spi_master_put(hw->master); |
7fba5340 BD |
389 | |
390 | err_nomem: | |
391 | return err; | |
392 | } | |
393 | ||
d1e44d9c | 394 | static int __exit s3c24xx_spi_remove(struct platform_device *dev) |
7fba5340 BD |
395 | { |
396 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); | |
397 | ||
398 | platform_set_drvdata(dev, NULL); | |
399 | ||
400 | spi_unregister_master(hw->master); | |
401 | ||
402 | clk_disable(hw->clk); | |
403 | clk_put(hw->clk); | |
404 | ||
405 | free_irq(hw->irq, hw); | |
406 | iounmap(hw->regs); | |
407 | ||
ee9c1fbf BD |
408 | if (hw->set_cs == s3c24xx_spi_gpiocs) |
409 | gpio_free(hw->pdata->pin_cs); | |
410 | ||
7fba5340 BD |
411 | release_resource(hw->ioarea); |
412 | kfree(hw->ioarea); | |
413 | ||
414 | spi_master_put(hw->master); | |
415 | return 0; | |
416 | } | |
417 | ||
418 | ||
419 | #ifdef CONFIG_PM | |
420 | ||
421 | static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg) | |
422 | { | |
ac88bcff | 423 | struct s3c24xx_spi *hw = platform_get_drvdata(pdev); |
7fba5340 | 424 | |
cf46b973 BD |
425 | if (hw->pdata && hw->pdata->gpio_setup) |
426 | hw->pdata->gpio_setup(hw->pdata, 0); | |
427 | ||
7fba5340 BD |
428 | clk_disable(hw->clk); |
429 | return 0; | |
430 | } | |
431 | ||
432 | static int s3c24xx_spi_resume(struct platform_device *pdev) | |
433 | { | |
ac88bcff | 434 | struct s3c24xx_spi *hw = platform_get_drvdata(pdev); |
7fba5340 | 435 | |
5aa6cf30 | 436 | s3c24xx_spi_initialsetup(hw); |
7fba5340 BD |
437 | return 0; |
438 | } | |
439 | ||
440 | #else | |
441 | #define s3c24xx_spi_suspend NULL | |
442 | #define s3c24xx_spi_resume NULL | |
443 | #endif | |
444 | ||
7e38c3c4 | 445 | MODULE_ALIAS("platform:s3c2410-spi"); |
42cde430 | 446 | static struct platform_driver s3c24xx_spi_driver = { |
d1e44d9c | 447 | .remove = __exit_p(s3c24xx_spi_remove), |
7fba5340 BD |
448 | .suspend = s3c24xx_spi_suspend, |
449 | .resume = s3c24xx_spi_resume, | |
450 | .driver = { | |
451 | .name = "s3c2410-spi", | |
452 | .owner = THIS_MODULE, | |
453 | }, | |
454 | }; | |
455 | ||
456 | static int __init s3c24xx_spi_init(void) | |
457 | { | |
42cde430 | 458 | return platform_driver_probe(&s3c24xx_spi_driver, s3c24xx_spi_probe); |
7fba5340 BD |
459 | } |
460 | ||
461 | static void __exit s3c24xx_spi_exit(void) | |
462 | { | |
42cde430 | 463 | platform_driver_unregister(&s3c24xx_spi_driver); |
7fba5340 BD |
464 | } |
465 | ||
466 | module_init(s3c24xx_spi_init); | |
467 | module_exit(s3c24xx_spi_exit); | |
468 | ||
469 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); | |
470 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
471 | MODULE_LICENSE("GPL"); |