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7fba5340 BD |
1 | /* linux/drivers/spi/spi_s3c24xx.c |
2 | * | |
3 | * Copyright (c) 2006 Ben Dooks | |
4 | * Copyright (c) 2006 Simtec Electronics | |
5 | * Ben Dooks <ben@simtec.co.uk> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | */ | |
12 | ||
7fba5340 BD |
13 | #include <linux/init.h> |
14 | #include <linux/spinlock.h> | |
15 | #include <linux/workqueue.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/clk.h> | |
21 | #include <linux/platform_device.h> | |
22 | ||
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/spi/spi_bitbang.h> | |
25 | ||
26 | #include <asm/io.h> | |
27 | #include <asm/dma.h> | |
28 | #include <asm/hardware.h> | |
29 | ||
30 | #include <asm/arch/regs-gpio.h> | |
47572b84 | 31 | #include <asm/plat-s3c24xx/regs-spi.h> |
7fba5340 BD |
32 | #include <asm/arch/spi.h> |
33 | ||
34 | struct s3c24xx_spi { | |
35 | /* bitbang has to be first */ | |
36 | struct spi_bitbang bitbang; | |
37 | struct completion done; | |
38 | ||
39 | void __iomem *regs; | |
40 | int irq; | |
41 | int len; | |
42 | int count; | |
43 | ||
6c912a3d | 44 | void (*set_cs)(struct s3c2410_spi_info *spi, |
8736b927 BD |
45 | int cs, int pol); |
46 | ||
7fba5340 BD |
47 | /* data buffers */ |
48 | const unsigned char *tx; | |
49 | unsigned char *rx; | |
50 | ||
51 | struct clk *clk; | |
52 | struct resource *ioarea; | |
53 | struct spi_master *master; | |
54 | struct spi_device *curdev; | |
55 | struct device *dev; | |
56 | struct s3c2410_spi_info *pdata; | |
57 | }; | |
58 | ||
59 | #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT) | |
60 | #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP) | |
61 | ||
62 | static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev) | |
63 | { | |
64 | return spi_master_get_devdata(sdev->master); | |
65 | } | |
66 | ||
8736b927 BD |
67 | static void s3c24xx_spi_gpiocs(struct s3c2410_spi_info *spi, int cs, int pol) |
68 | { | |
69 | s3c2410_gpio_setpin(spi->pin_cs, pol); | |
70 | } | |
71 | ||
7fba5340 BD |
72 | static void s3c24xx_spi_chipsel(struct spi_device *spi, int value) |
73 | { | |
74 | struct s3c24xx_spi *hw = to_hw(spi); | |
75 | unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0; | |
76 | unsigned int spcon; | |
77 | ||
78 | switch (value) { | |
79 | case BITBANG_CS_INACTIVE: | |
3d2c5b41 | 80 | hw->set_cs(hw->pdata, spi->chip_select, cspol^1); |
7fba5340 BD |
81 | break; |
82 | ||
83 | case BITBANG_CS_ACTIVE: | |
84 | spcon = readb(hw->regs + S3C2410_SPCON); | |
85 | ||
86 | if (spi->mode & SPI_CPHA) | |
87 | spcon |= S3C2410_SPCON_CPHA_FMTB; | |
88 | else | |
89 | spcon &= ~S3C2410_SPCON_CPHA_FMTB; | |
90 | ||
91 | if (spi->mode & SPI_CPOL) | |
92 | spcon |= S3C2410_SPCON_CPOL_HIGH; | |
93 | else | |
94 | spcon &= ~S3C2410_SPCON_CPOL_HIGH; | |
95 | ||
96 | spcon |= S3C2410_SPCON_ENSCK; | |
97 | ||
98 | /* write new configration */ | |
99 | ||
100 | writeb(spcon, hw->regs + S3C2410_SPCON); | |
3d2c5b41 | 101 | hw->set_cs(hw->pdata, spi->chip_select, cspol); |
7fba5340 BD |
102 | |
103 | break; | |
7fba5340 BD |
104 | } |
105 | } | |
106 | ||
107 | static int s3c24xx_spi_setupxfer(struct spi_device *spi, | |
108 | struct spi_transfer *t) | |
109 | { | |
110 | struct s3c24xx_spi *hw = to_hw(spi); | |
111 | unsigned int bpw; | |
112 | unsigned int hz; | |
113 | unsigned int div; | |
114 | ||
115 | bpw = t ? t->bits_per_word : spi->bits_per_word; | |
116 | hz = t ? t->speed_hz : spi->max_speed_hz; | |
117 | ||
118 | if (bpw != 8) { | |
119 | dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw); | |
120 | return -EINVAL; | |
121 | } | |
122 | ||
123 | div = clk_get_rate(hw->clk) / hz; | |
124 | ||
125 | /* is clk = pclk / (2 * (pre+1)), or is it | |
126 | * clk = (pclk * 2) / ( pre + 1) */ | |
127 | ||
128 | div = (div / 2) - 1; | |
129 | ||
130 | if (div < 0) | |
131 | div = 1; | |
132 | ||
133 | if (div > 255) | |
134 | div = 255; | |
135 | ||
136 | dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz); | |
137 | writeb(div, hw->regs + S3C2410_SPPRE); | |
138 | ||
139 | spin_lock(&hw->bitbang.lock); | |
140 | if (!hw->bitbang.busy) { | |
141 | hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); | |
142 | /* need to ndelay for 0.5 clocktick ? */ | |
143 | } | |
144 | spin_unlock(&hw->bitbang.lock); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
dccd573b DB |
149 | /* the spi->mode bits understood by this driver: */ |
150 | #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH) | |
151 | ||
7fba5340 BD |
152 | static int s3c24xx_spi_setup(struct spi_device *spi) |
153 | { | |
154 | int ret; | |
155 | ||
156 | if (!spi->bits_per_word) | |
157 | spi->bits_per_word = 8; | |
158 | ||
dccd573b DB |
159 | if (spi->mode & ~MODEBITS) { |
160 | dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n", | |
161 | spi->mode & ~MODEBITS); | |
7fba5340 | 162 | return -EINVAL; |
dccd573b | 163 | } |
7fba5340 BD |
164 | |
165 | ret = s3c24xx_spi_setupxfer(spi, NULL); | |
166 | if (ret < 0) { | |
167 | dev_err(&spi->dev, "setupxfer returned %d\n", ret); | |
168 | return ret; | |
169 | } | |
170 | ||
171 | dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", | |
172 | __FUNCTION__, spi->mode, spi->bits_per_word, | |
173 | spi->max_speed_hz); | |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
178 | static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count) | |
179 | { | |
4b1badf5 | 180 | return hw->tx ? hw->tx[count] : 0; |
7fba5340 BD |
181 | } |
182 | ||
183 | static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t) | |
184 | { | |
185 | struct s3c24xx_spi *hw = to_hw(spi); | |
186 | ||
187 | dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n", | |
188 | t->tx_buf, t->rx_buf, t->len); | |
189 | ||
190 | hw->tx = t->tx_buf; | |
191 | hw->rx = t->rx_buf; | |
192 | hw->len = t->len; | |
193 | hw->count = 0; | |
194 | ||
4bb5eba0 BD |
195 | init_completion(&hw->done); |
196 | ||
7fba5340 BD |
197 | /* send the first byte */ |
198 | writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT); | |
4bb5eba0 | 199 | |
7fba5340 BD |
200 | wait_for_completion(&hw->done); |
201 | ||
202 | return hw->count; | |
203 | } | |
204 | ||
7d12e780 | 205 | static irqreturn_t s3c24xx_spi_irq(int irq, void *dev) |
7fba5340 BD |
206 | { |
207 | struct s3c24xx_spi *hw = dev; | |
208 | unsigned int spsta = readb(hw->regs + S3C2410_SPSTA); | |
209 | unsigned int count = hw->count; | |
210 | ||
211 | if (spsta & S3C2410_SPSTA_DCOL) { | |
212 | dev_dbg(hw->dev, "data-collision\n"); | |
213 | complete(&hw->done); | |
214 | goto irq_done; | |
215 | } | |
216 | ||
217 | if (!(spsta & S3C2410_SPSTA_READY)) { | |
218 | dev_dbg(hw->dev, "spi not ready for tx?\n"); | |
219 | complete(&hw->done); | |
220 | goto irq_done; | |
221 | } | |
222 | ||
223 | hw->count++; | |
224 | ||
225 | if (hw->rx) | |
226 | hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT); | |
227 | ||
228 | count++; | |
229 | ||
230 | if (count < hw->len) | |
231 | writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT); | |
232 | else | |
233 | complete(&hw->done); | |
234 | ||
235 | irq_done: | |
236 | return IRQ_HANDLED; | |
237 | } | |
238 | ||
d1e44d9c | 239 | static int __init s3c24xx_spi_probe(struct platform_device *pdev) |
7fba5340 BD |
240 | { |
241 | struct s3c24xx_spi *hw; | |
242 | struct spi_master *master; | |
7fba5340 BD |
243 | struct resource *res; |
244 | int err = 0; | |
7fba5340 BD |
245 | |
246 | master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi)); | |
247 | if (master == NULL) { | |
248 | dev_err(&pdev->dev, "No memory for spi_master\n"); | |
249 | err = -ENOMEM; | |
250 | goto err_nomem; | |
251 | } | |
252 | ||
253 | hw = spi_master_get_devdata(master); | |
254 | memset(hw, 0, sizeof(struct s3c24xx_spi)); | |
255 | ||
256 | hw->master = spi_master_get(master); | |
257 | hw->pdata = pdev->dev.platform_data; | |
258 | hw->dev = &pdev->dev; | |
259 | ||
260 | if (hw->pdata == NULL) { | |
261 | dev_err(&pdev->dev, "No platform data supplied\n"); | |
262 | err = -ENOENT; | |
263 | goto err_no_pdata; | |
264 | } | |
265 | ||
266 | platform_set_drvdata(pdev, hw); | |
267 | init_completion(&hw->done); | |
268 | ||
269 | /* setup the state for the bitbang driver */ | |
270 | ||
271 | hw->bitbang.master = hw->master; | |
272 | hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer; | |
273 | hw->bitbang.chipselect = s3c24xx_spi_chipsel; | |
274 | hw->bitbang.txrx_bufs = s3c24xx_spi_txrx; | |
275 | hw->bitbang.master->setup = s3c24xx_spi_setup; | |
276 | ||
277 | dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang); | |
278 | ||
279 | /* find and map our resources */ | |
280 | ||
281 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
282 | if (res == NULL) { | |
283 | dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n"); | |
284 | err = -ENOENT; | |
285 | goto err_no_iores; | |
286 | } | |
287 | ||
288 | hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1, | |
289 | pdev->name); | |
290 | ||
291 | if (hw->ioarea == NULL) { | |
292 | dev_err(&pdev->dev, "Cannot reserve region\n"); | |
293 | err = -ENXIO; | |
294 | goto err_no_iores; | |
295 | } | |
296 | ||
297 | hw->regs = ioremap(res->start, (res->end - res->start)+1); | |
298 | if (hw->regs == NULL) { | |
299 | dev_err(&pdev->dev, "Cannot map IO\n"); | |
300 | err = -ENXIO; | |
301 | goto err_no_iomap; | |
302 | } | |
303 | ||
304 | hw->irq = platform_get_irq(pdev, 0); | |
305 | if (hw->irq < 0) { | |
306 | dev_err(&pdev->dev, "No IRQ specified\n"); | |
307 | err = -ENOENT; | |
308 | goto err_no_irq; | |
309 | } | |
310 | ||
311 | err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw); | |
312 | if (err) { | |
313 | dev_err(&pdev->dev, "Cannot claim IRQ\n"); | |
314 | goto err_no_irq; | |
315 | } | |
316 | ||
317 | hw->clk = clk_get(&pdev->dev, "spi"); | |
318 | if (IS_ERR(hw->clk)) { | |
319 | dev_err(&pdev->dev, "No clock for device\n"); | |
320 | err = PTR_ERR(hw->clk); | |
321 | goto err_no_clk; | |
322 | } | |
323 | ||
324 | /* for the moment, permanently enable the clock */ | |
325 | ||
326 | clk_enable(hw->clk); | |
327 | ||
328 | /* program defaults into the registers */ | |
329 | ||
330 | writeb(0xff, hw->regs + S3C2410_SPPRE); | |
331 | writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN); | |
332 | writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON); | |
333 | ||
334 | /* setup any gpio we can */ | |
335 | ||
336 | if (!hw->pdata->set_cs) { | |
8736b927 BD |
337 | hw->set_cs = s3c24xx_spi_gpiocs; |
338 | ||
7fba5340 BD |
339 | s3c2410_gpio_setpin(hw->pdata->pin_cs, 1); |
340 | s3c2410_gpio_cfgpin(hw->pdata->pin_cs, S3C2410_GPIO_OUTPUT); | |
8736b927 BD |
341 | } else |
342 | hw->set_cs = hw->pdata->set_cs; | |
7fba5340 BD |
343 | |
344 | /* register our spi controller */ | |
345 | ||
346 | err = spi_bitbang_start(&hw->bitbang); | |
347 | if (err) { | |
348 | dev_err(&pdev->dev, "Failed to register SPI master\n"); | |
349 | goto err_register; | |
350 | } | |
351 | ||
7fba5340 BD |
352 | return 0; |
353 | ||
354 | err_register: | |
355 | clk_disable(hw->clk); | |
356 | clk_put(hw->clk); | |
357 | ||
358 | err_no_clk: | |
359 | free_irq(hw->irq, hw); | |
360 | ||
361 | err_no_irq: | |
362 | iounmap(hw->regs); | |
363 | ||
364 | err_no_iomap: | |
365 | release_resource(hw->ioarea); | |
366 | kfree(hw->ioarea); | |
367 | ||
368 | err_no_iores: | |
369 | err_no_pdata: | |
370 | spi_master_put(hw->master);; | |
371 | ||
372 | err_nomem: | |
373 | return err; | |
374 | } | |
375 | ||
d1e44d9c | 376 | static int __exit s3c24xx_spi_remove(struct platform_device *dev) |
7fba5340 BD |
377 | { |
378 | struct s3c24xx_spi *hw = platform_get_drvdata(dev); | |
379 | ||
380 | platform_set_drvdata(dev, NULL); | |
381 | ||
382 | spi_unregister_master(hw->master); | |
383 | ||
384 | clk_disable(hw->clk); | |
385 | clk_put(hw->clk); | |
386 | ||
387 | free_irq(hw->irq, hw); | |
388 | iounmap(hw->regs); | |
389 | ||
390 | release_resource(hw->ioarea); | |
391 | kfree(hw->ioarea); | |
392 | ||
393 | spi_master_put(hw->master); | |
394 | return 0; | |
395 | } | |
396 | ||
397 | ||
398 | #ifdef CONFIG_PM | |
399 | ||
400 | static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg) | |
401 | { | |
ac88bcff | 402 | struct s3c24xx_spi *hw = platform_get_drvdata(pdev); |
7fba5340 BD |
403 | |
404 | clk_disable(hw->clk); | |
405 | return 0; | |
406 | } | |
407 | ||
408 | static int s3c24xx_spi_resume(struct platform_device *pdev) | |
409 | { | |
ac88bcff | 410 | struct s3c24xx_spi *hw = platform_get_drvdata(pdev); |
7fba5340 BD |
411 | |
412 | clk_enable(hw->clk); | |
413 | return 0; | |
414 | } | |
415 | ||
416 | #else | |
417 | #define s3c24xx_spi_suspend NULL | |
418 | #define s3c24xx_spi_resume NULL | |
419 | #endif | |
420 | ||
7e38c3c4 | 421 | MODULE_ALIAS("platform:s3c2410-spi"); |
7fba5340 | 422 | static struct platform_driver s3c24xx_spidrv = { |
d1e44d9c | 423 | .remove = __exit_p(s3c24xx_spi_remove), |
7fba5340 BD |
424 | .suspend = s3c24xx_spi_suspend, |
425 | .resume = s3c24xx_spi_resume, | |
426 | .driver = { | |
427 | .name = "s3c2410-spi", | |
428 | .owner = THIS_MODULE, | |
429 | }, | |
430 | }; | |
431 | ||
432 | static int __init s3c24xx_spi_init(void) | |
433 | { | |
d1e44d9c | 434 | return platform_driver_probe(&s3c24xx_spidrv, s3c24xx_spi_probe); |
7fba5340 BD |
435 | } |
436 | ||
437 | static void __exit s3c24xx_spi_exit(void) | |
438 | { | |
439 | platform_driver_unregister(&s3c24xx_spidrv); | |
440 | } | |
441 | ||
442 | module_init(s3c24xx_spi_init); | |
443 | module_exit(s3c24xx_spi_exit); | |
444 | ||
445 | MODULE_DESCRIPTION("S3C24XX SPI Driver"); | |
446 | MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>"); | |
447 | MODULE_LICENSE("GPL"); |