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f2cac67d AN |
1 | /* |
2 | * spi_txx9.c - TXx9 SPI controller driver. | |
3 | * | |
4 | * Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c | |
5 | * Copyright (C) 2000-2001 Toshiba Corporation | |
6 | * | |
7 | * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the | |
8 | * terms of the GNU General Public License version 2. This program is | |
9 | * licensed "as is" without any warranty of any kind, whether express | |
10 | * or implied. | |
11 | * | |
12 | * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) | |
13 | * | |
14 | * Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp) | |
15 | */ | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/spinlock.h> | |
23 | #include <linux/workqueue.h> | |
24 | #include <linux/spi/spi.h> | |
25 | #include <linux/err.h> | |
26 | #include <linux/clk.h> | |
ba0a7f39 | 27 | #include <linux/io.h> |
f2cac67d AN |
28 | #include <asm/gpio.h> |
29 | ||
30 | ||
31 | #define SPI_FIFO_SIZE 4 | |
32 | ||
33 | #define TXx9_SPMCR 0x00 | |
34 | #define TXx9_SPCR0 0x04 | |
35 | #define TXx9_SPCR1 0x08 | |
36 | #define TXx9_SPFS 0x0c | |
37 | #define TXx9_SPSR 0x14 | |
38 | #define TXx9_SPDR 0x18 | |
39 | ||
40 | /* SPMCR : SPI Master Control */ | |
41 | #define TXx9_SPMCR_OPMODE 0xc0 | |
42 | #define TXx9_SPMCR_CONFIG 0x40 | |
43 | #define TXx9_SPMCR_ACTIVE 0x80 | |
44 | #define TXx9_SPMCR_SPSTP 0x02 | |
45 | #define TXx9_SPMCR_BCLR 0x01 | |
46 | ||
47 | /* SPCR0 : SPI Control 0 */ | |
48 | #define TXx9_SPCR0_TXIFL_MASK 0xc000 | |
49 | #define TXx9_SPCR0_RXIFL_MASK 0x3000 | |
50 | #define TXx9_SPCR0_SIDIE 0x0800 | |
51 | #define TXx9_SPCR0_SOEIE 0x0400 | |
52 | #define TXx9_SPCR0_RBSIE 0x0200 | |
53 | #define TXx9_SPCR0_TBSIE 0x0100 | |
54 | #define TXx9_SPCR0_IFSPSE 0x0010 | |
55 | #define TXx9_SPCR0_SBOS 0x0004 | |
56 | #define TXx9_SPCR0_SPHA 0x0002 | |
57 | #define TXx9_SPCR0_SPOL 0x0001 | |
58 | ||
59 | /* SPSR : SPI Status */ | |
60 | #define TXx9_SPSR_TBSI 0x8000 | |
61 | #define TXx9_SPSR_RBSI 0x4000 | |
62 | #define TXx9_SPSR_TBS_MASK 0x3800 | |
63 | #define TXx9_SPSR_RBS_MASK 0x0700 | |
64 | #define TXx9_SPSR_SPOE 0x0080 | |
65 | #define TXx9_SPSR_IFSD 0x0008 | |
66 | #define TXx9_SPSR_SIDLE 0x0004 | |
67 | #define TXx9_SPSR_STRDY 0x0002 | |
68 | #define TXx9_SPSR_SRRDY 0x0001 | |
69 | ||
70 | ||
71 | struct txx9spi { | |
72 | struct workqueue_struct *workqueue; | |
73 | struct work_struct work; | |
74 | spinlock_t lock; /* protect 'queue' */ | |
75 | struct list_head queue; | |
76 | wait_queue_head_t waitq; | |
77 | void __iomem *membase; | |
f2cac67d AN |
78 | int baseclk; |
79 | struct clk *clk; | |
80 | u32 max_speed_hz, min_speed_hz; | |
81 | int last_chipselect; | |
82 | int last_chipselect_val; | |
83 | }; | |
84 | ||
85 | static u32 txx9spi_rd(struct txx9spi *c, int reg) | |
86 | { | |
87 | return __raw_readl(c->membase + reg); | |
88 | } | |
89 | static void txx9spi_wr(struct txx9spi *c, u32 val, int reg) | |
90 | { | |
91 | __raw_writel(val, c->membase + reg); | |
92 | } | |
93 | ||
94 | static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c, | |
95 | int on, unsigned int cs_delay) | |
96 | { | |
97 | int val = (spi->mode & SPI_CS_HIGH) ? on : !on; | |
98 | if (on) { | |
99 | /* deselect the chip with cs_change hint in last transfer */ | |
100 | if (c->last_chipselect >= 0) | |
101 | gpio_set_value(c->last_chipselect, | |
102 | !c->last_chipselect_val); | |
103 | c->last_chipselect = spi->chip_select; | |
104 | c->last_chipselect_val = val; | |
105 | } else { | |
106 | c->last_chipselect = -1; | |
107 | ndelay(cs_delay); /* CS Hold Time */ | |
108 | } | |
109 | gpio_set_value(spi->chip_select, val); | |
110 | ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */ | |
111 | } | |
112 | ||
f2cac67d AN |
113 | static int txx9spi_setup(struct spi_device *spi) |
114 | { | |
115 | struct txx9spi *c = spi_master_get_devdata(spi->master); | |
116 | u8 bits_per_word; | |
117 | ||
f2cac67d AN |
118 | if (!spi->max_speed_hz |
119 | || spi->max_speed_hz > c->max_speed_hz | |
120 | || spi->max_speed_hz < c->min_speed_hz) | |
121 | return -EINVAL; | |
122 | ||
7d077197 | 123 | bits_per_word = spi->bits_per_word; |
f2cac67d AN |
124 | if (bits_per_word != 8 && bits_per_word != 16) |
125 | return -EINVAL; | |
126 | ||
127 | if (gpio_direction_output(spi->chip_select, | |
128 | !(spi->mode & SPI_CS_HIGH))) { | |
129 | dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n"); | |
130 | return -EINVAL; | |
131 | } | |
132 | ||
133 | /* deselect chip */ | |
134 | spin_lock(&c->lock); | |
135 | txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz); | |
136 | spin_unlock(&c->lock); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | static irqreturn_t txx9spi_interrupt(int irq, void *dev_id) | |
142 | { | |
143 | struct txx9spi *c = dev_id; | |
144 | ||
145 | /* disable rx intr */ | |
146 | txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE, | |
147 | TXx9_SPCR0); | |
148 | wake_up(&c->waitq); | |
149 | return IRQ_HANDLED; | |
150 | } | |
151 | ||
152 | static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m) | |
153 | { | |
154 | struct spi_device *spi = m->spi; | |
155 | struct spi_transfer *t; | |
156 | unsigned int cs_delay; | |
157 | unsigned int cs_change = 1; | |
158 | int status = 0; | |
159 | u32 mcr; | |
160 | u32 prev_speed_hz = 0; | |
161 | u8 prev_bits_per_word = 0; | |
162 | ||
163 | /* CS setup/hold/recovery time in nsec */ | |
164 | cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz; | |
165 | ||
166 | mcr = txx9spi_rd(c, TXx9_SPMCR); | |
167 | if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) { | |
168 | dev_err(&spi->dev, "Bad mode.\n"); | |
169 | status = -EIO; | |
170 | goto exit; | |
171 | } | |
172 | mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR); | |
173 | ||
174 | /* enter config mode */ | |
175 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); | |
176 | txx9spi_wr(c, TXx9_SPCR0_SBOS | |
177 | | ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0) | |
178 | | ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0) | |
179 | | 0x08, | |
180 | TXx9_SPCR0); | |
181 | ||
182 | list_for_each_entry (t, &m->transfers, transfer_list) { | |
183 | const void *txbuf = t->tx_buf; | |
184 | void *rxbuf = t->rx_buf; | |
185 | u32 data; | |
186 | unsigned int len = t->len; | |
187 | unsigned int wsize; | |
188 | u32 speed_hz = t->speed_hz ? : spi->max_speed_hz; | |
189 | u8 bits_per_word = t->bits_per_word ? : spi->bits_per_word; | |
190 | ||
191 | bits_per_word = bits_per_word ? : 8; | |
192 | wsize = bits_per_word >> 3; /* in bytes */ | |
193 | ||
194 | if (prev_speed_hz != speed_hz | |
195 | || prev_bits_per_word != bits_per_word) { | |
196 | u32 n = (c->baseclk + speed_hz - 1) / speed_hz; | |
197 | if (n < 1) | |
198 | n = 1; | |
199 | else if (n > 0xff) | |
200 | n = 0xff; | |
201 | /* enter config mode */ | |
202 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, | |
203 | TXx9_SPMCR); | |
204 | txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1); | |
205 | /* enter active mode */ | |
206 | txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR); | |
207 | ||
208 | prev_speed_hz = speed_hz; | |
209 | prev_bits_per_word = bits_per_word; | |
210 | } | |
211 | ||
212 | if (cs_change) | |
213 | txx9spi_cs_func(spi, c, 1, cs_delay); | |
214 | cs_change = t->cs_change; | |
215 | while (len) { | |
216 | unsigned int count = SPI_FIFO_SIZE; | |
217 | int i; | |
218 | u32 cr0; | |
219 | ||
220 | if (len < count * wsize) | |
221 | count = len / wsize; | |
222 | /* now tx must be idle... */ | |
223 | while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE)) | |
224 | cpu_relax(); | |
225 | cr0 = txx9spi_rd(c, TXx9_SPCR0); | |
226 | cr0 &= ~TXx9_SPCR0_RXIFL_MASK; | |
227 | cr0 |= (count - 1) << 12; | |
228 | /* enable rx intr */ | |
229 | cr0 |= TXx9_SPCR0_RBSIE; | |
230 | txx9spi_wr(c, cr0, TXx9_SPCR0); | |
231 | /* send */ | |
232 | for (i = 0; i < count; i++) { | |
233 | if (txbuf) { | |
234 | data = (wsize == 1) | |
235 | ? *(const u8 *)txbuf | |
236 | : *(const u16 *)txbuf; | |
237 | txx9spi_wr(c, data, TXx9_SPDR); | |
238 | txbuf += wsize; | |
239 | } else | |
240 | txx9spi_wr(c, 0, TXx9_SPDR); | |
241 | } | |
242 | /* wait all rx data */ | |
243 | wait_event(c->waitq, | |
244 | txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI); | |
245 | /* receive */ | |
246 | for (i = 0; i < count; i++) { | |
247 | data = txx9spi_rd(c, TXx9_SPDR); | |
248 | if (rxbuf) { | |
249 | if (wsize == 1) | |
250 | *(u8 *)rxbuf = data; | |
251 | else | |
252 | *(u16 *)rxbuf = data; | |
253 | rxbuf += wsize; | |
254 | } | |
255 | } | |
256 | len -= count * wsize; | |
257 | } | |
258 | m->actual_length += t->len; | |
259 | if (t->delay_usecs) | |
260 | udelay(t->delay_usecs); | |
261 | ||
262 | if (!cs_change) | |
263 | continue; | |
264 | if (t->transfer_list.next == &m->transfers) | |
265 | break; | |
266 | /* sometimes a short mid-message deselect of the chip | |
267 | * may be needed to terminate a mode or command | |
268 | */ | |
269 | txx9spi_cs_func(spi, c, 0, cs_delay); | |
270 | } | |
271 | ||
272 | exit: | |
273 | m->status = status; | |
274 | m->complete(m->context); | |
275 | ||
276 | /* normally deactivate chipselect ... unless no error and | |
277 | * cs_change has hinted that the next message will probably | |
278 | * be for this chip too. | |
279 | */ | |
280 | if (!(status == 0 && cs_change)) | |
281 | txx9spi_cs_func(spi, c, 0, cs_delay); | |
282 | ||
283 | /* enter config mode */ | |
284 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); | |
285 | } | |
286 | ||
287 | static void txx9spi_work(struct work_struct *work) | |
288 | { | |
289 | struct txx9spi *c = container_of(work, struct txx9spi, work); | |
290 | unsigned long flags; | |
291 | ||
292 | spin_lock_irqsave(&c->lock, flags); | |
293 | while (!list_empty(&c->queue)) { | |
294 | struct spi_message *m; | |
295 | ||
296 | m = container_of(c->queue.next, struct spi_message, queue); | |
297 | list_del_init(&m->queue); | |
298 | spin_unlock_irqrestore(&c->lock, flags); | |
299 | ||
300 | txx9spi_work_one(c, m); | |
301 | ||
302 | spin_lock_irqsave(&c->lock, flags); | |
303 | } | |
304 | spin_unlock_irqrestore(&c->lock, flags); | |
305 | } | |
306 | ||
307 | static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m) | |
308 | { | |
309 | struct spi_master *master = spi->master; | |
310 | struct txx9spi *c = spi_master_get_devdata(master); | |
311 | struct spi_transfer *t; | |
312 | unsigned long flags; | |
313 | ||
314 | m->actual_length = 0; | |
315 | ||
316 | /* check each transfer's parameters */ | |
317 | list_for_each_entry (t, &m->transfers, transfer_list) { | |
318 | u32 speed_hz = t->speed_hz ? : spi->max_speed_hz; | |
319 | u8 bits_per_word = t->bits_per_word ? : spi->bits_per_word; | |
320 | ||
321 | bits_per_word = bits_per_word ? : 8; | |
322 | if (!t->tx_buf && !t->rx_buf && t->len) | |
323 | return -EINVAL; | |
324 | if (bits_per_word != 8 && bits_per_word != 16) | |
325 | return -EINVAL; | |
326 | if (t->len & ((bits_per_word >> 3) - 1)) | |
327 | return -EINVAL; | |
328 | if (speed_hz < c->min_speed_hz || speed_hz > c->max_speed_hz) | |
329 | return -EINVAL; | |
330 | } | |
331 | ||
332 | spin_lock_irqsave(&c->lock, flags); | |
333 | list_add_tail(&m->queue, &c->queue); | |
334 | queue_work(c->workqueue, &c->work); | |
335 | spin_unlock_irqrestore(&c->lock, flags); | |
336 | ||
337 | return 0; | |
338 | } | |
339 | ||
340 | static int __init txx9spi_probe(struct platform_device *dev) | |
341 | { | |
342 | struct spi_master *master; | |
343 | struct txx9spi *c; | |
344 | struct resource *res; | |
345 | int ret = -ENODEV; | |
346 | u32 mcr; | |
ba0a7f39 | 347 | int irq; |
f2cac67d AN |
348 | |
349 | master = spi_alloc_master(&dev->dev, sizeof(*c)); | |
350 | if (!master) | |
351 | return ret; | |
352 | c = spi_master_get_devdata(master); | |
f2cac67d AN |
353 | platform_set_drvdata(dev, master); |
354 | ||
355 | INIT_WORK(&c->work, txx9spi_work); | |
356 | spin_lock_init(&c->lock); | |
357 | INIT_LIST_HEAD(&c->queue); | |
358 | init_waitqueue_head(&c->waitq); | |
359 | ||
360 | c->clk = clk_get(&dev->dev, "spi-baseclk"); | |
361 | if (IS_ERR(c->clk)) { | |
362 | ret = PTR_ERR(c->clk); | |
363 | c->clk = NULL; | |
364 | goto exit; | |
365 | } | |
366 | ret = clk_enable(c->clk); | |
367 | if (ret) { | |
368 | clk_put(c->clk); | |
369 | c->clk = NULL; | |
370 | goto exit; | |
371 | } | |
372 | c->baseclk = clk_get_rate(c->clk); | |
373 | c->min_speed_hz = (c->baseclk + 0xff - 1) / 0xff; | |
374 | c->max_speed_hz = c->baseclk; | |
375 | ||
376 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
377 | if (!res) | |
ba0a7f39 AN |
378 | goto exit_busy; |
379 | if (!devm_request_mem_region(&dev->dev, | |
380 | res->start, res->end - res->start + 1, | |
381 | "spi_txx9")) | |
382 | goto exit_busy; | |
383 | c->membase = devm_ioremap(&dev->dev, | |
384 | res->start, res->end - res->start + 1); | |
f2cac67d | 385 | if (!c->membase) |
ba0a7f39 | 386 | goto exit_busy; |
f2cac67d AN |
387 | |
388 | /* enter config mode */ | |
389 | mcr = txx9spi_rd(c, TXx9_SPMCR); | |
390 | mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR); | |
391 | txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR); | |
392 | ||
ba0a7f39 AN |
393 | irq = platform_get_irq(dev, 0); |
394 | if (irq < 0) | |
395 | goto exit_busy; | |
396 | ret = devm_request_irq(&dev->dev, irq, txx9spi_interrupt, 0, | |
397 | "spi_txx9", c); | |
398 | if (ret) | |
f2cac67d | 399 | goto exit; |
f2cac67d | 400 | |
6c7377ab KS |
401 | c->workqueue = create_singlethread_workqueue( |
402 | dev_name(master->dev.parent)); | |
f2cac67d | 403 | if (!c->workqueue) |
ba0a7f39 | 404 | goto exit_busy; |
f2cac67d AN |
405 | c->last_chipselect = -1; |
406 | ||
407 | dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n", | |
ba0a7f39 | 408 | (unsigned long long)res->start, irq, |
f2cac67d AN |
409 | (c->baseclk + 500000) / 1000000); |
410 | ||
e7db06b5 DB |
411 | /* the spi->mode bits understood by this driver: */ |
412 | master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA; | |
413 | ||
f2cac67d AN |
414 | master->bus_num = dev->id; |
415 | master->setup = txx9spi_setup; | |
416 | master->transfer = txx9spi_transfer; | |
417 | master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */ | |
418 | ||
419 | ret = spi_register_master(master); | |
420 | if (ret) | |
421 | goto exit; | |
422 | return 0; | |
ba0a7f39 AN |
423 | exit_busy: |
424 | ret = -EBUSY; | |
f2cac67d AN |
425 | exit: |
426 | if (c->workqueue) | |
427 | destroy_workqueue(c->workqueue); | |
f2cac67d AN |
428 | if (c->clk) { |
429 | clk_disable(c->clk); | |
430 | clk_put(c->clk); | |
431 | } | |
432 | platform_set_drvdata(dev, NULL); | |
433 | spi_master_put(master); | |
434 | return ret; | |
435 | } | |
436 | ||
437 | static int __exit txx9spi_remove(struct platform_device *dev) | |
438 | { | |
439 | struct spi_master *master = spi_master_get(platform_get_drvdata(dev)); | |
440 | struct txx9spi *c = spi_master_get_devdata(master); | |
441 | ||
442 | spi_unregister_master(master); | |
443 | platform_set_drvdata(dev, NULL); | |
444 | destroy_workqueue(c->workqueue); | |
f2cac67d AN |
445 | clk_disable(c->clk); |
446 | clk_put(c->clk); | |
447 | spi_master_put(master); | |
448 | return 0; | |
449 | } | |
450 | ||
7e38c3c4 KS |
451 | /* work with hotplug and coldplug */ |
452 | MODULE_ALIAS("platform:spi_txx9"); | |
453 | ||
f2cac67d AN |
454 | static struct platform_driver txx9spi_driver = { |
455 | .remove = __exit_p(txx9spi_remove), | |
456 | .driver = { | |
4ccdb4c8 | 457 | .name = "spi_txx9", |
f2cac67d AN |
458 | .owner = THIS_MODULE, |
459 | }, | |
460 | }; | |
461 | ||
462 | static int __init txx9spi_init(void) | |
463 | { | |
464 | return platform_driver_probe(&txx9spi_driver, txx9spi_probe); | |
465 | } | |
466 | subsys_initcall(txx9spi_init); | |
467 | ||
468 | static void __exit txx9spi_exit(void) | |
469 | { | |
470 | platform_driver_unregister(&txx9spi_driver); | |
471 | } | |
472 | module_exit(txx9spi_exit); | |
473 | ||
474 | MODULE_DESCRIPTION("TXx9 SPI Driver"); | |
475 | MODULE_LICENSE("GPL"); |