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Commit | Line | Data |
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d0c6ae41 GA |
1 | /* |
2 | * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. | |
39ae93e3 KH |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
987a9f12 | 13 | #include <linux/bitmap.h> |
39ae93e3 KH |
14 | #include <linux/delay.h> |
15 | #include <linux/err.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/io.h> | |
67b563f1 JC |
18 | #include <linux/irqchip/chained_irq.h> |
19 | #include <linux/irqdomain.h> | |
20 | #include <linux/irq.h> | |
39ae93e3 KH |
21 | #include <linux/kernel.h> |
22 | #include <linux/module.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/slab.h> | |
26 | #include <linux/spmi.h> | |
27 | ||
28 | /* PMIC Arbiter configuration registers */ | |
29 | #define PMIC_ARB_VERSION 0x0000 | |
d0c6ae41 | 30 | #define PMIC_ARB_VERSION_V2_MIN 0x20010000 |
39ae93e3 KH |
31 | #define PMIC_ARB_INT_EN 0x0004 |
32 | ||
d0c6ae41 GA |
33 | /* PMIC Arbiter channel registers offsets */ |
34 | #define PMIC_ARB_CMD 0x00 | |
35 | #define PMIC_ARB_CONFIG 0x04 | |
36 | #define PMIC_ARB_STATUS 0x08 | |
37 | #define PMIC_ARB_WDATA0 0x10 | |
38 | #define PMIC_ARB_WDATA1 0x14 | |
39 | #define PMIC_ARB_RDATA0 0x18 | |
40 | #define PMIC_ARB_RDATA1 0x1C | |
41 | #define PMIC_ARB_REG_CHNL(N) (0x800 + 0x4 * (N)) | |
39ae93e3 KH |
42 | |
43 | /* Mapping Table */ | |
44 | #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N))) | |
45 | #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF) | |
46 | #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1) | |
47 | #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF) | |
48 | #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1) | |
49 | #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF) | |
50 | ||
39ae93e3 | 51 | #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */ |
987a9f12 SB |
52 | #define PMIC_ARB_MAX_PPID BIT(12) /* PPID is 12bit */ |
53 | #define PMIC_ARB_CHAN_VALID BIT(15) | |
39ae93e3 KH |
54 | |
55 | /* Ownership Table */ | |
56 | #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N))) | |
57 | #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7) | |
58 | ||
59 | /* Channel Status fields */ | |
60 | enum pmic_arb_chnl_status { | |
111a10bf AD |
61 | PMIC_ARB_STATUS_DONE = BIT(0), |
62 | PMIC_ARB_STATUS_FAILURE = BIT(1), | |
63 | PMIC_ARB_STATUS_DENIED = BIT(2), | |
64 | PMIC_ARB_STATUS_DROPPED = BIT(3), | |
39ae93e3 KH |
65 | }; |
66 | ||
67 | /* Command register fields */ | |
68 | #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8 | |
69 | ||
70 | /* Command Opcodes */ | |
71 | enum pmic_arb_cmd_op_code { | |
72 | PMIC_ARB_OP_EXT_WRITEL = 0, | |
73 | PMIC_ARB_OP_EXT_READL = 1, | |
74 | PMIC_ARB_OP_EXT_WRITE = 2, | |
75 | PMIC_ARB_OP_RESET = 3, | |
76 | PMIC_ARB_OP_SLEEP = 4, | |
77 | PMIC_ARB_OP_SHUTDOWN = 5, | |
78 | PMIC_ARB_OP_WAKEUP = 6, | |
79 | PMIC_ARB_OP_AUTHENTICATE = 7, | |
80 | PMIC_ARB_OP_MSTR_READ = 8, | |
81 | PMIC_ARB_OP_MSTR_WRITE = 9, | |
82 | PMIC_ARB_OP_EXT_READ = 13, | |
83 | PMIC_ARB_OP_WRITE = 14, | |
84 | PMIC_ARB_OP_READ = 15, | |
85 | PMIC_ARB_OP_ZERO_WRITE = 16, | |
86 | }; | |
87 | ||
88 | /* Maximum number of support PMIC peripherals */ | |
987a9f12 | 89 | #define PMIC_ARB_MAX_PERIPHS 512 |
39ae93e3 KH |
90 | #define PMIC_ARB_TIMEOUT_US 100 |
91 | #define PMIC_ARB_MAX_TRANS_BYTES (8) | |
92 | ||
93 | #define PMIC_ARB_APID_MASK 0xFF | |
94 | #define PMIC_ARB_PPID_MASK 0xFFF | |
95 | ||
96 | /* interrupt enable bit */ | |
97 | #define SPMI_PIC_ACC_ENABLE_BIT BIT(0) | |
98 | ||
d0c6ae41 GA |
99 | struct pmic_arb_ver_ops; |
100 | ||
6bc546e7 AD |
101 | struct apid_data { |
102 | u16 ppid; | |
103 | u8 owner; | |
104 | }; | |
105 | ||
39ae93e3 | 106 | /** |
111a10bf | 107 | * spmi_pmic_arb - SPMI PMIC Arbiter object |
39ae93e3 | 108 | * |
d0c6ae41 GA |
109 | * @rd_base: on v1 "core", on v2 "observer" register base off DT. |
110 | * @wr_base: on v1 "core", on v2 "chnls" register base off DT. | |
39ae93e3 KH |
111 | * @intr: address of the SPMI interrupt control registers. |
112 | * @cnfg: address of the PMIC Arbiter configuration registers. | |
113 | * @lock: lock to synchronize accesses. | |
d0c6ae41 | 114 | * @channel: execution environment channel to use for accesses. |
67b563f1 JC |
115 | * @irq: PMIC ARB interrupt. |
116 | * @ee: the current Execution Environment | |
117 | * @min_apid: minimum APID (used for bounding IRQ search) | |
118 | * @max_apid: maximum APID | |
57102ad7 | 119 | * @max_periph: maximum number of PMIC peripherals supported by HW. |
67b563f1 JC |
120 | * @mapping_table: in-memory copy of PPID -> APID mapping table. |
121 | * @domain: irq domain object for PMIC IRQ domain | |
122 | * @spmic: SPMI controller object | |
d0c6ae41 | 123 | * @ver_ops: version dependent operations. |
1ef1ce4e | 124 | * @ppid_to_apid in-memory copy of PPID -> channel (APID) mapping table. |
d0c6ae41 | 125 | * v2 only. |
39ae93e3 | 126 | */ |
111a10bf | 127 | struct spmi_pmic_arb { |
d0c6ae41 GA |
128 | void __iomem *rd_base; |
129 | void __iomem *wr_base; | |
39ae93e3 KH |
130 | void __iomem *intr; |
131 | void __iomem *cnfg; | |
987a9f12 SB |
132 | void __iomem *core; |
133 | resource_size_t core_size; | |
39ae93e3 KH |
134 | raw_spinlock_t lock; |
135 | u8 channel; | |
67b563f1 JC |
136 | int irq; |
137 | u8 ee; | |
987a9f12 SB |
138 | u16 min_apid; |
139 | u16 max_apid; | |
57102ad7 | 140 | u16 max_periph; |
987a9f12 SB |
141 | u32 *mapping_table; |
142 | DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); | |
67b563f1 JC |
143 | struct irq_domain *domain; |
144 | struct spmi_controller *spmic; | |
d0c6ae41 | 145 | const struct pmic_arb_ver_ops *ver_ops; |
1ef1ce4e AD |
146 | u16 *ppid_to_apid; |
147 | u16 last_apid; | |
6bc546e7 | 148 | struct apid_data apid_data[PMIC_ARB_MAX_PERIPHS]; |
d0c6ae41 GA |
149 | }; |
150 | ||
151 | /** | |
152 | * pmic_arb_ver: version dependent functionality. | |
153 | * | |
57102ad7 | 154 | * @mode: access rights to specified pmic peripheral. |
d0c6ae41 GA |
155 | * @non_data_cmd: on v1 issues an spmi non-data command. |
156 | * on v2 no HW support, returns -EOPNOTSUPP. | |
157 | * @offset: on v1 offset of per-ee channel. | |
158 | * on v2 offset of per-ee and per-ppid channel. | |
159 | * @fmt_cmd: formats a GENI/SPMI command. | |
160 | * @owner_acc_status: on v1 offset of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn | |
161 | * on v2 offset of SPMI_PIC_OWNERm_ACC_STATUSn. | |
162 | * @acc_enable: on v1 offset of PMIC_ARB_SPMI_PIC_ACC_ENABLEn | |
163 | * on v2 offset of SPMI_PIC_ACC_ENABLEn. | |
164 | * @irq_status: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_STATUSn | |
165 | * on v2 offset of SPMI_PIC_IRQ_STATUSn. | |
166 | * @irq_clear: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn | |
167 | * on v2 offset of SPMI_PIC_IRQ_CLEARn. | |
168 | */ | |
169 | struct pmic_arb_ver_ops { | |
7f1d4e58 AD |
170 | int (*ppid_to_apid)(struct spmi_pmic_arb *pa, u8 sid, u16 addr, |
171 | u8 *apid); | |
111a10bf | 172 | int (*mode)(struct spmi_pmic_arb *dev, u8 sid, u16 addr, |
57102ad7 | 173 | mode_t *mode); |
d0c6ae41 | 174 | /* spmi commands (read_cmd, write_cmd, cmd) functionality */ |
111a10bf | 175 | int (*offset)(struct spmi_pmic_arb *dev, u8 sid, u16 addr, |
987a9f12 | 176 | u32 *offset); |
d0c6ae41 GA |
177 | u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); |
178 | int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); | |
179 | /* Interrupts controller functionality (offset of PIC registers) */ | |
180 | u32 (*owner_acc_status)(u8 m, u8 n); | |
181 | u32 (*acc_enable)(u8 n); | |
182 | u32 (*irq_status)(u8 n); | |
183 | u32 (*irq_clear)(u8 n); | |
39ae93e3 KH |
184 | }; |
185 | ||
111a10bf | 186 | static inline void pmic_arb_base_write(struct spmi_pmic_arb *pa, |
39ae93e3 KH |
187 | u32 offset, u32 val) |
188 | { | |
111a10bf | 189 | writel_relaxed(val, pa->wr_base + offset); |
d0c6ae41 GA |
190 | } |
191 | ||
111a10bf | 192 | static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pa, |
d0c6ae41 GA |
193 | u32 offset, u32 val) |
194 | { | |
111a10bf | 195 | writel_relaxed(val, pa->rd_base + offset); |
39ae93e3 KH |
196 | } |
197 | ||
198 | /** | |
199 | * pa_read_data: reads pmic-arb's register and copy 1..4 bytes to buf | |
200 | * @bc: byte count -1. range: 0..3 | |
201 | * @reg: register's address | |
202 | * @buf: output parameter, length must be bc + 1 | |
203 | */ | |
111a10bf | 204 | static void pa_read_data(struct spmi_pmic_arb *pa, u8 *buf, u32 reg, u8 bc) |
39ae93e3 | 205 | { |
111a10bf AD |
206 | u32 data = __raw_readl(pa->rd_base + reg); |
207 | ||
39ae93e3 KH |
208 | memcpy(buf, &data, (bc & 3) + 1); |
209 | } | |
210 | ||
211 | /** | |
212 | * pa_write_data: write 1..4 bytes from buf to pmic-arb's register | |
213 | * @bc: byte-count -1. range: 0..3. | |
214 | * @reg: register's address. | |
215 | * @buf: buffer to write. length must be bc + 1. | |
216 | */ | |
217 | static void | |
111a10bf | 218 | pa_write_data(struct spmi_pmic_arb *pa, const u8 *buf, u32 reg, u8 bc) |
39ae93e3 KH |
219 | { |
220 | u32 data = 0; | |
111a10bf | 221 | |
39ae93e3 | 222 | memcpy(&data, buf, (bc & 3) + 1); |
111a10bf | 223 | pmic_arb_base_write(pa, reg, data); |
39ae93e3 KH |
224 | } |
225 | ||
d0c6ae41 GA |
226 | static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, |
227 | void __iomem *base, u8 sid, u16 addr) | |
39ae93e3 | 228 | { |
111a10bf | 229 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
39ae93e3 KH |
230 | u32 status = 0; |
231 | u32 timeout = PMIC_ARB_TIMEOUT_US; | |
987a9f12 SB |
232 | u32 offset; |
233 | int rc; | |
234 | ||
111a10bf | 235 | rc = pa->ver_ops->offset(pa, sid, addr, &offset); |
987a9f12 SB |
236 | if (rc) |
237 | return rc; | |
238 | ||
239 | offset += PMIC_ARB_STATUS; | |
39ae93e3 KH |
240 | |
241 | while (timeout--) { | |
d0c6ae41 | 242 | status = readl_relaxed(base + offset); |
39ae93e3 KH |
243 | |
244 | if (status & PMIC_ARB_STATUS_DONE) { | |
245 | if (status & PMIC_ARB_STATUS_DENIED) { | |
246 | dev_err(&ctrl->dev, | |
247 | "%s: transaction denied (0x%x)\n", | |
248 | __func__, status); | |
249 | return -EPERM; | |
250 | } | |
251 | ||
252 | if (status & PMIC_ARB_STATUS_FAILURE) { | |
253 | dev_err(&ctrl->dev, | |
254 | "%s: transaction failed (0x%x)\n", | |
255 | __func__, status); | |
256 | return -EIO; | |
257 | } | |
258 | ||
259 | if (status & PMIC_ARB_STATUS_DROPPED) { | |
260 | dev_err(&ctrl->dev, | |
261 | "%s: transaction dropped (0x%x)\n", | |
262 | __func__, status); | |
263 | return -EIO; | |
264 | } | |
265 | ||
266 | return 0; | |
267 | } | |
268 | udelay(1); | |
269 | } | |
270 | ||
271 | dev_err(&ctrl->dev, | |
272 | "%s: timeout, status 0x%x\n", | |
273 | __func__, status); | |
274 | return -ETIMEDOUT; | |
275 | } | |
276 | ||
d0c6ae41 GA |
277 | static int |
278 | pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) | |
39ae93e3 | 279 | { |
111a10bf | 280 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
39ae93e3 KH |
281 | unsigned long flags; |
282 | u32 cmd; | |
283 | int rc; | |
987a9f12 SB |
284 | u32 offset; |
285 | ||
111a10bf | 286 | rc = pa->ver_ops->offset(pa, sid, 0, &offset); |
987a9f12 SB |
287 | if (rc) |
288 | return rc; | |
39ae93e3 KH |
289 | |
290 | cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); | |
291 | ||
111a10bf AD |
292 | raw_spin_lock_irqsave(&pa->lock, flags); |
293 | pmic_arb_base_write(pa, offset + PMIC_ARB_CMD, cmd); | |
294 | rc = pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, 0); | |
295 | raw_spin_unlock_irqrestore(&pa->lock, flags); | |
39ae93e3 KH |
296 | |
297 | return rc; | |
298 | } | |
299 | ||
d0c6ae41 GA |
300 | static int |
301 | pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) | |
302 | { | |
303 | return -EOPNOTSUPP; | |
304 | } | |
305 | ||
306 | /* Non-data command */ | |
307 | static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) | |
308 | { | |
111a10bf | 309 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
d0c6ae41 GA |
310 | |
311 | dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); | |
312 | ||
313 | /* Check for valid non-data command */ | |
314 | if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) | |
315 | return -EINVAL; | |
316 | ||
111a10bf | 317 | return pa->ver_ops->non_data_cmd(ctrl, opc, sid); |
d0c6ae41 GA |
318 | } |
319 | ||
39ae93e3 KH |
320 | static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
321 | u16 addr, u8 *buf, size_t len) | |
322 | { | |
111a10bf | 323 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
39ae93e3 KH |
324 | unsigned long flags; |
325 | u8 bc = len - 1; | |
326 | u32 cmd; | |
327 | int rc; | |
987a9f12 | 328 | u32 offset; |
57102ad7 | 329 | mode_t mode; |
987a9f12 | 330 | |
111a10bf | 331 | rc = pa->ver_ops->offset(pa, sid, addr, &offset); |
987a9f12 SB |
332 | if (rc) |
333 | return rc; | |
39ae93e3 | 334 | |
111a10bf | 335 | rc = pa->ver_ops->mode(pa, sid, addr, &mode); |
57102ad7 AD |
336 | if (rc) |
337 | return rc; | |
338 | ||
339 | if (!(mode & S_IRUSR)) { | |
111a10bf | 340 | dev_err(&pa->spmic->dev, |
57102ad7 AD |
341 | "error: impermissible read from peripheral sid:%d addr:0x%x\n", |
342 | sid, addr); | |
343 | return -EPERM; | |
344 | } | |
345 | ||
39ae93e3 KH |
346 | if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { |
347 | dev_err(&ctrl->dev, | |
d0c6ae41 | 348 | "pmic-arb supports 1..%d bytes per trans, but:%zu requested", |
39ae93e3 KH |
349 | PMIC_ARB_MAX_TRANS_BYTES, len); |
350 | return -EINVAL; | |
351 | } | |
352 | ||
353 | /* Check the opcode */ | |
354 | if (opc >= 0x60 && opc <= 0x7F) | |
355 | opc = PMIC_ARB_OP_READ; | |
356 | else if (opc >= 0x20 && opc <= 0x2F) | |
357 | opc = PMIC_ARB_OP_EXT_READ; | |
358 | else if (opc >= 0x38 && opc <= 0x3F) | |
359 | opc = PMIC_ARB_OP_EXT_READL; | |
360 | else | |
361 | return -EINVAL; | |
362 | ||
111a10bf | 363 | cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc); |
39ae93e3 | 364 | |
111a10bf AD |
365 | raw_spin_lock_irqsave(&pa->lock, flags); |
366 | pmic_arb_set_rd_cmd(pa, offset + PMIC_ARB_CMD, cmd); | |
367 | rc = pmic_arb_wait_for_done(ctrl, pa->rd_base, sid, addr); | |
39ae93e3 KH |
368 | if (rc) |
369 | goto done; | |
370 | ||
111a10bf | 371 | pa_read_data(pa, buf, offset + PMIC_ARB_RDATA0, |
39ae93e3 KH |
372 | min_t(u8, bc, 3)); |
373 | ||
374 | if (bc > 3) | |
111a10bf | 375 | pa_read_data(pa, buf + 4, offset + PMIC_ARB_RDATA1, bc - 4); |
39ae93e3 KH |
376 | |
377 | done: | |
111a10bf | 378 | raw_spin_unlock_irqrestore(&pa->lock, flags); |
39ae93e3 KH |
379 | return rc; |
380 | } | |
381 | ||
382 | static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, | |
383 | u16 addr, const u8 *buf, size_t len) | |
384 | { | |
111a10bf | 385 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
39ae93e3 KH |
386 | unsigned long flags; |
387 | u8 bc = len - 1; | |
388 | u32 cmd; | |
389 | int rc; | |
987a9f12 | 390 | u32 offset; |
57102ad7 | 391 | mode_t mode; |
987a9f12 | 392 | |
111a10bf | 393 | rc = pa->ver_ops->offset(pa, sid, addr, &offset); |
987a9f12 SB |
394 | if (rc) |
395 | return rc; | |
39ae93e3 | 396 | |
111a10bf | 397 | rc = pa->ver_ops->mode(pa, sid, addr, &mode); |
57102ad7 AD |
398 | if (rc) |
399 | return rc; | |
400 | ||
401 | if (!(mode & S_IWUSR)) { | |
111a10bf | 402 | dev_err(&pa->spmic->dev, |
57102ad7 AD |
403 | "error: impermissible write to peripheral sid:%d addr:0x%x\n", |
404 | sid, addr); | |
405 | return -EPERM; | |
406 | } | |
407 | ||
39ae93e3 KH |
408 | if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { |
409 | dev_err(&ctrl->dev, | |
d0c6ae41 | 410 | "pmic-arb supports 1..%d bytes per trans, but:%zu requested", |
39ae93e3 KH |
411 | PMIC_ARB_MAX_TRANS_BYTES, len); |
412 | return -EINVAL; | |
413 | } | |
414 | ||
415 | /* Check the opcode */ | |
416 | if (opc >= 0x40 && opc <= 0x5F) | |
417 | opc = PMIC_ARB_OP_WRITE; | |
418 | else if (opc >= 0x00 && opc <= 0x0F) | |
419 | opc = PMIC_ARB_OP_EXT_WRITE; | |
420 | else if (opc >= 0x30 && opc <= 0x37) | |
421 | opc = PMIC_ARB_OP_EXT_WRITEL; | |
9b76968d | 422 | else if (opc >= 0x80) |
39ae93e3 KH |
423 | opc = PMIC_ARB_OP_ZERO_WRITE; |
424 | else | |
425 | return -EINVAL; | |
426 | ||
111a10bf | 427 | cmd = pa->ver_ops->fmt_cmd(opc, sid, addr, bc); |
39ae93e3 KH |
428 | |
429 | /* Write data to FIFOs */ | |
111a10bf AD |
430 | raw_spin_lock_irqsave(&pa->lock, flags); |
431 | pa_write_data(pa, buf, offset + PMIC_ARB_WDATA0, min_t(u8, bc, 3)); | |
39ae93e3 | 432 | if (bc > 3) |
111a10bf | 433 | pa_write_data(pa, buf + 4, offset + PMIC_ARB_WDATA1, bc - 4); |
39ae93e3 KH |
434 | |
435 | /* Start the transaction */ | |
111a10bf AD |
436 | pmic_arb_base_write(pa, offset + PMIC_ARB_CMD, cmd); |
437 | rc = pmic_arb_wait_for_done(ctrl, pa->wr_base, sid, addr); | |
438 | raw_spin_unlock_irqrestore(&pa->lock, flags); | |
39ae93e3 KH |
439 | |
440 | return rc; | |
441 | } | |
442 | ||
67b563f1 JC |
443 | enum qpnpint_regs { |
444 | QPNPINT_REG_RT_STS = 0x10, | |
445 | QPNPINT_REG_SET_TYPE = 0x11, | |
446 | QPNPINT_REG_POLARITY_HIGH = 0x12, | |
447 | QPNPINT_REG_POLARITY_LOW = 0x13, | |
448 | QPNPINT_REG_LATCHED_CLR = 0x14, | |
449 | QPNPINT_REG_EN_SET = 0x15, | |
450 | QPNPINT_REG_EN_CLR = 0x16, | |
451 | QPNPINT_REG_LATCHED_STS = 0x18, | |
452 | }; | |
453 | ||
454 | struct spmi_pmic_arb_qpnpint_type { | |
455 | u8 type; /* 1 -> edge */ | |
456 | u8 polarity_high; | |
457 | u8 polarity_low; | |
458 | } __packed; | |
459 | ||
460 | /* Simplified accessor functions for irqchip callbacks */ | |
461 | static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, | |
462 | size_t len) | |
463 | { | |
111a10bf | 464 | struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); |
67b563f1 JC |
465 | u8 sid = d->hwirq >> 24; |
466 | u8 per = d->hwirq >> 16; | |
467 | ||
468 | if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, | |
469 | (per << 8) + reg, buf, len)) | |
470 | dev_err_ratelimited(&pa->spmic->dev, | |
471 | "failed irqchip transaction on %x\n", | |
472 | d->irq); | |
473 | } | |
474 | ||
475 | static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) | |
476 | { | |
111a10bf | 477 | struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); |
67b563f1 JC |
478 | u8 sid = d->hwirq >> 24; |
479 | u8 per = d->hwirq >> 16; | |
480 | ||
481 | if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid, | |
482 | (per << 8) + reg, buf, len)) | |
483 | dev_err_ratelimited(&pa->spmic->dev, | |
484 | "failed irqchip transaction on %x\n", | |
485 | d->irq); | |
486 | } | |
487 | ||
6bc546e7 AD |
488 | static void cleanup_irq(struct spmi_pmic_arb *pa, u8 apid, int id) |
489 | { | |
490 | u16 ppid = pa->apid_data[apid].ppid; | |
491 | u8 sid = ppid >> 8; | |
492 | u8 per = ppid & 0xFF; | |
493 | u8 irq_mask = BIT(id); | |
494 | ||
495 | writel_relaxed(irq_mask, pa->intr + pa->ver_ops->irq_clear(apid)); | |
496 | ||
497 | if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, | |
498 | (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1)) | |
499 | dev_err_ratelimited(&pa->spmic->dev, | |
500 | "failed to ack irq_mask = 0x%x for ppid = %x\n", | |
501 | irq_mask, ppid); | |
502 | ||
503 | if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, | |
504 | (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1)) | |
505 | dev_err_ratelimited(&pa->spmic->dev, | |
506 | "failed to ack irq_mask = 0x%x for ppid = %x\n", | |
507 | irq_mask, ppid); | |
508 | } | |
509 | ||
111a10bf | 510 | static void periph_interrupt(struct spmi_pmic_arb *pa, u8 apid) |
67b563f1 JC |
511 | { |
512 | unsigned int irq; | |
513 | u32 status; | |
514 | int id; | |
515 | ||
d0c6ae41 | 516 | status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid)); |
67b563f1 JC |
517 | while (status) { |
518 | id = ffs(status) - 1; | |
111a10bf | 519 | status &= ~BIT(id); |
67b563f1 | 520 | irq = irq_find_mapping(pa->domain, |
6bc546e7 | 521 | pa->apid_data[apid].ppid << 16 |
67b563f1 JC |
522 | | id << 8 |
523 | | apid); | |
6bc546e7 AD |
524 | if (irq == 0) { |
525 | cleanup_irq(pa, apid, id); | |
526 | continue; | |
527 | } | |
67b563f1 JC |
528 | generic_handle_irq(irq); |
529 | } | |
530 | } | |
531 | ||
bd0b9ac4 | 532 | static void pmic_arb_chained_irq(struct irq_desc *desc) |
67b563f1 | 533 | { |
111a10bf | 534 | struct spmi_pmic_arb *pa = irq_desc_get_handler_data(desc); |
7fe88f3c | 535 | struct irq_chip *chip = irq_desc_get_chip(desc); |
67b563f1 JC |
536 | void __iomem *intr = pa->intr; |
537 | int first = pa->min_apid >> 5; | |
538 | int last = pa->max_apid >> 5; | |
539 | u32 status; | |
540 | int i, id; | |
541 | ||
542 | chained_irq_enter(chip, desc); | |
543 | ||
544 | for (i = first; i <= last; ++i) { | |
545 | status = readl_relaxed(intr + | |
d0c6ae41 | 546 | pa->ver_ops->owner_acc_status(pa->ee, i)); |
67b563f1 JC |
547 | while (status) { |
548 | id = ffs(status) - 1; | |
111a10bf | 549 | status &= ~BIT(id); |
67b563f1 JC |
550 | periph_interrupt(pa, id + i * 32); |
551 | } | |
552 | } | |
553 | ||
554 | chained_irq_exit(chip, desc); | |
555 | } | |
556 | ||
557 | static void qpnpint_irq_ack(struct irq_data *d) | |
558 | { | |
111a10bf | 559 | struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); |
67b563f1 JC |
560 | u8 irq = d->hwirq >> 8; |
561 | u8 apid = d->hwirq; | |
67b563f1 JC |
562 | u8 data; |
563 | ||
111a10bf | 564 | writel_relaxed(BIT(irq), pa->intr + pa->ver_ops->irq_clear(apid)); |
67b563f1 | 565 | |
111a10bf | 566 | data = BIT(irq); |
67b563f1 JC |
567 | qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); |
568 | } | |
569 | ||
570 | static void qpnpint_irq_mask(struct irq_data *d) | |
571 | { | |
67b563f1 | 572 | u8 irq = d->hwirq >> 8; |
6bc546e7 | 573 | u8 data = BIT(irq); |
67b563f1 | 574 | |
67b563f1 JC |
575 | qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); |
576 | } | |
577 | ||
578 | static void qpnpint_irq_unmask(struct irq_data *d) | |
579 | { | |
111a10bf | 580 | struct spmi_pmic_arb *pa = irq_data_get_irq_chip_data(d); |
67b563f1 JC |
581 | u8 irq = d->hwirq >> 8; |
582 | u8 apid = d->hwirq; | |
cee0fad7 | 583 | u8 buf[2]; |
67b563f1 | 584 | |
6bc546e7 AD |
585 | writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, |
586 | pa->intr + pa->ver_ops->acc_enable(apid)); | |
67b563f1 | 587 | |
cee0fad7 AD |
588 | qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); |
589 | if (!(buf[0] & BIT(irq))) { | |
590 | /* | |
591 | * Since the interrupt is currently disabled, write to both the | |
592 | * LATCHED_CLR and EN_SET registers so that a spurious interrupt | |
593 | * cannot be triggered when the interrupt is enabled | |
594 | */ | |
595 | buf[0] = BIT(irq); | |
596 | buf[1] = BIT(irq); | |
597 | qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2); | |
598 | } | |
67b563f1 JC |
599 | } |
600 | ||
67b563f1 JC |
601 | static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) |
602 | { | |
603 | struct spmi_pmic_arb_qpnpint_type type; | |
604 | u8 irq = d->hwirq >> 8; | |
111a10bf | 605 | u8 bit_mask_irq = BIT(irq); |
67b563f1 JC |
606 | |
607 | qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); | |
608 | ||
609 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { | |
111a10bf | 610 | type.type |= bit_mask_irq; |
67b563f1 | 611 | if (flow_type & IRQF_TRIGGER_RISING) |
111a10bf | 612 | type.polarity_high |= bit_mask_irq; |
67b563f1 | 613 | if (flow_type & IRQF_TRIGGER_FALLING) |
111a10bf | 614 | type.polarity_low |= bit_mask_irq; |
67b563f1 JC |
615 | } else { |
616 | if ((flow_type & (IRQF_TRIGGER_HIGH)) && | |
617 | (flow_type & (IRQF_TRIGGER_LOW))) | |
618 | return -EINVAL; | |
619 | ||
111a10bf | 620 | type.type &= ~bit_mask_irq; /* level trig */ |
67b563f1 | 621 | if (flow_type & IRQF_TRIGGER_HIGH) |
111a10bf | 622 | type.polarity_high |= bit_mask_irq; |
67b563f1 | 623 | else |
111a10bf | 624 | type.polarity_low |= bit_mask_irq; |
67b563f1 JC |
625 | } |
626 | ||
627 | qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); | |
628 | return 0; | |
629 | } | |
630 | ||
60be4230 CC |
631 | static int qpnpint_get_irqchip_state(struct irq_data *d, |
632 | enum irqchip_irq_state which, | |
633 | bool *state) | |
634 | { | |
635 | u8 irq = d->hwirq >> 8; | |
636 | u8 status = 0; | |
637 | ||
638 | if (which != IRQCHIP_STATE_LINE_LEVEL) | |
639 | return -EINVAL; | |
640 | ||
641 | qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1); | |
642 | *state = !!(status & BIT(irq)); | |
643 | ||
644 | return 0; | |
645 | } | |
646 | ||
67b563f1 JC |
647 | static struct irq_chip pmic_arb_irqchip = { |
648 | .name = "pmic_arb", | |
67b563f1 JC |
649 | .irq_ack = qpnpint_irq_ack, |
650 | .irq_mask = qpnpint_irq_mask, | |
651 | .irq_unmask = qpnpint_irq_unmask, | |
652 | .irq_set_type = qpnpint_irq_set_type, | |
60be4230 | 653 | .irq_get_irqchip_state = qpnpint_get_irqchip_state, |
67b563f1 JC |
654 | .flags = IRQCHIP_MASK_ON_SUSPEND |
655 | | IRQCHIP_SKIP_SET_WAKE, | |
656 | }; | |
657 | ||
67b563f1 JC |
658 | static int qpnpint_irq_domain_dt_translate(struct irq_domain *d, |
659 | struct device_node *controller, | |
660 | const u32 *intspec, | |
661 | unsigned int intsize, | |
662 | unsigned long *out_hwirq, | |
663 | unsigned int *out_type) | |
664 | { | |
111a10bf | 665 | struct spmi_pmic_arb *pa = d->host_data; |
7f1d4e58 | 666 | int rc; |
67b563f1 JC |
667 | u8 apid; |
668 | ||
669 | dev_dbg(&pa->spmic->dev, | |
670 | "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n", | |
671 | intspec[0], intspec[1], intspec[2]); | |
672 | ||
5d4c9bc7 | 673 | if (irq_domain_get_of_node(d) != controller) |
67b563f1 JC |
674 | return -EINVAL; |
675 | if (intsize != 4) | |
676 | return -EINVAL; | |
677 | if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7) | |
678 | return -EINVAL; | |
679 | ||
7f1d4e58 AD |
680 | rc = pa->ver_ops->ppid_to_apid(pa, intspec[0], |
681 | (intspec[1] << 8), &apid); | |
682 | if (rc < 0) { | |
683 | dev_err(&pa->spmic->dev, | |
684 | "failed to xlate sid = 0x%x, periph = 0x%x, irq = %x rc = %d\n", | |
685 | intspec[0], intspec[1], intspec[2], rc); | |
686 | return rc; | |
687 | } | |
67b563f1 JC |
688 | |
689 | /* Keep track of {max,min}_apid for bounding search during interrupt */ | |
690 | if (apid > pa->max_apid) | |
691 | pa->max_apid = apid; | |
692 | if (apid < pa->min_apid) | |
693 | pa->min_apid = apid; | |
694 | ||
f6dda8e2 AD |
695 | *out_hwirq = (intspec[0] & 0xF) << 24 |
696 | | (intspec[1] & 0xFF) << 16 | |
697 | | (intspec[2] & 0x7) << 8 | |
67b563f1 JC |
698 | | apid; |
699 | *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; | |
700 | ||
701 | dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq); | |
702 | ||
703 | return 0; | |
704 | } | |
705 | ||
706 | static int qpnpint_irq_domain_map(struct irq_domain *d, | |
707 | unsigned int virq, | |
708 | irq_hw_number_t hwirq) | |
709 | { | |
111a10bf | 710 | struct spmi_pmic_arb *pa = d->host_data; |
67b563f1 JC |
711 | |
712 | dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq); | |
713 | ||
714 | irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq); | |
715 | irq_set_chip_data(virq, d->host_data); | |
716 | irq_set_noprobe(virq); | |
717 | return 0; | |
718 | } | |
719 | ||
7f1d4e58 AD |
720 | static int |
721 | pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u8 *apid) | |
722 | { | |
723 | u16 ppid = sid << 8 | ((addr >> 8) & 0xFF); | |
724 | u32 *mapping_table = pa->mapping_table; | |
725 | int index = 0, i; | |
726 | u16 apid_valid; | |
727 | u32 data; | |
728 | ||
729 | apid_valid = pa->ppid_to_apid[ppid]; | |
730 | if (apid_valid & PMIC_ARB_CHAN_VALID) { | |
731 | *apid = (apid_valid & ~PMIC_ARB_CHAN_VALID); | |
732 | return 0; | |
733 | } | |
734 | ||
735 | for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { | |
736 | if (!test_and_set_bit(index, pa->mapping_table_valid)) | |
737 | mapping_table[index] = readl_relaxed(pa->cnfg + | |
738 | SPMI_MAPPING_TABLE_REG(index)); | |
739 | ||
740 | data = mapping_table[index]; | |
741 | ||
742 | if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) { | |
743 | if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) { | |
744 | index = SPMI_MAPPING_BIT_IS_1_RESULT(data); | |
745 | } else { | |
746 | *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data); | |
747 | pa->ppid_to_apid[ppid] | |
748 | = *apid | PMIC_ARB_CHAN_VALID; | |
6bc546e7 | 749 | pa->apid_data[*apid].ppid = ppid; |
7f1d4e58 AD |
750 | return 0; |
751 | } | |
752 | } else { | |
753 | if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) { | |
754 | index = SPMI_MAPPING_BIT_IS_0_RESULT(data); | |
755 | } else { | |
756 | *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data); | |
757 | pa->ppid_to_apid[ppid] | |
758 | = *apid | PMIC_ARB_CHAN_VALID; | |
6bc546e7 | 759 | pa->apid_data[*apid].ppid = ppid; |
7f1d4e58 AD |
760 | return 0; |
761 | } | |
762 | } | |
763 | } | |
764 | ||
765 | return -ENODEV; | |
766 | } | |
767 | ||
57102ad7 | 768 | static int |
111a10bf | 769 | pmic_arb_mode_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode) |
57102ad7 AD |
770 | { |
771 | *mode = S_IRUSR | S_IWUSR; | |
772 | return 0; | |
773 | } | |
774 | ||
d0c6ae41 | 775 | /* v1 offset per ee */ |
987a9f12 | 776 | static int |
111a10bf | 777 | pmic_arb_offset_v1(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u32 *offset) |
d0c6ae41 | 778 | { |
987a9f12 SB |
779 | *offset = 0x800 + 0x80 * pa->channel; |
780 | return 0; | |
781 | } | |
782 | ||
1ef1ce4e | 783 | static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pa, u16 ppid) |
987a9f12 SB |
784 | { |
785 | u32 regval, offset; | |
1ef1ce4e | 786 | u16 apid; |
987a9f12 SB |
787 | u16 id; |
788 | ||
789 | /* | |
790 | * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid. | |
1ef1ce4e | 791 | * ppid_to_apid is an in-memory invert of that table. |
987a9f12 | 792 | */ |
1ef1ce4e | 793 | for (apid = pa->last_apid; apid < pa->max_periph; apid++) { |
57102ad7 | 794 | regval = readl_relaxed(pa->cnfg + |
1ef1ce4e | 795 | SPMI_OWNERSHIP_TABLE_REG(apid)); |
6bc546e7 | 796 | pa->apid_data[apid].owner = SPMI_OWNERSHIP_PERIPH2OWNER(regval); |
57102ad7 | 797 | |
1ef1ce4e | 798 | offset = PMIC_ARB_REG_CHNL(apid); |
987a9f12 SB |
799 | if (offset >= pa->core_size) |
800 | break; | |
801 | ||
802 | regval = readl_relaxed(pa->core + offset); | |
803 | if (!regval) | |
804 | continue; | |
805 | ||
806 | id = (regval >> 8) & PMIC_ARB_PPID_MASK; | |
1ef1ce4e | 807 | pa->ppid_to_apid[id] = apid | PMIC_ARB_CHAN_VALID; |
6bc546e7 | 808 | pa->apid_data[apid].ppid = id; |
987a9f12 | 809 | if (id == ppid) { |
1ef1ce4e | 810 | apid |= PMIC_ARB_CHAN_VALID; |
987a9f12 SB |
811 | break; |
812 | } | |
813 | } | |
1ef1ce4e | 814 | pa->last_apid = apid & ~PMIC_ARB_CHAN_VALID; |
987a9f12 | 815 | |
1ef1ce4e | 816 | return apid; |
d0c6ae41 GA |
817 | } |
818 | ||
987a9f12 | 819 | |
57102ad7 | 820 | static int |
7f1d4e58 | 821 | pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u8 *apid) |
57102ad7 AD |
822 | { |
823 | u16 ppid = (sid << 8) | (addr >> 8); | |
7f1d4e58 | 824 | u16 apid_valid; |
57102ad7 | 825 | |
7f1d4e58 AD |
826 | apid_valid = pa->ppid_to_apid[ppid]; |
827 | if (!(apid_valid & PMIC_ARB_CHAN_VALID)) | |
828 | apid_valid = pmic_arb_find_apid(pa, ppid); | |
829 | if (!(apid_valid & PMIC_ARB_CHAN_VALID)) | |
57102ad7 AD |
830 | return -ENODEV; |
831 | ||
7f1d4e58 AD |
832 | *apid = (apid_valid & ~PMIC_ARB_CHAN_VALID); |
833 | return 0; | |
834 | } | |
835 | ||
836 | static int | |
837 | pmic_arb_mode_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, mode_t *mode) | |
838 | { | |
839 | u8 apid; | |
7f1d4e58 AD |
840 | int rc; |
841 | ||
842 | rc = pmic_arb_ppid_to_apid_v2(pa, sid, addr, &apid); | |
843 | if (rc < 0) | |
844 | return rc; | |
845 | ||
57102ad7 AD |
846 | *mode = 0; |
847 | *mode |= S_IRUSR; | |
848 | ||
6bc546e7 | 849 | if (pa->ee == pa->apid_data[apid].owner) |
57102ad7 AD |
850 | *mode |= S_IWUSR; |
851 | return 0; | |
852 | } | |
853 | ||
1ef1ce4e | 854 | /* v2 offset per ppid and per ee */ |
987a9f12 | 855 | static int |
111a10bf | 856 | pmic_arb_offset_v2(struct spmi_pmic_arb *pa, u8 sid, u16 addr, u32 *offset) |
d0c6ae41 | 857 | { |
7f1d4e58 AD |
858 | u8 apid; |
859 | int rc; | |
987a9f12 | 860 | |
7f1d4e58 AD |
861 | rc = pmic_arb_ppid_to_apid_v2(pa, sid, addr, &apid); |
862 | if (rc < 0) | |
863 | return rc; | |
d0c6ae41 | 864 | |
1ef1ce4e | 865 | *offset = 0x1000 * pa->ee + 0x8000 * apid; |
987a9f12 | 866 | return 0; |
d0c6ae41 GA |
867 | } |
868 | ||
869 | static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc) | |
870 | { | |
871 | return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7); | |
872 | } | |
873 | ||
874 | static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc) | |
875 | { | |
876 | return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7); | |
877 | } | |
878 | ||
879 | static u32 pmic_arb_owner_acc_status_v1(u8 m, u8 n) | |
880 | { | |
881 | return 0x20 * m + 0x4 * n; | |
882 | } | |
883 | ||
884 | static u32 pmic_arb_owner_acc_status_v2(u8 m, u8 n) | |
885 | { | |
886 | return 0x100000 + 0x1000 * m + 0x4 * n; | |
887 | } | |
888 | ||
889 | static u32 pmic_arb_acc_enable_v1(u8 n) | |
890 | { | |
891 | return 0x200 + 0x4 * n; | |
892 | } | |
893 | ||
894 | static u32 pmic_arb_acc_enable_v2(u8 n) | |
895 | { | |
896 | return 0x1000 * n; | |
897 | } | |
898 | ||
899 | static u32 pmic_arb_irq_status_v1(u8 n) | |
900 | { | |
901 | return 0x600 + 0x4 * n; | |
902 | } | |
903 | ||
904 | static u32 pmic_arb_irq_status_v2(u8 n) | |
905 | { | |
906 | return 0x4 + 0x1000 * n; | |
907 | } | |
908 | ||
909 | static u32 pmic_arb_irq_clear_v1(u8 n) | |
910 | { | |
911 | return 0xA00 + 0x4 * n; | |
912 | } | |
913 | ||
914 | static u32 pmic_arb_irq_clear_v2(u8 n) | |
915 | { | |
916 | return 0x8 + 0x1000 * n; | |
917 | } | |
918 | ||
919 | static const struct pmic_arb_ver_ops pmic_arb_v1 = { | |
7f1d4e58 | 920 | .ppid_to_apid = pmic_arb_ppid_to_apid_v1, |
57102ad7 | 921 | .mode = pmic_arb_mode_v1, |
d0c6ae41 GA |
922 | .non_data_cmd = pmic_arb_non_data_cmd_v1, |
923 | .offset = pmic_arb_offset_v1, | |
924 | .fmt_cmd = pmic_arb_fmt_cmd_v1, | |
925 | .owner_acc_status = pmic_arb_owner_acc_status_v1, | |
926 | .acc_enable = pmic_arb_acc_enable_v1, | |
927 | .irq_status = pmic_arb_irq_status_v1, | |
928 | .irq_clear = pmic_arb_irq_clear_v1, | |
929 | }; | |
930 | ||
931 | static const struct pmic_arb_ver_ops pmic_arb_v2 = { | |
7f1d4e58 | 932 | .ppid_to_apid = pmic_arb_ppid_to_apid_v2, |
57102ad7 | 933 | .mode = pmic_arb_mode_v2, |
d0c6ae41 GA |
934 | .non_data_cmd = pmic_arb_non_data_cmd_v2, |
935 | .offset = pmic_arb_offset_v2, | |
936 | .fmt_cmd = pmic_arb_fmt_cmd_v2, | |
937 | .owner_acc_status = pmic_arb_owner_acc_status_v2, | |
938 | .acc_enable = pmic_arb_acc_enable_v2, | |
939 | .irq_status = pmic_arb_irq_status_v2, | |
940 | .irq_clear = pmic_arb_irq_clear_v2, | |
941 | }; | |
942 | ||
67b563f1 JC |
943 | static const struct irq_domain_ops pmic_arb_irq_domain_ops = { |
944 | .map = qpnpint_irq_domain_map, | |
945 | .xlate = qpnpint_irq_domain_dt_translate, | |
946 | }; | |
947 | ||
39ae93e3 KH |
948 | static int spmi_pmic_arb_probe(struct platform_device *pdev) |
949 | { | |
111a10bf | 950 | struct spmi_pmic_arb *pa; |
39ae93e3 KH |
951 | struct spmi_controller *ctrl; |
952 | struct resource *res; | |
d0c6ae41 GA |
953 | void __iomem *core; |
954 | u32 channel, ee, hw_ver; | |
987a9f12 | 955 | int err; |
d0c6ae41 | 956 | bool is_v1; |
39ae93e3 KH |
957 | |
958 | ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa)); | |
959 | if (!ctrl) | |
960 | return -ENOMEM; | |
961 | ||
962 | pa = spmi_controller_get_drvdata(ctrl); | |
67b563f1 | 963 | pa->spmic = ctrl; |
39ae93e3 KH |
964 | |
965 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); | |
987a9f12 | 966 | pa->core_size = resource_size(res); |
57102ad7 AD |
967 | if (pa->core_size <= 0x800) { |
968 | dev_err(&pdev->dev, "core_size is smaller than 0x800. Failing Probe\n"); | |
969 | err = -EINVAL; | |
970 | goto err_put_ctrl; | |
971 | } | |
972 | ||
d0c6ae41 GA |
973 | core = devm_ioremap_resource(&ctrl->dev, res); |
974 | if (IS_ERR(core)) { | |
975 | err = PTR_ERR(core); | |
39ae93e3 KH |
976 | goto err_put_ctrl; |
977 | } | |
978 | ||
d0c6ae41 GA |
979 | hw_ver = readl_relaxed(core + PMIC_ARB_VERSION); |
980 | is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN); | |
981 | ||
982 | dev_info(&ctrl->dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), | |
983 | hw_ver); | |
984 | ||
985 | if (is_v1) { | |
986 | pa->ver_ops = &pmic_arb_v1; | |
987 | pa->wr_base = core; | |
988 | pa->rd_base = core; | |
989 | } else { | |
987a9f12 | 990 | pa->core = core; |
d0c6ae41 GA |
991 | pa->ver_ops = &pmic_arb_v2; |
992 | ||
57102ad7 AD |
993 | /* the apid to ppid table starts at PMIC_ARB_REG_CHNL(0) */ |
994 | pa->max_periph = (pa->core_size - PMIC_ARB_REG_CHNL(0)) / 4; | |
995 | ||
d0c6ae41 GA |
996 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, |
997 | "obsrvr"); | |
998 | pa->rd_base = devm_ioremap_resource(&ctrl->dev, res); | |
999 | if (IS_ERR(pa->rd_base)) { | |
1000 | err = PTR_ERR(pa->rd_base); | |
1001 | goto err_put_ctrl; | |
1002 | } | |
1003 | ||
1004 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
1005 | "chnls"); | |
1006 | pa->wr_base = devm_ioremap_resource(&ctrl->dev, res); | |
1007 | if (IS_ERR(pa->wr_base)) { | |
1008 | err = PTR_ERR(pa->wr_base); | |
1009 | goto err_put_ctrl; | |
1010 | } | |
1011 | ||
1ef1ce4e | 1012 | pa->ppid_to_apid = devm_kcalloc(&ctrl->dev, |
987a9f12 | 1013 | PMIC_ARB_MAX_PPID, |
1ef1ce4e | 1014 | sizeof(*pa->ppid_to_apid), |
987a9f12 | 1015 | GFP_KERNEL); |
1ef1ce4e | 1016 | if (!pa->ppid_to_apid) { |
d0c6ae41 GA |
1017 | err = -ENOMEM; |
1018 | goto err_put_ctrl; | |
1019 | } | |
d0c6ae41 GA |
1020 | } |
1021 | ||
39ae93e3 KH |
1022 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); |
1023 | pa->intr = devm_ioremap_resource(&ctrl->dev, res); | |
1024 | if (IS_ERR(pa->intr)) { | |
1025 | err = PTR_ERR(pa->intr); | |
1026 | goto err_put_ctrl; | |
1027 | } | |
1028 | ||
1029 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg"); | |
1030 | pa->cnfg = devm_ioremap_resource(&ctrl->dev, res); | |
1031 | if (IS_ERR(pa->cnfg)) { | |
1032 | err = PTR_ERR(pa->cnfg); | |
1033 | goto err_put_ctrl; | |
1034 | } | |
1035 | ||
67b563f1 JC |
1036 | pa->irq = platform_get_irq_byname(pdev, "periph_irq"); |
1037 | if (pa->irq < 0) { | |
1038 | err = pa->irq; | |
1039 | goto err_put_ctrl; | |
1040 | } | |
1041 | ||
39ae93e3 KH |
1042 | err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); |
1043 | if (err) { | |
1044 | dev_err(&pdev->dev, "channel unspecified.\n"); | |
1045 | goto err_put_ctrl; | |
1046 | } | |
1047 | ||
1048 | if (channel > 5) { | |
1049 | dev_err(&pdev->dev, "invalid channel (%u) specified.\n", | |
1050 | channel); | |
e98cc182 | 1051 | err = -EINVAL; |
39ae93e3 KH |
1052 | goto err_put_ctrl; |
1053 | } | |
1054 | ||
1055 | pa->channel = channel; | |
1056 | ||
67b563f1 JC |
1057 | err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee); |
1058 | if (err) { | |
1059 | dev_err(&pdev->dev, "EE unspecified.\n"); | |
1060 | goto err_put_ctrl; | |
1061 | } | |
1062 | ||
1063 | if (ee > 5) { | |
1064 | dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee); | |
1065 | err = -EINVAL; | |
1066 | goto err_put_ctrl; | |
1067 | } | |
1068 | ||
1069 | pa->ee = ee; | |
1070 | ||
987a9f12 SB |
1071 | pa->mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS - 1, |
1072 | sizeof(*pa->mapping_table), GFP_KERNEL); | |
1073 | if (!pa->mapping_table) { | |
1074 | err = -ENOMEM; | |
1075 | goto err_put_ctrl; | |
1076 | } | |
67b563f1 JC |
1077 | |
1078 | /* Initialize max_apid/min_apid to the opposite bounds, during | |
1079 | * the irq domain translation, we are sure to update these */ | |
1080 | pa->max_apid = 0; | |
1081 | pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1; | |
1082 | ||
39ae93e3 KH |
1083 | platform_set_drvdata(pdev, ctrl); |
1084 | raw_spin_lock_init(&pa->lock); | |
1085 | ||
1086 | ctrl->cmd = pmic_arb_cmd; | |
1087 | ctrl->read_cmd = pmic_arb_read_cmd; | |
1088 | ctrl->write_cmd = pmic_arb_write_cmd; | |
1089 | ||
67b563f1 JC |
1090 | dev_dbg(&pdev->dev, "adding irq domain\n"); |
1091 | pa->domain = irq_domain_add_tree(pdev->dev.of_node, | |
1092 | &pmic_arb_irq_domain_ops, pa); | |
1093 | if (!pa->domain) { | |
1094 | dev_err(&pdev->dev, "unable to create irq_domain\n"); | |
1095 | err = -ENOMEM; | |
1096 | goto err_put_ctrl; | |
1097 | } | |
1098 | ||
fb68ba6d | 1099 | irq_set_chained_handler_and_data(pa->irq, pmic_arb_chained_irq, pa); |
67b563f1 | 1100 | |
39ae93e3 KH |
1101 | err = spmi_controller_add(ctrl); |
1102 | if (err) | |
67b563f1 | 1103 | goto err_domain_remove; |
39ae93e3 | 1104 | |
39ae93e3 KH |
1105 | return 0; |
1106 | ||
67b563f1 | 1107 | err_domain_remove: |
fb68ba6d | 1108 | irq_set_chained_handler_and_data(pa->irq, NULL, NULL); |
67b563f1 | 1109 | irq_domain_remove(pa->domain); |
39ae93e3 KH |
1110 | err_put_ctrl: |
1111 | spmi_controller_put(ctrl); | |
1112 | return err; | |
1113 | } | |
1114 | ||
1115 | static int spmi_pmic_arb_remove(struct platform_device *pdev) | |
1116 | { | |
1117 | struct spmi_controller *ctrl = platform_get_drvdata(pdev); | |
111a10bf | 1118 | struct spmi_pmic_arb *pa = spmi_controller_get_drvdata(ctrl); |
39ae93e3 | 1119 | spmi_controller_remove(ctrl); |
fb68ba6d | 1120 | irq_set_chained_handler_and_data(pa->irq, NULL, NULL); |
67b563f1 | 1121 | irq_domain_remove(pa->domain); |
39ae93e3 KH |
1122 | spmi_controller_put(ctrl); |
1123 | return 0; | |
1124 | } | |
1125 | ||
1126 | static const struct of_device_id spmi_pmic_arb_match_table[] = { | |
1127 | { .compatible = "qcom,spmi-pmic-arb", }, | |
1128 | {}, | |
1129 | }; | |
1130 | MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table); | |
1131 | ||
1132 | static struct platform_driver spmi_pmic_arb_driver = { | |
1133 | .probe = spmi_pmic_arb_probe, | |
1134 | .remove = spmi_pmic_arb_remove, | |
1135 | .driver = { | |
1136 | .name = "spmi_pmic_arb", | |
39ae93e3 KH |
1137 | .of_match_table = spmi_pmic_arb_match_table, |
1138 | }, | |
1139 | }; | |
1140 | module_platform_driver(spmi_pmic_arb_driver); | |
1141 | ||
1142 | MODULE_LICENSE("GPL v2"); | |
1143 | MODULE_ALIAS("platform:spmi_pmic_arb"); |