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d0c6ae41 GA |
1 | /* |
2 | * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. | |
39ae93e3 KH |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 and | |
6 | * only version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
13 | #include <linux/delay.h> | |
14 | #include <linux/err.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/io.h> | |
67b563f1 JC |
17 | #include <linux/irqchip/chained_irq.h> |
18 | #include <linux/irqdomain.h> | |
19 | #include <linux/irq.h> | |
39ae93e3 KH |
20 | #include <linux/kernel.h> |
21 | #include <linux/module.h> | |
22 | #include <linux/of.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/slab.h> | |
25 | #include <linux/spmi.h> | |
26 | ||
27 | /* PMIC Arbiter configuration registers */ | |
28 | #define PMIC_ARB_VERSION 0x0000 | |
d0c6ae41 | 29 | #define PMIC_ARB_VERSION_V2_MIN 0x20010000 |
39ae93e3 KH |
30 | #define PMIC_ARB_INT_EN 0x0004 |
31 | ||
d0c6ae41 GA |
32 | /* PMIC Arbiter channel registers offsets */ |
33 | #define PMIC_ARB_CMD 0x00 | |
34 | #define PMIC_ARB_CONFIG 0x04 | |
35 | #define PMIC_ARB_STATUS 0x08 | |
36 | #define PMIC_ARB_WDATA0 0x10 | |
37 | #define PMIC_ARB_WDATA1 0x14 | |
38 | #define PMIC_ARB_RDATA0 0x18 | |
39 | #define PMIC_ARB_RDATA1 0x1C | |
40 | #define PMIC_ARB_REG_CHNL(N) (0x800 + 0x4 * (N)) | |
39ae93e3 KH |
41 | |
42 | /* Mapping Table */ | |
43 | #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N))) | |
44 | #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF) | |
45 | #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1) | |
46 | #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF) | |
47 | #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1) | |
48 | #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF) | |
49 | ||
50 | #define SPMI_MAPPING_TABLE_LEN 255 | |
51 | #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */ | |
d0c6ae41 | 52 | #define PPID_TO_CHAN_TABLE_SZ BIT(12) /* PPID is 12bit chan is 1byte*/ |
39ae93e3 KH |
53 | |
54 | /* Ownership Table */ | |
55 | #define SPMI_OWNERSHIP_TABLE_REG(N) (0x0700 + (4 * (N))) | |
56 | #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7) | |
57 | ||
58 | /* Channel Status fields */ | |
59 | enum pmic_arb_chnl_status { | |
60 | PMIC_ARB_STATUS_DONE = (1 << 0), | |
61 | PMIC_ARB_STATUS_FAILURE = (1 << 1), | |
62 | PMIC_ARB_STATUS_DENIED = (1 << 2), | |
63 | PMIC_ARB_STATUS_DROPPED = (1 << 3), | |
64 | }; | |
65 | ||
66 | /* Command register fields */ | |
67 | #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8 | |
68 | ||
69 | /* Command Opcodes */ | |
70 | enum pmic_arb_cmd_op_code { | |
71 | PMIC_ARB_OP_EXT_WRITEL = 0, | |
72 | PMIC_ARB_OP_EXT_READL = 1, | |
73 | PMIC_ARB_OP_EXT_WRITE = 2, | |
74 | PMIC_ARB_OP_RESET = 3, | |
75 | PMIC_ARB_OP_SLEEP = 4, | |
76 | PMIC_ARB_OP_SHUTDOWN = 5, | |
77 | PMIC_ARB_OP_WAKEUP = 6, | |
78 | PMIC_ARB_OP_AUTHENTICATE = 7, | |
79 | PMIC_ARB_OP_MSTR_READ = 8, | |
80 | PMIC_ARB_OP_MSTR_WRITE = 9, | |
81 | PMIC_ARB_OP_EXT_READ = 13, | |
82 | PMIC_ARB_OP_WRITE = 14, | |
83 | PMIC_ARB_OP_READ = 15, | |
84 | PMIC_ARB_OP_ZERO_WRITE = 16, | |
85 | }; | |
86 | ||
87 | /* Maximum number of support PMIC peripherals */ | |
88 | #define PMIC_ARB_MAX_PERIPHS 256 | |
d0c6ae41 | 89 | #define PMIC_ARB_MAX_CHNL 128 |
39ae93e3 KH |
90 | #define PMIC_ARB_PERIPH_ID_VALID (1 << 15) |
91 | #define PMIC_ARB_TIMEOUT_US 100 | |
92 | #define PMIC_ARB_MAX_TRANS_BYTES (8) | |
93 | ||
94 | #define PMIC_ARB_APID_MASK 0xFF | |
95 | #define PMIC_ARB_PPID_MASK 0xFFF | |
96 | ||
97 | /* interrupt enable bit */ | |
98 | #define SPMI_PIC_ACC_ENABLE_BIT BIT(0) | |
99 | ||
d0c6ae41 GA |
100 | struct pmic_arb_ver_ops; |
101 | ||
39ae93e3 KH |
102 | /** |
103 | * spmi_pmic_arb_dev - SPMI PMIC Arbiter object | |
104 | * | |
d0c6ae41 GA |
105 | * @rd_base: on v1 "core", on v2 "observer" register base off DT. |
106 | * @wr_base: on v1 "core", on v2 "chnls" register base off DT. | |
39ae93e3 KH |
107 | * @intr: address of the SPMI interrupt control registers. |
108 | * @cnfg: address of the PMIC Arbiter configuration registers. | |
109 | * @lock: lock to synchronize accesses. | |
d0c6ae41 | 110 | * @channel: execution environment channel to use for accesses. |
67b563f1 JC |
111 | * @irq: PMIC ARB interrupt. |
112 | * @ee: the current Execution Environment | |
113 | * @min_apid: minimum APID (used for bounding IRQ search) | |
114 | * @max_apid: maximum APID | |
115 | * @mapping_table: in-memory copy of PPID -> APID mapping table. | |
116 | * @domain: irq domain object for PMIC IRQ domain | |
117 | * @spmic: SPMI controller object | |
d0c6ae41 GA |
118 | * @apid_to_ppid: in-memory copy of APID -> PPID mapping table. |
119 | * @ver_ops: version dependent operations. | |
120 | * @ppid_to_chan in-memory copy of PPID -> channel (APID) mapping table. | |
121 | * v2 only. | |
39ae93e3 KH |
122 | */ |
123 | struct spmi_pmic_arb_dev { | |
d0c6ae41 GA |
124 | void __iomem *rd_base; |
125 | void __iomem *wr_base; | |
39ae93e3 KH |
126 | void __iomem *intr; |
127 | void __iomem *cnfg; | |
128 | raw_spinlock_t lock; | |
129 | u8 channel; | |
67b563f1 JC |
130 | int irq; |
131 | u8 ee; | |
132 | u8 min_apid; | |
133 | u8 max_apid; | |
134 | u32 mapping_table[SPMI_MAPPING_TABLE_LEN]; | |
135 | struct irq_domain *domain; | |
136 | struct spmi_controller *spmic; | |
137 | u16 apid_to_ppid[256]; | |
d0c6ae41 GA |
138 | const struct pmic_arb_ver_ops *ver_ops; |
139 | u8 *ppid_to_chan; | |
140 | }; | |
141 | ||
142 | /** | |
143 | * pmic_arb_ver: version dependent functionality. | |
144 | * | |
145 | * @non_data_cmd: on v1 issues an spmi non-data command. | |
146 | * on v2 no HW support, returns -EOPNOTSUPP. | |
147 | * @offset: on v1 offset of per-ee channel. | |
148 | * on v2 offset of per-ee and per-ppid channel. | |
149 | * @fmt_cmd: formats a GENI/SPMI command. | |
150 | * @owner_acc_status: on v1 offset of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn | |
151 | * on v2 offset of SPMI_PIC_OWNERm_ACC_STATUSn. | |
152 | * @acc_enable: on v1 offset of PMIC_ARB_SPMI_PIC_ACC_ENABLEn | |
153 | * on v2 offset of SPMI_PIC_ACC_ENABLEn. | |
154 | * @irq_status: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_STATUSn | |
155 | * on v2 offset of SPMI_PIC_IRQ_STATUSn. | |
156 | * @irq_clear: on v1 offset of PMIC_ARB_SPMI_PIC_IRQ_CLEARn | |
157 | * on v2 offset of SPMI_PIC_IRQ_CLEARn. | |
158 | */ | |
159 | struct pmic_arb_ver_ops { | |
160 | /* spmi commands (read_cmd, write_cmd, cmd) functionality */ | |
161 | u32 (*offset)(struct spmi_pmic_arb_dev *dev, u8 sid, u16 addr); | |
162 | u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); | |
163 | int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); | |
164 | /* Interrupts controller functionality (offset of PIC registers) */ | |
165 | u32 (*owner_acc_status)(u8 m, u8 n); | |
166 | u32 (*acc_enable)(u8 n); | |
167 | u32 (*irq_status)(u8 n); | |
168 | u32 (*irq_clear)(u8 n); | |
39ae93e3 KH |
169 | }; |
170 | ||
171 | static inline u32 pmic_arb_base_read(struct spmi_pmic_arb_dev *dev, u32 offset) | |
172 | { | |
d0c6ae41 | 173 | return readl_relaxed(dev->rd_base + offset); |
39ae93e3 KH |
174 | } |
175 | ||
176 | static inline void pmic_arb_base_write(struct spmi_pmic_arb_dev *dev, | |
177 | u32 offset, u32 val) | |
178 | { | |
d0c6ae41 GA |
179 | writel_relaxed(val, dev->wr_base + offset); |
180 | } | |
181 | ||
182 | static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb_dev *dev, | |
183 | u32 offset, u32 val) | |
184 | { | |
185 | writel_relaxed(val, dev->rd_base + offset); | |
39ae93e3 KH |
186 | } |
187 | ||
188 | /** | |
189 | * pa_read_data: reads pmic-arb's register and copy 1..4 bytes to buf | |
190 | * @bc: byte count -1. range: 0..3 | |
191 | * @reg: register's address | |
192 | * @buf: output parameter, length must be bc + 1 | |
193 | */ | |
194 | static void pa_read_data(struct spmi_pmic_arb_dev *dev, u8 *buf, u32 reg, u8 bc) | |
195 | { | |
196 | u32 data = pmic_arb_base_read(dev, reg); | |
197 | memcpy(buf, &data, (bc & 3) + 1); | |
198 | } | |
199 | ||
200 | /** | |
201 | * pa_write_data: write 1..4 bytes from buf to pmic-arb's register | |
202 | * @bc: byte-count -1. range: 0..3. | |
203 | * @reg: register's address. | |
204 | * @buf: buffer to write. length must be bc + 1. | |
205 | */ | |
206 | static void | |
207 | pa_write_data(struct spmi_pmic_arb_dev *dev, const u8 *buf, u32 reg, u8 bc) | |
208 | { | |
209 | u32 data = 0; | |
210 | memcpy(&data, buf, (bc & 3) + 1); | |
211 | pmic_arb_base_write(dev, reg, data); | |
212 | } | |
213 | ||
d0c6ae41 GA |
214 | static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, |
215 | void __iomem *base, u8 sid, u16 addr) | |
39ae93e3 KH |
216 | { |
217 | struct spmi_pmic_arb_dev *dev = spmi_controller_get_drvdata(ctrl); | |
218 | u32 status = 0; | |
219 | u32 timeout = PMIC_ARB_TIMEOUT_US; | |
d0c6ae41 | 220 | u32 offset = dev->ver_ops->offset(dev, sid, addr) + PMIC_ARB_STATUS; |
39ae93e3 KH |
221 | |
222 | while (timeout--) { | |
d0c6ae41 | 223 | status = readl_relaxed(base + offset); |
39ae93e3 KH |
224 | |
225 | if (status & PMIC_ARB_STATUS_DONE) { | |
226 | if (status & PMIC_ARB_STATUS_DENIED) { | |
227 | dev_err(&ctrl->dev, | |
228 | "%s: transaction denied (0x%x)\n", | |
229 | __func__, status); | |
230 | return -EPERM; | |
231 | } | |
232 | ||
233 | if (status & PMIC_ARB_STATUS_FAILURE) { | |
234 | dev_err(&ctrl->dev, | |
235 | "%s: transaction failed (0x%x)\n", | |
236 | __func__, status); | |
237 | return -EIO; | |
238 | } | |
239 | ||
240 | if (status & PMIC_ARB_STATUS_DROPPED) { | |
241 | dev_err(&ctrl->dev, | |
242 | "%s: transaction dropped (0x%x)\n", | |
243 | __func__, status); | |
244 | return -EIO; | |
245 | } | |
246 | ||
247 | return 0; | |
248 | } | |
249 | udelay(1); | |
250 | } | |
251 | ||
252 | dev_err(&ctrl->dev, | |
253 | "%s: timeout, status 0x%x\n", | |
254 | __func__, status); | |
255 | return -ETIMEDOUT; | |
256 | } | |
257 | ||
d0c6ae41 GA |
258 | static int |
259 | pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) | |
39ae93e3 KH |
260 | { |
261 | struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); | |
262 | unsigned long flags; | |
263 | u32 cmd; | |
264 | int rc; | |
d0c6ae41 | 265 | u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, 0); |
39ae93e3 KH |
266 | |
267 | cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); | |
268 | ||
269 | raw_spin_lock_irqsave(&pmic_arb->lock, flags); | |
d0c6ae41 GA |
270 | pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); |
271 | rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0); | |
39ae93e3 KH |
272 | raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); |
273 | ||
274 | return rc; | |
275 | } | |
276 | ||
d0c6ae41 GA |
277 | static int |
278 | pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) | |
279 | { | |
280 | return -EOPNOTSUPP; | |
281 | } | |
282 | ||
283 | /* Non-data command */ | |
284 | static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) | |
285 | { | |
286 | struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); | |
287 | ||
288 | dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); | |
289 | ||
290 | /* Check for valid non-data command */ | |
291 | if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) | |
292 | return -EINVAL; | |
293 | ||
294 | return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); | |
295 | } | |
296 | ||
39ae93e3 KH |
297 | static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, |
298 | u16 addr, u8 *buf, size_t len) | |
299 | { | |
300 | struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); | |
301 | unsigned long flags; | |
302 | u8 bc = len - 1; | |
303 | u32 cmd; | |
304 | int rc; | |
d0c6ae41 | 305 | u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, addr); |
39ae93e3 KH |
306 | |
307 | if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { | |
308 | dev_err(&ctrl->dev, | |
d0c6ae41 | 309 | "pmic-arb supports 1..%d bytes per trans, but:%zu requested", |
39ae93e3 KH |
310 | PMIC_ARB_MAX_TRANS_BYTES, len); |
311 | return -EINVAL; | |
312 | } | |
313 | ||
314 | /* Check the opcode */ | |
315 | if (opc >= 0x60 && opc <= 0x7F) | |
316 | opc = PMIC_ARB_OP_READ; | |
317 | else if (opc >= 0x20 && opc <= 0x2F) | |
318 | opc = PMIC_ARB_OP_EXT_READ; | |
319 | else if (opc >= 0x38 && opc <= 0x3F) | |
320 | opc = PMIC_ARB_OP_EXT_READL; | |
321 | else | |
322 | return -EINVAL; | |
323 | ||
d0c6ae41 | 324 | cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); |
39ae93e3 KH |
325 | |
326 | raw_spin_lock_irqsave(&pmic_arb->lock, flags); | |
d0c6ae41 GA |
327 | pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd); |
328 | rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr); | |
39ae93e3 KH |
329 | if (rc) |
330 | goto done; | |
331 | ||
d0c6ae41 | 332 | pa_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0, |
39ae93e3 KH |
333 | min_t(u8, bc, 3)); |
334 | ||
335 | if (bc > 3) | |
336 | pa_read_data(pmic_arb, buf + 4, | |
d0c6ae41 | 337 | offset + PMIC_ARB_RDATA1, bc - 4); |
39ae93e3 KH |
338 | |
339 | done: | |
340 | raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); | |
341 | return rc; | |
342 | } | |
343 | ||
344 | static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, | |
345 | u16 addr, const u8 *buf, size_t len) | |
346 | { | |
347 | struct spmi_pmic_arb_dev *pmic_arb = spmi_controller_get_drvdata(ctrl); | |
348 | unsigned long flags; | |
349 | u8 bc = len - 1; | |
350 | u32 cmd; | |
351 | int rc; | |
d0c6ae41 | 352 | u32 offset = pmic_arb->ver_ops->offset(pmic_arb, sid, addr); |
39ae93e3 KH |
353 | |
354 | if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { | |
355 | dev_err(&ctrl->dev, | |
d0c6ae41 | 356 | "pmic-arb supports 1..%d bytes per trans, but:%zu requested", |
39ae93e3 KH |
357 | PMIC_ARB_MAX_TRANS_BYTES, len); |
358 | return -EINVAL; | |
359 | } | |
360 | ||
361 | /* Check the opcode */ | |
362 | if (opc >= 0x40 && opc <= 0x5F) | |
363 | opc = PMIC_ARB_OP_WRITE; | |
364 | else if (opc >= 0x00 && opc <= 0x0F) | |
365 | opc = PMIC_ARB_OP_EXT_WRITE; | |
366 | else if (opc >= 0x30 && opc <= 0x37) | |
367 | opc = PMIC_ARB_OP_EXT_WRITEL; | |
368 | else if (opc >= 0x80 && opc <= 0xFF) | |
369 | opc = PMIC_ARB_OP_ZERO_WRITE; | |
370 | else | |
371 | return -EINVAL; | |
372 | ||
d0c6ae41 | 373 | cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); |
39ae93e3 KH |
374 | |
375 | /* Write data to FIFOs */ | |
376 | raw_spin_lock_irqsave(&pmic_arb->lock, flags); | |
d0c6ae41 GA |
377 | pa_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0, |
378 | min_t(u8, bc, 3)); | |
39ae93e3 KH |
379 | if (bc > 3) |
380 | pa_write_data(pmic_arb, buf + 4, | |
d0c6ae41 | 381 | offset + PMIC_ARB_WDATA1, bc - 4); |
39ae93e3 KH |
382 | |
383 | /* Start the transaction */ | |
d0c6ae41 GA |
384 | pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); |
385 | rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr); | |
39ae93e3 KH |
386 | raw_spin_unlock_irqrestore(&pmic_arb->lock, flags); |
387 | ||
388 | return rc; | |
389 | } | |
390 | ||
67b563f1 JC |
391 | enum qpnpint_regs { |
392 | QPNPINT_REG_RT_STS = 0x10, | |
393 | QPNPINT_REG_SET_TYPE = 0x11, | |
394 | QPNPINT_REG_POLARITY_HIGH = 0x12, | |
395 | QPNPINT_REG_POLARITY_LOW = 0x13, | |
396 | QPNPINT_REG_LATCHED_CLR = 0x14, | |
397 | QPNPINT_REG_EN_SET = 0x15, | |
398 | QPNPINT_REG_EN_CLR = 0x16, | |
399 | QPNPINT_REG_LATCHED_STS = 0x18, | |
400 | }; | |
401 | ||
402 | struct spmi_pmic_arb_qpnpint_type { | |
403 | u8 type; /* 1 -> edge */ | |
404 | u8 polarity_high; | |
405 | u8 polarity_low; | |
406 | } __packed; | |
407 | ||
408 | /* Simplified accessor functions for irqchip callbacks */ | |
409 | static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, | |
410 | size_t len) | |
411 | { | |
412 | struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); | |
413 | u8 sid = d->hwirq >> 24; | |
414 | u8 per = d->hwirq >> 16; | |
415 | ||
416 | if (pmic_arb_write_cmd(pa->spmic, SPMI_CMD_EXT_WRITEL, sid, | |
417 | (per << 8) + reg, buf, len)) | |
418 | dev_err_ratelimited(&pa->spmic->dev, | |
419 | "failed irqchip transaction on %x\n", | |
420 | d->irq); | |
421 | } | |
422 | ||
423 | static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) | |
424 | { | |
425 | struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); | |
426 | u8 sid = d->hwirq >> 24; | |
427 | u8 per = d->hwirq >> 16; | |
428 | ||
429 | if (pmic_arb_read_cmd(pa->spmic, SPMI_CMD_EXT_READL, sid, | |
430 | (per << 8) + reg, buf, len)) | |
431 | dev_err_ratelimited(&pa->spmic->dev, | |
432 | "failed irqchip transaction on %x\n", | |
433 | d->irq); | |
434 | } | |
435 | ||
436 | static void periph_interrupt(struct spmi_pmic_arb_dev *pa, u8 apid) | |
437 | { | |
438 | unsigned int irq; | |
439 | u32 status; | |
440 | int id; | |
441 | ||
d0c6ae41 | 442 | status = readl_relaxed(pa->intr + pa->ver_ops->irq_status(apid)); |
67b563f1 JC |
443 | while (status) { |
444 | id = ffs(status) - 1; | |
445 | status &= ~(1 << id); | |
446 | irq = irq_find_mapping(pa->domain, | |
447 | pa->apid_to_ppid[apid] << 16 | |
448 | | id << 8 | |
449 | | apid); | |
450 | generic_handle_irq(irq); | |
451 | } | |
452 | } | |
453 | ||
bd0b9ac4 | 454 | static void pmic_arb_chained_irq(struct irq_desc *desc) |
67b563f1 | 455 | { |
7fe88f3c JL |
456 | struct spmi_pmic_arb_dev *pa = irq_desc_get_handler_data(desc); |
457 | struct irq_chip *chip = irq_desc_get_chip(desc); | |
67b563f1 JC |
458 | void __iomem *intr = pa->intr; |
459 | int first = pa->min_apid >> 5; | |
460 | int last = pa->max_apid >> 5; | |
461 | u32 status; | |
462 | int i, id; | |
463 | ||
464 | chained_irq_enter(chip, desc); | |
465 | ||
466 | for (i = first; i <= last; ++i) { | |
467 | status = readl_relaxed(intr + | |
d0c6ae41 | 468 | pa->ver_ops->owner_acc_status(pa->ee, i)); |
67b563f1 JC |
469 | while (status) { |
470 | id = ffs(status) - 1; | |
471 | status &= ~(1 << id); | |
472 | periph_interrupt(pa, id + i * 32); | |
473 | } | |
474 | } | |
475 | ||
476 | chained_irq_exit(chip, desc); | |
477 | } | |
478 | ||
479 | static void qpnpint_irq_ack(struct irq_data *d) | |
480 | { | |
481 | struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); | |
482 | u8 irq = d->hwirq >> 8; | |
483 | u8 apid = d->hwirq; | |
484 | unsigned long flags; | |
485 | u8 data; | |
486 | ||
487 | raw_spin_lock_irqsave(&pa->lock, flags); | |
d0c6ae41 | 488 | writel_relaxed(1 << irq, pa->intr + pa->ver_ops->irq_clear(apid)); |
67b563f1 JC |
489 | raw_spin_unlock_irqrestore(&pa->lock, flags); |
490 | ||
491 | data = 1 << irq; | |
492 | qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); | |
493 | } | |
494 | ||
495 | static void qpnpint_irq_mask(struct irq_data *d) | |
496 | { | |
497 | struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); | |
498 | u8 irq = d->hwirq >> 8; | |
499 | u8 apid = d->hwirq; | |
500 | unsigned long flags; | |
501 | u32 status; | |
502 | u8 data; | |
503 | ||
504 | raw_spin_lock_irqsave(&pa->lock, flags); | |
d0c6ae41 | 505 | status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); |
67b563f1 JC |
506 | if (status & SPMI_PIC_ACC_ENABLE_BIT) { |
507 | status = status & ~SPMI_PIC_ACC_ENABLE_BIT; | |
d0c6ae41 GA |
508 | writel_relaxed(status, pa->intr + |
509 | pa->ver_ops->acc_enable(apid)); | |
67b563f1 JC |
510 | } |
511 | raw_spin_unlock_irqrestore(&pa->lock, flags); | |
512 | ||
513 | data = 1 << irq; | |
514 | qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); | |
515 | } | |
516 | ||
517 | static void qpnpint_irq_unmask(struct irq_data *d) | |
518 | { | |
519 | struct spmi_pmic_arb_dev *pa = irq_data_get_irq_chip_data(d); | |
520 | u8 irq = d->hwirq >> 8; | |
521 | u8 apid = d->hwirq; | |
522 | unsigned long flags; | |
523 | u32 status; | |
524 | u8 data; | |
525 | ||
526 | raw_spin_lock_irqsave(&pa->lock, flags); | |
d0c6ae41 | 527 | status = readl_relaxed(pa->intr + pa->ver_ops->acc_enable(apid)); |
67b563f1 JC |
528 | if (!(status & SPMI_PIC_ACC_ENABLE_BIT)) { |
529 | writel_relaxed(status | SPMI_PIC_ACC_ENABLE_BIT, | |
d0c6ae41 | 530 | pa->intr + pa->ver_ops->acc_enable(apid)); |
67b563f1 JC |
531 | } |
532 | raw_spin_unlock_irqrestore(&pa->lock, flags); | |
533 | ||
534 | data = 1 << irq; | |
535 | qpnpint_spmi_write(d, QPNPINT_REG_EN_SET, &data, 1); | |
536 | } | |
537 | ||
538 | static void qpnpint_irq_enable(struct irq_data *d) | |
539 | { | |
540 | u8 irq = d->hwirq >> 8; | |
541 | u8 data; | |
542 | ||
543 | qpnpint_irq_unmask(d); | |
544 | ||
545 | data = 1 << irq; | |
546 | qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); | |
547 | } | |
548 | ||
549 | static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) | |
550 | { | |
551 | struct spmi_pmic_arb_qpnpint_type type; | |
552 | u8 irq = d->hwirq >> 8; | |
553 | ||
554 | qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); | |
555 | ||
556 | if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { | |
557 | type.type |= 1 << irq; | |
558 | if (flow_type & IRQF_TRIGGER_RISING) | |
559 | type.polarity_high |= 1 << irq; | |
560 | if (flow_type & IRQF_TRIGGER_FALLING) | |
561 | type.polarity_low |= 1 << irq; | |
562 | } else { | |
563 | if ((flow_type & (IRQF_TRIGGER_HIGH)) && | |
564 | (flow_type & (IRQF_TRIGGER_LOW))) | |
565 | return -EINVAL; | |
566 | ||
567 | type.type &= ~(1 << irq); /* level trig */ | |
568 | if (flow_type & IRQF_TRIGGER_HIGH) | |
569 | type.polarity_high |= 1 << irq; | |
570 | else | |
571 | type.polarity_low |= 1 << irq; | |
572 | } | |
573 | ||
574 | qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type)); | |
575 | return 0; | |
576 | } | |
577 | ||
60be4230 CC |
578 | static int qpnpint_get_irqchip_state(struct irq_data *d, |
579 | enum irqchip_irq_state which, | |
580 | bool *state) | |
581 | { | |
582 | u8 irq = d->hwirq >> 8; | |
583 | u8 status = 0; | |
584 | ||
585 | if (which != IRQCHIP_STATE_LINE_LEVEL) | |
586 | return -EINVAL; | |
587 | ||
588 | qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1); | |
589 | *state = !!(status & BIT(irq)); | |
590 | ||
591 | return 0; | |
592 | } | |
593 | ||
67b563f1 JC |
594 | static struct irq_chip pmic_arb_irqchip = { |
595 | .name = "pmic_arb", | |
596 | .irq_enable = qpnpint_irq_enable, | |
597 | .irq_ack = qpnpint_irq_ack, | |
598 | .irq_mask = qpnpint_irq_mask, | |
599 | .irq_unmask = qpnpint_irq_unmask, | |
600 | .irq_set_type = qpnpint_irq_set_type, | |
60be4230 | 601 | .irq_get_irqchip_state = qpnpint_get_irqchip_state, |
67b563f1 JC |
602 | .flags = IRQCHIP_MASK_ON_SUSPEND |
603 | | IRQCHIP_SKIP_SET_WAKE, | |
604 | }; | |
605 | ||
606 | struct spmi_pmic_arb_irq_spec { | |
607 | unsigned slave:4; | |
608 | unsigned per:8; | |
609 | unsigned irq:3; | |
610 | }; | |
611 | ||
612 | static int search_mapping_table(struct spmi_pmic_arb_dev *pa, | |
613 | struct spmi_pmic_arb_irq_spec *spec, | |
614 | u8 *apid) | |
615 | { | |
616 | u16 ppid = spec->slave << 8 | spec->per; | |
617 | u32 *mapping_table = pa->mapping_table; | |
618 | int index = 0, i; | |
619 | u32 data; | |
620 | ||
621 | for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { | |
622 | data = mapping_table[index]; | |
623 | ||
624 | if (ppid & (1 << SPMI_MAPPING_BIT_INDEX(data))) { | |
625 | if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) { | |
626 | index = SPMI_MAPPING_BIT_IS_1_RESULT(data); | |
627 | } else { | |
628 | *apid = SPMI_MAPPING_BIT_IS_1_RESULT(data); | |
629 | return 0; | |
630 | } | |
631 | } else { | |
632 | if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) { | |
633 | index = SPMI_MAPPING_BIT_IS_0_RESULT(data); | |
634 | } else { | |
635 | *apid = SPMI_MAPPING_BIT_IS_0_RESULT(data); | |
636 | return 0; | |
637 | } | |
638 | } | |
639 | } | |
640 | ||
641 | return -ENODEV; | |
642 | } | |
643 | ||
644 | static int qpnpint_irq_domain_dt_translate(struct irq_domain *d, | |
645 | struct device_node *controller, | |
646 | const u32 *intspec, | |
647 | unsigned int intsize, | |
648 | unsigned long *out_hwirq, | |
649 | unsigned int *out_type) | |
650 | { | |
651 | struct spmi_pmic_arb_dev *pa = d->host_data; | |
652 | struct spmi_pmic_arb_irq_spec spec; | |
653 | int err; | |
654 | u8 apid; | |
655 | ||
656 | dev_dbg(&pa->spmic->dev, | |
657 | "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n", | |
658 | intspec[0], intspec[1], intspec[2]); | |
659 | ||
5d4c9bc7 | 660 | if (irq_domain_get_of_node(d) != controller) |
67b563f1 JC |
661 | return -EINVAL; |
662 | if (intsize != 4) | |
663 | return -EINVAL; | |
664 | if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7) | |
665 | return -EINVAL; | |
666 | ||
667 | spec.slave = intspec[0]; | |
668 | spec.per = intspec[1]; | |
669 | spec.irq = intspec[2]; | |
670 | ||
671 | err = search_mapping_table(pa, &spec, &apid); | |
672 | if (err) | |
673 | return err; | |
674 | ||
675 | pa->apid_to_ppid[apid] = spec.slave << 8 | spec.per; | |
676 | ||
677 | /* Keep track of {max,min}_apid for bounding search during interrupt */ | |
678 | if (apid > pa->max_apid) | |
679 | pa->max_apid = apid; | |
680 | if (apid < pa->min_apid) | |
681 | pa->min_apid = apid; | |
682 | ||
683 | *out_hwirq = spec.slave << 24 | |
684 | | spec.per << 16 | |
685 | | spec.irq << 8 | |
686 | | apid; | |
687 | *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; | |
688 | ||
689 | dev_dbg(&pa->spmic->dev, "out_hwirq = %lu\n", *out_hwirq); | |
690 | ||
691 | return 0; | |
692 | } | |
693 | ||
694 | static int qpnpint_irq_domain_map(struct irq_domain *d, | |
695 | unsigned int virq, | |
696 | irq_hw_number_t hwirq) | |
697 | { | |
698 | struct spmi_pmic_arb_dev *pa = d->host_data; | |
699 | ||
700 | dev_dbg(&pa->spmic->dev, "virq = %u, hwirq = %lu\n", virq, hwirq); | |
701 | ||
702 | irq_set_chip_and_handler(virq, &pmic_arb_irqchip, handle_level_irq); | |
703 | irq_set_chip_data(virq, d->host_data); | |
704 | irq_set_noprobe(virq); | |
705 | return 0; | |
706 | } | |
707 | ||
d0c6ae41 GA |
708 | /* v1 offset per ee */ |
709 | static u32 pmic_arb_offset_v1(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr) | |
710 | { | |
711 | return 0x800 + 0x80 * pa->channel; | |
712 | } | |
713 | ||
714 | /* v2 offset per ppid (chan) and per ee */ | |
715 | static u32 pmic_arb_offset_v2(struct spmi_pmic_arb_dev *pa, u8 sid, u16 addr) | |
716 | { | |
717 | u16 ppid = (sid << 8) | (addr >> 8); | |
718 | u8 chan = pa->ppid_to_chan[ppid]; | |
719 | ||
720 | return 0x1000 * pa->ee + 0x8000 * chan; | |
721 | } | |
722 | ||
723 | static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc) | |
724 | { | |
725 | return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7); | |
726 | } | |
727 | ||
728 | static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc) | |
729 | { | |
730 | return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7); | |
731 | } | |
732 | ||
733 | static u32 pmic_arb_owner_acc_status_v1(u8 m, u8 n) | |
734 | { | |
735 | return 0x20 * m + 0x4 * n; | |
736 | } | |
737 | ||
738 | static u32 pmic_arb_owner_acc_status_v2(u8 m, u8 n) | |
739 | { | |
740 | return 0x100000 + 0x1000 * m + 0x4 * n; | |
741 | } | |
742 | ||
743 | static u32 pmic_arb_acc_enable_v1(u8 n) | |
744 | { | |
745 | return 0x200 + 0x4 * n; | |
746 | } | |
747 | ||
748 | static u32 pmic_arb_acc_enable_v2(u8 n) | |
749 | { | |
750 | return 0x1000 * n; | |
751 | } | |
752 | ||
753 | static u32 pmic_arb_irq_status_v1(u8 n) | |
754 | { | |
755 | return 0x600 + 0x4 * n; | |
756 | } | |
757 | ||
758 | static u32 pmic_arb_irq_status_v2(u8 n) | |
759 | { | |
760 | return 0x4 + 0x1000 * n; | |
761 | } | |
762 | ||
763 | static u32 pmic_arb_irq_clear_v1(u8 n) | |
764 | { | |
765 | return 0xA00 + 0x4 * n; | |
766 | } | |
767 | ||
768 | static u32 pmic_arb_irq_clear_v2(u8 n) | |
769 | { | |
770 | return 0x8 + 0x1000 * n; | |
771 | } | |
772 | ||
773 | static const struct pmic_arb_ver_ops pmic_arb_v1 = { | |
774 | .non_data_cmd = pmic_arb_non_data_cmd_v1, | |
775 | .offset = pmic_arb_offset_v1, | |
776 | .fmt_cmd = pmic_arb_fmt_cmd_v1, | |
777 | .owner_acc_status = pmic_arb_owner_acc_status_v1, | |
778 | .acc_enable = pmic_arb_acc_enable_v1, | |
779 | .irq_status = pmic_arb_irq_status_v1, | |
780 | .irq_clear = pmic_arb_irq_clear_v1, | |
781 | }; | |
782 | ||
783 | static const struct pmic_arb_ver_ops pmic_arb_v2 = { | |
784 | .non_data_cmd = pmic_arb_non_data_cmd_v2, | |
785 | .offset = pmic_arb_offset_v2, | |
786 | .fmt_cmd = pmic_arb_fmt_cmd_v2, | |
787 | .owner_acc_status = pmic_arb_owner_acc_status_v2, | |
788 | .acc_enable = pmic_arb_acc_enable_v2, | |
789 | .irq_status = pmic_arb_irq_status_v2, | |
790 | .irq_clear = pmic_arb_irq_clear_v2, | |
791 | }; | |
792 | ||
67b563f1 JC |
793 | static const struct irq_domain_ops pmic_arb_irq_domain_ops = { |
794 | .map = qpnpint_irq_domain_map, | |
795 | .xlate = qpnpint_irq_domain_dt_translate, | |
796 | }; | |
797 | ||
39ae93e3 KH |
798 | static int spmi_pmic_arb_probe(struct platform_device *pdev) |
799 | { | |
800 | struct spmi_pmic_arb_dev *pa; | |
801 | struct spmi_controller *ctrl; | |
802 | struct resource *res; | |
d0c6ae41 GA |
803 | void __iomem *core; |
804 | u32 channel, ee, hw_ver; | |
39ae93e3 | 805 | int err, i; |
d0c6ae41 | 806 | bool is_v1; |
39ae93e3 KH |
807 | |
808 | ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pa)); | |
809 | if (!ctrl) | |
810 | return -ENOMEM; | |
811 | ||
812 | pa = spmi_controller_get_drvdata(ctrl); | |
67b563f1 | 813 | pa->spmic = ctrl; |
39ae93e3 KH |
814 | |
815 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); | |
d0c6ae41 GA |
816 | core = devm_ioremap_resource(&ctrl->dev, res); |
817 | if (IS_ERR(core)) { | |
818 | err = PTR_ERR(core); | |
39ae93e3 KH |
819 | goto err_put_ctrl; |
820 | } | |
821 | ||
d0c6ae41 GA |
822 | hw_ver = readl_relaxed(core + PMIC_ARB_VERSION); |
823 | is_v1 = (hw_ver < PMIC_ARB_VERSION_V2_MIN); | |
824 | ||
825 | dev_info(&ctrl->dev, "PMIC Arb Version-%d (0x%x)\n", (is_v1 ? 1 : 2), | |
826 | hw_ver); | |
827 | ||
828 | if (is_v1) { | |
829 | pa->ver_ops = &pmic_arb_v1; | |
830 | pa->wr_base = core; | |
831 | pa->rd_base = core; | |
832 | } else { | |
833 | u8 chan; | |
834 | u16 ppid; | |
835 | u32 regval; | |
836 | ||
837 | pa->ver_ops = &pmic_arb_v2; | |
838 | ||
839 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
840 | "obsrvr"); | |
841 | pa->rd_base = devm_ioremap_resource(&ctrl->dev, res); | |
842 | if (IS_ERR(pa->rd_base)) { | |
843 | err = PTR_ERR(pa->rd_base); | |
844 | goto err_put_ctrl; | |
845 | } | |
846 | ||
847 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, | |
848 | "chnls"); | |
849 | pa->wr_base = devm_ioremap_resource(&ctrl->dev, res); | |
850 | if (IS_ERR(pa->wr_base)) { | |
851 | err = PTR_ERR(pa->wr_base); | |
852 | goto err_put_ctrl; | |
853 | } | |
854 | ||
855 | pa->ppid_to_chan = devm_kzalloc(&ctrl->dev, | |
856 | PPID_TO_CHAN_TABLE_SZ, GFP_KERNEL); | |
857 | if (!pa->ppid_to_chan) { | |
858 | err = -ENOMEM; | |
859 | goto err_put_ctrl; | |
860 | } | |
861 | /* | |
862 | * PMIC_ARB_REG_CHNL is a table in HW mapping channel to ppid. | |
863 | * ppid_to_chan is an in-memory invert of that table. | |
864 | */ | |
865 | for (chan = 0; chan < PMIC_ARB_MAX_CHNL; ++chan) { | |
866 | regval = readl_relaxed(core + PMIC_ARB_REG_CHNL(chan)); | |
867 | if (!regval) | |
868 | continue; | |
869 | ||
870 | ppid = (regval >> 8) & 0xFFF; | |
871 | pa->ppid_to_chan[ppid] = chan; | |
872 | } | |
873 | } | |
874 | ||
39ae93e3 KH |
875 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr"); |
876 | pa->intr = devm_ioremap_resource(&ctrl->dev, res); | |
877 | if (IS_ERR(pa->intr)) { | |
878 | err = PTR_ERR(pa->intr); | |
879 | goto err_put_ctrl; | |
880 | } | |
881 | ||
882 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg"); | |
883 | pa->cnfg = devm_ioremap_resource(&ctrl->dev, res); | |
884 | if (IS_ERR(pa->cnfg)) { | |
885 | err = PTR_ERR(pa->cnfg); | |
886 | goto err_put_ctrl; | |
887 | } | |
888 | ||
67b563f1 JC |
889 | pa->irq = platform_get_irq_byname(pdev, "periph_irq"); |
890 | if (pa->irq < 0) { | |
891 | err = pa->irq; | |
892 | goto err_put_ctrl; | |
893 | } | |
894 | ||
39ae93e3 KH |
895 | err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); |
896 | if (err) { | |
897 | dev_err(&pdev->dev, "channel unspecified.\n"); | |
898 | goto err_put_ctrl; | |
899 | } | |
900 | ||
901 | if (channel > 5) { | |
902 | dev_err(&pdev->dev, "invalid channel (%u) specified.\n", | |
903 | channel); | |
904 | goto err_put_ctrl; | |
905 | } | |
906 | ||
907 | pa->channel = channel; | |
908 | ||
67b563f1 JC |
909 | err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee); |
910 | if (err) { | |
911 | dev_err(&pdev->dev, "EE unspecified.\n"); | |
912 | goto err_put_ctrl; | |
913 | } | |
914 | ||
915 | if (ee > 5) { | |
916 | dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee); | |
917 | err = -EINVAL; | |
918 | goto err_put_ctrl; | |
919 | } | |
920 | ||
921 | pa->ee = ee; | |
922 | ||
923 | for (i = 0; i < ARRAY_SIZE(pa->mapping_table); ++i) | |
924 | pa->mapping_table[i] = readl_relaxed( | |
925 | pa->cnfg + SPMI_MAPPING_TABLE_REG(i)); | |
926 | ||
927 | /* Initialize max_apid/min_apid to the opposite bounds, during | |
928 | * the irq domain translation, we are sure to update these */ | |
929 | pa->max_apid = 0; | |
930 | pa->min_apid = PMIC_ARB_MAX_PERIPHS - 1; | |
931 | ||
39ae93e3 KH |
932 | platform_set_drvdata(pdev, ctrl); |
933 | raw_spin_lock_init(&pa->lock); | |
934 | ||
935 | ctrl->cmd = pmic_arb_cmd; | |
936 | ctrl->read_cmd = pmic_arb_read_cmd; | |
937 | ctrl->write_cmd = pmic_arb_write_cmd; | |
938 | ||
67b563f1 JC |
939 | dev_dbg(&pdev->dev, "adding irq domain\n"); |
940 | pa->domain = irq_domain_add_tree(pdev->dev.of_node, | |
941 | &pmic_arb_irq_domain_ops, pa); | |
942 | if (!pa->domain) { | |
943 | dev_err(&pdev->dev, "unable to create irq_domain\n"); | |
944 | err = -ENOMEM; | |
945 | goto err_put_ctrl; | |
946 | } | |
947 | ||
fb68ba6d | 948 | irq_set_chained_handler_and_data(pa->irq, pmic_arb_chained_irq, pa); |
67b563f1 | 949 | |
39ae93e3 KH |
950 | err = spmi_controller_add(ctrl); |
951 | if (err) | |
67b563f1 | 952 | goto err_domain_remove; |
39ae93e3 | 953 | |
39ae93e3 KH |
954 | return 0; |
955 | ||
67b563f1 | 956 | err_domain_remove: |
fb68ba6d | 957 | irq_set_chained_handler_and_data(pa->irq, NULL, NULL); |
67b563f1 | 958 | irq_domain_remove(pa->domain); |
39ae93e3 KH |
959 | err_put_ctrl: |
960 | spmi_controller_put(ctrl); | |
961 | return err; | |
962 | } | |
963 | ||
964 | static int spmi_pmic_arb_remove(struct platform_device *pdev) | |
965 | { | |
966 | struct spmi_controller *ctrl = platform_get_drvdata(pdev); | |
67b563f1 | 967 | struct spmi_pmic_arb_dev *pa = spmi_controller_get_drvdata(ctrl); |
39ae93e3 | 968 | spmi_controller_remove(ctrl); |
fb68ba6d | 969 | irq_set_chained_handler_and_data(pa->irq, NULL, NULL); |
67b563f1 | 970 | irq_domain_remove(pa->domain); |
39ae93e3 KH |
971 | spmi_controller_put(ctrl); |
972 | return 0; | |
973 | } | |
974 | ||
975 | static const struct of_device_id spmi_pmic_arb_match_table[] = { | |
976 | { .compatible = "qcom,spmi-pmic-arb", }, | |
977 | {}, | |
978 | }; | |
979 | MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table); | |
980 | ||
981 | static struct platform_driver spmi_pmic_arb_driver = { | |
982 | .probe = spmi_pmic_arb_probe, | |
983 | .remove = spmi_pmic_arb_remove, | |
984 | .driver = { | |
985 | .name = "spmi_pmic_arb", | |
39ae93e3 KH |
986 | .of_match_table = spmi_pmic_arb_match_table, |
987 | }, | |
988 | }; | |
989 | module_platform_driver(spmi_pmic_arb_driver); | |
990 | ||
991 | MODULE_LICENSE("GPL v2"); | |
992 | MODULE_ALIAS("platform:spmi_pmic_arb"); |