]>
Commit | Line | Data |
---|---|---|
61e115a5 MB |
1 | /* |
2 | * Sonics Silicon Backplane | |
3 | * Subsystem core | |
4 | * | |
5 | * Copyright 2005, Broadcom Corporation | |
6 | * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> | |
7 | * | |
8 | * Licensed under the GNU/GPL. See COPYING for details. | |
9 | */ | |
10 | ||
11 | #include "ssb_private.h" | |
12 | ||
13 | #include <linux/delay.h> | |
6faf035c | 14 | #include <linux/io.h> |
61e115a5 MB |
15 | #include <linux/ssb/ssb.h> |
16 | #include <linux/ssb/ssb_regs.h> | |
aab547ce | 17 | #include <linux/ssb/ssb_driver_gige.h> |
61e115a5 MB |
18 | #include <linux/dma-mapping.h> |
19 | #include <linux/pci.h> | |
24ea602e | 20 | #include <linux/mmc/sdio_func.h> |
61e115a5 MB |
21 | |
22 | #include <pcmcia/cs_types.h> | |
23 | #include <pcmcia/cs.h> | |
24 | #include <pcmcia/cistpl.h> | |
25 | #include <pcmcia/ds.h> | |
26 | ||
27 | ||
28 | MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); | |
29 | MODULE_LICENSE("GPL"); | |
30 | ||
31 | ||
32 | /* Temporary list of yet-to-be-attached buses */ | |
33 | static LIST_HEAD(attach_queue); | |
34 | /* List if running buses */ | |
35 | static LIST_HEAD(buses); | |
36 | /* Software ID counter */ | |
37 | static unsigned int next_busnumber; | |
38 | /* buses_mutes locks the two buslists and the next_busnumber. | |
39 | * Don't lock this directly, but use ssb_buses_[un]lock() below. */ | |
40 | static DEFINE_MUTEX(buses_mutex); | |
41 | ||
42 | /* There are differences in the codeflow, if the bus is | |
43 | * initialized from early boot, as various needed services | |
44 | * are not available early. This is a mechanism to delay | |
45 | * these initializations to after early boot has finished. | |
46 | * It's also used to avoid mutex locking, as that's not | |
47 | * available and needed early. */ | |
48 | static bool ssb_is_early_boot = 1; | |
49 | ||
50 | static void ssb_buses_lock(void); | |
51 | static void ssb_buses_unlock(void); | |
52 | ||
53 | ||
54 | #ifdef CONFIG_SSB_PCIHOST | |
55 | struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) | |
56 | { | |
57 | struct ssb_bus *bus; | |
58 | ||
59 | ssb_buses_lock(); | |
60 | list_for_each_entry(bus, &buses, list) { | |
61 | if (bus->bustype == SSB_BUSTYPE_PCI && | |
62 | bus->host_pci == pdev) | |
63 | goto found; | |
64 | } | |
65 | bus = NULL; | |
66 | found: | |
67 | ssb_buses_unlock(); | |
68 | ||
69 | return bus; | |
70 | } | |
71 | #endif /* CONFIG_SSB_PCIHOST */ | |
72 | ||
e7ec2e32 MB |
73 | #ifdef CONFIG_SSB_PCMCIAHOST |
74 | struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev) | |
75 | { | |
76 | struct ssb_bus *bus; | |
77 | ||
78 | ssb_buses_lock(); | |
79 | list_for_each_entry(bus, &buses, list) { | |
80 | if (bus->bustype == SSB_BUSTYPE_PCMCIA && | |
81 | bus->host_pcmcia == pdev) | |
82 | goto found; | |
83 | } | |
84 | bus = NULL; | |
85 | found: | |
86 | ssb_buses_unlock(); | |
87 | ||
88 | return bus; | |
89 | } | |
90 | #endif /* CONFIG_SSB_PCMCIAHOST */ | |
91 | ||
24ea602e AH |
92 | #ifdef CONFIG_SSB_SDIOHOST |
93 | struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func) | |
94 | { | |
95 | struct ssb_bus *bus; | |
96 | ||
97 | ssb_buses_lock(); | |
98 | list_for_each_entry(bus, &buses, list) { | |
99 | if (bus->bustype == SSB_BUSTYPE_SDIO && | |
100 | bus->host_sdio == func) | |
101 | goto found; | |
102 | } | |
103 | bus = NULL; | |
104 | found: | |
105 | ssb_buses_unlock(); | |
106 | ||
107 | return bus; | |
108 | } | |
109 | #endif /* CONFIG_SSB_SDIOHOST */ | |
110 | ||
aab547ce MB |
111 | int ssb_for_each_bus_call(unsigned long data, |
112 | int (*func)(struct ssb_bus *bus, unsigned long data)) | |
113 | { | |
114 | struct ssb_bus *bus; | |
115 | int res; | |
116 | ||
117 | ssb_buses_lock(); | |
118 | list_for_each_entry(bus, &buses, list) { | |
119 | res = func(bus, data); | |
120 | if (res >= 0) { | |
121 | ssb_buses_unlock(); | |
122 | return res; | |
123 | } | |
124 | } | |
125 | ssb_buses_unlock(); | |
126 | ||
127 | return -ENODEV; | |
128 | } | |
129 | ||
61e115a5 MB |
130 | static struct ssb_device *ssb_device_get(struct ssb_device *dev) |
131 | { | |
132 | if (dev) | |
133 | get_device(dev->dev); | |
134 | return dev; | |
135 | } | |
136 | ||
137 | static void ssb_device_put(struct ssb_device *dev) | |
138 | { | |
139 | if (dev) | |
140 | put_device(dev->dev); | |
141 | } | |
142 | ||
3ba6018a MB |
143 | static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv) |
144 | { | |
145 | if (drv) | |
146 | get_driver(&drv->drv); | |
147 | return drv; | |
148 | } | |
149 | ||
150 | static inline void ssb_driver_put(struct ssb_driver *drv) | |
151 | { | |
152 | if (drv) | |
153 | put_driver(&drv->drv); | |
154 | } | |
155 | ||
61e115a5 MB |
156 | static int ssb_device_resume(struct device *dev) |
157 | { | |
158 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
159 | struct ssb_driver *ssb_drv; | |
61e115a5 MB |
160 | int err = 0; |
161 | ||
61e115a5 MB |
162 | if (dev->driver) { |
163 | ssb_drv = drv_to_ssb_drv(dev->driver); | |
164 | if (ssb_drv && ssb_drv->resume) | |
165 | err = ssb_drv->resume(ssb_dev); | |
166 | if (err) | |
167 | goto out; | |
168 | } | |
169 | out: | |
170 | return err; | |
171 | } | |
172 | ||
61e115a5 MB |
173 | static int ssb_device_suspend(struct device *dev, pm_message_t state) |
174 | { | |
175 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
176 | struct ssb_driver *ssb_drv; | |
61e115a5 MB |
177 | int err = 0; |
178 | ||
179 | if (dev->driver) { | |
180 | ssb_drv = drv_to_ssb_drv(dev->driver); | |
181 | if (ssb_drv && ssb_drv->suspend) | |
182 | err = ssb_drv->suspend(ssb_dev, state); | |
183 | if (err) | |
184 | goto out; | |
185 | } | |
8fe2b65a MB |
186 | out: |
187 | return err; | |
188 | } | |
61e115a5 | 189 | |
8fe2b65a MB |
190 | int ssb_bus_resume(struct ssb_bus *bus) |
191 | { | |
192 | int err; | |
193 | ||
194 | /* Reset HW state information in memory, so that HW is | |
195 | * completely reinitialized. */ | |
196 | bus->mapped_device = NULL; | |
197 | #ifdef CONFIG_SSB_DRIVER_PCICORE | |
198 | bus->pcicore.setup_done = 0; | |
199 | #endif | |
200 | ||
201 | err = ssb_bus_powerup(bus, 0); | |
202 | if (err) | |
203 | return err; | |
204 | err = ssb_pcmcia_hardware_setup(bus); | |
205 | if (err) { | |
206 | ssb_bus_may_powerdown(bus); | |
207 | return err; | |
61e115a5 | 208 | } |
8fe2b65a MB |
209 | ssb_chipco_resume(&bus->chipco); |
210 | ssb_bus_may_powerdown(bus); | |
61e115a5 | 211 | |
8fe2b65a MB |
212 | return 0; |
213 | } | |
214 | EXPORT_SYMBOL(ssb_bus_resume); | |
215 | ||
216 | int ssb_bus_suspend(struct ssb_bus *bus) | |
217 | { | |
218 | ssb_chipco_suspend(&bus->chipco); | |
219 | ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); | |
220 | ||
221 | return 0; | |
61e115a5 | 222 | } |
8fe2b65a | 223 | EXPORT_SYMBOL(ssb_bus_suspend); |
61e115a5 | 224 | |
d72bb40f | 225 | #ifdef CONFIG_SSB_SPROM |
3ba6018a MB |
226 | /** ssb_devices_freeze - Freeze all devices on the bus. |
227 | * | |
228 | * After freezing no device driver will be handling a device | |
229 | * on this bus anymore. ssb_devices_thaw() must be called after | |
230 | * a successful freeze to reactivate the devices. | |
231 | * | |
232 | * @bus: The bus. | |
233 | * @ctx: Context structure. Pass this to ssb_devices_thaw(). | |
234 | */ | |
235 | int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx) | |
61e115a5 | 236 | { |
3ba6018a MB |
237 | struct ssb_device *sdev; |
238 | struct ssb_driver *sdrv; | |
239 | unsigned int i; | |
240 | ||
241 | memset(ctx, 0, sizeof(*ctx)); | |
242 | ctx->bus = bus; | |
243 | SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen)); | |
61e115a5 | 244 | |
61e115a5 | 245 | for (i = 0; i < bus->nr_devices; i++) { |
3ba6018a MB |
246 | sdev = ssb_device_get(&bus->devices[i]); |
247 | ||
248 | if (!sdev->dev || !sdev->dev->driver || | |
249 | !device_is_registered(sdev->dev)) { | |
250 | ssb_device_put(sdev); | |
61e115a5 | 251 | continue; |
61e115a5 | 252 | } |
3ba6018a MB |
253 | sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver)); |
254 | if (!sdrv || SSB_WARN_ON(!sdrv->remove)) { | |
255 | ssb_device_put(sdev); | |
61e115a5 | 256 | continue; |
61e115a5 | 257 | } |
3ba6018a MB |
258 | sdrv->remove(sdev); |
259 | ctx->device_frozen[i] = 1; | |
61e115a5 MB |
260 | } |
261 | ||
262 | return 0; | |
61e115a5 MB |
263 | } |
264 | ||
3ba6018a MB |
265 | /** ssb_devices_thaw - Unfreeze all devices on the bus. |
266 | * | |
267 | * This will re-attach the device drivers and re-init the devices. | |
268 | * | |
269 | * @ctx: The context structure from ssb_devices_freeze() | |
270 | */ | |
271 | int ssb_devices_thaw(struct ssb_freeze_context *ctx) | |
61e115a5 | 272 | { |
3ba6018a MB |
273 | struct ssb_bus *bus = ctx->bus; |
274 | struct ssb_device *sdev; | |
275 | struct ssb_driver *sdrv; | |
276 | unsigned int i; | |
277 | int err, result = 0; | |
61e115a5 MB |
278 | |
279 | for (i = 0; i < bus->nr_devices; i++) { | |
3ba6018a | 280 | if (!ctx->device_frozen[i]) |
61e115a5 | 281 | continue; |
3ba6018a MB |
282 | sdev = &bus->devices[i]; |
283 | ||
284 | if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver)) | |
61e115a5 | 285 | continue; |
3ba6018a MB |
286 | sdrv = drv_to_ssb_drv(sdev->dev->driver); |
287 | if (SSB_WARN_ON(!sdrv || !sdrv->probe)) | |
61e115a5 | 288 | continue; |
3ba6018a MB |
289 | |
290 | err = sdrv->probe(sdev, &sdev->id); | |
61e115a5 MB |
291 | if (err) { |
292 | ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", | |
3ba6018a MB |
293 | dev_name(sdev->dev)); |
294 | result = err; | |
61e115a5 | 295 | } |
3ba6018a MB |
296 | ssb_driver_put(sdrv); |
297 | ssb_device_put(sdev); | |
61e115a5 MB |
298 | } |
299 | ||
3ba6018a | 300 | return result; |
61e115a5 | 301 | } |
d72bb40f | 302 | #endif /* CONFIG_SSB_SPROM */ |
61e115a5 MB |
303 | |
304 | static void ssb_device_shutdown(struct device *dev) | |
305 | { | |
306 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
307 | struct ssb_driver *ssb_drv; | |
308 | ||
309 | if (!dev->driver) | |
310 | return; | |
311 | ssb_drv = drv_to_ssb_drv(dev->driver); | |
312 | if (ssb_drv && ssb_drv->shutdown) | |
313 | ssb_drv->shutdown(ssb_dev); | |
314 | } | |
315 | ||
316 | static int ssb_device_remove(struct device *dev) | |
317 | { | |
318 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
319 | struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); | |
320 | ||
321 | if (ssb_drv && ssb_drv->remove) | |
322 | ssb_drv->remove(ssb_dev); | |
323 | ssb_device_put(ssb_dev); | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
328 | static int ssb_device_probe(struct device *dev) | |
329 | { | |
330 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
331 | struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); | |
332 | int err = 0; | |
333 | ||
334 | ssb_device_get(ssb_dev); | |
335 | if (ssb_drv && ssb_drv->probe) | |
336 | err = ssb_drv->probe(ssb_dev, &ssb_dev->id); | |
337 | if (err) | |
338 | ssb_device_put(ssb_dev); | |
339 | ||
340 | return err; | |
341 | } | |
342 | ||
343 | static int ssb_match_devid(const struct ssb_device_id *tabid, | |
344 | const struct ssb_device_id *devid) | |
345 | { | |
346 | if ((tabid->vendor != devid->vendor) && | |
347 | tabid->vendor != SSB_ANY_VENDOR) | |
348 | return 0; | |
349 | if ((tabid->coreid != devid->coreid) && | |
350 | tabid->coreid != SSB_ANY_ID) | |
351 | return 0; | |
352 | if ((tabid->revision != devid->revision) && | |
353 | tabid->revision != SSB_ANY_REV) | |
354 | return 0; | |
355 | return 1; | |
356 | } | |
357 | ||
358 | static int ssb_bus_match(struct device *dev, struct device_driver *drv) | |
359 | { | |
360 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
361 | struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); | |
362 | const struct ssb_device_id *id; | |
363 | ||
364 | for (id = ssb_drv->id_table; | |
365 | id->vendor || id->coreid || id->revision; | |
366 | id++) { | |
367 | if (ssb_match_devid(id, &ssb_dev->id)) | |
368 | return 1; /* found */ | |
369 | } | |
370 | ||
371 | return 0; | |
372 | } | |
373 | ||
7ac0326c | 374 | static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) |
61e115a5 MB |
375 | { |
376 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
61e115a5 MB |
377 | |
378 | if (!dev) | |
379 | return -ENODEV; | |
380 | ||
7ac0326c | 381 | return add_uevent_var(env, |
61e115a5 MB |
382 | "MODALIAS=ssb:v%04Xid%04Xrev%02X", |
383 | ssb_dev->id.vendor, ssb_dev->id.coreid, | |
384 | ssb_dev->id.revision); | |
61e115a5 MB |
385 | } |
386 | ||
387 | static struct bus_type ssb_bustype = { | |
388 | .name = "ssb", | |
389 | .match = ssb_bus_match, | |
390 | .probe = ssb_device_probe, | |
391 | .remove = ssb_device_remove, | |
392 | .shutdown = ssb_device_shutdown, | |
393 | .suspend = ssb_device_suspend, | |
394 | .resume = ssb_device_resume, | |
395 | .uevent = ssb_device_uevent, | |
396 | }; | |
397 | ||
398 | static void ssb_buses_lock(void) | |
399 | { | |
400 | /* See the comment at the ssb_is_early_boot definition */ | |
401 | if (!ssb_is_early_boot) | |
402 | mutex_lock(&buses_mutex); | |
403 | } | |
404 | ||
405 | static void ssb_buses_unlock(void) | |
406 | { | |
407 | /* See the comment at the ssb_is_early_boot definition */ | |
408 | if (!ssb_is_early_boot) | |
409 | mutex_unlock(&buses_mutex); | |
410 | } | |
411 | ||
412 | static void ssb_devices_unregister(struct ssb_bus *bus) | |
413 | { | |
414 | struct ssb_device *sdev; | |
415 | int i; | |
416 | ||
417 | for (i = bus->nr_devices - 1; i >= 0; i--) { | |
418 | sdev = &(bus->devices[i]); | |
419 | if (sdev->dev) | |
420 | device_unregister(sdev->dev); | |
421 | } | |
422 | } | |
423 | ||
424 | void ssb_bus_unregister(struct ssb_bus *bus) | |
425 | { | |
426 | ssb_buses_lock(); | |
427 | ssb_devices_unregister(bus); | |
428 | list_del(&bus->list); | |
429 | ssb_buses_unlock(); | |
430 | ||
e7ec2e32 | 431 | ssb_pcmcia_exit(bus); |
61e115a5 MB |
432 | ssb_pci_exit(bus); |
433 | ssb_iounmap(bus); | |
434 | } | |
435 | EXPORT_SYMBOL(ssb_bus_unregister); | |
436 | ||
437 | static void ssb_release_dev(struct device *dev) | |
438 | { | |
439 | struct __ssb_dev_wrapper *devwrap; | |
440 | ||
441 | devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); | |
442 | kfree(devwrap); | |
443 | } | |
444 | ||
445 | static int ssb_devices_register(struct ssb_bus *bus) | |
446 | { | |
447 | struct ssb_device *sdev; | |
448 | struct device *dev; | |
449 | struct __ssb_dev_wrapper *devwrap; | |
450 | int i, err = 0; | |
451 | int dev_idx = 0; | |
452 | ||
453 | for (i = 0; i < bus->nr_devices; i++) { | |
454 | sdev = &(bus->devices[i]); | |
455 | ||
456 | /* We don't register SSB-system devices to the kernel, | |
457 | * as the drivers for them are built into SSB. */ | |
458 | switch (sdev->id.coreid) { | |
459 | case SSB_DEV_CHIPCOMMON: | |
460 | case SSB_DEV_PCI: | |
461 | case SSB_DEV_PCIE: | |
462 | case SSB_DEV_PCMCIA: | |
463 | case SSB_DEV_MIPS: | |
464 | case SSB_DEV_MIPS_3302: | |
465 | case SSB_DEV_EXTIF: | |
466 | continue; | |
467 | } | |
468 | ||
469 | devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); | |
470 | if (!devwrap) { | |
471 | ssb_printk(KERN_ERR PFX | |
472 | "Could not allocate device\n"); | |
473 | err = -ENOMEM; | |
474 | goto error; | |
475 | } | |
476 | dev = &devwrap->dev; | |
477 | devwrap->sdev = sdev; | |
478 | ||
479 | dev->release = ssb_release_dev; | |
480 | dev->bus = &ssb_bustype; | |
b7b05fe7 | 481 | dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx); |
61e115a5 MB |
482 | |
483 | switch (bus->bustype) { | |
484 | case SSB_BUSTYPE_PCI: | |
485 | #ifdef CONFIG_SSB_PCIHOST | |
486 | sdev->irq = bus->host_pci->irq; | |
487 | dev->parent = &bus->host_pci->dev; | |
488 | #endif | |
489 | break; | |
490 | case SSB_BUSTYPE_PCMCIA: | |
491 | #ifdef CONFIG_SSB_PCMCIAHOST | |
60d78c44 | 492 | sdev->irq = bus->host_pcmcia->irq.AssignedIRQ; |
61e115a5 | 493 | dev->parent = &bus->host_pcmcia->dev; |
24ea602e AH |
494 | #endif |
495 | break; | |
496 | case SSB_BUSTYPE_SDIO: | |
391ae22a | 497 | #ifdef CONFIG_SSB_SDIOHOST |
24ea602e | 498 | dev->parent = &bus->host_sdio->dev; |
61e115a5 MB |
499 | #endif |
500 | break; | |
501 | case SSB_BUSTYPE_SSB: | |
ac82da33 | 502 | dev->dma_mask = &dev->coherent_dma_mask; |
61e115a5 MB |
503 | break; |
504 | } | |
505 | ||
506 | sdev->dev = dev; | |
507 | err = device_register(dev); | |
508 | if (err) { | |
509 | ssb_printk(KERN_ERR PFX | |
510 | "Could not register %s\n", | |
b7b05fe7 | 511 | dev_name(dev)); |
61e115a5 MB |
512 | /* Set dev to NULL to not unregister |
513 | * dev on error unwinding. */ | |
514 | sdev->dev = NULL; | |
515 | kfree(devwrap); | |
516 | goto error; | |
517 | } | |
518 | dev_idx++; | |
519 | } | |
520 | ||
521 | return 0; | |
522 | error: | |
523 | /* Unwind the already registered devices. */ | |
524 | ssb_devices_unregister(bus); | |
525 | return err; | |
526 | } | |
527 | ||
528 | /* Needs ssb_buses_lock() */ | |
529 | static int ssb_attach_queued_buses(void) | |
530 | { | |
531 | struct ssb_bus *bus, *n; | |
532 | int err = 0; | |
533 | int drop_them_all = 0; | |
534 | ||
535 | list_for_each_entry_safe(bus, n, &attach_queue, list) { | |
536 | if (drop_them_all) { | |
537 | list_del(&bus->list); | |
538 | continue; | |
539 | } | |
540 | /* Can't init the PCIcore in ssb_bus_register(), as that | |
541 | * is too early in boot for embedded systems | |
542 | * (no udelay() available). So do it here in attach stage. | |
543 | */ | |
544 | err = ssb_bus_powerup(bus, 0); | |
545 | if (err) | |
546 | goto error; | |
547 | ssb_pcicore_init(&bus->pcicore); | |
548 | ssb_bus_may_powerdown(bus); | |
549 | ||
550 | err = ssb_devices_register(bus); | |
551 | error: | |
552 | if (err) { | |
553 | drop_them_all = 1; | |
554 | list_del(&bus->list); | |
555 | continue; | |
556 | } | |
557 | list_move_tail(&bus->list, &buses); | |
558 | } | |
559 | ||
560 | return err; | |
561 | } | |
562 | ||
ffc7689d MB |
563 | static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset) |
564 | { | |
565 | struct ssb_bus *bus = dev->bus; | |
566 | ||
567 | offset += dev->core_index * SSB_CORE_SIZE; | |
568 | return readb(bus->mmio + offset); | |
569 | } | |
570 | ||
61e115a5 MB |
571 | static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) |
572 | { | |
573 | struct ssb_bus *bus = dev->bus; | |
574 | ||
575 | offset += dev->core_index * SSB_CORE_SIZE; | |
576 | return readw(bus->mmio + offset); | |
577 | } | |
578 | ||
579 | static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset) | |
580 | { | |
581 | struct ssb_bus *bus = dev->bus; | |
582 | ||
583 | offset += dev->core_index * SSB_CORE_SIZE; | |
584 | return readl(bus->mmio + offset); | |
585 | } | |
586 | ||
d625a29b MB |
587 | #ifdef CONFIG_SSB_BLOCKIO |
588 | static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer, | |
589 | size_t count, u16 offset, u8 reg_width) | |
590 | { | |
591 | struct ssb_bus *bus = dev->bus; | |
592 | void __iomem *addr; | |
593 | ||
594 | offset += dev->core_index * SSB_CORE_SIZE; | |
595 | addr = bus->mmio + offset; | |
596 | ||
597 | switch (reg_width) { | |
598 | case sizeof(u8): { | |
599 | u8 *buf = buffer; | |
600 | ||
601 | while (count) { | |
602 | *buf = __raw_readb(addr); | |
603 | buf++; | |
604 | count--; | |
605 | } | |
606 | break; | |
607 | } | |
608 | case sizeof(u16): { | |
609 | __le16 *buf = buffer; | |
610 | ||
611 | SSB_WARN_ON(count & 1); | |
612 | while (count) { | |
613 | *buf = (__force __le16)__raw_readw(addr); | |
614 | buf++; | |
615 | count -= 2; | |
616 | } | |
617 | break; | |
618 | } | |
619 | case sizeof(u32): { | |
620 | __le32 *buf = buffer; | |
621 | ||
622 | SSB_WARN_ON(count & 3); | |
623 | while (count) { | |
624 | *buf = (__force __le32)__raw_readl(addr); | |
625 | buf++; | |
626 | count -= 4; | |
627 | } | |
628 | break; | |
629 | } | |
630 | default: | |
631 | SSB_WARN_ON(1); | |
632 | } | |
633 | } | |
634 | #endif /* CONFIG_SSB_BLOCKIO */ | |
635 | ||
ffc7689d MB |
636 | static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value) |
637 | { | |
638 | struct ssb_bus *bus = dev->bus; | |
639 | ||
640 | offset += dev->core_index * SSB_CORE_SIZE; | |
641 | writeb(value, bus->mmio + offset); | |
642 | } | |
643 | ||
61e115a5 MB |
644 | static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) |
645 | { | |
646 | struct ssb_bus *bus = dev->bus; | |
647 | ||
648 | offset += dev->core_index * SSB_CORE_SIZE; | |
649 | writew(value, bus->mmio + offset); | |
650 | } | |
651 | ||
652 | static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value) | |
653 | { | |
654 | struct ssb_bus *bus = dev->bus; | |
655 | ||
656 | offset += dev->core_index * SSB_CORE_SIZE; | |
657 | writel(value, bus->mmio + offset); | |
658 | } | |
659 | ||
d625a29b MB |
660 | #ifdef CONFIG_SSB_BLOCKIO |
661 | static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer, | |
662 | size_t count, u16 offset, u8 reg_width) | |
663 | { | |
664 | struct ssb_bus *bus = dev->bus; | |
665 | void __iomem *addr; | |
666 | ||
667 | offset += dev->core_index * SSB_CORE_SIZE; | |
668 | addr = bus->mmio + offset; | |
669 | ||
670 | switch (reg_width) { | |
671 | case sizeof(u8): { | |
672 | const u8 *buf = buffer; | |
673 | ||
674 | while (count) { | |
675 | __raw_writeb(*buf, addr); | |
676 | buf++; | |
677 | count--; | |
678 | } | |
679 | break; | |
680 | } | |
681 | case sizeof(u16): { | |
682 | const __le16 *buf = buffer; | |
683 | ||
684 | SSB_WARN_ON(count & 1); | |
685 | while (count) { | |
686 | __raw_writew((__force u16)(*buf), addr); | |
687 | buf++; | |
688 | count -= 2; | |
689 | } | |
690 | break; | |
691 | } | |
692 | case sizeof(u32): { | |
693 | const __le32 *buf = buffer; | |
694 | ||
695 | SSB_WARN_ON(count & 3); | |
696 | while (count) { | |
697 | __raw_writel((__force u32)(*buf), addr); | |
698 | buf++; | |
699 | count -= 4; | |
700 | } | |
701 | break; | |
702 | } | |
703 | default: | |
704 | SSB_WARN_ON(1); | |
705 | } | |
706 | } | |
707 | #endif /* CONFIG_SSB_BLOCKIO */ | |
708 | ||
61e115a5 MB |
709 | /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ |
710 | static const struct ssb_bus_ops ssb_ssb_ops = { | |
ffc7689d | 711 | .read8 = ssb_ssb_read8, |
61e115a5 MB |
712 | .read16 = ssb_ssb_read16, |
713 | .read32 = ssb_ssb_read32, | |
ffc7689d | 714 | .write8 = ssb_ssb_write8, |
61e115a5 MB |
715 | .write16 = ssb_ssb_write16, |
716 | .write32 = ssb_ssb_write32, | |
d625a29b MB |
717 | #ifdef CONFIG_SSB_BLOCKIO |
718 | .block_read = ssb_ssb_block_read, | |
719 | .block_write = ssb_ssb_block_write, | |
720 | #endif | |
61e115a5 MB |
721 | }; |
722 | ||
723 | static int ssb_fetch_invariants(struct ssb_bus *bus, | |
724 | ssb_invariants_func_t get_invariants) | |
725 | { | |
726 | struct ssb_init_invariants iv; | |
727 | int err; | |
728 | ||
729 | memset(&iv, 0, sizeof(iv)); | |
730 | err = get_invariants(bus, &iv); | |
731 | if (err) | |
732 | goto out; | |
733 | memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); | |
734 | memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); | |
7cb44615 | 735 | bus->has_cardbus_slot = iv.has_cardbus_slot; |
61e115a5 MB |
736 | out: |
737 | return err; | |
738 | } | |
739 | ||
740 | static int ssb_bus_register(struct ssb_bus *bus, | |
741 | ssb_invariants_func_t get_invariants, | |
742 | unsigned long baseaddr) | |
743 | { | |
744 | int err; | |
745 | ||
746 | spin_lock_init(&bus->bar_lock); | |
747 | INIT_LIST_HEAD(&bus->list); | |
53521d8c MB |
748 | #ifdef CONFIG_SSB_EMBEDDED |
749 | spin_lock_init(&bus->gpio_lock); | |
750 | #endif | |
61e115a5 MB |
751 | |
752 | /* Powerup the bus */ | |
753 | err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); | |
754 | if (err) | |
755 | goto out; | |
24ea602e AH |
756 | |
757 | /* Init SDIO-host device (if any), before the scan */ | |
758 | err = ssb_sdio_init(bus); | |
759 | if (err) | |
760 | goto err_disable_xtal; | |
761 | ||
61e115a5 MB |
762 | ssb_buses_lock(); |
763 | bus->busnumber = next_busnumber; | |
764 | /* Scan for devices (cores) */ | |
765 | err = ssb_bus_scan(bus, baseaddr); | |
766 | if (err) | |
24ea602e | 767 | goto err_sdio_exit; |
61e115a5 MB |
768 | |
769 | /* Init PCI-host device (if any) */ | |
770 | err = ssb_pci_init(bus); | |
771 | if (err) | |
772 | goto err_unmap; | |
773 | /* Init PCMCIA-host device (if any) */ | |
774 | err = ssb_pcmcia_init(bus); | |
775 | if (err) | |
776 | goto err_pci_exit; | |
777 | ||
778 | /* Initialize basic system devices (if available) */ | |
779 | err = ssb_bus_powerup(bus, 0); | |
780 | if (err) | |
781 | goto err_pcmcia_exit; | |
782 | ssb_chipcommon_init(&bus->chipco); | |
783 | ssb_mipscore_init(&bus->mipscore); | |
784 | err = ssb_fetch_invariants(bus, get_invariants); | |
785 | if (err) { | |
786 | ssb_bus_may_powerdown(bus); | |
787 | goto err_pcmcia_exit; | |
788 | } | |
789 | ssb_bus_may_powerdown(bus); | |
790 | ||
791 | /* Queue it for attach. | |
792 | * See the comment at the ssb_is_early_boot definition. */ | |
793 | list_add_tail(&bus->list, &attach_queue); | |
794 | if (!ssb_is_early_boot) { | |
795 | /* This is not early boot, so we must attach the bus now */ | |
796 | err = ssb_attach_queued_buses(); | |
797 | if (err) | |
798 | goto err_dequeue; | |
799 | } | |
800 | next_busnumber++; | |
801 | ssb_buses_unlock(); | |
802 | ||
803 | out: | |
804 | return err; | |
805 | ||
806 | err_dequeue: | |
807 | list_del(&bus->list); | |
808 | err_pcmcia_exit: | |
e7ec2e32 | 809 | ssb_pcmcia_exit(bus); |
61e115a5 MB |
810 | err_pci_exit: |
811 | ssb_pci_exit(bus); | |
812 | err_unmap: | |
813 | ssb_iounmap(bus); | |
24ea602e AH |
814 | err_sdio_exit: |
815 | ssb_sdio_exit(bus); | |
61e115a5 MB |
816 | err_disable_xtal: |
817 | ssb_buses_unlock(); | |
818 | ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); | |
819 | return err; | |
820 | } | |
821 | ||
822 | #ifdef CONFIG_SSB_PCIHOST | |
823 | int ssb_bus_pcibus_register(struct ssb_bus *bus, | |
824 | struct pci_dev *host_pci) | |
825 | { | |
826 | int err; | |
827 | ||
828 | bus->bustype = SSB_BUSTYPE_PCI; | |
829 | bus->host_pci = host_pci; | |
830 | bus->ops = &ssb_pci_ops; | |
831 | ||
832 | err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); | |
833 | if (!err) { | |
834 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " | |
b7b05fe7 | 835 | "PCI device %s\n", dev_name(&host_pci->dev)); |
61e115a5 MB |
836 | } |
837 | ||
838 | return err; | |
839 | } | |
840 | EXPORT_SYMBOL(ssb_bus_pcibus_register); | |
841 | #endif /* CONFIG_SSB_PCIHOST */ | |
842 | ||
843 | #ifdef CONFIG_SSB_PCMCIAHOST | |
844 | int ssb_bus_pcmciabus_register(struct ssb_bus *bus, | |
845 | struct pcmcia_device *pcmcia_dev, | |
846 | unsigned long baseaddr) | |
847 | { | |
848 | int err; | |
849 | ||
850 | bus->bustype = SSB_BUSTYPE_PCMCIA; | |
851 | bus->host_pcmcia = pcmcia_dev; | |
852 | bus->ops = &ssb_pcmcia_ops; | |
853 | ||
854 | err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); | |
855 | if (!err) { | |
856 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " | |
857 | "PCMCIA device %s\n", pcmcia_dev->devname); | |
858 | } | |
859 | ||
860 | return err; | |
861 | } | |
862 | EXPORT_SYMBOL(ssb_bus_pcmciabus_register); | |
863 | #endif /* CONFIG_SSB_PCMCIAHOST */ | |
864 | ||
24ea602e AH |
865 | #ifdef CONFIG_SSB_SDIOHOST |
866 | int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func, | |
867 | unsigned int quirks) | |
868 | { | |
869 | int err; | |
870 | ||
871 | bus->bustype = SSB_BUSTYPE_SDIO; | |
872 | bus->host_sdio = func; | |
873 | bus->ops = &ssb_sdio_ops; | |
874 | bus->quirks = quirks; | |
875 | ||
876 | err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0); | |
877 | if (!err) { | |
878 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " | |
879 | "SDIO device %s\n", sdio_func_id(func)); | |
880 | } | |
881 | ||
882 | return err; | |
883 | } | |
884 | EXPORT_SYMBOL(ssb_bus_sdiobus_register); | |
885 | #endif /* CONFIG_SSB_PCMCIAHOST */ | |
886 | ||
61e115a5 MB |
887 | int ssb_bus_ssbbus_register(struct ssb_bus *bus, |
888 | unsigned long baseaddr, | |
889 | ssb_invariants_func_t get_invariants) | |
890 | { | |
891 | int err; | |
892 | ||
893 | bus->bustype = SSB_BUSTYPE_SSB; | |
894 | bus->ops = &ssb_ssb_ops; | |
895 | ||
896 | err = ssb_bus_register(bus, get_invariants, baseaddr); | |
897 | if (!err) { | |
898 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at " | |
899 | "address 0x%08lX\n", baseaddr); | |
900 | } | |
901 | ||
902 | return err; | |
903 | } | |
904 | ||
905 | int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) | |
906 | { | |
907 | drv->drv.name = drv->name; | |
908 | drv->drv.bus = &ssb_bustype; | |
909 | drv->drv.owner = owner; | |
910 | ||
911 | return driver_register(&drv->drv); | |
912 | } | |
913 | EXPORT_SYMBOL(__ssb_driver_register); | |
914 | ||
915 | void ssb_driver_unregister(struct ssb_driver *drv) | |
916 | { | |
917 | driver_unregister(&drv->drv); | |
918 | } | |
919 | EXPORT_SYMBOL(ssb_driver_unregister); | |
920 | ||
921 | void ssb_set_devtypedata(struct ssb_device *dev, void *data) | |
922 | { | |
923 | struct ssb_bus *bus = dev->bus; | |
924 | struct ssb_device *ent; | |
925 | int i; | |
926 | ||
927 | for (i = 0; i < bus->nr_devices; i++) { | |
928 | ent = &(bus->devices[i]); | |
929 | if (ent->id.vendor != dev->id.vendor) | |
930 | continue; | |
931 | if (ent->id.coreid != dev->id.coreid) | |
932 | continue; | |
933 | ||
934 | ent->devtypedata = data; | |
935 | } | |
936 | } | |
937 | EXPORT_SYMBOL(ssb_set_devtypedata); | |
938 | ||
939 | static u32 clkfactor_f6_resolve(u32 v) | |
940 | { | |
941 | /* map the magic values */ | |
942 | switch (v) { | |
943 | case SSB_CHIPCO_CLK_F6_2: | |
944 | return 2; | |
945 | case SSB_CHIPCO_CLK_F6_3: | |
946 | return 3; | |
947 | case SSB_CHIPCO_CLK_F6_4: | |
948 | return 4; | |
949 | case SSB_CHIPCO_CLK_F6_5: | |
950 | return 5; | |
951 | case SSB_CHIPCO_CLK_F6_6: | |
952 | return 6; | |
953 | case SSB_CHIPCO_CLK_F6_7: | |
954 | return 7; | |
955 | } | |
956 | return 0; | |
957 | } | |
958 | ||
959 | /* Calculate the speed the backplane would run at a given set of clockcontrol values */ | |
960 | u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) | |
961 | { | |
962 | u32 n1, n2, clock, m1, m2, m3, mc; | |
963 | ||
964 | n1 = (n & SSB_CHIPCO_CLK_N1); | |
965 | n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); | |
966 | ||
967 | switch (plltype) { | |
968 | case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ | |
969 | if (m & SSB_CHIPCO_CLK_T6_MMASK) | |
970 | return SSB_CHIPCO_CLK_T6_M0; | |
971 | return SSB_CHIPCO_CLK_T6_M1; | |
972 | case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ | |
973 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ | |
974 | case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ | |
975 | case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ | |
976 | n1 = clkfactor_f6_resolve(n1); | |
977 | n2 += SSB_CHIPCO_CLK_F5_BIAS; | |
978 | break; | |
979 | case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ | |
980 | n1 += SSB_CHIPCO_CLK_T2_BIAS; | |
981 | n2 += SSB_CHIPCO_CLK_T2_BIAS; | |
982 | SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); | |
983 | SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); | |
984 | break; | |
985 | case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ | |
986 | return 100000000; | |
987 | default: | |
988 | SSB_WARN_ON(1); | |
989 | } | |
990 | ||
991 | switch (plltype) { | |
992 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ | |
993 | case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ | |
994 | clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; | |
995 | break; | |
996 | default: | |
997 | clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; | |
998 | } | |
999 | if (!clock) | |
1000 | return 0; | |
1001 | ||
1002 | m1 = (m & SSB_CHIPCO_CLK_M1); | |
1003 | m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); | |
1004 | m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); | |
1005 | mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); | |
1006 | ||
1007 | switch (plltype) { | |
1008 | case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ | |
1009 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ | |
1010 | case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ | |
1011 | case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ | |
1012 | m1 = clkfactor_f6_resolve(m1); | |
1013 | if ((plltype == SSB_PLLTYPE_1) || | |
1014 | (plltype == SSB_PLLTYPE_3)) | |
1015 | m2 += SSB_CHIPCO_CLK_F5_BIAS; | |
1016 | else | |
1017 | m2 = clkfactor_f6_resolve(m2); | |
1018 | m3 = clkfactor_f6_resolve(m3); | |
1019 | ||
1020 | switch (mc) { | |
1021 | case SSB_CHIPCO_CLK_MC_BYPASS: | |
1022 | return clock; | |
1023 | case SSB_CHIPCO_CLK_MC_M1: | |
1024 | return (clock / m1); | |
1025 | case SSB_CHIPCO_CLK_MC_M1M2: | |
1026 | return (clock / (m1 * m2)); | |
1027 | case SSB_CHIPCO_CLK_MC_M1M2M3: | |
1028 | return (clock / (m1 * m2 * m3)); | |
1029 | case SSB_CHIPCO_CLK_MC_M1M3: | |
1030 | return (clock / (m1 * m3)); | |
1031 | } | |
1032 | return 0; | |
1033 | case SSB_PLLTYPE_2: | |
1034 | m1 += SSB_CHIPCO_CLK_T2_BIAS; | |
1035 | m2 += SSB_CHIPCO_CLK_T2M2_BIAS; | |
1036 | m3 += SSB_CHIPCO_CLK_T2_BIAS; | |
1037 | SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); | |
1038 | SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); | |
1039 | SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); | |
1040 | ||
1041 | if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) | |
1042 | clock /= m1; | |
1043 | if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) | |
1044 | clock /= m2; | |
1045 | if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) | |
1046 | clock /= m3; | |
1047 | return clock; | |
1048 | default: | |
1049 | SSB_WARN_ON(1); | |
1050 | } | |
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | /* Get the current speed the backplane is running at */ | |
1055 | u32 ssb_clockspeed(struct ssb_bus *bus) | |
1056 | { | |
1057 | u32 rate; | |
1058 | u32 plltype; | |
1059 | u32 clkctl_n, clkctl_m; | |
1060 | ||
1061 | if (ssb_extif_available(&bus->extif)) | |
1062 | ssb_extif_get_clockcontrol(&bus->extif, &plltype, | |
1063 | &clkctl_n, &clkctl_m); | |
1064 | else if (bus->chipco.dev) | |
1065 | ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, | |
1066 | &clkctl_n, &clkctl_m); | |
1067 | else | |
1068 | return 0; | |
1069 | ||
1070 | if (bus->chip_id == 0x5365) { | |
1071 | rate = 100000000; | |
1072 | } else { | |
1073 | rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); | |
1074 | if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ | |
1075 | rate /= 2; | |
1076 | } | |
1077 | ||
1078 | return rate; | |
1079 | } | |
1080 | EXPORT_SYMBOL(ssb_clockspeed); | |
1081 | ||
1082 | static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) | |
1083 | { | |
c272ef44 LF |
1084 | u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; |
1085 | ||
61e115a5 MB |
1086 | /* The REJECT bit changed position in TMSLOW between |
1087 | * Backplane revisions. */ | |
c272ef44 | 1088 | switch (rev) { |
61e115a5 MB |
1089 | case SSB_IDLOW_SSBREV_22: |
1090 | return SSB_TMSLOW_REJECT_22; | |
1091 | case SSB_IDLOW_SSBREV_23: | |
1092 | return SSB_TMSLOW_REJECT_23; | |
c272ef44 LF |
1093 | case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */ |
1094 | case SSB_IDLOW_SSBREV_25: /* same here */ | |
1095 | case SSB_IDLOW_SSBREV_26: /* same here */ | |
1096 | case SSB_IDLOW_SSBREV_27: /* same here */ | |
1097 | return SSB_TMSLOW_REJECT_23; /* this is a guess */ | |
61e115a5 | 1098 | default: |
c272ef44 | 1099 | printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); |
61e115a5 MB |
1100 | WARN_ON(1); |
1101 | } | |
1102 | return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23); | |
1103 | } | |
1104 | ||
1105 | int ssb_device_is_enabled(struct ssb_device *dev) | |
1106 | { | |
1107 | u32 val; | |
1108 | u32 reject; | |
1109 | ||
1110 | reject = ssb_tmslow_reject_bitmask(dev); | |
1111 | val = ssb_read32(dev, SSB_TMSLOW); | |
1112 | val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; | |
1113 | ||
1114 | return (val == SSB_TMSLOW_CLOCK); | |
1115 | } | |
1116 | EXPORT_SYMBOL(ssb_device_is_enabled); | |
1117 | ||
1118 | static void ssb_flush_tmslow(struct ssb_device *dev) | |
1119 | { | |
1120 | /* Make _really_ sure the device has finished the TMSLOW | |
1121 | * register write transaction, as we risk running into | |
1122 | * a machine check exception otherwise. | |
1123 | * Do this by reading the register back to commit the | |
1124 | * PCI write and delay an additional usec for the device | |
1125 | * to react to the change. */ | |
1126 | ssb_read32(dev, SSB_TMSLOW); | |
1127 | udelay(1); | |
1128 | } | |
1129 | ||
1130 | void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) | |
1131 | { | |
1132 | u32 val; | |
1133 | ||
1134 | ssb_device_disable(dev, core_specific_flags); | |
1135 | ssb_write32(dev, SSB_TMSLOW, | |
1136 | SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | | |
1137 | SSB_TMSLOW_FGC | core_specific_flags); | |
1138 | ssb_flush_tmslow(dev); | |
1139 | ||
1140 | /* Clear SERR if set. This is a hw bug workaround. */ | |
1141 | if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) | |
1142 | ssb_write32(dev, SSB_TMSHIGH, 0); | |
1143 | ||
1144 | val = ssb_read32(dev, SSB_IMSTATE); | |
1145 | if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { | |
1146 | val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); | |
1147 | ssb_write32(dev, SSB_IMSTATE, val); | |
1148 | } | |
1149 | ||
1150 | ssb_write32(dev, SSB_TMSLOW, | |
1151 | SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | | |
1152 | core_specific_flags); | |
1153 | ssb_flush_tmslow(dev); | |
1154 | ||
1155 | ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | | |
1156 | core_specific_flags); | |
1157 | ssb_flush_tmslow(dev); | |
1158 | } | |
1159 | EXPORT_SYMBOL(ssb_device_enable); | |
1160 | ||
1161 | /* Wait for a bit in a register to get set or unset. | |
1162 | * timeout is in units of ten-microseconds */ | |
1163 | static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask, | |
1164 | int timeout, int set) | |
1165 | { | |
1166 | int i; | |
1167 | u32 val; | |
1168 | ||
1169 | for (i = 0; i < timeout; i++) { | |
1170 | val = ssb_read32(dev, reg); | |
1171 | if (set) { | |
1172 | if (val & bitmask) | |
1173 | return 0; | |
1174 | } else { | |
1175 | if (!(val & bitmask)) | |
1176 | return 0; | |
1177 | } | |
1178 | udelay(10); | |
1179 | } | |
1180 | printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " | |
1181 | "register %04X to %s.\n", | |
1182 | bitmask, reg, (set ? "set" : "clear")); | |
1183 | ||
1184 | return -ETIMEDOUT; | |
1185 | } | |
1186 | ||
1187 | void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) | |
1188 | { | |
1189 | u32 reject; | |
1190 | ||
1191 | if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) | |
1192 | return; | |
1193 | ||
1194 | reject = ssb_tmslow_reject_bitmask(dev); | |
1195 | ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); | |
1196 | ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1); | |
1197 | ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); | |
1198 | ssb_write32(dev, SSB_TMSLOW, | |
1199 | SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | | |
1200 | reject | SSB_TMSLOW_RESET | | |
1201 | core_specific_flags); | |
1202 | ssb_flush_tmslow(dev); | |
1203 | ||
1204 | ssb_write32(dev, SSB_TMSLOW, | |
1205 | reject | SSB_TMSLOW_RESET | | |
1206 | core_specific_flags); | |
1207 | ssb_flush_tmslow(dev); | |
1208 | } | |
1209 | EXPORT_SYMBOL(ssb_device_disable); | |
1210 | ||
1211 | u32 ssb_dma_translation(struct ssb_device *dev) | |
1212 | { | |
1213 | switch (dev->bus->bustype) { | |
1214 | case SSB_BUSTYPE_SSB: | |
1215 | return 0; | |
1216 | case SSB_BUSTYPE_PCI: | |
61e115a5 | 1217 | return SSB_PCI_DMA; |
f225763a MB |
1218 | default: |
1219 | __ssb_dma_not_implemented(dev); | |
61e115a5 MB |
1220 | } |
1221 | return 0; | |
1222 | } | |
1223 | EXPORT_SYMBOL(ssb_dma_translation); | |
1224 | ||
f225763a | 1225 | int ssb_dma_set_mask(struct ssb_device *dev, u64 mask) |
61e115a5 | 1226 | { |
7f37441c | 1227 | #ifdef CONFIG_SSB_PCIHOST |
f225763a | 1228 | int err; |
7f37441c | 1229 | #endif |
61e115a5 | 1230 | |
f225763a MB |
1231 | switch (dev->bus->bustype) { |
1232 | case SSB_BUSTYPE_PCI: | |
7f37441c | 1233 | #ifdef CONFIG_SSB_PCIHOST |
f225763a | 1234 | err = pci_set_dma_mask(dev->bus->host_pci, mask); |
e6340361 MB |
1235 | if (err) |
1236 | return err; | |
f225763a | 1237 | err = pci_set_consistent_dma_mask(dev->bus->host_pci, mask); |
e6340361 | 1238 | return err; |
7f37441c | 1239 | #endif |
f225763a MB |
1240 | case SSB_BUSTYPE_SSB: |
1241 | return dma_set_mask(dev->dev, mask); | |
1242 | default: | |
1243 | __ssb_dma_not_implemented(dev); | |
e6340361 | 1244 | } |
f225763a | 1245 | return -ENOSYS; |
61e115a5 MB |
1246 | } |
1247 | EXPORT_SYMBOL(ssb_dma_set_mask); | |
1248 | ||
f225763a MB |
1249 | void * ssb_dma_alloc_consistent(struct ssb_device *dev, size_t size, |
1250 | dma_addr_t *dma_handle, gfp_t gfp_flags) | |
1251 | { | |
1252 | switch (dev->bus->bustype) { | |
1253 | case SSB_BUSTYPE_PCI: | |
7f37441c | 1254 | #ifdef CONFIG_SSB_PCIHOST |
f225763a MB |
1255 | if (gfp_flags & GFP_DMA) { |
1256 | /* Workaround: The PCI API does not support passing | |
1257 | * a GFP flag. */ | |
1258 | return dma_alloc_coherent(&dev->bus->host_pci->dev, | |
1259 | size, dma_handle, gfp_flags); | |
1260 | } | |
1261 | return pci_alloc_consistent(dev->bus->host_pci, size, dma_handle); | |
7f37441c | 1262 | #endif |
f225763a MB |
1263 | case SSB_BUSTYPE_SSB: |
1264 | return dma_alloc_coherent(dev->dev, size, dma_handle, gfp_flags); | |
1265 | default: | |
1266 | __ssb_dma_not_implemented(dev); | |
1267 | } | |
1268 | return NULL; | |
1269 | } | |
1270 | EXPORT_SYMBOL(ssb_dma_alloc_consistent); | |
1271 | ||
1272 | void ssb_dma_free_consistent(struct ssb_device *dev, size_t size, | |
1273 | void *vaddr, dma_addr_t dma_handle, | |
1274 | gfp_t gfp_flags) | |
1275 | { | |
1276 | switch (dev->bus->bustype) { | |
1277 | case SSB_BUSTYPE_PCI: | |
7f37441c | 1278 | #ifdef CONFIG_SSB_PCIHOST |
f225763a MB |
1279 | if (gfp_flags & GFP_DMA) { |
1280 | /* Workaround: The PCI API does not support passing | |
1281 | * a GFP flag. */ | |
1282 | dma_free_coherent(&dev->bus->host_pci->dev, | |
1283 | size, vaddr, dma_handle); | |
1284 | return; | |
1285 | } | |
1286 | pci_free_consistent(dev->bus->host_pci, size, | |
1287 | vaddr, dma_handle); | |
1288 | return; | |
7f37441c | 1289 | #endif |
f225763a MB |
1290 | case SSB_BUSTYPE_SSB: |
1291 | dma_free_coherent(dev->dev, size, vaddr, dma_handle); | |
1292 | return; | |
1293 | default: | |
1294 | __ssb_dma_not_implemented(dev); | |
1295 | } | |
1296 | } | |
1297 | EXPORT_SYMBOL(ssb_dma_free_consistent); | |
1298 | ||
61e115a5 MB |
1299 | int ssb_bus_may_powerdown(struct ssb_bus *bus) |
1300 | { | |
1301 | struct ssb_chipcommon *cc; | |
1302 | int err = 0; | |
1303 | ||
1304 | /* On buses where more than one core may be working | |
1305 | * at a time, we must not powerdown stuff if there are | |
1306 | * still cores that may want to run. */ | |
1307 | if (bus->bustype == SSB_BUSTYPE_SSB) | |
1308 | goto out; | |
1309 | ||
1310 | cc = &bus->chipco; | |
881400a2 SB |
1311 | |
1312 | if (!cc->dev) | |
1313 | goto out; | |
1314 | if (cc->dev->id.revision < 5) | |
1315 | goto out; | |
1316 | ||
61e115a5 MB |
1317 | ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); |
1318 | err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); | |
1319 | if (err) | |
1320 | goto error; | |
1321 | out: | |
1322 | #ifdef CONFIG_SSB_DEBUG | |
1323 | bus->powered_up = 0; | |
1324 | #endif | |
1325 | return err; | |
1326 | error: | |
1327 | ssb_printk(KERN_ERR PFX "Bus powerdown failed\n"); | |
1328 | goto out; | |
1329 | } | |
1330 | EXPORT_SYMBOL(ssb_bus_may_powerdown); | |
1331 | ||
1332 | int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) | |
1333 | { | |
1334 | struct ssb_chipcommon *cc; | |
1335 | int err; | |
1336 | enum ssb_clkmode mode; | |
1337 | ||
1338 | err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); | |
1339 | if (err) | |
1340 | goto error; | |
1341 | cc = &bus->chipco; | |
1342 | mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; | |
1343 | ssb_chipco_set_clockmode(cc, mode); | |
1344 | ||
1345 | #ifdef CONFIG_SSB_DEBUG | |
1346 | bus->powered_up = 1; | |
1347 | #endif | |
1348 | return 0; | |
1349 | error: | |
1350 | ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); | |
1351 | return err; | |
1352 | } | |
1353 | EXPORT_SYMBOL(ssb_bus_powerup); | |
1354 | ||
1355 | u32 ssb_admatch_base(u32 adm) | |
1356 | { | |
1357 | u32 base = 0; | |
1358 | ||
1359 | switch (adm & SSB_ADM_TYPE) { | |
1360 | case SSB_ADM_TYPE0: | |
1361 | base = (adm & SSB_ADM_BASE0); | |
1362 | break; | |
1363 | case SSB_ADM_TYPE1: | |
1364 | SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ | |
1365 | base = (adm & SSB_ADM_BASE1); | |
1366 | break; | |
1367 | case SSB_ADM_TYPE2: | |
1368 | SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ | |
1369 | base = (adm & SSB_ADM_BASE2); | |
1370 | break; | |
1371 | default: | |
1372 | SSB_WARN_ON(1); | |
1373 | } | |
1374 | ||
1375 | return base; | |
1376 | } | |
1377 | EXPORT_SYMBOL(ssb_admatch_base); | |
1378 | ||
1379 | u32 ssb_admatch_size(u32 adm) | |
1380 | { | |
1381 | u32 size = 0; | |
1382 | ||
1383 | switch (adm & SSB_ADM_TYPE) { | |
1384 | case SSB_ADM_TYPE0: | |
1385 | size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); | |
1386 | break; | |
1387 | case SSB_ADM_TYPE1: | |
1388 | SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ | |
1389 | size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); | |
1390 | break; | |
1391 | case SSB_ADM_TYPE2: | |
1392 | SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ | |
1393 | size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); | |
1394 | break; | |
1395 | default: | |
1396 | SSB_WARN_ON(1); | |
1397 | } | |
1398 | size = (1 << (size + 1)); | |
1399 | ||
1400 | return size; | |
1401 | } | |
1402 | EXPORT_SYMBOL(ssb_admatch_size); | |
1403 | ||
1404 | static int __init ssb_modinit(void) | |
1405 | { | |
1406 | int err; | |
1407 | ||
1408 | /* See the comment at the ssb_is_early_boot definition */ | |
1409 | ssb_is_early_boot = 0; | |
1410 | err = bus_register(&ssb_bustype); | |
1411 | if (err) | |
1412 | return err; | |
1413 | ||
1414 | /* Maybe we already registered some buses at early boot. | |
1415 | * Check for this and attach them | |
1416 | */ | |
1417 | ssb_buses_lock(); | |
1418 | err = ssb_attach_queued_buses(); | |
1419 | ssb_buses_unlock(); | |
e6c463e3 | 1420 | if (err) { |
61e115a5 | 1421 | bus_unregister(&ssb_bustype); |
e6c463e3 MB |
1422 | goto out; |
1423 | } | |
61e115a5 MB |
1424 | |
1425 | err = b43_pci_ssb_bridge_init(); | |
1426 | if (err) { | |
1427 | ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge " | |
aab547ce MB |
1428 | "initialization failed\n"); |
1429 | /* don't fail SSB init because of this */ | |
1430 | err = 0; | |
1431 | } | |
1432 | err = ssb_gige_init(); | |
1433 | if (err) { | |
1434 | ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet " | |
1435 | "driver initialization failed\n"); | |
61e115a5 MB |
1436 | /* don't fail SSB init because of this */ |
1437 | err = 0; | |
1438 | } | |
e6c463e3 | 1439 | out: |
61e115a5 MB |
1440 | return err; |
1441 | } | |
8d8c90e3 MB |
1442 | /* ssb must be initialized after PCI but before the ssb drivers. |
1443 | * That means we must use some initcall between subsys_initcall | |
1444 | * and device_initcall. */ | |
1445 | fs_initcall(ssb_modinit); | |
61e115a5 MB |
1446 | |
1447 | static void __exit ssb_modexit(void) | |
1448 | { | |
aab547ce | 1449 | ssb_gige_exit(); |
61e115a5 MB |
1450 | b43_pci_ssb_bridge_exit(); |
1451 | bus_unregister(&ssb_bustype); | |
1452 | } | |
1453 | module_exit(ssb_modexit) |