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61e115a5 MB |
1 | /* |
2 | * Sonics Silicon Backplane | |
3 | * Subsystem core | |
4 | * | |
5 | * Copyright 2005, Broadcom Corporation | |
6 | * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> | |
7 | * | |
8 | * Licensed under the GNU/GPL. See COPYING for details. | |
9 | */ | |
10 | ||
11 | #include "ssb_private.h" | |
12 | ||
13 | #include <linux/delay.h> | |
6faf035c | 14 | #include <linux/io.h> |
61e115a5 MB |
15 | #include <linux/ssb/ssb.h> |
16 | #include <linux/ssb/ssb_regs.h> | |
aab547ce | 17 | #include <linux/ssb/ssb_driver_gige.h> |
61e115a5 MB |
18 | #include <linux/dma-mapping.h> |
19 | #include <linux/pci.h> | |
20 | ||
21 | #include <pcmcia/cs_types.h> | |
22 | #include <pcmcia/cs.h> | |
23 | #include <pcmcia/cistpl.h> | |
24 | #include <pcmcia/ds.h> | |
25 | ||
26 | ||
27 | MODULE_DESCRIPTION("Sonics Silicon Backplane driver"); | |
28 | MODULE_LICENSE("GPL"); | |
29 | ||
30 | ||
31 | /* Temporary list of yet-to-be-attached buses */ | |
32 | static LIST_HEAD(attach_queue); | |
33 | /* List if running buses */ | |
34 | static LIST_HEAD(buses); | |
35 | /* Software ID counter */ | |
36 | static unsigned int next_busnumber; | |
37 | /* buses_mutes locks the two buslists and the next_busnumber. | |
38 | * Don't lock this directly, but use ssb_buses_[un]lock() below. */ | |
39 | static DEFINE_MUTEX(buses_mutex); | |
40 | ||
41 | /* There are differences in the codeflow, if the bus is | |
42 | * initialized from early boot, as various needed services | |
43 | * are not available early. This is a mechanism to delay | |
44 | * these initializations to after early boot has finished. | |
45 | * It's also used to avoid mutex locking, as that's not | |
46 | * available and needed early. */ | |
47 | static bool ssb_is_early_boot = 1; | |
48 | ||
49 | static void ssb_buses_lock(void); | |
50 | static void ssb_buses_unlock(void); | |
51 | ||
52 | ||
53 | #ifdef CONFIG_SSB_PCIHOST | |
54 | struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev) | |
55 | { | |
56 | struct ssb_bus *bus; | |
57 | ||
58 | ssb_buses_lock(); | |
59 | list_for_each_entry(bus, &buses, list) { | |
60 | if (bus->bustype == SSB_BUSTYPE_PCI && | |
61 | bus->host_pci == pdev) | |
62 | goto found; | |
63 | } | |
64 | bus = NULL; | |
65 | found: | |
66 | ssb_buses_unlock(); | |
67 | ||
68 | return bus; | |
69 | } | |
70 | #endif /* CONFIG_SSB_PCIHOST */ | |
71 | ||
e7ec2e32 MB |
72 | #ifdef CONFIG_SSB_PCMCIAHOST |
73 | struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev) | |
74 | { | |
75 | struct ssb_bus *bus; | |
76 | ||
77 | ssb_buses_lock(); | |
78 | list_for_each_entry(bus, &buses, list) { | |
79 | if (bus->bustype == SSB_BUSTYPE_PCMCIA && | |
80 | bus->host_pcmcia == pdev) | |
81 | goto found; | |
82 | } | |
83 | bus = NULL; | |
84 | found: | |
85 | ssb_buses_unlock(); | |
86 | ||
87 | return bus; | |
88 | } | |
89 | #endif /* CONFIG_SSB_PCMCIAHOST */ | |
90 | ||
aab547ce MB |
91 | int ssb_for_each_bus_call(unsigned long data, |
92 | int (*func)(struct ssb_bus *bus, unsigned long data)) | |
93 | { | |
94 | struct ssb_bus *bus; | |
95 | int res; | |
96 | ||
97 | ssb_buses_lock(); | |
98 | list_for_each_entry(bus, &buses, list) { | |
99 | res = func(bus, data); | |
100 | if (res >= 0) { | |
101 | ssb_buses_unlock(); | |
102 | return res; | |
103 | } | |
104 | } | |
105 | ssb_buses_unlock(); | |
106 | ||
107 | return -ENODEV; | |
108 | } | |
109 | ||
61e115a5 MB |
110 | static struct ssb_device *ssb_device_get(struct ssb_device *dev) |
111 | { | |
112 | if (dev) | |
113 | get_device(dev->dev); | |
114 | return dev; | |
115 | } | |
116 | ||
117 | static void ssb_device_put(struct ssb_device *dev) | |
118 | { | |
119 | if (dev) | |
120 | put_device(dev->dev); | |
121 | } | |
122 | ||
123 | static int ssb_bus_resume(struct ssb_bus *bus) | |
124 | { | |
125 | int err; | |
126 | ||
127 | ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); | |
128 | err = ssb_pcmcia_init(bus); | |
129 | if (err) { | |
130 | /* No need to disable XTAL, as we don't have one on PCMCIA. */ | |
131 | return err; | |
132 | } | |
133 | ssb_chipco_resume(&bus->chipco); | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
138 | static int ssb_device_resume(struct device *dev) | |
139 | { | |
140 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
141 | struct ssb_driver *ssb_drv; | |
142 | struct ssb_bus *bus; | |
143 | int err = 0; | |
144 | ||
145 | bus = ssb_dev->bus; | |
146 | if (bus->suspend_cnt == bus->nr_devices) { | |
147 | err = ssb_bus_resume(bus); | |
148 | if (err) | |
149 | return err; | |
150 | } | |
151 | bus->suspend_cnt--; | |
152 | if (dev->driver) { | |
153 | ssb_drv = drv_to_ssb_drv(dev->driver); | |
154 | if (ssb_drv && ssb_drv->resume) | |
155 | err = ssb_drv->resume(ssb_dev); | |
156 | if (err) | |
157 | goto out; | |
158 | } | |
159 | out: | |
160 | return err; | |
161 | } | |
162 | ||
163 | static void ssb_bus_suspend(struct ssb_bus *bus, pm_message_t state) | |
164 | { | |
165 | ssb_chipco_suspend(&bus->chipco, state); | |
166 | ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); | |
167 | ||
168 | /* Reset HW state information in memory, so that HW is | |
169 | * completely reinitialized on resume. */ | |
170 | bus->mapped_device = NULL; | |
171 | #ifdef CONFIG_SSB_DRIVER_PCICORE | |
172 | bus->pcicore.setup_done = 0; | |
173 | #endif | |
174 | #ifdef CONFIG_SSB_DEBUG | |
175 | bus->powered_up = 0; | |
176 | #endif | |
177 | } | |
178 | ||
179 | static int ssb_device_suspend(struct device *dev, pm_message_t state) | |
180 | { | |
181 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
182 | struct ssb_driver *ssb_drv; | |
183 | struct ssb_bus *bus; | |
184 | int err = 0; | |
185 | ||
186 | if (dev->driver) { | |
187 | ssb_drv = drv_to_ssb_drv(dev->driver); | |
188 | if (ssb_drv && ssb_drv->suspend) | |
189 | err = ssb_drv->suspend(ssb_dev, state); | |
190 | if (err) | |
191 | goto out; | |
192 | } | |
193 | ||
194 | bus = ssb_dev->bus; | |
195 | bus->suspend_cnt++; | |
196 | if (bus->suspend_cnt == bus->nr_devices) { | |
197 | /* All devices suspended. Shutdown the bus. */ | |
198 | ssb_bus_suspend(bus, state); | |
199 | } | |
200 | ||
201 | out: | |
202 | return err; | |
203 | } | |
204 | ||
205 | #ifdef CONFIG_SSB_PCIHOST | |
206 | int ssb_devices_freeze(struct ssb_bus *bus) | |
207 | { | |
208 | struct ssb_device *dev; | |
209 | struct ssb_driver *drv; | |
210 | int err = 0; | |
211 | int i; | |
212 | pm_message_t state = PMSG_FREEZE; | |
213 | ||
214 | /* First check that we are capable to freeze all devices. */ | |
215 | for (i = 0; i < bus->nr_devices; i++) { | |
216 | dev = &(bus->devices[i]); | |
217 | if (!dev->dev || | |
218 | !dev->dev->driver || | |
219 | !device_is_registered(dev->dev)) | |
220 | continue; | |
221 | drv = drv_to_ssb_drv(dev->dev->driver); | |
222 | if (!drv) | |
223 | continue; | |
224 | if (!drv->suspend) { | |
225 | /* Nope, can't suspend this one. */ | |
226 | return -EOPNOTSUPP; | |
227 | } | |
228 | } | |
229 | /* Now suspend all devices */ | |
230 | for (i = 0; i < bus->nr_devices; i++) { | |
231 | dev = &(bus->devices[i]); | |
232 | if (!dev->dev || | |
233 | !dev->dev->driver || | |
234 | !device_is_registered(dev->dev)) | |
235 | continue; | |
236 | drv = drv_to_ssb_drv(dev->dev->driver); | |
237 | if (!drv) | |
238 | continue; | |
239 | err = drv->suspend(dev, state); | |
240 | if (err) { | |
241 | ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n", | |
242 | dev->dev->bus_id); | |
243 | goto err_unwind; | |
244 | } | |
245 | } | |
246 | ||
247 | return 0; | |
248 | err_unwind: | |
249 | for (i--; i >= 0; i--) { | |
250 | dev = &(bus->devices[i]); | |
251 | if (!dev->dev || | |
252 | !dev->dev->driver || | |
253 | !device_is_registered(dev->dev)) | |
254 | continue; | |
255 | drv = drv_to_ssb_drv(dev->dev->driver); | |
256 | if (!drv) | |
257 | continue; | |
258 | if (drv->resume) | |
259 | drv->resume(dev); | |
260 | } | |
261 | return err; | |
262 | } | |
263 | ||
264 | int ssb_devices_thaw(struct ssb_bus *bus) | |
265 | { | |
266 | struct ssb_device *dev; | |
267 | struct ssb_driver *drv; | |
268 | int err; | |
269 | int i; | |
270 | ||
271 | for (i = 0; i < bus->nr_devices; i++) { | |
272 | dev = &(bus->devices[i]); | |
273 | if (!dev->dev || | |
274 | !dev->dev->driver || | |
275 | !device_is_registered(dev->dev)) | |
276 | continue; | |
277 | drv = drv_to_ssb_drv(dev->dev->driver); | |
278 | if (!drv) | |
279 | continue; | |
280 | if (SSB_WARN_ON(!drv->resume)) | |
281 | continue; | |
282 | err = drv->resume(dev); | |
283 | if (err) { | |
284 | ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n", | |
285 | dev->dev->bus_id); | |
286 | } | |
287 | } | |
288 | ||
289 | return 0; | |
290 | } | |
291 | #endif /* CONFIG_SSB_PCIHOST */ | |
292 | ||
293 | static void ssb_device_shutdown(struct device *dev) | |
294 | { | |
295 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
296 | struct ssb_driver *ssb_drv; | |
297 | ||
298 | if (!dev->driver) | |
299 | return; | |
300 | ssb_drv = drv_to_ssb_drv(dev->driver); | |
301 | if (ssb_drv && ssb_drv->shutdown) | |
302 | ssb_drv->shutdown(ssb_dev); | |
303 | } | |
304 | ||
305 | static int ssb_device_remove(struct device *dev) | |
306 | { | |
307 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
308 | struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); | |
309 | ||
310 | if (ssb_drv && ssb_drv->remove) | |
311 | ssb_drv->remove(ssb_dev); | |
312 | ssb_device_put(ssb_dev); | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | static int ssb_device_probe(struct device *dev) | |
318 | { | |
319 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
320 | struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver); | |
321 | int err = 0; | |
322 | ||
323 | ssb_device_get(ssb_dev); | |
324 | if (ssb_drv && ssb_drv->probe) | |
325 | err = ssb_drv->probe(ssb_dev, &ssb_dev->id); | |
326 | if (err) | |
327 | ssb_device_put(ssb_dev); | |
328 | ||
329 | return err; | |
330 | } | |
331 | ||
332 | static int ssb_match_devid(const struct ssb_device_id *tabid, | |
333 | const struct ssb_device_id *devid) | |
334 | { | |
335 | if ((tabid->vendor != devid->vendor) && | |
336 | tabid->vendor != SSB_ANY_VENDOR) | |
337 | return 0; | |
338 | if ((tabid->coreid != devid->coreid) && | |
339 | tabid->coreid != SSB_ANY_ID) | |
340 | return 0; | |
341 | if ((tabid->revision != devid->revision) && | |
342 | tabid->revision != SSB_ANY_REV) | |
343 | return 0; | |
344 | return 1; | |
345 | } | |
346 | ||
347 | static int ssb_bus_match(struct device *dev, struct device_driver *drv) | |
348 | { | |
349 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
350 | struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv); | |
351 | const struct ssb_device_id *id; | |
352 | ||
353 | for (id = ssb_drv->id_table; | |
354 | id->vendor || id->coreid || id->revision; | |
355 | id++) { | |
356 | if (ssb_match_devid(id, &ssb_dev->id)) | |
357 | return 1; /* found */ | |
358 | } | |
359 | ||
360 | return 0; | |
361 | } | |
362 | ||
7ac0326c | 363 | static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env) |
61e115a5 MB |
364 | { |
365 | struct ssb_device *ssb_dev = dev_to_ssb_dev(dev); | |
61e115a5 MB |
366 | |
367 | if (!dev) | |
368 | return -ENODEV; | |
369 | ||
7ac0326c | 370 | return add_uevent_var(env, |
61e115a5 MB |
371 | "MODALIAS=ssb:v%04Xid%04Xrev%02X", |
372 | ssb_dev->id.vendor, ssb_dev->id.coreid, | |
373 | ssb_dev->id.revision); | |
61e115a5 MB |
374 | } |
375 | ||
376 | static struct bus_type ssb_bustype = { | |
377 | .name = "ssb", | |
378 | .match = ssb_bus_match, | |
379 | .probe = ssb_device_probe, | |
380 | .remove = ssb_device_remove, | |
381 | .shutdown = ssb_device_shutdown, | |
382 | .suspend = ssb_device_suspend, | |
383 | .resume = ssb_device_resume, | |
384 | .uevent = ssb_device_uevent, | |
385 | }; | |
386 | ||
387 | static void ssb_buses_lock(void) | |
388 | { | |
389 | /* See the comment at the ssb_is_early_boot definition */ | |
390 | if (!ssb_is_early_boot) | |
391 | mutex_lock(&buses_mutex); | |
392 | } | |
393 | ||
394 | static void ssb_buses_unlock(void) | |
395 | { | |
396 | /* See the comment at the ssb_is_early_boot definition */ | |
397 | if (!ssb_is_early_boot) | |
398 | mutex_unlock(&buses_mutex); | |
399 | } | |
400 | ||
401 | static void ssb_devices_unregister(struct ssb_bus *bus) | |
402 | { | |
403 | struct ssb_device *sdev; | |
404 | int i; | |
405 | ||
406 | for (i = bus->nr_devices - 1; i >= 0; i--) { | |
407 | sdev = &(bus->devices[i]); | |
408 | if (sdev->dev) | |
409 | device_unregister(sdev->dev); | |
410 | } | |
411 | } | |
412 | ||
413 | void ssb_bus_unregister(struct ssb_bus *bus) | |
414 | { | |
415 | ssb_buses_lock(); | |
416 | ssb_devices_unregister(bus); | |
417 | list_del(&bus->list); | |
418 | ssb_buses_unlock(); | |
419 | ||
e7ec2e32 | 420 | ssb_pcmcia_exit(bus); |
61e115a5 MB |
421 | ssb_pci_exit(bus); |
422 | ssb_iounmap(bus); | |
423 | } | |
424 | EXPORT_SYMBOL(ssb_bus_unregister); | |
425 | ||
426 | static void ssb_release_dev(struct device *dev) | |
427 | { | |
428 | struct __ssb_dev_wrapper *devwrap; | |
429 | ||
430 | devwrap = container_of(dev, struct __ssb_dev_wrapper, dev); | |
431 | kfree(devwrap); | |
432 | } | |
433 | ||
434 | static int ssb_devices_register(struct ssb_bus *bus) | |
435 | { | |
436 | struct ssb_device *sdev; | |
437 | struct device *dev; | |
438 | struct __ssb_dev_wrapper *devwrap; | |
439 | int i, err = 0; | |
440 | int dev_idx = 0; | |
441 | ||
442 | for (i = 0; i < bus->nr_devices; i++) { | |
443 | sdev = &(bus->devices[i]); | |
444 | ||
445 | /* We don't register SSB-system devices to the kernel, | |
446 | * as the drivers for them are built into SSB. */ | |
447 | switch (sdev->id.coreid) { | |
448 | case SSB_DEV_CHIPCOMMON: | |
449 | case SSB_DEV_PCI: | |
450 | case SSB_DEV_PCIE: | |
451 | case SSB_DEV_PCMCIA: | |
452 | case SSB_DEV_MIPS: | |
453 | case SSB_DEV_MIPS_3302: | |
454 | case SSB_DEV_EXTIF: | |
455 | continue; | |
456 | } | |
457 | ||
458 | devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL); | |
459 | if (!devwrap) { | |
460 | ssb_printk(KERN_ERR PFX | |
461 | "Could not allocate device\n"); | |
462 | err = -ENOMEM; | |
463 | goto error; | |
464 | } | |
465 | dev = &devwrap->dev; | |
466 | devwrap->sdev = sdev; | |
467 | ||
468 | dev->release = ssb_release_dev; | |
469 | dev->bus = &ssb_bustype; | |
470 | snprintf(dev->bus_id, sizeof(dev->bus_id), | |
471 | "ssb%u:%d", bus->busnumber, dev_idx); | |
472 | ||
473 | switch (bus->bustype) { | |
474 | case SSB_BUSTYPE_PCI: | |
475 | #ifdef CONFIG_SSB_PCIHOST | |
476 | sdev->irq = bus->host_pci->irq; | |
477 | dev->parent = &bus->host_pci->dev; | |
478 | #endif | |
479 | break; | |
480 | case SSB_BUSTYPE_PCMCIA: | |
481 | #ifdef CONFIG_SSB_PCMCIAHOST | |
60d78c44 | 482 | sdev->irq = bus->host_pcmcia->irq.AssignedIRQ; |
61e115a5 MB |
483 | dev->parent = &bus->host_pcmcia->dev; |
484 | #endif | |
485 | break; | |
486 | case SSB_BUSTYPE_SSB: | |
487 | break; | |
488 | } | |
489 | ||
490 | sdev->dev = dev; | |
491 | err = device_register(dev); | |
492 | if (err) { | |
493 | ssb_printk(KERN_ERR PFX | |
494 | "Could not register %s\n", | |
495 | dev->bus_id); | |
496 | /* Set dev to NULL to not unregister | |
497 | * dev on error unwinding. */ | |
498 | sdev->dev = NULL; | |
499 | kfree(devwrap); | |
500 | goto error; | |
501 | } | |
502 | dev_idx++; | |
503 | } | |
504 | ||
505 | return 0; | |
506 | error: | |
507 | /* Unwind the already registered devices. */ | |
508 | ssb_devices_unregister(bus); | |
509 | return err; | |
510 | } | |
511 | ||
512 | /* Needs ssb_buses_lock() */ | |
513 | static int ssb_attach_queued_buses(void) | |
514 | { | |
515 | struct ssb_bus *bus, *n; | |
516 | int err = 0; | |
517 | int drop_them_all = 0; | |
518 | ||
519 | list_for_each_entry_safe(bus, n, &attach_queue, list) { | |
520 | if (drop_them_all) { | |
521 | list_del(&bus->list); | |
522 | continue; | |
523 | } | |
524 | /* Can't init the PCIcore in ssb_bus_register(), as that | |
525 | * is too early in boot for embedded systems | |
526 | * (no udelay() available). So do it here in attach stage. | |
527 | */ | |
528 | err = ssb_bus_powerup(bus, 0); | |
529 | if (err) | |
530 | goto error; | |
531 | ssb_pcicore_init(&bus->pcicore); | |
532 | ssb_bus_may_powerdown(bus); | |
533 | ||
534 | err = ssb_devices_register(bus); | |
535 | error: | |
536 | if (err) { | |
537 | drop_them_all = 1; | |
538 | list_del(&bus->list); | |
539 | continue; | |
540 | } | |
541 | list_move_tail(&bus->list, &buses); | |
542 | } | |
543 | ||
544 | return err; | |
545 | } | |
546 | ||
ffc7689d MB |
547 | static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset) |
548 | { | |
549 | struct ssb_bus *bus = dev->bus; | |
550 | ||
551 | offset += dev->core_index * SSB_CORE_SIZE; | |
552 | return readb(bus->mmio + offset); | |
553 | } | |
554 | ||
61e115a5 MB |
555 | static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset) |
556 | { | |
557 | struct ssb_bus *bus = dev->bus; | |
558 | ||
559 | offset += dev->core_index * SSB_CORE_SIZE; | |
560 | return readw(bus->mmio + offset); | |
561 | } | |
562 | ||
563 | static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset) | |
564 | { | |
565 | struct ssb_bus *bus = dev->bus; | |
566 | ||
567 | offset += dev->core_index * SSB_CORE_SIZE; | |
568 | return readl(bus->mmio + offset); | |
569 | } | |
570 | ||
ffc7689d MB |
571 | static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value) |
572 | { | |
573 | struct ssb_bus *bus = dev->bus; | |
574 | ||
575 | offset += dev->core_index * SSB_CORE_SIZE; | |
576 | writeb(value, bus->mmio + offset); | |
577 | } | |
578 | ||
61e115a5 MB |
579 | static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value) |
580 | { | |
581 | struct ssb_bus *bus = dev->bus; | |
582 | ||
583 | offset += dev->core_index * SSB_CORE_SIZE; | |
584 | writew(value, bus->mmio + offset); | |
585 | } | |
586 | ||
587 | static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value) | |
588 | { | |
589 | struct ssb_bus *bus = dev->bus; | |
590 | ||
591 | offset += dev->core_index * SSB_CORE_SIZE; | |
592 | writel(value, bus->mmio + offset); | |
593 | } | |
594 | ||
595 | /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */ | |
596 | static const struct ssb_bus_ops ssb_ssb_ops = { | |
ffc7689d | 597 | .read8 = ssb_ssb_read8, |
61e115a5 MB |
598 | .read16 = ssb_ssb_read16, |
599 | .read32 = ssb_ssb_read32, | |
ffc7689d | 600 | .write8 = ssb_ssb_write8, |
61e115a5 MB |
601 | .write16 = ssb_ssb_write16, |
602 | .write32 = ssb_ssb_write32, | |
603 | }; | |
604 | ||
605 | static int ssb_fetch_invariants(struct ssb_bus *bus, | |
606 | ssb_invariants_func_t get_invariants) | |
607 | { | |
608 | struct ssb_init_invariants iv; | |
609 | int err; | |
610 | ||
611 | memset(&iv, 0, sizeof(iv)); | |
612 | err = get_invariants(bus, &iv); | |
613 | if (err) | |
614 | goto out; | |
615 | memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo)); | |
616 | memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom)); | |
7cb44615 | 617 | bus->has_cardbus_slot = iv.has_cardbus_slot; |
61e115a5 MB |
618 | out: |
619 | return err; | |
620 | } | |
621 | ||
622 | static int ssb_bus_register(struct ssb_bus *bus, | |
623 | ssb_invariants_func_t get_invariants, | |
624 | unsigned long baseaddr) | |
625 | { | |
626 | int err; | |
627 | ||
628 | spin_lock_init(&bus->bar_lock); | |
629 | INIT_LIST_HEAD(&bus->list); | |
53521d8c MB |
630 | #ifdef CONFIG_SSB_EMBEDDED |
631 | spin_lock_init(&bus->gpio_lock); | |
632 | #endif | |
61e115a5 MB |
633 | |
634 | /* Powerup the bus */ | |
635 | err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); | |
636 | if (err) | |
637 | goto out; | |
638 | ssb_buses_lock(); | |
639 | bus->busnumber = next_busnumber; | |
640 | /* Scan for devices (cores) */ | |
641 | err = ssb_bus_scan(bus, baseaddr); | |
642 | if (err) | |
643 | goto err_disable_xtal; | |
644 | ||
645 | /* Init PCI-host device (if any) */ | |
646 | err = ssb_pci_init(bus); | |
647 | if (err) | |
648 | goto err_unmap; | |
649 | /* Init PCMCIA-host device (if any) */ | |
650 | err = ssb_pcmcia_init(bus); | |
651 | if (err) | |
652 | goto err_pci_exit; | |
653 | ||
654 | /* Initialize basic system devices (if available) */ | |
655 | err = ssb_bus_powerup(bus, 0); | |
656 | if (err) | |
657 | goto err_pcmcia_exit; | |
658 | ssb_chipcommon_init(&bus->chipco); | |
659 | ssb_mipscore_init(&bus->mipscore); | |
660 | err = ssb_fetch_invariants(bus, get_invariants); | |
661 | if (err) { | |
662 | ssb_bus_may_powerdown(bus); | |
663 | goto err_pcmcia_exit; | |
664 | } | |
665 | ssb_bus_may_powerdown(bus); | |
666 | ||
667 | /* Queue it for attach. | |
668 | * See the comment at the ssb_is_early_boot definition. */ | |
669 | list_add_tail(&bus->list, &attach_queue); | |
670 | if (!ssb_is_early_boot) { | |
671 | /* This is not early boot, so we must attach the bus now */ | |
672 | err = ssb_attach_queued_buses(); | |
673 | if (err) | |
674 | goto err_dequeue; | |
675 | } | |
676 | next_busnumber++; | |
677 | ssb_buses_unlock(); | |
678 | ||
679 | out: | |
680 | return err; | |
681 | ||
682 | err_dequeue: | |
683 | list_del(&bus->list); | |
684 | err_pcmcia_exit: | |
e7ec2e32 | 685 | ssb_pcmcia_exit(bus); |
61e115a5 MB |
686 | err_pci_exit: |
687 | ssb_pci_exit(bus); | |
688 | err_unmap: | |
689 | ssb_iounmap(bus); | |
690 | err_disable_xtal: | |
691 | ssb_buses_unlock(); | |
692 | ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); | |
693 | return err; | |
694 | } | |
695 | ||
696 | #ifdef CONFIG_SSB_PCIHOST | |
697 | int ssb_bus_pcibus_register(struct ssb_bus *bus, | |
698 | struct pci_dev *host_pci) | |
699 | { | |
700 | int err; | |
701 | ||
702 | bus->bustype = SSB_BUSTYPE_PCI; | |
703 | bus->host_pci = host_pci; | |
704 | bus->ops = &ssb_pci_ops; | |
705 | ||
706 | err = ssb_bus_register(bus, ssb_pci_get_invariants, 0); | |
707 | if (!err) { | |
708 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " | |
709 | "PCI device %s\n", host_pci->dev.bus_id); | |
710 | } | |
711 | ||
712 | return err; | |
713 | } | |
714 | EXPORT_SYMBOL(ssb_bus_pcibus_register); | |
715 | #endif /* CONFIG_SSB_PCIHOST */ | |
716 | ||
717 | #ifdef CONFIG_SSB_PCMCIAHOST | |
718 | int ssb_bus_pcmciabus_register(struct ssb_bus *bus, | |
719 | struct pcmcia_device *pcmcia_dev, | |
720 | unsigned long baseaddr) | |
721 | { | |
722 | int err; | |
723 | ||
724 | bus->bustype = SSB_BUSTYPE_PCMCIA; | |
725 | bus->host_pcmcia = pcmcia_dev; | |
726 | bus->ops = &ssb_pcmcia_ops; | |
727 | ||
728 | err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr); | |
729 | if (!err) { | |
730 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " | |
731 | "PCMCIA device %s\n", pcmcia_dev->devname); | |
732 | } | |
733 | ||
734 | return err; | |
735 | } | |
736 | EXPORT_SYMBOL(ssb_bus_pcmciabus_register); | |
737 | #endif /* CONFIG_SSB_PCMCIAHOST */ | |
738 | ||
739 | int ssb_bus_ssbbus_register(struct ssb_bus *bus, | |
740 | unsigned long baseaddr, | |
741 | ssb_invariants_func_t get_invariants) | |
742 | { | |
743 | int err; | |
744 | ||
745 | bus->bustype = SSB_BUSTYPE_SSB; | |
746 | bus->ops = &ssb_ssb_ops; | |
747 | ||
748 | err = ssb_bus_register(bus, get_invariants, baseaddr); | |
749 | if (!err) { | |
750 | ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at " | |
751 | "address 0x%08lX\n", baseaddr); | |
752 | } | |
753 | ||
754 | return err; | |
755 | } | |
756 | ||
757 | int __ssb_driver_register(struct ssb_driver *drv, struct module *owner) | |
758 | { | |
759 | drv->drv.name = drv->name; | |
760 | drv->drv.bus = &ssb_bustype; | |
761 | drv->drv.owner = owner; | |
762 | ||
763 | return driver_register(&drv->drv); | |
764 | } | |
765 | EXPORT_SYMBOL(__ssb_driver_register); | |
766 | ||
767 | void ssb_driver_unregister(struct ssb_driver *drv) | |
768 | { | |
769 | driver_unregister(&drv->drv); | |
770 | } | |
771 | EXPORT_SYMBOL(ssb_driver_unregister); | |
772 | ||
773 | void ssb_set_devtypedata(struct ssb_device *dev, void *data) | |
774 | { | |
775 | struct ssb_bus *bus = dev->bus; | |
776 | struct ssb_device *ent; | |
777 | int i; | |
778 | ||
779 | for (i = 0; i < bus->nr_devices; i++) { | |
780 | ent = &(bus->devices[i]); | |
781 | if (ent->id.vendor != dev->id.vendor) | |
782 | continue; | |
783 | if (ent->id.coreid != dev->id.coreid) | |
784 | continue; | |
785 | ||
786 | ent->devtypedata = data; | |
787 | } | |
788 | } | |
789 | EXPORT_SYMBOL(ssb_set_devtypedata); | |
790 | ||
791 | static u32 clkfactor_f6_resolve(u32 v) | |
792 | { | |
793 | /* map the magic values */ | |
794 | switch (v) { | |
795 | case SSB_CHIPCO_CLK_F6_2: | |
796 | return 2; | |
797 | case SSB_CHIPCO_CLK_F6_3: | |
798 | return 3; | |
799 | case SSB_CHIPCO_CLK_F6_4: | |
800 | return 4; | |
801 | case SSB_CHIPCO_CLK_F6_5: | |
802 | return 5; | |
803 | case SSB_CHIPCO_CLK_F6_6: | |
804 | return 6; | |
805 | case SSB_CHIPCO_CLK_F6_7: | |
806 | return 7; | |
807 | } | |
808 | return 0; | |
809 | } | |
810 | ||
811 | /* Calculate the speed the backplane would run at a given set of clockcontrol values */ | |
812 | u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m) | |
813 | { | |
814 | u32 n1, n2, clock, m1, m2, m3, mc; | |
815 | ||
816 | n1 = (n & SSB_CHIPCO_CLK_N1); | |
817 | n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT); | |
818 | ||
819 | switch (plltype) { | |
820 | case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */ | |
821 | if (m & SSB_CHIPCO_CLK_T6_MMASK) | |
822 | return SSB_CHIPCO_CLK_T6_M0; | |
823 | return SSB_CHIPCO_CLK_T6_M1; | |
824 | case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ | |
825 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ | |
826 | case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ | |
827 | case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ | |
828 | n1 = clkfactor_f6_resolve(n1); | |
829 | n2 += SSB_CHIPCO_CLK_F5_BIAS; | |
830 | break; | |
831 | case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */ | |
832 | n1 += SSB_CHIPCO_CLK_T2_BIAS; | |
833 | n2 += SSB_CHIPCO_CLK_T2_BIAS; | |
834 | SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7))); | |
835 | SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23))); | |
836 | break; | |
837 | case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */ | |
838 | return 100000000; | |
839 | default: | |
840 | SSB_WARN_ON(1); | |
841 | } | |
842 | ||
843 | switch (plltype) { | |
844 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ | |
845 | case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ | |
846 | clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2; | |
847 | break; | |
848 | default: | |
849 | clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2; | |
850 | } | |
851 | if (!clock) | |
852 | return 0; | |
853 | ||
854 | m1 = (m & SSB_CHIPCO_CLK_M1); | |
855 | m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); | |
856 | m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT); | |
857 | mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT); | |
858 | ||
859 | switch (plltype) { | |
860 | case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */ | |
861 | case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */ | |
862 | case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */ | |
863 | case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */ | |
864 | m1 = clkfactor_f6_resolve(m1); | |
865 | if ((plltype == SSB_PLLTYPE_1) || | |
866 | (plltype == SSB_PLLTYPE_3)) | |
867 | m2 += SSB_CHIPCO_CLK_F5_BIAS; | |
868 | else | |
869 | m2 = clkfactor_f6_resolve(m2); | |
870 | m3 = clkfactor_f6_resolve(m3); | |
871 | ||
872 | switch (mc) { | |
873 | case SSB_CHIPCO_CLK_MC_BYPASS: | |
874 | return clock; | |
875 | case SSB_CHIPCO_CLK_MC_M1: | |
876 | return (clock / m1); | |
877 | case SSB_CHIPCO_CLK_MC_M1M2: | |
878 | return (clock / (m1 * m2)); | |
879 | case SSB_CHIPCO_CLK_MC_M1M2M3: | |
880 | return (clock / (m1 * m2 * m3)); | |
881 | case SSB_CHIPCO_CLK_MC_M1M3: | |
882 | return (clock / (m1 * m3)); | |
883 | } | |
884 | return 0; | |
885 | case SSB_PLLTYPE_2: | |
886 | m1 += SSB_CHIPCO_CLK_T2_BIAS; | |
887 | m2 += SSB_CHIPCO_CLK_T2M2_BIAS; | |
888 | m3 += SSB_CHIPCO_CLK_T2_BIAS; | |
889 | SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7))); | |
890 | SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10))); | |
891 | SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7))); | |
892 | ||
893 | if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP)) | |
894 | clock /= m1; | |
895 | if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP)) | |
896 | clock /= m2; | |
897 | if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP)) | |
898 | clock /= m3; | |
899 | return clock; | |
900 | default: | |
901 | SSB_WARN_ON(1); | |
902 | } | |
903 | return 0; | |
904 | } | |
905 | ||
906 | /* Get the current speed the backplane is running at */ | |
907 | u32 ssb_clockspeed(struct ssb_bus *bus) | |
908 | { | |
909 | u32 rate; | |
910 | u32 plltype; | |
911 | u32 clkctl_n, clkctl_m; | |
912 | ||
913 | if (ssb_extif_available(&bus->extif)) | |
914 | ssb_extif_get_clockcontrol(&bus->extif, &plltype, | |
915 | &clkctl_n, &clkctl_m); | |
916 | else if (bus->chipco.dev) | |
917 | ssb_chipco_get_clockcontrol(&bus->chipco, &plltype, | |
918 | &clkctl_n, &clkctl_m); | |
919 | else | |
920 | return 0; | |
921 | ||
922 | if (bus->chip_id == 0x5365) { | |
923 | rate = 100000000; | |
924 | } else { | |
925 | rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m); | |
926 | if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */ | |
927 | rate /= 2; | |
928 | } | |
929 | ||
930 | return rate; | |
931 | } | |
932 | EXPORT_SYMBOL(ssb_clockspeed); | |
933 | ||
934 | static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev) | |
935 | { | |
c272ef44 LF |
936 | u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV; |
937 | ||
61e115a5 MB |
938 | /* The REJECT bit changed position in TMSLOW between |
939 | * Backplane revisions. */ | |
c272ef44 | 940 | switch (rev) { |
61e115a5 MB |
941 | case SSB_IDLOW_SSBREV_22: |
942 | return SSB_TMSLOW_REJECT_22; | |
943 | case SSB_IDLOW_SSBREV_23: | |
944 | return SSB_TMSLOW_REJECT_23; | |
c272ef44 LF |
945 | case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */ |
946 | case SSB_IDLOW_SSBREV_25: /* same here */ | |
947 | case SSB_IDLOW_SSBREV_26: /* same here */ | |
948 | case SSB_IDLOW_SSBREV_27: /* same here */ | |
949 | return SSB_TMSLOW_REJECT_23; /* this is a guess */ | |
61e115a5 | 950 | default: |
c272ef44 | 951 | printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev); |
61e115a5 MB |
952 | WARN_ON(1); |
953 | } | |
954 | return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23); | |
955 | } | |
956 | ||
957 | int ssb_device_is_enabled(struct ssb_device *dev) | |
958 | { | |
959 | u32 val; | |
960 | u32 reject; | |
961 | ||
962 | reject = ssb_tmslow_reject_bitmask(dev); | |
963 | val = ssb_read32(dev, SSB_TMSLOW); | |
964 | val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject; | |
965 | ||
966 | return (val == SSB_TMSLOW_CLOCK); | |
967 | } | |
968 | EXPORT_SYMBOL(ssb_device_is_enabled); | |
969 | ||
970 | static void ssb_flush_tmslow(struct ssb_device *dev) | |
971 | { | |
972 | /* Make _really_ sure the device has finished the TMSLOW | |
973 | * register write transaction, as we risk running into | |
974 | * a machine check exception otherwise. | |
975 | * Do this by reading the register back to commit the | |
976 | * PCI write and delay an additional usec for the device | |
977 | * to react to the change. */ | |
978 | ssb_read32(dev, SSB_TMSLOW); | |
979 | udelay(1); | |
980 | } | |
981 | ||
982 | void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags) | |
983 | { | |
984 | u32 val; | |
985 | ||
986 | ssb_device_disable(dev, core_specific_flags); | |
987 | ssb_write32(dev, SSB_TMSLOW, | |
988 | SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK | | |
989 | SSB_TMSLOW_FGC | core_specific_flags); | |
990 | ssb_flush_tmslow(dev); | |
991 | ||
992 | /* Clear SERR if set. This is a hw bug workaround. */ | |
993 | if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR) | |
994 | ssb_write32(dev, SSB_TMSHIGH, 0); | |
995 | ||
996 | val = ssb_read32(dev, SSB_IMSTATE); | |
997 | if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) { | |
998 | val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO); | |
999 | ssb_write32(dev, SSB_IMSTATE, val); | |
1000 | } | |
1001 | ||
1002 | ssb_write32(dev, SSB_TMSLOW, | |
1003 | SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC | | |
1004 | core_specific_flags); | |
1005 | ssb_flush_tmslow(dev); | |
1006 | ||
1007 | ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK | | |
1008 | core_specific_flags); | |
1009 | ssb_flush_tmslow(dev); | |
1010 | } | |
1011 | EXPORT_SYMBOL(ssb_device_enable); | |
1012 | ||
1013 | /* Wait for a bit in a register to get set or unset. | |
1014 | * timeout is in units of ten-microseconds */ | |
1015 | static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask, | |
1016 | int timeout, int set) | |
1017 | { | |
1018 | int i; | |
1019 | u32 val; | |
1020 | ||
1021 | for (i = 0; i < timeout; i++) { | |
1022 | val = ssb_read32(dev, reg); | |
1023 | if (set) { | |
1024 | if (val & bitmask) | |
1025 | return 0; | |
1026 | } else { | |
1027 | if (!(val & bitmask)) | |
1028 | return 0; | |
1029 | } | |
1030 | udelay(10); | |
1031 | } | |
1032 | printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on " | |
1033 | "register %04X to %s.\n", | |
1034 | bitmask, reg, (set ? "set" : "clear")); | |
1035 | ||
1036 | return -ETIMEDOUT; | |
1037 | } | |
1038 | ||
1039 | void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags) | |
1040 | { | |
1041 | u32 reject; | |
1042 | ||
1043 | if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET) | |
1044 | return; | |
1045 | ||
1046 | reject = ssb_tmslow_reject_bitmask(dev); | |
1047 | ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK); | |
1048 | ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1); | |
1049 | ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0); | |
1050 | ssb_write32(dev, SSB_TMSLOW, | |
1051 | SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK | | |
1052 | reject | SSB_TMSLOW_RESET | | |
1053 | core_specific_flags); | |
1054 | ssb_flush_tmslow(dev); | |
1055 | ||
1056 | ssb_write32(dev, SSB_TMSLOW, | |
1057 | reject | SSB_TMSLOW_RESET | | |
1058 | core_specific_flags); | |
1059 | ssb_flush_tmslow(dev); | |
1060 | } | |
1061 | EXPORT_SYMBOL(ssb_device_disable); | |
1062 | ||
1063 | u32 ssb_dma_translation(struct ssb_device *dev) | |
1064 | { | |
1065 | switch (dev->bus->bustype) { | |
1066 | case SSB_BUSTYPE_SSB: | |
1067 | return 0; | |
1068 | case SSB_BUSTYPE_PCI: | |
1069 | case SSB_BUSTYPE_PCMCIA: | |
1070 | return SSB_PCI_DMA; | |
1071 | } | |
1072 | return 0; | |
1073 | } | |
1074 | EXPORT_SYMBOL(ssb_dma_translation); | |
1075 | ||
1076 | int ssb_dma_set_mask(struct ssb_device *ssb_dev, u64 mask) | |
1077 | { | |
1078 | struct device *dev = ssb_dev->dev; | |
1079 | ||
1080 | #ifdef CONFIG_SSB_PCIHOST | |
1081 | if (ssb_dev->bus->bustype == SSB_BUSTYPE_PCI && | |
1082 | !dma_supported(dev, mask)) | |
1083 | return -EIO; | |
1084 | #endif | |
1085 | dev->coherent_dma_mask = mask; | |
1086 | dev->dma_mask = &dev->coherent_dma_mask; | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | EXPORT_SYMBOL(ssb_dma_set_mask); | |
1091 | ||
1092 | int ssb_bus_may_powerdown(struct ssb_bus *bus) | |
1093 | { | |
1094 | struct ssb_chipcommon *cc; | |
1095 | int err = 0; | |
1096 | ||
1097 | /* On buses where more than one core may be working | |
1098 | * at a time, we must not powerdown stuff if there are | |
1099 | * still cores that may want to run. */ | |
1100 | if (bus->bustype == SSB_BUSTYPE_SSB) | |
1101 | goto out; | |
1102 | ||
1103 | cc = &bus->chipco; | |
1104 | ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW); | |
1105 | err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0); | |
1106 | if (err) | |
1107 | goto error; | |
1108 | out: | |
1109 | #ifdef CONFIG_SSB_DEBUG | |
1110 | bus->powered_up = 0; | |
1111 | #endif | |
1112 | return err; | |
1113 | error: | |
1114 | ssb_printk(KERN_ERR PFX "Bus powerdown failed\n"); | |
1115 | goto out; | |
1116 | } | |
1117 | EXPORT_SYMBOL(ssb_bus_may_powerdown); | |
1118 | ||
1119 | int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl) | |
1120 | { | |
1121 | struct ssb_chipcommon *cc; | |
1122 | int err; | |
1123 | enum ssb_clkmode mode; | |
1124 | ||
1125 | err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1); | |
1126 | if (err) | |
1127 | goto error; | |
1128 | cc = &bus->chipco; | |
1129 | mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST; | |
1130 | ssb_chipco_set_clockmode(cc, mode); | |
1131 | ||
1132 | #ifdef CONFIG_SSB_DEBUG | |
1133 | bus->powered_up = 1; | |
1134 | #endif | |
1135 | return 0; | |
1136 | error: | |
1137 | ssb_printk(KERN_ERR PFX "Bus powerup failed\n"); | |
1138 | return err; | |
1139 | } | |
1140 | EXPORT_SYMBOL(ssb_bus_powerup); | |
1141 | ||
1142 | u32 ssb_admatch_base(u32 adm) | |
1143 | { | |
1144 | u32 base = 0; | |
1145 | ||
1146 | switch (adm & SSB_ADM_TYPE) { | |
1147 | case SSB_ADM_TYPE0: | |
1148 | base = (adm & SSB_ADM_BASE0); | |
1149 | break; | |
1150 | case SSB_ADM_TYPE1: | |
1151 | SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ | |
1152 | base = (adm & SSB_ADM_BASE1); | |
1153 | break; | |
1154 | case SSB_ADM_TYPE2: | |
1155 | SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ | |
1156 | base = (adm & SSB_ADM_BASE2); | |
1157 | break; | |
1158 | default: | |
1159 | SSB_WARN_ON(1); | |
1160 | } | |
1161 | ||
1162 | return base; | |
1163 | } | |
1164 | EXPORT_SYMBOL(ssb_admatch_base); | |
1165 | ||
1166 | u32 ssb_admatch_size(u32 adm) | |
1167 | { | |
1168 | u32 size = 0; | |
1169 | ||
1170 | switch (adm & SSB_ADM_TYPE) { | |
1171 | case SSB_ADM_TYPE0: | |
1172 | size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT); | |
1173 | break; | |
1174 | case SSB_ADM_TYPE1: | |
1175 | SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ | |
1176 | size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT); | |
1177 | break; | |
1178 | case SSB_ADM_TYPE2: | |
1179 | SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */ | |
1180 | size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT); | |
1181 | break; | |
1182 | default: | |
1183 | SSB_WARN_ON(1); | |
1184 | } | |
1185 | size = (1 << (size + 1)); | |
1186 | ||
1187 | return size; | |
1188 | } | |
1189 | EXPORT_SYMBOL(ssb_admatch_size); | |
1190 | ||
1191 | static int __init ssb_modinit(void) | |
1192 | { | |
1193 | int err; | |
1194 | ||
1195 | /* See the comment at the ssb_is_early_boot definition */ | |
1196 | ssb_is_early_boot = 0; | |
1197 | err = bus_register(&ssb_bustype); | |
1198 | if (err) | |
1199 | return err; | |
1200 | ||
1201 | /* Maybe we already registered some buses at early boot. | |
1202 | * Check for this and attach them | |
1203 | */ | |
1204 | ssb_buses_lock(); | |
1205 | err = ssb_attach_queued_buses(); | |
1206 | ssb_buses_unlock(); | |
1207 | if (err) | |
1208 | bus_unregister(&ssb_bustype); | |
1209 | ||
1210 | err = b43_pci_ssb_bridge_init(); | |
1211 | if (err) { | |
1212 | ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge " | |
aab547ce MB |
1213 | "initialization failed\n"); |
1214 | /* don't fail SSB init because of this */ | |
1215 | err = 0; | |
1216 | } | |
1217 | err = ssb_gige_init(); | |
1218 | if (err) { | |
1219 | ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet " | |
1220 | "driver initialization failed\n"); | |
61e115a5 MB |
1221 | /* don't fail SSB init because of this */ |
1222 | err = 0; | |
1223 | } | |
1224 | ||
1225 | return err; | |
1226 | } | |
8d8c90e3 MB |
1227 | /* ssb must be initialized after PCI but before the ssb drivers. |
1228 | * That means we must use some initcall between subsys_initcall | |
1229 | * and device_initcall. */ | |
1230 | fs_initcall(ssb_modinit); | |
61e115a5 MB |
1231 | |
1232 | static void __exit ssb_modexit(void) | |
1233 | { | |
aab547ce | 1234 | ssb_gige_exit(); |
61e115a5 MB |
1235 | b43_pci_ssb_bridge_exit(); |
1236 | bus_unregister(&ssb_bustype); | |
1237 | } | |
1238 | module_exit(ssb_modexit) |