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ce44bf5b | 1 | /* Copyright (c) 2009-2013, The Linux Foundation. All rights reserved. |
e44b0cee KH |
2 | * Copyright (c) 2010, Google Inc. |
3 | * | |
4 | * Original authors: Code Aurora Forum | |
5 | * | |
6 | * Author: Dima Zavin <dima@android.com> | |
7 | * - Largely rewritten from original to not be an i2c driver. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 and | |
11 | * only version 2 as published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
18 | ||
19 | #define pr_fmt(fmt) "%s: " fmt, __func__ | |
20 | ||
21 | #include <linux/delay.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/slab.h> | |
ce44bf5b | 27 | #include <linux/ssbi.h> |
e44b0cee | 28 | #include <linux/module.h> |
97f00f71 DB |
29 | #include <linux/of.h> |
30 | #include <linux/of_device.h> | |
e44b0cee KH |
31 | |
32 | /* SSBI 2.0 controller registers */ | |
33 | #define SSBI2_CMD 0x0008 | |
34 | #define SSBI2_RD 0x0010 | |
35 | #define SSBI2_STATUS 0x0014 | |
36 | #define SSBI2_MODE2 0x001C | |
37 | ||
38 | /* SSBI_CMD fields */ | |
39 | #define SSBI_CMD_RDWRN (1 << 24) | |
40 | ||
41 | /* SSBI_STATUS fields */ | |
42 | #define SSBI_STATUS_RD_READY (1 << 2) | |
43 | #define SSBI_STATUS_READY (1 << 1) | |
44 | #define SSBI_STATUS_MCHN_BUSY (1 << 0) | |
45 | ||
46 | /* SSBI_MODE2 fields */ | |
47 | #define SSBI_MODE2_REG_ADDR_15_8_SHFT 0x04 | |
48 | #define SSBI_MODE2_REG_ADDR_15_8_MASK (0x7f << SSBI_MODE2_REG_ADDR_15_8_SHFT) | |
49 | ||
50 | #define SET_SSBI_MODE2_REG_ADDR_15_8(MD, AD) \ | |
51 | (((MD) & 0x0F) | ((((AD) >> 8) << SSBI_MODE2_REG_ADDR_15_8_SHFT) & \ | |
52 | SSBI_MODE2_REG_ADDR_15_8_MASK)) | |
53 | ||
54 | /* SSBI PMIC Arbiter command registers */ | |
55 | #define SSBI_PA_CMD 0x0000 | |
56 | #define SSBI_PA_RD_STATUS 0x0004 | |
57 | ||
58 | /* SSBI_PA_CMD fields */ | |
59 | #define SSBI_PA_CMD_RDWRN (1 << 24) | |
60 | #define SSBI_PA_CMD_ADDR_MASK 0x7fff /* REG_ADDR_7_0, REG_ADDR_8_14*/ | |
61 | ||
62 | /* SSBI_PA_RD_STATUS fields */ | |
63 | #define SSBI_PA_RD_STATUS_TRANS_DONE (1 << 27) | |
64 | #define SSBI_PA_RD_STATUS_TRANS_DENIED (1 << 26) | |
65 | ||
66 | #define SSBI_TIMEOUT_US 100 | |
67 | ||
ce44bf5b | 68 | struct ssbi { |
e44b0cee KH |
69 | struct device *slave; |
70 | void __iomem *base; | |
71 | spinlock_t lock; | |
ce44bf5b DB |
72 | enum ssbi_controller_type controller_type; |
73 | int (*read)(struct ssbi *, u16 addr, u8 *buf, int len); | |
74 | int (*write)(struct ssbi *, u16 addr, u8 *buf, int len); | |
e44b0cee KH |
75 | }; |
76 | ||
ce44bf5b | 77 | #define to_ssbi(dev) platform_get_drvdata(to_platform_device(dev)) |
e44b0cee | 78 | |
ce44bf5b | 79 | static inline u32 ssbi_readl(struct ssbi *ssbi, u32 reg) |
e44b0cee KH |
80 | { |
81 | return readl(ssbi->base + reg); | |
82 | } | |
83 | ||
ce44bf5b | 84 | static inline void ssbi_writel(struct ssbi *ssbi, u32 val, u32 reg) |
e44b0cee KH |
85 | { |
86 | writel(val, ssbi->base + reg); | |
87 | } | |
88 | ||
3f7a73b5 DB |
89 | /* |
90 | * Via private exchange with one of the original authors, the hardware | |
91 | * should generally finish a transaction in about 5us. The worst | |
92 | * case, is when using the arbiter and both other CPUs have just | |
93 | * started trying to use the SSBI bus will result in a time of about | |
94 | * 20us. It should never take longer than this. | |
95 | * | |
96 | * As such, this wait merely spins, with a udelay. | |
97 | */ | |
ce44bf5b | 98 | static int ssbi_wait_mask(struct ssbi *ssbi, u32 set_mask, u32 clr_mask) |
e44b0cee KH |
99 | { |
100 | u32 timeout = SSBI_TIMEOUT_US; | |
101 | u32 val; | |
102 | ||
103 | while (timeout--) { | |
104 | val = ssbi_readl(ssbi, SSBI2_STATUS); | |
105 | if (((val & set_mask) == set_mask) && ((val & clr_mask) == 0)) | |
106 | return 0; | |
107 | udelay(1); | |
108 | } | |
109 | ||
e44b0cee KH |
110 | return -ETIMEDOUT; |
111 | } | |
112 | ||
113 | static int | |
ce44bf5b | 114 | ssbi_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len) |
e44b0cee KH |
115 | { |
116 | u32 cmd = SSBI_CMD_RDWRN | ((addr & 0xff) << 16); | |
117 | int ret = 0; | |
118 | ||
119 | if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) { | |
120 | u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2); | |
121 | mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr); | |
122 | ssbi_writel(ssbi, mode2, SSBI2_MODE2); | |
123 | } | |
124 | ||
125 | while (len) { | |
126 | ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0); | |
127 | if (ret) | |
128 | goto err; | |
129 | ||
130 | ssbi_writel(ssbi, cmd, SSBI2_CMD); | |
131 | ret = ssbi_wait_mask(ssbi, SSBI_STATUS_RD_READY, 0); | |
132 | if (ret) | |
133 | goto err; | |
134 | *buf++ = ssbi_readl(ssbi, SSBI2_RD) & 0xff; | |
135 | len--; | |
136 | } | |
137 | ||
138 | err: | |
139 | return ret; | |
140 | } | |
141 | ||
142 | static int | |
ce44bf5b | 143 | ssbi_write_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len) |
e44b0cee KH |
144 | { |
145 | int ret = 0; | |
146 | ||
147 | if (ssbi->controller_type == MSM_SBI_CTRL_SSBI2) { | |
148 | u32 mode2 = ssbi_readl(ssbi, SSBI2_MODE2); | |
149 | mode2 = SET_SSBI_MODE2_REG_ADDR_15_8(mode2, addr); | |
150 | ssbi_writel(ssbi, mode2, SSBI2_MODE2); | |
151 | } | |
152 | ||
153 | while (len) { | |
154 | ret = ssbi_wait_mask(ssbi, SSBI_STATUS_READY, 0); | |
155 | if (ret) | |
156 | goto err; | |
157 | ||
158 | ssbi_writel(ssbi, ((addr & 0xff) << 16) | *buf, SSBI2_CMD); | |
159 | ret = ssbi_wait_mask(ssbi, 0, SSBI_STATUS_MCHN_BUSY); | |
160 | if (ret) | |
161 | goto err; | |
162 | buf++; | |
163 | len--; | |
164 | } | |
165 | ||
166 | err: | |
167 | return ret; | |
168 | } | |
169 | ||
3f7a73b5 DB |
170 | /* |
171 | * See ssbi_wait_mask for an explanation of the time and the | |
172 | * busywait. | |
173 | */ | |
e44b0cee | 174 | static inline int |
ce44bf5b | 175 | ssbi_pa_transfer(struct ssbi *ssbi, u32 cmd, u8 *data) |
e44b0cee KH |
176 | { |
177 | u32 timeout = SSBI_TIMEOUT_US; | |
178 | u32 rd_status = 0; | |
179 | ||
180 | ssbi_writel(ssbi, cmd, SSBI_PA_CMD); | |
181 | ||
182 | while (timeout--) { | |
183 | rd_status = ssbi_readl(ssbi, SSBI_PA_RD_STATUS); | |
184 | ||
37799ef4 | 185 | if (rd_status & SSBI_PA_RD_STATUS_TRANS_DENIED) |
e44b0cee | 186 | return -EPERM; |
e44b0cee KH |
187 | |
188 | if (rd_status & SSBI_PA_RD_STATUS_TRANS_DONE) { | |
189 | if (data) | |
190 | *data = rd_status & 0xff; | |
191 | return 0; | |
192 | } | |
193 | udelay(1); | |
194 | } | |
195 | ||
e44b0cee KH |
196 | return -ETIMEDOUT; |
197 | } | |
198 | ||
199 | static int | |
ce44bf5b | 200 | ssbi_pa_read_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len) |
e44b0cee KH |
201 | { |
202 | u32 cmd; | |
203 | int ret = 0; | |
204 | ||
205 | cmd = SSBI_PA_CMD_RDWRN | (addr & SSBI_PA_CMD_ADDR_MASK) << 8; | |
206 | ||
207 | while (len) { | |
ce44bf5b | 208 | ret = ssbi_pa_transfer(ssbi, cmd, buf); |
e44b0cee KH |
209 | if (ret) |
210 | goto err; | |
211 | buf++; | |
212 | len--; | |
213 | } | |
214 | ||
215 | err: | |
216 | return ret; | |
217 | } | |
218 | ||
219 | static int | |
ce44bf5b | 220 | ssbi_pa_write_bytes(struct ssbi *ssbi, u16 addr, u8 *buf, int len) |
e44b0cee KH |
221 | { |
222 | u32 cmd; | |
223 | int ret = 0; | |
224 | ||
225 | while (len) { | |
226 | cmd = (addr & SSBI_PA_CMD_ADDR_MASK) << 8 | *buf; | |
ce44bf5b | 227 | ret = ssbi_pa_transfer(ssbi, cmd, NULL); |
e44b0cee KH |
228 | if (ret) |
229 | goto err; | |
230 | buf++; | |
231 | len--; | |
232 | } | |
233 | ||
234 | err: | |
235 | return ret; | |
236 | } | |
237 | ||
ce44bf5b | 238 | int ssbi_read(struct device *dev, u16 addr, u8 *buf, int len) |
e44b0cee | 239 | { |
ce44bf5b | 240 | struct ssbi *ssbi = to_ssbi(dev); |
e44b0cee KH |
241 | unsigned long flags; |
242 | int ret; | |
243 | ||
e44b0cee KH |
244 | spin_lock_irqsave(&ssbi->lock, flags); |
245 | ret = ssbi->read(ssbi, addr, buf, len); | |
246 | spin_unlock_irqrestore(&ssbi->lock, flags); | |
247 | ||
248 | return ret; | |
249 | } | |
ce44bf5b | 250 | EXPORT_SYMBOL_GPL(ssbi_read); |
e44b0cee | 251 | |
ce44bf5b | 252 | int ssbi_write(struct device *dev, u16 addr, u8 *buf, int len) |
e44b0cee | 253 | { |
ce44bf5b | 254 | struct ssbi *ssbi = to_ssbi(dev); |
e44b0cee KH |
255 | unsigned long flags; |
256 | int ret; | |
257 | ||
e44b0cee KH |
258 | spin_lock_irqsave(&ssbi->lock, flags); |
259 | ret = ssbi->write(ssbi, addr, buf, len); | |
260 | spin_unlock_irqrestore(&ssbi->lock, flags); | |
261 | ||
262 | return ret; | |
263 | } | |
ce44bf5b | 264 | EXPORT_SYMBOL_GPL(ssbi_write); |
e44b0cee | 265 | |
ce44bf5b | 266 | static int ssbi_probe(struct platform_device *pdev) |
e44b0cee | 267 | { |
97f00f71 | 268 | struct device_node *np = pdev->dev.of_node; |
e44b0cee | 269 | struct resource *mem_res; |
ce44bf5b | 270 | struct ssbi *ssbi; |
e44b0cee | 271 | int ret = 0; |
97f00f71 | 272 | const char *type; |
e44b0cee | 273 | |
ce44bf5b | 274 | ssbi = kzalloc(sizeof(struct ssbi), GFP_KERNEL); |
e44b0cee KH |
275 | if (!ssbi) { |
276 | pr_err("can not allocate ssbi_data\n"); | |
277 | return -ENOMEM; | |
278 | } | |
279 | ||
280 | mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
281 | if (!mem_res) { | |
282 | pr_err("missing mem resource\n"); | |
283 | ret = -EINVAL; | |
284 | goto err_get_mem_res; | |
285 | } | |
286 | ||
287 | ssbi->base = ioremap(mem_res->start, resource_size(mem_res)); | |
288 | if (!ssbi->base) { | |
289 | pr_err("ioremap of 0x%p failed\n", (void *)mem_res->start); | |
290 | ret = -EINVAL; | |
291 | goto err_ioremap; | |
292 | } | |
e44b0cee KH |
293 | platform_set_drvdata(pdev, ssbi); |
294 | ||
97f00f71 DB |
295 | type = of_get_property(np, "qcom,controller-type", NULL); |
296 | if (type == NULL) { | |
297 | pr_err("Missing qcom,controller-type property\n"); | |
298 | ret = -EINVAL; | |
299 | goto err_ssbi_controller; | |
300 | } | |
301 | dev_info(&pdev->dev, "SSBI controller type: '%s'\n", type); | |
302 | if (strcmp(type, "ssbi") == 0) | |
303 | ssbi->controller_type = MSM_SBI_CTRL_SSBI; | |
304 | else if (strcmp(type, "ssbi2") == 0) | |
305 | ssbi->controller_type = MSM_SBI_CTRL_SSBI2; | |
306 | else if (strcmp(type, "pmic-arbiter") == 0) | |
307 | ssbi->controller_type = MSM_SBI_CTRL_PMIC_ARBITER; | |
308 | else { | |
309 | pr_err("Unknown qcom,controller-type\n"); | |
310 | ret = -EINVAL; | |
311 | goto err_ssbi_controller; | |
312 | } | |
313 | ||
e44b0cee | 314 | if (ssbi->controller_type == MSM_SBI_CTRL_PMIC_ARBITER) { |
ce44bf5b DB |
315 | ssbi->read = ssbi_pa_read_bytes; |
316 | ssbi->write = ssbi_pa_write_bytes; | |
e44b0cee | 317 | } else { |
ce44bf5b DB |
318 | ssbi->read = ssbi_read_bytes; |
319 | ssbi->write = ssbi_write_bytes; | |
e44b0cee KH |
320 | } |
321 | ||
322 | spin_lock_init(&ssbi->lock); | |
323 | ||
97f00f71 | 324 | ret = of_platform_populate(np, NULL, NULL, &pdev->dev); |
e44b0cee | 325 | if (ret) |
97f00f71 | 326 | goto err_ssbi_controller; |
e44b0cee KH |
327 | |
328 | return 0; | |
329 | ||
97f00f71 | 330 | err_ssbi_controller: |
e44b0cee KH |
331 | platform_set_drvdata(pdev, NULL); |
332 | iounmap(ssbi->base); | |
333 | err_ioremap: | |
334 | err_get_mem_res: | |
335 | kfree(ssbi); | |
336 | return ret; | |
337 | } | |
338 | ||
ce44bf5b | 339 | static int ssbi_remove(struct platform_device *pdev) |
e44b0cee | 340 | { |
ce44bf5b | 341 | struct ssbi *ssbi = platform_get_drvdata(pdev); |
e44b0cee KH |
342 | |
343 | platform_set_drvdata(pdev, NULL); | |
344 | iounmap(ssbi->base); | |
345 | kfree(ssbi); | |
346 | return 0; | |
347 | } | |
348 | ||
97f00f71 DB |
349 | static struct of_device_id ssbi_match_table[] = { |
350 | { .compatible = "qcom,ssbi" }, | |
351 | {} | |
352 | }; | |
353 | ||
ce44bf5b DB |
354 | static struct platform_driver ssbi_driver = { |
355 | .probe = ssbi_probe, | |
356 | .remove = ssbi_remove, | |
e44b0cee | 357 | .driver = { |
ce44bf5b | 358 | .name = "ssbi", |
e44b0cee | 359 | .owner = THIS_MODULE, |
97f00f71 | 360 | .of_match_table = ssbi_match_table, |
e44b0cee KH |
361 | }, |
362 | }; | |
363 | ||
ce44bf5b | 364 | static int __init ssbi_init(void) |
e44b0cee | 365 | { |
ce44bf5b | 366 | return platform_driver_register(&ssbi_driver); |
e44b0cee | 367 | } |
ce44bf5b | 368 | module_init(ssbi_init); |
e44b0cee | 369 | |
ce44bf5b | 370 | static void __exit ssbi_exit(void) |
e44b0cee | 371 | { |
ce44bf5b | 372 | platform_driver_unregister(&ssbi_driver); |
e44b0cee | 373 | } |
ce44bf5b | 374 | module_exit(ssbi_exit) |
e44b0cee KH |
375 | |
376 | MODULE_LICENSE("GPL v2"); | |
377 | MODULE_VERSION("1.0"); | |
ce44bf5b | 378 | MODULE_ALIAS("platform:ssbi"); |
e44b0cee | 379 | MODULE_AUTHOR("Dima Zavin <dima@android.com>"); |