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479e2f44 SS |
1 | /* |
2 | * Copyright (C) 2005 - 2008 ServerEngines | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Contact Information: | |
11 | * linux-drivers@serverengines.com | |
12 | * | |
13 | * ServerEngines | |
14 | * 209 N. Fair Oaks Ave | |
15 | * Sunnyvale, CA 94085 | |
16 | */ | |
17 | /* | |
18 | * Autogenerated by srcgen version: 0127 | |
19 | */ | |
20 | #ifndef __pcicfg_amap_h__ | |
21 | #define __pcicfg_amap_h__ | |
22 | ||
23 | /* Vendor and Device ID Register. */ | |
24 | struct BE_PCICFG_ID_CSR_AMAP { | |
25 | u8 vendorid[16]; /* DWORD 0 */ | |
26 | u8 deviceid[16]; /* DWORD 0 */ | |
27 | } __packed; | |
28 | struct PCICFG_ID_CSR_AMAP { | |
29 | u32 dw[1]; | |
30 | }; | |
31 | ||
32 | /* IO Bar Register. */ | |
33 | struct BE_PCICFG_IOBAR_CSR_AMAP { | |
34 | u8 iospace; /* DWORD 0 */ | |
35 | u8 rsvd0[7]; /* DWORD 0 */ | |
36 | u8 iobar[24]; /* DWORD 0 */ | |
37 | } __packed; | |
38 | struct PCICFG_IOBAR_CSR_AMAP { | |
39 | u32 dw[1]; | |
40 | }; | |
41 | ||
42 | /* Memory BAR 0 Register. */ | |
43 | struct BE_PCICFG_MEMBAR0_CSR_AMAP { | |
44 | u8 memspace; /* DWORD 0 */ | |
45 | u8 type[2]; /* DWORD 0 */ | |
46 | u8 pf; /* DWORD 0 */ | |
47 | u8 rsvd0[10]; /* DWORD 0 */ | |
48 | u8 membar0[18]; /* DWORD 0 */ | |
49 | } __packed; | |
50 | struct PCICFG_MEMBAR0_CSR_AMAP { | |
51 | u32 dw[1]; | |
52 | }; | |
53 | ||
54 | /* Memory BAR 1 - Low Address Register. */ | |
55 | struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP { | |
56 | u8 memspace; /* DWORD 0 */ | |
57 | u8 type[2]; /* DWORD 0 */ | |
58 | u8 pf; /* DWORD 0 */ | |
59 | u8 rsvd0[13]; /* DWORD 0 */ | |
60 | u8 membar1lo[15]; /* DWORD 0 */ | |
61 | } __packed; | |
62 | struct PCICFG_MEMBAR1_LO_CSR_AMAP { | |
63 | u32 dw[1]; | |
64 | }; | |
65 | ||
66 | /* Memory BAR 1 - High Address Register. */ | |
67 | struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP { | |
68 | u8 membar1hi[32]; /* DWORD 0 */ | |
69 | } __packed; | |
70 | struct PCICFG_MEMBAR1_HI_CSR_AMAP { | |
71 | u32 dw[1]; | |
72 | }; | |
73 | ||
74 | /* Memory BAR 2 - Low Address Register. */ | |
75 | struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP { | |
76 | u8 memspace; /* DWORD 0 */ | |
77 | u8 type[2]; /* DWORD 0 */ | |
78 | u8 pf; /* DWORD 0 */ | |
79 | u8 rsvd0[17]; /* DWORD 0 */ | |
80 | u8 membar2lo[11]; /* DWORD 0 */ | |
81 | } __packed; | |
82 | struct PCICFG_MEMBAR2_LO_CSR_AMAP { | |
83 | u32 dw[1]; | |
84 | }; | |
85 | ||
86 | /* Memory BAR 2 - High Address Register. */ | |
87 | struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP { | |
88 | u8 membar2hi[32]; /* DWORD 0 */ | |
89 | } __packed; | |
90 | struct PCICFG_MEMBAR2_HI_CSR_AMAP { | |
91 | u32 dw[1]; | |
92 | }; | |
93 | ||
94 | /* Subsystem Vendor and ID (Function 0) Register. */ | |
95 | struct BE_PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP { | |
96 | u8 subsys_vendor_id[16]; /* DWORD 0 */ | |
97 | u8 subsys_id[16]; /* DWORD 0 */ | |
98 | } __packed; | |
99 | struct PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP { | |
100 | u32 dw[1]; | |
101 | }; | |
102 | ||
103 | /* Subsystem Vendor and ID (Function 1) Register. */ | |
104 | struct BE_PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP { | |
105 | u8 subsys_vendor_id[16]; /* DWORD 0 */ | |
106 | u8 subsys_id[16]; /* DWORD 0 */ | |
107 | } __packed; | |
108 | struct PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP { | |
109 | u32 dw[1]; | |
110 | }; | |
111 | ||
112 | /* Semaphore Register. */ | |
113 | struct BE_PCICFG_SEMAPHORE_CSR_AMAP { | |
114 | u8 locked; /* DWORD 0 */ | |
115 | u8 rsvd0[31]; /* DWORD 0 */ | |
116 | } __packed; | |
117 | struct PCICFG_SEMAPHORE_CSR_AMAP { | |
118 | u32 dw[1]; | |
119 | }; | |
120 | ||
121 | /* Soft Reset Register. */ | |
122 | struct BE_PCICFG_SOFT_RESET_CSR_AMAP { | |
123 | u8 rsvd0[7]; /* DWORD 0 */ | |
124 | u8 softreset; /* DWORD 0 */ | |
125 | u8 rsvd1[16]; /* DWORD 0 */ | |
126 | u8 nec_ll_rcvdetect_i[8]; /* DWORD 0 */ | |
127 | } __packed; | |
128 | struct PCICFG_SOFT_RESET_CSR_AMAP { | |
129 | u32 dw[1]; | |
130 | }; | |
131 | ||
132 | /* Unrecoverable Error Status (Low) Register. Each bit corresponds to | |
133 | * an internal Unrecoverable Error. These are set by hardware and may be | |
134 | * cleared by writing a one to the respective bit(s) to be cleared. Any | |
135 | * bit being set that is also unmasked will result in Unrecoverable Error | |
136 | * interrupt notification to the host CPU and/or Server Management chip | |
137 | * and the transitioning of BladeEngine to an Offline state. | |
138 | */ | |
139 | struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP { | |
140 | u8 cev_ue_status; /* DWORD 0 */ | |
141 | u8 ctx_ue_status; /* DWORD 0 */ | |
142 | u8 dbuf_ue_status; /* DWORD 0 */ | |
143 | u8 erx_ue_status; /* DWORD 0 */ | |
144 | u8 host_ue_status; /* DWORD 0 */ | |
145 | u8 mpu_ue_status; /* DWORD 0 */ | |
146 | u8 ndma_ue_status; /* DWORD 0 */ | |
147 | u8 ptc_ue_status; /* DWORD 0 */ | |
148 | u8 rdma_ue_status; /* DWORD 0 */ | |
149 | u8 rxf_ue_status; /* DWORD 0 */ | |
150 | u8 rxips_ue_status; /* DWORD 0 */ | |
151 | u8 rxulp0_ue_status; /* DWORD 0 */ | |
152 | u8 rxulp1_ue_status; /* DWORD 0 */ | |
153 | u8 rxulp2_ue_status; /* DWORD 0 */ | |
154 | u8 tim_ue_status; /* DWORD 0 */ | |
155 | u8 tpost_ue_status; /* DWORD 0 */ | |
156 | u8 tpre_ue_status; /* DWORD 0 */ | |
157 | u8 txips_ue_status; /* DWORD 0 */ | |
158 | u8 txulp0_ue_status; /* DWORD 0 */ | |
159 | u8 txulp1_ue_status; /* DWORD 0 */ | |
160 | u8 uc_ue_status; /* DWORD 0 */ | |
161 | u8 wdma_ue_status; /* DWORD 0 */ | |
162 | u8 txulp2_ue_status; /* DWORD 0 */ | |
163 | u8 host1_ue_status; /* DWORD 0 */ | |
164 | u8 p0_ob_link_ue_status; /* DWORD 0 */ | |
165 | u8 p1_ob_link_ue_status; /* DWORD 0 */ | |
166 | u8 host_gpio_ue_status; /* DWORD 0 */ | |
167 | u8 mbox_netw_ue_status; /* DWORD 0 */ | |
168 | u8 mbox_stor_ue_status; /* DWORD 0 */ | |
169 | u8 axgmac0_ue_status; /* DWORD 0 */ | |
170 | u8 axgmac1_ue_status; /* DWORD 0 */ | |
171 | u8 mpu_intpend_ue_status; /* DWORD 0 */ | |
172 | } __packed; | |
173 | struct PCICFG_UE_STATUS_LOW_CSR_AMAP { | |
174 | u32 dw[1]; | |
175 | }; | |
176 | ||
177 | /* Unrecoverable Error Status (High) Register. Each bit corresponds to | |
178 | * an internal Unrecoverable Error. These are set by hardware and may be | |
179 | * cleared by writing a one to the respective bit(s) to be cleared. Any | |
180 | * bit being set that is also unmasked will result in Unrecoverable Error | |
181 | * interrupt notification to the host CPU and/or Server Management chip; | |
182 | * and the transitioning of BladeEngine to an Offline state. | |
183 | */ | |
184 | struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP { | |
185 | u8 jtag_ue_status; /* DWORD 0 */ | |
186 | u8 lpcmemhost_ue_status; /* DWORD 0 */ | |
187 | u8 mgmt_mac_ue_status; /* DWORD 0 */ | |
188 | u8 mpu_iram_ue_status; /* DWORD 0 */ | |
189 | u8 pcs0online_ue_status; /* DWORD 0 */ | |
190 | u8 pcs1online_ue_status; /* DWORD 0 */ | |
191 | u8 pctl0_ue_status; /* DWORD 0 */ | |
192 | u8 pctl1_ue_status; /* DWORD 0 */ | |
193 | u8 pmem_ue_status; /* DWORD 0 */ | |
194 | u8 rr_ue_status; /* DWORD 0 */ | |
195 | u8 rxpp_ue_status; /* DWORD 0 */ | |
196 | u8 txpb_ue_status; /* DWORD 0 */ | |
197 | u8 txp_ue_status; /* DWORD 0 */ | |
198 | u8 xaui_ue_status; /* DWORD 0 */ | |
199 | u8 arm_ue_status; /* DWORD 0 */ | |
200 | u8 ipc_ue_status; /* DWORD 0 */ | |
201 | u8 rsvd0[16]; /* DWORD 0 */ | |
202 | } __packed; | |
203 | struct PCICFG_UE_STATUS_HI_CSR_AMAP { | |
204 | u32 dw[1]; | |
205 | }; | |
206 | ||
207 | /* Unrecoverable Error Mask (Low) Register. Each bit, when set to one, | |
208 | * will mask the associated Unrecoverable Error status bit from notification | |
209 | * of Unrecoverable Error to the host CPU and/or Server Managment chip and the | |
210 | * transitioning of all BladeEngine units to an Offline state. | |
211 | */ | |
212 | struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP { | |
213 | u8 cev_ue_mask; /* DWORD 0 */ | |
214 | u8 ctx_ue_mask; /* DWORD 0 */ | |
215 | u8 dbuf_ue_mask; /* DWORD 0 */ | |
216 | u8 erx_ue_mask; /* DWORD 0 */ | |
217 | u8 host_ue_mask; /* DWORD 0 */ | |
218 | u8 mpu_ue_mask; /* DWORD 0 */ | |
219 | u8 ndma_ue_mask; /* DWORD 0 */ | |
220 | u8 ptc_ue_mask; /* DWORD 0 */ | |
221 | u8 rdma_ue_mask; /* DWORD 0 */ | |
222 | u8 rxf_ue_mask; /* DWORD 0 */ | |
223 | u8 rxips_ue_mask; /* DWORD 0 */ | |
224 | u8 rxulp0_ue_mask; /* DWORD 0 */ | |
225 | u8 rxulp1_ue_mask; /* DWORD 0 */ | |
226 | u8 rxulp2_ue_mask; /* DWORD 0 */ | |
227 | u8 tim_ue_mask; /* DWORD 0 */ | |
228 | u8 tpost_ue_mask; /* DWORD 0 */ | |
229 | u8 tpre_ue_mask; /* DWORD 0 */ | |
230 | u8 txips_ue_mask; /* DWORD 0 */ | |
231 | u8 txulp0_ue_mask; /* DWORD 0 */ | |
232 | u8 txulp1_ue_mask; /* DWORD 0 */ | |
233 | u8 uc_ue_mask; /* DWORD 0 */ | |
234 | u8 wdma_ue_mask; /* DWORD 0 */ | |
235 | u8 txulp2_ue_mask; /* DWORD 0 */ | |
236 | u8 host1_ue_mask; /* DWORD 0 */ | |
237 | u8 p0_ob_link_ue_mask; /* DWORD 0 */ | |
238 | u8 p1_ob_link_ue_mask; /* DWORD 0 */ | |
239 | u8 host_gpio_ue_mask; /* DWORD 0 */ | |
240 | u8 mbox_netw_ue_mask; /* DWORD 0 */ | |
241 | u8 mbox_stor_ue_mask; /* DWORD 0 */ | |
242 | u8 axgmac0_ue_mask; /* DWORD 0 */ | |
243 | u8 axgmac1_ue_mask; /* DWORD 0 */ | |
244 | u8 mpu_intpend_ue_mask; /* DWORD 0 */ | |
245 | } __packed; | |
246 | struct PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP { | |
247 | u32 dw[1]; | |
248 | }; | |
249 | ||
250 | /* Unrecoverable Error Mask (High) Register. Each bit, when set to one, | |
251 | * will mask the associated Unrecoverable Error status bit from notification | |
252 | * of Unrecoverable Error to the host CPU and/or Server Managment chip and the | |
253 | * transitioning of all BladeEngine units to an Offline state. | |
254 | */ | |
255 | struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP { | |
256 | u8 jtag_ue_mask; /* DWORD 0 */ | |
257 | u8 lpcmemhost_ue_mask; /* DWORD 0 */ | |
258 | u8 mgmt_mac_ue_mask; /* DWORD 0 */ | |
259 | u8 mpu_iram_ue_mask; /* DWORD 0 */ | |
260 | u8 pcs0online_ue_mask; /* DWORD 0 */ | |
261 | u8 pcs1online_ue_mask; /* DWORD 0 */ | |
262 | u8 pctl0_ue_mask; /* DWORD 0 */ | |
263 | u8 pctl1_ue_mask; /* DWORD 0 */ | |
264 | u8 pmem_ue_mask; /* DWORD 0 */ | |
265 | u8 rr_ue_mask; /* DWORD 0 */ | |
266 | u8 rxpp_ue_mask; /* DWORD 0 */ | |
267 | u8 txpb_ue_mask; /* DWORD 0 */ | |
268 | u8 txp_ue_mask; /* DWORD 0 */ | |
269 | u8 xaui_ue_mask; /* DWORD 0 */ | |
270 | u8 arm_ue_mask; /* DWORD 0 */ | |
271 | u8 ipc_ue_mask; /* DWORD 0 */ | |
272 | u8 rsvd0[16]; /* DWORD 0 */ | |
273 | } __packed; | |
274 | struct PCICFG_UE_STATUS_HI_MASK_CSR_AMAP { | |
275 | u32 dw[1]; | |
276 | }; | |
277 | ||
278 | /* Online Control Register 0. This register controls various units within | |
279 | * BladeEngine being in an Online or Offline state. | |
280 | */ | |
281 | struct BE_PCICFG_ONLINE0_CSR_AMAP { | |
282 | u8 cev_online; /* DWORD 0 */ | |
283 | u8 ctx_online; /* DWORD 0 */ | |
284 | u8 dbuf_online; /* DWORD 0 */ | |
285 | u8 erx_online; /* DWORD 0 */ | |
286 | u8 host_online; /* DWORD 0 */ | |
287 | u8 mpu_online; /* DWORD 0 */ | |
288 | u8 ndma_online; /* DWORD 0 */ | |
289 | u8 ptc_online; /* DWORD 0 */ | |
290 | u8 rdma_online; /* DWORD 0 */ | |
291 | u8 rxf_online; /* DWORD 0 */ | |
292 | u8 rxips_online; /* DWORD 0 */ | |
293 | u8 rxulp0_online; /* DWORD 0 */ | |
294 | u8 rxulp1_online; /* DWORD 0 */ | |
295 | u8 rxulp2_online; /* DWORD 0 */ | |
296 | u8 tim_online; /* DWORD 0 */ | |
297 | u8 tpost_online; /* DWORD 0 */ | |
298 | u8 tpre_online; /* DWORD 0 */ | |
299 | u8 txips_online; /* DWORD 0 */ | |
300 | u8 txulp0_online; /* DWORD 0 */ | |
301 | u8 txulp1_online; /* DWORD 0 */ | |
302 | u8 uc_online; /* DWORD 0 */ | |
303 | u8 wdma_online; /* DWORD 0 */ | |
304 | u8 txulp2_online; /* DWORD 0 */ | |
305 | u8 host1_online; /* DWORD 0 */ | |
306 | u8 p0_ob_link_online; /* DWORD 0 */ | |
307 | u8 p1_ob_link_online; /* DWORD 0 */ | |
308 | u8 host_gpio_online; /* DWORD 0 */ | |
309 | u8 mbox_netw_online; /* DWORD 0 */ | |
310 | u8 mbox_stor_online; /* DWORD 0 */ | |
311 | u8 axgmac0_online; /* DWORD 0 */ | |
312 | u8 axgmac1_online; /* DWORD 0 */ | |
313 | u8 mpu_intpend_online; /* DWORD 0 */ | |
314 | } __packed; | |
315 | struct PCICFG_ONLINE0_CSR_AMAP { | |
316 | u32 dw[1]; | |
317 | }; | |
318 | ||
319 | /* Online Control Register 1. This register controls various units within | |
320 | * BladeEngine being in an Online or Offline state. | |
321 | */ | |
322 | struct BE_PCICFG_ONLINE1_CSR_AMAP { | |
323 | u8 jtag_online; /* DWORD 0 */ | |
324 | u8 lpcmemhost_online; /* DWORD 0 */ | |
325 | u8 mgmt_mac_online; /* DWORD 0 */ | |
326 | u8 mpu_iram_online; /* DWORD 0 */ | |
327 | u8 pcs0online_online; /* DWORD 0 */ | |
328 | u8 pcs1online_online; /* DWORD 0 */ | |
329 | u8 pctl0_online; /* DWORD 0 */ | |
330 | u8 pctl1_online; /* DWORD 0 */ | |
331 | u8 pmem_online; /* DWORD 0 */ | |
332 | u8 rr_online; /* DWORD 0 */ | |
333 | u8 rxpp_online; /* DWORD 0 */ | |
334 | u8 txpb_online; /* DWORD 0 */ | |
335 | u8 txp_online; /* DWORD 0 */ | |
336 | u8 xaui_online; /* DWORD 0 */ | |
337 | u8 arm_online; /* DWORD 0 */ | |
338 | u8 ipc_online; /* DWORD 0 */ | |
339 | u8 rsvd0[16]; /* DWORD 0 */ | |
340 | } __packed; | |
341 | struct PCICFG_ONLINE1_CSR_AMAP { | |
342 | u32 dw[1]; | |
343 | }; | |
344 | ||
345 | /* Host Timer Register. */ | |
346 | struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP { | |
347 | u8 hosttimer[24]; /* DWORD 0 */ | |
348 | u8 hostintr; /* DWORD 0 */ | |
349 | u8 rsvd0[7]; /* DWORD 0 */ | |
350 | } __packed; | |
351 | struct PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP { | |
352 | u32 dw[1]; | |
353 | }; | |
354 | ||
355 | /* Scratchpad Register (for software use). */ | |
356 | struct BE_PCICFG_SCRATCHPAD_CSR_AMAP { | |
357 | u8 scratchpad[32]; /* DWORD 0 */ | |
358 | } __packed; | |
359 | struct PCICFG_SCRATCHPAD_CSR_AMAP { | |
360 | u32 dw[1]; | |
361 | }; | |
362 | ||
363 | /* PCI Express Capabilities Register. */ | |
364 | struct BE_PCICFG_PCIE_CAP_CSR_AMAP { | |
365 | u8 capid[8]; /* DWORD 0 */ | |
366 | u8 nextcap[8]; /* DWORD 0 */ | |
367 | u8 capver[4]; /* DWORD 0 */ | |
368 | u8 devport[4]; /* DWORD 0 */ | |
369 | u8 rsvd0[6]; /* DWORD 0 */ | |
370 | u8 rsvd1[2]; /* DWORD 0 */ | |
371 | } __packed; | |
372 | struct PCICFG_PCIE_CAP_CSR_AMAP { | |
373 | u32 dw[1]; | |
374 | }; | |
375 | ||
376 | /* PCI Express Device Capabilities Register. */ | |
377 | struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP { | |
378 | u8 payload[3]; /* DWORD 0 */ | |
379 | u8 rsvd0[3]; /* DWORD 0 */ | |
380 | u8 lo_lat[3]; /* DWORD 0 */ | |
381 | u8 l1_lat[3]; /* DWORD 0 */ | |
382 | u8 rsvd1[3]; /* DWORD 0 */ | |
383 | u8 rsvd2[3]; /* DWORD 0 */ | |
384 | u8 pwr_value[8]; /* DWORD 0 */ | |
385 | u8 pwr_scale[2]; /* DWORD 0 */ | |
386 | u8 rsvd3[4]; /* DWORD 0 */ | |
387 | } __packed; | |
388 | struct PCICFG_PCIE_DEVCAP_CSR_AMAP { | |
389 | u32 dw[1]; | |
390 | }; | |
391 | ||
392 | /* PCI Express Device Control/Status Registers. */ | |
393 | struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP { | |
394 | u8 CorrErrReportEn; /* DWORD 0 */ | |
395 | u8 NonFatalErrReportEn; /* DWORD 0 */ | |
396 | u8 FatalErrReportEn; /* DWORD 0 */ | |
397 | u8 UnsuppReqReportEn; /* DWORD 0 */ | |
398 | u8 EnableRelaxOrder; /* DWORD 0 */ | |
399 | u8 Max_Payload_Size[3]; /* DWORD 0 */ | |
400 | u8 ExtendTagFieldEnable; /* DWORD 0 */ | |
401 | u8 PhantomFnEnable; /* DWORD 0 */ | |
402 | u8 AuxPwrPMEnable; /* DWORD 0 */ | |
403 | u8 EnableNoSnoop; /* DWORD 0 */ | |
404 | u8 Max_Read_Req_Size[3]; /* DWORD 0 */ | |
405 | u8 rsvd0; /* DWORD 0 */ | |
406 | u8 CorrErrDetect; /* DWORD 0 */ | |
407 | u8 NonFatalErrDetect; /* DWORD 0 */ | |
408 | u8 FatalErrDetect; /* DWORD 0 */ | |
409 | u8 UnsuppReqDetect; /* DWORD 0 */ | |
410 | u8 AuxPwrDetect; /* DWORD 0 */ | |
411 | u8 TransPending; /* DWORD 0 */ | |
412 | u8 rsvd1[10]; /* DWORD 0 */ | |
413 | } __packed; | |
414 | struct PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP { | |
415 | u32 dw[1]; | |
416 | }; | |
417 | ||
418 | /* PCI Express Link Capabilities Register. */ | |
419 | struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP { | |
420 | u8 MaxLinkSpeed[4]; /* DWORD 0 */ | |
421 | u8 MaxLinkWidth[6]; /* DWORD 0 */ | |
422 | u8 ASPMSupport[2]; /* DWORD 0 */ | |
423 | u8 L0sExitLat[3]; /* DWORD 0 */ | |
424 | u8 L1ExitLat[3]; /* DWORD 0 */ | |
425 | u8 rsvd0[6]; /* DWORD 0 */ | |
426 | u8 PortNum[8]; /* DWORD 0 */ | |
427 | } __packed; | |
428 | struct PCICFG_PCIE_LINK_CAP_CSR_AMAP { | |
429 | u32 dw[1]; | |
430 | }; | |
431 | ||
432 | /* PCI Express Link Status Register. */ | |
433 | struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP { | |
434 | u8 ASPMCtl[2]; /* DWORD 0 */ | |
435 | u8 rsvd0; /* DWORD 0 */ | |
436 | u8 ReadCmplBndry; /* DWORD 0 */ | |
437 | u8 LinkDisable; /* DWORD 0 */ | |
438 | u8 RetrainLink; /* DWORD 0 */ | |
439 | u8 CommonClkConfig; /* DWORD 0 */ | |
440 | u8 ExtendSync; /* DWORD 0 */ | |
441 | u8 rsvd1[8]; /* DWORD 0 */ | |
442 | u8 LinkSpeed[4]; /* DWORD 0 */ | |
443 | u8 NegLinkWidth[6]; /* DWORD 0 */ | |
444 | u8 LinkTrainErr; /* DWORD 0 */ | |
445 | u8 LinkTrain; /* DWORD 0 */ | |
446 | u8 SlotClkConfig; /* DWORD 0 */ | |
447 | u8 rsvd2[3]; /* DWORD 0 */ | |
448 | } __packed; | |
449 | struct PCICFG_PCIE_LINK_STATUS_CSR_AMAP { | |
450 | u32 dw[1]; | |
451 | }; | |
452 | ||
453 | /* PCI Express MSI Configuration Register. */ | |
454 | struct BE_PCICFG_MSI_CSR_AMAP { | |
455 | u8 capid[8]; /* DWORD 0 */ | |
456 | u8 nextptr[8]; /* DWORD 0 */ | |
457 | u8 tablesize[11]; /* DWORD 0 */ | |
458 | u8 rsvd0[3]; /* DWORD 0 */ | |
459 | u8 funcmask; /* DWORD 0 */ | |
460 | u8 en; /* DWORD 0 */ | |
461 | } __packed; | |
462 | struct PCICFG_MSI_CSR_AMAP { | |
463 | u32 dw[1]; | |
464 | }; | |
465 | ||
466 | /* MSI-X Table Offset Register. */ | |
467 | struct BE_PCICFG_MSIX_TABLE_CSR_AMAP { | |
468 | u8 tablebir[3]; /* DWORD 0 */ | |
469 | u8 offset[29]; /* DWORD 0 */ | |
470 | } __packed; | |
471 | struct PCICFG_MSIX_TABLE_CSR_AMAP { | |
472 | u32 dw[1]; | |
473 | }; | |
474 | ||
475 | /* MSI-X PBA Offset Register. */ | |
476 | struct BE_PCICFG_MSIX_PBA_CSR_AMAP { | |
477 | u8 pbabir[3]; /* DWORD 0 */ | |
478 | u8 offset[29]; /* DWORD 0 */ | |
479 | } __packed; | |
480 | struct PCICFG_MSIX_PBA_CSR_AMAP { | |
481 | u32 dw[1]; | |
482 | }; | |
483 | ||
484 | /* PCI Express MSI-X Message Vector Control Register. */ | |
485 | struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP { | |
486 | u8 vector_control; /* DWORD 0 */ | |
487 | u8 rsvd0[31]; /* DWORD 0 */ | |
488 | } __packed; | |
489 | struct PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP { | |
490 | u32 dw[1]; | |
491 | }; | |
492 | ||
493 | /* PCI Express MSI-X Message Data Register. */ | |
494 | struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP { | |
495 | u8 data[16]; /* DWORD 0 */ | |
496 | u8 rsvd0[16]; /* DWORD 0 */ | |
497 | } __packed; | |
498 | struct PCICFG_MSIX_MSG_DATA_CSR_AMAP { | |
499 | u32 dw[1]; | |
500 | }; | |
501 | ||
502 | /* PCI Express MSI-X Message Address Register - High Part. */ | |
503 | struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP { | |
504 | u8 addr[32]; /* DWORD 0 */ | |
505 | } __packed; | |
506 | struct PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP { | |
507 | u32 dw[1]; | |
508 | }; | |
509 | ||
510 | /* PCI Express MSI-X Message Address Register - Low Part. */ | |
511 | struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP { | |
512 | u8 rsvd0[2]; /* DWORD 0 */ | |
513 | u8 addr[30]; /* DWORD 0 */ | |
514 | } __packed; | |
515 | struct PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP { | |
516 | u32 dw[1]; | |
517 | }; | |
518 | ||
519 | struct BE_PCICFG_ANON_18_RSVD_AMAP { | |
520 | u8 rsvd0[32]; /* DWORD 0 */ | |
521 | } __packed; | |
522 | struct PCICFG_ANON_18_RSVD_AMAP { | |
523 | u32 dw[1]; | |
524 | }; | |
525 | ||
526 | struct BE_PCICFG_ANON_19_RSVD_AMAP { | |
527 | u8 rsvd0[32]; /* DWORD 0 */ | |
528 | } __packed; | |
529 | struct PCICFG_ANON_19_RSVD_AMAP { | |
530 | u32 dw[1]; | |
531 | }; | |
532 | ||
533 | struct BE_PCICFG_ANON_20_RSVD_AMAP { | |
534 | u8 rsvd0[32]; /* DWORD 0 */ | |
535 | u8 rsvd1[25][32]; /* DWORD 1 */ | |
536 | } __packed; | |
537 | struct PCICFG_ANON_20_RSVD_AMAP { | |
538 | u32 dw[26]; | |
539 | }; | |
540 | ||
541 | struct BE_PCICFG_ANON_21_RSVD_AMAP { | |
542 | u8 rsvd0[32]; /* DWORD 0 */ | |
543 | u8 rsvd1[1919][32]; /* DWORD 1 */ | |
544 | } __packed; | |
545 | struct PCICFG_ANON_21_RSVD_AMAP { | |
546 | u32 dw[1920]; | |
547 | }; | |
548 | ||
549 | struct BE_PCICFG_ANON_22_MESSAGE_AMAP { | |
550 | struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP vec_ctrl; | |
551 | struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP msg_data; | |
552 | struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP addr_hi; | |
553 | struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP addr_low; | |
554 | } __packed; | |
555 | struct PCICFG_ANON_22_MESSAGE_AMAP { | |
556 | u32 dw[4]; | |
557 | }; | |
558 | ||
559 | struct BE_PCICFG_ANON_23_RSVD_AMAP { | |
560 | u8 rsvd0[32]; /* DWORD 0 */ | |
561 | u8 rsvd1[895][32]; /* DWORD 1 */ | |
562 | } __packed; | |
563 | struct PCICFG_ANON_23_RSVD_AMAP { | |
564 | u32 dw[896]; | |
565 | }; | |
566 | ||
567 | /* These PCI Configuration Space registers are for the Storage Function of | |
568 | * BladeEngine (Function 0). In the memory map of the registers below their | |
569 | * table, | |
570 | */ | |
571 | struct BE_PCICFG0_CSRMAP_AMAP { | |
572 | struct BE_PCICFG_ID_CSR_AMAP id; | |
573 | u8 rsvd0[32]; /* DWORD 1 */ | |
574 | u8 rsvd1[32]; /* DWORD 2 */ | |
575 | u8 rsvd2[32]; /* DWORD 3 */ | |
576 | struct BE_PCICFG_IOBAR_CSR_AMAP iobar; | |
577 | struct BE_PCICFG_MEMBAR0_CSR_AMAP membar0; | |
578 | struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP membar1_lo; | |
579 | struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP membar1_hi; | |
580 | struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP membar2_lo; | |
581 | struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP membar2_hi; | |
582 | u8 rsvd3[32]; /* DWORD 10 */ | |
583 | struct BE_PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP subsystem_id; | |
584 | u8 rsvd4[32]; /* DWORD 12 */ | |
585 | u8 rsvd5[32]; /* DWORD 13 */ | |
586 | u8 rsvd6[32]; /* DWORD 14 */ | |
587 | u8 rsvd7[32]; /* DWORD 15 */ | |
588 | struct BE_PCICFG_SEMAPHORE_CSR_AMAP semaphore[4]; | |
589 | struct BE_PCICFG_SOFT_RESET_CSR_AMAP soft_reset; | |
590 | u8 rsvd8[32]; /* DWORD 21 */ | |
591 | struct BE_PCICFG_SCRATCHPAD_CSR_AMAP scratchpad; | |
592 | u8 rsvd9[32]; /* DWORD 23 */ | |
593 | u8 rsvd10[32]; /* DWORD 24 */ | |
594 | u8 rsvd11[32]; /* DWORD 25 */ | |
595 | u8 rsvd12[32]; /* DWORD 26 */ | |
596 | u8 rsvd13[32]; /* DWORD 27 */ | |
597 | u8 rsvd14[2][32]; /* DWORD 28 */ | |
598 | u8 rsvd15[32]; /* DWORD 30 */ | |
599 | u8 rsvd16[32]; /* DWORD 31 */ | |
600 | u8 rsvd17[8][32]; /* DWORD 32 */ | |
601 | struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP ue_status_low; | |
602 | struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP ue_status_hi; | |
603 | struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP ue_status_low_mask; | |
604 | struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP ue_status_hi_mask; | |
605 | struct BE_PCICFG_ONLINE0_CSR_AMAP online0; | |
606 | struct BE_PCICFG_ONLINE1_CSR_AMAP online1; | |
607 | u8 rsvd18[32]; /* DWORD 46 */ | |
608 | u8 rsvd19[32]; /* DWORD 47 */ | |
609 | u8 rsvd20[32]; /* DWORD 48 */ | |
610 | u8 rsvd21[32]; /* DWORD 49 */ | |
611 | struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP host_timer_int_ctrl; | |
612 | u8 rsvd22[32]; /* DWORD 51 */ | |
613 | struct BE_PCICFG_PCIE_CAP_CSR_AMAP pcie_cap; | |
614 | struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP pcie_devcap; | |
615 | struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP pcie_control_status; | |
616 | struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP pcie_link_cap; | |
617 | struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP pcie_link_status; | |
618 | struct BE_PCICFG_MSI_CSR_AMAP msi; | |
619 | struct BE_PCICFG_MSIX_TABLE_CSR_AMAP msix_table_offset; | |
620 | struct BE_PCICFG_MSIX_PBA_CSR_AMAP msix_pba_offset; | |
621 | u8 rsvd23[32]; /* DWORD 60 */ | |
622 | u8 rsvd24[32]; /* DWORD 61 */ | |
623 | u8 rsvd25[32]; /* DWORD 62 */ | |
624 | u8 rsvd26[32]; /* DWORD 63 */ | |
625 | u8 rsvd27[32]; /* DWORD 64 */ | |
626 | u8 rsvd28[32]; /* DWORD 65 */ | |
627 | u8 rsvd29[32]; /* DWORD 66 */ | |
628 | u8 rsvd30[32]; /* DWORD 67 */ | |
629 | u8 rsvd31[32]; /* DWORD 68 */ | |
630 | u8 rsvd32[32]; /* DWORD 69 */ | |
631 | u8 rsvd33[32]; /* DWORD 70 */ | |
632 | u8 rsvd34[32]; /* DWORD 71 */ | |
633 | u8 rsvd35[32]; /* DWORD 72 */ | |
634 | u8 rsvd36[32]; /* DWORD 73 */ | |
635 | u8 rsvd37[32]; /* DWORD 74 */ | |
636 | u8 rsvd38[32]; /* DWORD 75 */ | |
637 | u8 rsvd39[32]; /* DWORD 76 */ | |
638 | u8 rsvd40[32]; /* DWORD 77 */ | |
639 | u8 rsvd41[32]; /* DWORD 78 */ | |
640 | u8 rsvd42[32]; /* DWORD 79 */ | |
641 | u8 rsvd43[32]; /* DWORD 80 */ | |
642 | u8 rsvd44[32]; /* DWORD 81 */ | |
643 | u8 rsvd45[32]; /* DWORD 82 */ | |
644 | u8 rsvd46[32]; /* DWORD 83 */ | |
645 | u8 rsvd47[32]; /* DWORD 84 */ | |
646 | u8 rsvd48[32]; /* DWORD 85 */ | |
647 | u8 rsvd49[32]; /* DWORD 86 */ | |
648 | u8 rsvd50[32]; /* DWORD 87 */ | |
649 | u8 rsvd51[32]; /* DWORD 88 */ | |
650 | u8 rsvd52[32]; /* DWORD 89 */ | |
651 | u8 rsvd53[32]; /* DWORD 90 */ | |
652 | u8 rsvd54[32]; /* DWORD 91 */ | |
653 | u8 rsvd55[32]; /* DWORD 92 */ | |
654 | u8 rsvd56[832]; /* DWORD 93 */ | |
655 | u8 rsvd57[32]; /* DWORD 119 */ | |
656 | u8 rsvd58[32]; /* DWORD 120 */ | |
657 | u8 rsvd59[32]; /* DWORD 121 */ | |
658 | u8 rsvd60[32]; /* DWORD 122 */ | |
659 | u8 rsvd61[32]; /* DWORD 123 */ | |
660 | u8 rsvd62[32]; /* DWORD 124 */ | |
661 | u8 rsvd63[32]; /* DWORD 125 */ | |
662 | u8 rsvd64[32]; /* DWORD 126 */ | |
663 | u8 rsvd65[32]; /* DWORD 127 */ | |
664 | u8 rsvd66[61440]; /* DWORD 128 */ | |
665 | struct BE_PCICFG_ANON_22_MESSAGE_AMAP message[32]; | |
666 | u8 rsvd67[28672]; /* DWORD 2176 */ | |
667 | u8 rsvd68[32]; /* DWORD 3072 */ | |
668 | u8 rsvd69[1023][32]; /* DWORD 3073 */ | |
669 | } __packed; | |
670 | struct PCICFG0_CSRMAP_AMAP { | |
671 | u32 dw[4096]; | |
672 | }; | |
673 | ||
674 | struct BE_PCICFG_ANON_24_RSVD_AMAP { | |
675 | u8 rsvd0[32]; /* DWORD 0 */ | |
676 | } __packed; | |
677 | struct PCICFG_ANON_24_RSVD_AMAP { | |
678 | u32 dw[1]; | |
679 | }; | |
680 | ||
681 | struct BE_PCICFG_ANON_25_RSVD_AMAP { | |
682 | u8 rsvd0[32]; /* DWORD 0 */ | |
683 | } __packed; | |
684 | struct PCICFG_ANON_25_RSVD_AMAP { | |
685 | u32 dw[1]; | |
686 | }; | |
687 | ||
688 | struct BE_PCICFG_ANON_26_RSVD_AMAP { | |
689 | u8 rsvd0[32]; /* DWORD 0 */ | |
690 | } __packed; | |
691 | struct PCICFG_ANON_26_RSVD_AMAP { | |
692 | u32 dw[1]; | |
693 | }; | |
694 | ||
695 | struct BE_PCICFG_ANON_27_RSVD_AMAP { | |
696 | u8 rsvd0[32]; /* DWORD 0 */ | |
697 | u8 rsvd1[32]; /* DWORD 1 */ | |
698 | } __packed; | |
699 | struct PCICFG_ANON_27_RSVD_AMAP { | |
700 | u32 dw[2]; | |
701 | }; | |
702 | ||
703 | struct BE_PCICFG_ANON_28_RSVD_AMAP { | |
704 | u8 rsvd0[32]; /* DWORD 0 */ | |
705 | u8 rsvd1[3][32]; /* DWORD 1 */ | |
706 | } __packed; | |
707 | struct PCICFG_ANON_28_RSVD_AMAP { | |
708 | u32 dw[4]; | |
709 | }; | |
710 | ||
711 | struct BE_PCICFG_ANON_29_RSVD_AMAP { | |
712 | u8 rsvd0[32]; /* DWORD 0 */ | |
713 | u8 rsvd1[36][32]; /* DWORD 1 */ | |
714 | } __packed; | |
715 | struct PCICFG_ANON_29_RSVD_AMAP { | |
716 | u32 dw[37]; | |
717 | }; | |
718 | ||
719 | struct BE_PCICFG_ANON_30_RSVD_AMAP { | |
720 | u8 rsvd0[32]; /* DWORD 0 */ | |
721 | u8 rsvd1[1930][32]; /* DWORD 1 */ | |
722 | } __packed; | |
723 | struct PCICFG_ANON_30_RSVD_AMAP { | |
724 | u32 dw[1931]; | |
725 | }; | |
726 | ||
727 | struct BE_PCICFG_ANON_31_MESSAGE_AMAP { | |
728 | struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP vec_ctrl; | |
729 | struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP msg_data; | |
730 | struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP addr_hi; | |
731 | struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP addr_low; | |
732 | } __packed; | |
733 | struct PCICFG_ANON_31_MESSAGE_AMAP { | |
734 | u32 dw[4]; | |
735 | }; | |
736 | ||
737 | struct BE_PCICFG_ANON_32_RSVD_AMAP { | |
738 | u8 rsvd0[32]; /* DWORD 0 */ | |
739 | u8 rsvd1[895][32]; /* DWORD 1 */ | |
740 | } __packed; | |
741 | struct PCICFG_ANON_32_RSVD_AMAP { | |
742 | u32 dw[896]; | |
743 | }; | |
744 | ||
745 | /* This PCI configuration space register map is for the Networking Function of | |
746 | * BladeEngine (Function 1). | |
747 | */ | |
748 | struct BE_PCICFG1_CSRMAP_AMAP { | |
749 | struct BE_PCICFG_ID_CSR_AMAP id; | |
750 | u8 rsvd0[32]; /* DWORD 1 */ | |
751 | u8 rsvd1[32]; /* DWORD 2 */ | |
752 | u8 rsvd2[32]; /* DWORD 3 */ | |
753 | struct BE_PCICFG_IOBAR_CSR_AMAP iobar; | |
754 | struct BE_PCICFG_MEMBAR0_CSR_AMAP membar0; | |
755 | struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP membar1_lo; | |
756 | struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP membar1_hi; | |
757 | struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP membar2_lo; | |
758 | struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP membar2_hi; | |
759 | u8 rsvd3[32]; /* DWORD 10 */ | |
760 | struct BE_PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP subsystem_id; | |
761 | u8 rsvd4[32]; /* DWORD 12 */ | |
762 | u8 rsvd5[32]; /* DWORD 13 */ | |
763 | u8 rsvd6[32]; /* DWORD 14 */ | |
764 | u8 rsvd7[32]; /* DWORD 15 */ | |
765 | struct BE_PCICFG_SEMAPHORE_CSR_AMAP semaphore[4]; | |
766 | struct BE_PCICFG_SOFT_RESET_CSR_AMAP soft_reset; | |
767 | u8 rsvd8[32]; /* DWORD 21 */ | |
768 | struct BE_PCICFG_SCRATCHPAD_CSR_AMAP scratchpad; | |
769 | u8 rsvd9[32]; /* DWORD 23 */ | |
770 | u8 rsvd10[32]; /* DWORD 24 */ | |
771 | u8 rsvd11[32]; /* DWORD 25 */ | |
772 | u8 rsvd12[32]; /* DWORD 26 */ | |
773 | u8 rsvd13[32]; /* DWORD 27 */ | |
774 | u8 rsvd14[2][32]; /* DWORD 28 */ | |
775 | u8 rsvd15[32]; /* DWORD 30 */ | |
776 | u8 rsvd16[32]; /* DWORD 31 */ | |
777 | u8 rsvd17[8][32]; /* DWORD 32 */ | |
778 | struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP ue_status_low; | |
779 | struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP ue_status_hi; | |
780 | struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP ue_status_low_mask; | |
781 | struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP ue_status_hi_mask; | |
782 | struct BE_PCICFG_ONLINE0_CSR_AMAP online0; | |
783 | struct BE_PCICFG_ONLINE1_CSR_AMAP online1; | |
784 | u8 rsvd18[32]; /* DWORD 46 */ | |
785 | u8 rsvd19[32]; /* DWORD 47 */ | |
786 | u8 rsvd20[32]; /* DWORD 48 */ | |
787 | u8 rsvd21[32]; /* DWORD 49 */ | |
788 | struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP host_timer_int_ctrl; | |
789 | u8 rsvd22[32]; /* DWORD 51 */ | |
790 | struct BE_PCICFG_PCIE_CAP_CSR_AMAP pcie_cap; | |
791 | struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP pcie_devcap; | |
792 | struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP pcie_control_status; | |
793 | struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP pcie_link_cap; | |
794 | struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP pcie_link_status; | |
795 | struct BE_PCICFG_MSI_CSR_AMAP msi; | |
796 | struct BE_PCICFG_MSIX_TABLE_CSR_AMAP msix_table_offset; | |
797 | struct BE_PCICFG_MSIX_PBA_CSR_AMAP msix_pba_offset; | |
798 | u8 rsvd23[64]; /* DWORD 60 */ | |
799 | u8 rsvd24[32]; /* DWORD 62 */ | |
800 | u8 rsvd25[32]; /* DWORD 63 */ | |
801 | u8 rsvd26[32]; /* DWORD 64 */ | |
802 | u8 rsvd27[32]; /* DWORD 65 */ | |
803 | u8 rsvd28[32]; /* DWORD 66 */ | |
804 | u8 rsvd29[32]; /* DWORD 67 */ | |
805 | u8 rsvd30[32]; /* DWORD 68 */ | |
806 | u8 rsvd31[32]; /* DWORD 69 */ | |
807 | u8 rsvd32[32]; /* DWORD 70 */ | |
808 | u8 rsvd33[32]; /* DWORD 71 */ | |
809 | u8 rsvd34[32]; /* DWORD 72 */ | |
810 | u8 rsvd35[32]; /* DWORD 73 */ | |
811 | u8 rsvd36[32]; /* DWORD 74 */ | |
812 | u8 rsvd37[128]; /* DWORD 75 */ | |
813 | u8 rsvd38[32]; /* DWORD 79 */ | |
814 | u8 rsvd39[1184]; /* DWORD 80 */ | |
815 | u8 rsvd40[61792]; /* DWORD 117 */ | |
816 | struct BE_PCICFG_ANON_31_MESSAGE_AMAP message[32]; | |
817 | u8 rsvd41[28672]; /* DWORD 2176 */ | |
818 | u8 rsvd42[32]; /* DWORD 3072 */ | |
819 | u8 rsvd43[1023][32]; /* DWORD 3073 */ | |
820 | } __packed; | |
821 | struct PCICFG1_CSRMAP_AMAP { | |
822 | u32 dw[4096]; | |
823 | }; | |
824 | ||
825 | #endif /* __pcicfg_amap_h__ */ |