[mirror_ubuntu-bionic-kernel.git] / drivers / staging / brcm80211 / include / bcmdefs.h

/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef	_bcmdefs_h_
#define	_bcmdefs_h_

#define	SI_BUS			0
#define	PCI_BUS			1
#define	PCMCIA_BUS		2
#define SDIO_BUS		3
#define JTAG_BUS		4
#define USB_BUS			5
#define SPI_BUS			6


#ifndef OFF
#define	OFF	0
#endif

#ifndef ON
#define	ON	1		/* ON = 1 */
#endif

#define	AUTO	(-1)		/* Auto = -1 */

#ifdef mips
#define BCMFASTPATH		__attribute__ ((__section__(".text.fastpath")))
#else
#define BCMFASTPATH
#endif

/* Bus types */
#define	SI_BUS			0	/* SOC Interconnect */
#define	PCI_BUS			1	/* PCI target */
#define SDIO_BUS		3	/* SDIO target */
#define JTAG_BUS		4	/* JTAG */
#define USB_BUS			5	/* USB (does not support R/W REG) */
#define SPI_BUS			6	/* gSPI target */
#define RPC_BUS			7	/* RPC target */

#define CHIPTYPE(bus) 	(bus)
#define CHIPID(chip)	(chip)
#define CHIPREV(rev)	(rev)

/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
#define DMADDR_MASK_32 0x0	/* Address mask for 32-bits */
#define DMADDR_MASK_30 0xc0000000	/* Address mask for 30-bits */
#define DMADDR_MASK_0  0xffffffff	/* Address mask for 0-bits (hi-part) */

#define	DMADDRWIDTH_30  30	/* 30-bit addressing capability */
#define	DMADDRWIDTH_32  32	/* 32-bit addressing capability */
#define	DMADDRWIDTH_63  63	/* 64-bit addressing capability */
#define	DMADDRWIDTH_64  64	/* 64-bit addressing capability */

#ifdef BCMDMA64OSL
typedef struct {
	u32 loaddr;
	u32 hiaddr;
} dma64addr_t;

typedef dma64addr_t dmaaddr_t;
#define PHYSADDRHI(_pa) ((_pa).hiaddr)
#define PHYSADDRHISET(_pa, _val) \
	do { \
		(_pa).hiaddr = (_val);		\
	} while (0)
#define PHYSADDRLO(_pa) ((_pa).loaddr)
#define PHYSADDRLOSET(_pa, _val) \
	do { \
		(_pa).loaddr = (_val);		\
	} while (0)

#else
typedef unsigned long dmaaddr_t;
#define PHYSADDRHI(_pa) (0)
#define PHYSADDRHISET(_pa, _val)
#define PHYSADDRLO(_pa) ((_pa))
#define PHYSADDRLOSET(_pa, _val) \
	do { \
		(_pa) = (_val);			\
	} while (0)
#endif				/* BCMDMA64OSL */

/* One physical DMA segment */
typedef struct {
	dmaaddr_t addr;
	u32 length;
} hnddma_seg_t;

#define MAX_DMA_SEGS 4

typedef struct {
	void *oshdmah;		/* Opaque handle for OSL to store its information */
	uint origsize;		/* Size of the virtual packet */
	uint nsegs;
	hnddma_seg_t segs[MAX_DMA_SEGS];
} hnddma_seg_map_t;

/* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
 * By doing, we avoid the need  to allocate an extra buffer for the header when bridging to WL.
 * There is a compile time check in wlc.c which ensure that this value is at least as big
 * as TXOFF. This value is used in dma_rxfill (hnddma.c).
 */

#define BCMEXTRAHDROOM 172

#ifdef BCMDBG
#ifndef BCMDBG_ASSERT
#define BCMDBG_ASSERT
#endif	/* BCMDBG_ASSERT */
#endif	/* BCMDBG */

/* Macros for doing definition and get/set of bitfields
 * Usage example, e.g. a three-bit field (bits 4-6):
 *    #define <NAME>_M	BITFIELD_MASK(3)
 *    #define <NAME>_S	4
 * ...
 *    regval = R_REG(osh, &regs->regfoo);
 *    field = GFIELD(regval, <NAME>);
 *    regval = SFIELD(regval, <NAME>, 1);
 *    W_REG(osh, &regs->regfoo, regval);
 */
#define BITFIELD_MASK(width) \
		(((unsigned)1 << (width)) - 1)
#define GFIELD(val, field) \
		(((val) >> field ## _S) & field ## _M)
#define SFIELD(val, field, bits) \
		(((val) & (~(field ## _M << field ## _S))) | \
		 ((unsigned)(bits) << field ## _S))

/* Max. nvram variable table size */
#define	MAXSZ_NVRAM_VARS	4096

#endif				/* _bcmdefs_h_ */
Commit	Line	Data
a9533e7e HP	1	/*
	2	* Copyright (c) 2010 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
	17	#ifndef _bcmdefs_h_
	18	#define _bcmdefs_h_
	19
cf2b4488 HP	20	#define SI_BUS 0
	21	#define PCI_BUS 1
	22	#define PCMCIA_BUS 2
	23	#define SDIO_BUS 3
	24	#define JTAG_BUS 4
	25	#define USB_BUS 5
	26	#define SPI_BUS 6
a1c16ed2 GKH	27
	28
	29	#ifndef OFF
	30	#define OFF 0
	31	#endif
	32
	33	#ifndef ON
	34	#define ON 1 /* ON = 1 */
	35	#endif
	36
	37	#define AUTO (-1) /* Auto = -1 */
a9533e7e	38
a9533e7e HP	39	#ifdef mips
	40	#define BCMFASTPATH __attribute__ ((__section__(".text.fastpath")))
	41	#else
	42	#define BCMFASTPATH
	43	#endif
	44
a9533e7e HP	45	/* Bus types */
	46	#define SI_BUS 0 /* SOC Interconnect */
	47	#define PCI_BUS 1 /* PCI target */
	48	#define SDIO_BUS 3 /* SDIO target */
	49	#define JTAG_BUS 4 /* JTAG */
	50	#define USB_BUS 5 /* USB (does not support R/W REG) */
	51	#define SPI_BUS 6 /* gSPI target */
	52	#define RPC_BUS 7 /* RPC target */
	53
a9533e7e	54	#define CHIPTYPE(bus) (bus)
a9533e7e	55	#define CHIPID(chip) (chip)
a9533e7e	56	#define CHIPREV(rev) (rev)
a9533e7e HP	57
	58	/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
	59	#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
	60	#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
	61	#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
	62
	63	#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
	64	#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
	65	#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
	66	#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
	67
	68	#ifdef BCMDMA64OSL
	69	typedef struct {
66cbd3ab GKH	70	u32 loaddr;
66cbd3ab GKH	71	u32 hiaddr;
a9533e7e HP	72	} dma64addr_t;
	73
	74	typedef dma64addr_t dmaaddr_t;
	75	#define PHYSADDRHI(_pa) ((_pa).hiaddr)
	76	#define PHYSADDRHISET(_pa, _val) \
	77	do { \
	78	(_pa).hiaddr = (_val); \
	79	} while (0)
	80	#define PHYSADDRLO(_pa) ((_pa).loaddr)
	81	#define PHYSADDRLOSET(_pa, _val) \
	82	do { \
	83	(_pa).loaddr = (_val); \
	84	} while (0)
	85
	86	#else
	87	typedef unsigned long dmaaddr_t;
	88	#define PHYSADDRHI(_pa) (0)
	89	#define PHYSADDRHISET(_pa, _val)
	90	#define PHYSADDRLO(_pa) ((_pa))
	91	#define PHYSADDRLOSET(_pa, _val) \
	92	do { \
	93	(_pa) = (_val); \
	94	} while (0)
	95	#endif /* BCMDMA64OSL */
	96
	97	/* One physical DMA segment */
	98	typedef struct {
	99	dmaaddr_t addr;
66cbd3ab	100	u32 length;
a9533e7e HP	101	} hnddma_seg_t;
	102
	103	#define MAX_DMA_SEGS 4
	104
	105	typedef struct {
	106	void oshdmah; / Opaque handle for OSL to store its information */
	107	uint origsize; /* Size of the virtual packet */
	108	uint nsegs;
	109	hnddma_seg_t segs[MAX_DMA_SEGS];
	110	} hnddma_seg_map_t;
	111
	112	/* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
	113	* By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
	114	* There is a compile time check in wlc.c which ensure that this value is at least as big
	115	* as TXOFF. This value is used in dma_rxfill (hnddma.c).
	116	*/
	117
	118	#define BCMEXTRAHDROOM 172
	119
a9533e7e	120	#ifdef BCMDBG
a9533e7e HP	121	#ifndef BCMDBG_ASSERT
a9533e7e HP	122	#define BCMDBG_ASSERT
53b6b34d BR	123	#endif /* BCMDBG_ASSERT */
53b6b34d BR	124	#endif /* BCMDBG */
a9533e7e HP	125
	126	/* Macros for doing definition and get/set of bitfields
	127	* Usage example, e.g. a three-bit field (bits 4-6):
	128	* #define <NAME>_M BITFIELD_MASK(3)
	129	* #define <NAME>_S 4
	130	* ...
	131	* regval = R_REG(osh, &regs->regfoo);
	132	* field = GFIELD(regval, <NAME>);
	133	* regval = SFIELD(regval, <NAME>, 1);
	134	* W_REG(osh, &regs->regfoo, regval);
	135	*/
	136	#define BITFIELD_MASK(width) \
	137	(((unsigned)1 << (width)) - 1)
	138	#define GFIELD(val, field) \
	139	(((val) >> field ## _S) & field ## _M)
	140	#define SFIELD(val, field, bits) \
	141	(((val) & (~(field ## _M << field ## _S))) \| \
	142	((unsigned)(bits) << field ## _S))
	143
a9533e7e HP	144	/* Max. nvram variable table size */
	145	#define MAXSZ_NVRAM_VARS 4096
	146
a9533e7e	147	#endif /* _bcmdefs_h_ */