[mirror_ubuntu-bionic-kernel.git] / drivers / staging / brcm80211 / util / aiutils.c

/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/delay.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <bcmdefs.h>
#ifdef BRCM_FULLMAC
#include <linux/netdevice.h>
#endif
#include <osl.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <bcmutils.h>
#include <siutils.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <bcmdevs.h>

#define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \
		(CHIPREV(sih->chiprev) == 0) && \
		(sii->coreid[sii->curidx] == MIPS74K_CORE_ID))

/* EROM parsing */

static u32
get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
{
	u32 ent;
	uint inv = 0, nom = 0;

	while (true) {
		ent = R_REG(si_osh(sih), *eromptr);
		(*eromptr)++;

		if (mask == 0)
			break;

		if ((ent & ER_VALID) == 0) {
			inv++;
			continue;
		}

		if (ent == (ER_END | ER_VALID))
			break;

		if ((ent & mask) == match)
			break;

		nom++;
	}

	SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
	if (inv + nom) {
		SI_VMSG(("  after %d invalid and %d non-matching entries\n",
			 inv, nom));
	}
	return ent;
}

static u32
get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
	u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
{
	u32 asd, sz, szd;

	asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
	if (((asd & ER_TAG1) != ER_ADD) ||
	    (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
	    ((asd & AD_ST_MASK) != st)) {
		/* This is not what we want, "push" it back */
		(*eromptr)--;
		return 0;
	}
	*addrl = asd & AD_ADDR_MASK;
	if (asd & AD_AG32)
		*addrh = get_erom_ent(sih, eromptr, 0, 0);
	else
		*addrh = 0;
	*sizeh = 0;
	sz = asd & AD_SZ_MASK;
	if (sz == AD_SZ_SZD) {
		szd = get_erom_ent(sih, eromptr, 0, 0);
		*sizel = szd & SD_SZ_MASK;
		if (szd & SD_SG32)
			*sizeh = get_erom_ent(sih, eromptr, 0, 0);
	} else
		*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);

	SI_VMSG(("  SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
		 sp, ad, st, *sizeh, *sizel, *addrh, *addrl));

	return asd;
}

static void ai_hwfixup(si_info_t *sii)
{
}

/* parse the enumeration rom to identify all cores */
void ai_scan(si_t *sih, void *regs, uint devid)
{
	si_info_t *sii = SI_INFO(sih);
	chipcregs_t *cc = (chipcregs_t *) regs;
	u32 erombase, *eromptr, *eromlim;

	erombase = R_REG(sii->osh, &cc->eromptr);

	switch (sih->bustype) {
	case SI_BUS:
		eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
		break;

	case PCI_BUS:
		/* Set wrappers address */
		sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);

		/* Now point the window at the erom */
		pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, erombase);
		eromptr = regs;
		break;

#ifdef BCMSDIO
	case SPI_BUS:
	case SDIO_BUS:
#endif				/* BCMSDIO */
		eromptr = (u32 *)(unsigned long)erombase;
		break;

	default:
		SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
			  sih->bustype));
		ASSERT(0);
		return;
	}
	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));

	SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
	while (eromptr < eromlim) {
		u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
		u32 mpd, asd, addrl, addrh, sizel, sizeh;
		u32 *base;
		uint i, j, idx;
		bool br;

		br = false;

		/* Grok a component */
		cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
		if (cia == (ER_END | ER_VALID)) {
			SI_VMSG(("Found END of erom after %d cores\n",
				 sii->numcores));
			ai_hwfixup(sii);
			return;
		}
		base = eromptr - 1;
		cib = get_erom_ent(sih, &eromptr, 0, 0);

		if ((cib & ER_TAG) != ER_CI) {
			SI_ERROR(("CIA not followed by CIB\n"));
			goto error;
		}

		cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
		mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
		crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
		nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
		nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
		nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
		nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;

		SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));

		if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
			continue;
		if ((nmw + nsw == 0)) {
			/* A component which is not a core */
			if (cid == OOB_ROUTER_CORE_ID) {
				asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
					      &addrl, &addrh, &sizel, &sizeh);
				if (asd != 0) {
					sii->oob_router = addrl;
				}
			}
			continue;
		}

		idx = sii->numcores;
/*		sii->eromptr[idx] = base; */
		sii->cia[idx] = cia;
		sii->cib[idx] = cib;
		sii->coreid[idx] = cid;

		for (i = 0; i < nmp; i++) {
			mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
			if ((mpd & ER_TAG) != ER_MP) {
				SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
				goto error;
			}
			SI_VMSG(("  Master port %d, mp: %d id: %d\n", i,
				 (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
				 (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
		}

		/* First Slave Address Descriptor should be port 0:
		 * the main register space for the core
		 */
		asd =
		    get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
			    &sizel, &sizeh);
		if (asd == 0) {
			/* Try again to see if it is a bridge */
			asd =
			    get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
				    &addrh, &sizel, &sizeh);
			if (asd != 0)
				br = true;
			else if ((addrh != 0) || (sizeh != 0)
				 || (sizel != SI_CORE_SIZE)) {
				SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
				goto error;
			}
		}
		sii->coresba[idx] = addrl;
		sii->coresba_size[idx] = sizel;
		/* Get any more ASDs in port 0 */
		j = 1;
		do {
			asd =
			    get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
				    &addrh, &sizel, &sizeh);
			if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
				sii->coresba2[idx] = addrl;
				sii->coresba2_size[idx] = sizel;
			}
			j++;
		} while (asd != 0);

		/* Go through the ASDs for other slave ports */
		for (i = 1; i < nsp; i++) {
			j = 0;
			do {
				asd =
				    get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
					    &addrl, &addrh, &sizel, &sizeh);
			} while (asd != 0);
			if (j == 0) {
				SI_ERROR((" SP %d has no address descriptors\n",
					  i));
				goto error;
			}
		}

		/* Now get master wrappers */
		for (i = 0; i < nmw; i++) {
			asd =
			    get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
				    &addrh, &sizel, &sizeh);
			if (asd == 0) {
				SI_ERROR(("Missing descriptor for MW %d\n", i));
				goto error;
			}
			if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
				SI_ERROR(("Master wrapper %d is not 4KB\n", i));
				goto error;
			}
			if (i == 0)
				sii->wrapba[idx] = addrl;
		}

		/* And finally slave wrappers */
		for (i = 0; i < nsw; i++) {
			uint fwp = (nsp == 1) ? 0 : 1;
			asd =
			    get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
				    &addrl, &addrh, &sizel, &sizeh);
			if (asd == 0) {
				SI_ERROR(("Missing descriptor for SW %d\n", i));
				goto error;
			}
			if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
				SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
				goto error;
			}
			if ((nmw == 0) && (i == 0))
				sii->wrapba[idx] = addrl;
		}

		/* Don't record bridges */
		if (br)
			continue;

		/* Done with core */
		sii->numcores++;
	}

	SI_ERROR(("Reached end of erom without finding END"));

 error:
	sii->numcores = 0;
	return;
}

/* This function changes the logical "focus" to the indicated core.
 * Return the current core's virtual address.
 */
void *ai_setcoreidx(si_t *sih, uint coreidx)
{
	si_info_t *sii = SI_INFO(sih);
	u32 addr = sii->coresba[coreidx];
	u32 wrap = sii->wrapba[coreidx];
	void *regs;

	if (coreidx >= sii->numcores)
		return NULL;

	/*
	 * If the user has provided an interrupt mask enabled function,
	 * then assert interrupts are disabled before switching the core.
	 */
	ASSERT((sii->intrsenabled_fn == NULL)
	       || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));

	switch (sih->bustype) {
	case SI_BUS:
		/* map new one */
		if (!sii->regs[coreidx]) {
			sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
			ASSERT(GOODREGS(sii->regs[coreidx]));
		}
		sii->curmap = regs = sii->regs[coreidx];
		if (!sii->wrappers[coreidx]) {
			sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
			ASSERT(GOODREGS(sii->wrappers[coreidx]));
		}
		sii->curwrap = sii->wrappers[coreidx];
		break;

	case PCI_BUS:
		/* point bar0 window */
		pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, addr);
		regs = sii->curmap;
		/* point bar0 2nd 4KB window */
		pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN2, wrap);
		break;

#ifdef BCMSDIO
	case SPI_BUS:
	case SDIO_BUS:
#endif				/* BCMSDIO */
		sii->curmap = regs = (void *)(unsigned long)addr;
		sii->curwrap = (void *)(unsigned long)wrap;
		break;

	default:
		ASSERT(0);
		regs = NULL;
		break;
	}

	sii->curmap = regs;
	sii->curidx = coreidx;

	return regs;
}

/* Return the number of address spaces in current core */
int ai_numaddrspaces(si_t *sih)
{
	return 2;
}

/* Return the address of the nth address space in the current core */
u32 ai_addrspace(si_t *sih, uint asidx)
{
	si_info_t *sii;
	uint cidx;

	sii = SI_INFO(sih);
	cidx = sii->curidx;

	if (asidx == 0)
		return sii->coresba[cidx];
	else if (asidx == 1)
		return sii->coresba2[cidx];
	else {
		SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
		return 0;
	}
}

/* Return the size of the nth address space in the current core */
u32 ai_addrspacesize(si_t *sih, uint asidx)
{
	si_info_t *sii;
	uint cidx;

	sii = SI_INFO(sih);
	cidx = sii->curidx;

	if (asidx == 0)
		return sii->coresba_size[cidx];
	else if (asidx == 1)
		return sii->coresba2_size[cidx];
	else {
		SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
		return 0;
	}
}

uint ai_flag(si_t *sih)
{
	si_info_t *sii;
	aidmp_t *ai;

	sii = SI_INFO(sih);
	if (BCM47162_DMP()) {
		SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
		return sii->curidx;
	}
	ai = sii->curwrap;

	return R_REG(sii->osh, &ai->oobselouta30) & 0x1f;
}

void ai_setint(si_t *sih, int siflag)
{
}

void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
{
	si_info_t *sii = SI_INFO(sih);
	u32 *w = (u32 *) sii->curwrap;
	W_REG(sii->osh, w + (offset / 4), val);
	return;
}

uint ai_corevendor(si_t *sih)
{
	si_info_t *sii;
	u32 cia;

	sii = SI_INFO(sih);
	cia = sii->cia[sii->curidx];
	return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
}

uint ai_corerev(si_t *sih)
{
	si_info_t *sii;
	u32 cib;

	sii = SI_INFO(sih);
	cib = sii->cib[sii->curidx];
	return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
}

bool ai_iscoreup(si_t *sih)
{
	si_info_t *sii;
	aidmp_t *ai;

	sii = SI_INFO(sih);
	ai = sii->curwrap;

	return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
		 SICF_CLOCK_EN)
		&& ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
}

/*
 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
 * switch back to the original core, and return the new value.
 *
 * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
 *
 * Also, when using pci/pcie, we can optimize away the core switching for pci registers
 * and (on newer pci cores) chipcommon registers.
 */
uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
	uint origidx = 0;
	u32 *r = NULL;
	uint w;
	uint intr_val = 0;
	bool fast = false;
	si_info_t *sii;

	sii = SI_INFO(sih);

	ASSERT(GOODIDX(coreidx));
	ASSERT(regoff < SI_CORE_SIZE);
	ASSERT((val & ~mask) == 0);

	if (coreidx >= SI_MAXCORES)
		return 0;

	if (sih->bustype == SI_BUS) {
		/* If internal bus, we can always get at everything */
		fast = true;
		/* map if does not exist */
		if (!sii->regs[coreidx]) {
			sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
						     SI_CORE_SIZE);
			ASSERT(GOODREGS(sii->regs[coreidx]));
		}
		r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
	} else if (sih->bustype == PCI_BUS) {
		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */

		if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
			/* Chipc registers are mapped at 12KB */

			fast = true;
			r = (u32 *) ((char *)sii->curmap +
					PCI_16KB0_CCREGS_OFFSET + regoff);
		} else if (sii->pub.buscoreidx == coreidx) {
			/* pci registers are at either in the last 2KB of an 8KB window
			 * or, in pcie and pci rev 13 at 8KB
			 */
			fast = true;
			if (SI_FAST(sii))
				r = (u32 *) ((char *)sii->curmap +
						PCI_16KB0_PCIREGS_OFFSET +
						regoff);
			else
				r = (u32 *) ((char *)sii->curmap +
						((regoff >= SBCONFIGOFF) ?
						 PCI_BAR0_PCISBR_OFFSET :
						 PCI_BAR0_PCIREGS_OFFSET) +
						regoff);
		}
	}

	if (!fast) {
		INTR_OFF(sii, intr_val);

		/* save current core index */
		origidx = si_coreidx(&sii->pub);

		/* switch core */
		r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
				regoff);
	}
	ASSERT(r != NULL);

	/* mask and set */
	if (mask || val) {
		w = (R_REG(sii->osh, r) & ~mask) | val;
		W_REG(sii->osh, r, w);
	}

	/* readback */
	w = R_REG(sii->osh, r);

	if (!fast) {
		/* restore core index */
		if (origidx != coreidx)
			ai_setcoreidx(&sii->pub, origidx);

		INTR_RESTORE(sii, intr_val);
	}

	return w;
}

void ai_core_disable(si_t *sih, u32 bits)
{
	si_info_t *sii;
	volatile u32 dummy;
	aidmp_t *ai;

	sii = SI_INFO(sih);

	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	/* if core is already in reset, just return */
	if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
		return;

	W_REG(sii->osh, &ai->ioctrl, bits);
	dummy = R_REG(sii->osh, &ai->ioctrl);
	udelay(10);

	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
	udelay(1);
}

/* reset and re-enable a core
 * inputs:
 * bits - core specific bits that are set during and after reset sequence
 * resetbits - core specific bits that are set only during reset sequence
 */
void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
{
	si_info_t *sii;
	aidmp_t *ai;
	volatile u32 dummy;

	sii = SI_INFO(sih);
	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	/*
	 * Must do the disable sequence first to work for arbitrary current core state.
	 */
	ai_core_disable(sih, (bits | resetbits));

	/*
	 * Now do the initialization sequence.
	 */
	W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
	dummy = R_REG(sii->osh, &ai->ioctrl);
	W_REG(sii->osh, &ai->resetctrl, 0);
	udelay(1);

	W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
	dummy = R_REG(sii->osh, &ai->ioctrl);
	udelay(1);
}

void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
{
	si_info_t *sii;
	aidmp_t *ai;
	u32 w;

	sii = SI_INFO(sih);

	if (BCM47162_DMP()) {
		SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
			  __func__));
		return;
	}

	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	ASSERT((val & ~mask) == 0);

	if (mask || val) {
		w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
		W_REG(sii->osh, &ai->ioctrl, w);
	}
}

u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
{
	si_info_t *sii;
	aidmp_t *ai;
	u32 w;

	sii = SI_INFO(sih);
	if (BCM47162_DMP()) {
		SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
			  __func__));
		return 0;
	}

	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	ASSERT((val & ~mask) == 0);

	if (mask || val) {
		w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
		W_REG(sii->osh, &ai->ioctrl, w);
	}

	return R_REG(sii->osh, &ai->ioctrl);
}

u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
{
	si_info_t *sii;
	aidmp_t *ai;
	u32 w;

	sii = SI_INFO(sih);
	if (BCM47162_DMP()) {
		SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
		return 0;
	}

	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	ASSERT((val & ~mask) == 0);
	ASSERT((mask & ~SISF_CORE_BITS) == 0);

	if (mask || val) {
		w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
		W_REG(sii->osh, &ai->iostatus, w);
	}

	return R_REG(sii->osh, &ai->iostatus);
}
Commit	Line	Data
a9533e7e HP	1	/*
	2	* Copyright (c) 2010 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
01d11441	17	#include <linux/delay.h>
3327989a BR	18	#include <linux/kernel.h>
3327989a BR	19	#include <linux/string.h>
a1c16ed2	20	#include <bcmdefs.h>
c6ac24e9 BR	21	#ifdef BRCM_FULLMAC
	22	#include <linux/netdevice.h>
	23	#endif
a1c16ed2	24	#include <osl.h>
c6ac24e9 BR	25	#include <linux/module.h>
c6ac24e9 BR	26	#include <linux/pci.h>
a9533e7e HP	27	#include <bcmutils.h>
	28	#include <siutils.h>
	29	#include <hndsoc.h>
	30	#include <sbchipc.h>
	31	#include <pcicfg.h>
	32	#include <bcmdevs.h>
	33
	34	#define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \
	35	(CHIPREV(sih->chiprev) == 0) && \
	36	(sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
	37
	38	/* EROM parsing */
	39
66cbd3ab GKH	40	static u32
66cbd3ab GKH	41	get_erom_ent(si_t sih, u32 *eromptr, u32 mask, u32 match)
a9533e7e	42	{
66cbd3ab	43	u32 ent;
a9533e7e HP	44	uint inv = 0, nom = 0;
a9533e7e HP	45
0f0881b0	46	while (true) {
a9533e7e HP	47	ent = R_REG(si_osh(sih), *eromptr);
	48	(*eromptr)++;
	49
	50	if (mask == 0)
	51	break;
	52
	53	if ((ent & ER_VALID) == 0) {
	54	inv++;
	55	continue;
	56	}
	57
	58	if (ent == (ER_END \| ER_VALID))
	59	break;
	60
	61	if ((ent & mask) == match)
	62	break;
	63
	64	nom++;
	65	}
	66
	67	SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
	68	if (inv + nom) {
	69	SI_VMSG((" after %d invalid and %d non-matching entries\n",
	70	inv, nom));
	71	}
	72	return ent;
	73	}
	74
66cbd3ab GKH	75	static u32
	76	get_asd(si_t sih, u32 *eromptr, uint sp, uint ad, uint st,
	77	u32 addrl, u32 addrh, u32 sizel, u32 sizeh)
a9533e7e	78	{
66cbd3ab	79	u32 asd, sz, szd;
a9533e7e HP	80
	81	asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
	82	if (((asd & ER_TAG1) != ER_ADD) \|\|
	83	(((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) \|\|
	84	((asd & AD_ST_MASK) != st)) {
	85	/* This is not what we want, "push" it back */
	86	(*eromptr)--;
	87	return 0;
	88	}
	89	*addrl = asd & AD_ADDR_MASK;
	90	if (asd & AD_AG32)
	91	*addrh = get_erom_ent(sih, eromptr, 0, 0);
	92	else
	93	*addrh = 0;
	94	*sizeh = 0;
	95	sz = asd & AD_SZ_MASK;
	96	if (sz == AD_SZ_SZD) {
	97	szd = get_erom_ent(sih, eromptr, 0, 0);
	98	*sizel = szd & SD_SZ_MASK;
	99	if (szd & SD_SG32)
	100	*sizeh = get_erom_ent(sih, eromptr, 0, 0);
	101	} else
	102	*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
	103
	104	SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
	105	sp, ad, st, sizeh, sizel, addrh, addrl));
	106
	107	return asd;
	108	}
	109
7cc4a4c0	110	static void ai_hwfixup(si_info_t *sii)
a9533e7e HP	111	{
	112	}
	113
	114	/* parse the enumeration rom to identify all cores */
0d2f0724	115	void ai_scan(si_t sih, void regs, uint devid)
a2627bc0	116	{
a9533e7e HP	117	si_info_t *sii = SI_INFO(sih);
a9533e7e HP	118	chipcregs_t cc = (chipcregs_t ) regs;
66cbd3ab	119	u32 erombase, eromptr, eromlim;
a9533e7e HP	120
	121	erombase = R_REG(sii->osh, &cc->eromptr);
	122
fa7a1db2	123	switch (sih->bustype) {
a9533e7e	124	case SI_BUS:
66cbd3ab	125	eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
a9533e7e HP	126	break;
	127
	128	case PCI_BUS:
	129	/* Set wrappers address */
f024c48a	130	sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);
a9533e7e HP	131
a9533e7e HP	132	/* Now point the window at the erom */
57d8cd23	133	pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, erombase);
a9533e7e HP	134	eromptr = regs;
	135	break;
	136
	137	#ifdef BCMSDIO
	138	case SPI_BUS:
	139	case SDIO_BUS:
	140	#endif /* BCMSDIO */
6ddcfdcf	141	eromptr = (u32 *)(unsigned long)erombase;
a9533e7e HP	142	break;
	143
	144	default:
	145	SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
	146	sih->bustype));
	147	ASSERT(0);
	148	return;
	149	}
66cbd3ab	150	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
a9533e7e HP	151
	152	SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
	153	while (eromptr < eromlim) {
66cbd3ab GKH	154	u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
	155	u32 mpd, asd, addrl, addrh, sizel, sizeh;
	156	u32 *base;
a9533e7e HP	157	uint i, j, idx;
	158	bool br;
	159
0965ae88	160	br = false;
a9533e7e HP	161
	162	/* Grok a component */
	163	cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
	164	if (cia == (ER_END \| ER_VALID)) {
	165	SI_VMSG(("Found END of erom after %d cores\n",
	166	sii->numcores));
	167	ai_hwfixup(sii);
	168	return;
	169	}
	170	base = eromptr - 1;
	171	cib = get_erom_ent(sih, &eromptr, 0, 0);
	172
	173	if ((cib & ER_TAG) != ER_CI) {
	174	SI_ERROR(("CIA not followed by CIB\n"));
	175	goto error;
	176	}
	177
	178	cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
	179	mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
	180	crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
	181	nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
	182	nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
	183	nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
	184	nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
	185
	186	SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));
	187
	188	if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) \|\| (nsp == 0))
	189	continue;
	190	if ((nmw + nsw == 0)) {
	191	/* A component which is not a core */
	192	if (cid == OOB_ROUTER_CORE_ID) {
	193	asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
	194	&addrl, &addrh, &sizel, &sizeh);
	195	if (asd != 0) {
	196	sii->oob_router = addrl;
	197	}
	198	}
	199	continue;
	200	}
	201
	202	idx = sii->numcores;
	203	/* sii->eromptr[idx] = base; */
	204	sii->cia[idx] = cia;
	205	sii->cib[idx] = cib;
	206	sii->coreid[idx] = cid;
	207
	208	for (i = 0; i < nmp; i++) {
	209	mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
	210	if ((mpd & ER_TAG) != ER_MP) {
	211	SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
	212	goto error;
	213	}
	214	SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
	215	(mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
	216	(mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
	217	}
	218
	219	/* First Slave Address Descriptor should be port 0:
	220	* the main register space for the core
	221	*/
	222	asd =
	223	get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
	224	&sizel, &sizeh);
225	if (asd == 0) {
226	/* Try again to see if it is a bridge */
227	asd =
228	get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
229	&addrh, &sizel, &sizeh);
230	if (asd != 0)
0f0881b0	231	br = true;
a9533e7e HP	232	else if ((addrh != 0) \|\| (sizeh != 0)
	233	\|\| (sizel != SI_CORE_SIZE)) {
	234	SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
	235	goto error;
	236	}
	237	}
	238	sii->coresba[idx] = addrl;
	239	sii->coresba_size[idx] = sizel;
	240	/* Get any more ASDs in port 0 */
	241	j = 1;
	242	do {
	243	asd =
	244	get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
	245	&addrh, &sizel, &sizeh);
	246	if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
	247	sii->coresba2[idx] = addrl;
	248	sii->coresba2_size[idx] = sizel;
	249	}
	250	j++;
	251	} while (asd != 0);
	252
	253	/* Go through the ASDs for other slave ports */
	254	for (i = 1; i < nsp; i++) {
	255	j = 0;
	256	do {
	257	asd =
	258	get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
	259	&addrl, &addrh, &sizel, &sizeh);
	260	} while (asd != 0);
	261	if (j == 0) {
	262	SI_ERROR((" SP %d has no address descriptors\n",
	263	i));
	264	goto error;
	265	}
	266	}
	267
	268	/* Now get master wrappers */
	269	for (i = 0; i < nmw; i++) {
	270	asd =
	271	get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
	272	&addrh, &sizel, &sizeh);
	273	if (asd == 0) {
	274	SI_ERROR(("Missing descriptor for MW %d\n", i));
	275	goto error;
	276	}
	277	if ((sizeh != 0) \|\| (sizel != SI_CORE_SIZE)) {
	278	SI_ERROR(("Master wrapper %d is not 4KB\n", i));
	279	goto error;
	280	}
	281	if (i == 0)
	282	sii->wrapba[idx] = addrl;
	283	}
	284
	285	/* And finally slave wrappers */
	286	for (i = 0; i < nsw; i++) {
	287	uint fwp = (nsp == 1) ? 0 : 1;
	288	asd =
	289	get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
	290	&addrl, &addrh, &sizel, &sizeh);
	291	if (asd == 0) {
	292	SI_ERROR(("Missing descriptor for SW %d\n", i));
	293	goto error;
	294	}
	295	if ((sizeh != 0) \|\| (sizel != SI_CORE_SIZE)) {
296	SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
297	goto error;
298	}
299	if ((nmw == 0) && (i == 0))
300	sii->wrapba[idx] = addrl;
301	}
302
303	/* Don't record bridges */
304	if (br)
305	continue;
306
307	/* Done with core */
308	sii->numcores++;
309	}
310
311	SI_ERROR(("Reached end of erom without finding END"));
312
313	error:
314	sii->numcores = 0;
315	return;
316	}
317
318	/* This function changes the logical "focus" to the indicated core.
319	* Return the current core's virtual address.
320	*/
7cc4a4c0	321	void ai_setcoreidx(si_t sih, uint coreidx)
a9533e7e HP	322	{
a9533e7e HP	323	si_info_t *sii = SI_INFO(sih);
66cbd3ab GKH	324	u32 addr = sii->coresba[coreidx];
66cbd3ab GKH	325	u32 wrap = sii->wrapba[coreidx];
a9533e7e HP	326	void *regs;
	327
	328	if (coreidx >= sii->numcores)
90ea2296	329	return NULL;
a9533e7e HP	330
	331	/*
	332	* If the user has provided an interrupt mask enabled function,
	333	* then assert interrupts are disabled before switching the core.
	334	*/
	335	ASSERT((sii->intrsenabled_fn == NULL)
	336	\|\| !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));
	337
fa7a1db2	338	switch (sih->bustype) {
a9533e7e HP	339	case SI_BUS:
	340	/* map new one */
	341	if (!sii->regs[coreidx]) {
	342	sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
	343	ASSERT(GOODREGS(sii->regs[coreidx]));
	344	}
	345	sii->curmap = regs = sii->regs[coreidx];
	346	if (!sii->wrappers[coreidx]) {
	347	sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
	348	ASSERT(GOODREGS(sii->wrappers[coreidx]));
	349	}
	350	sii->curwrap = sii->wrappers[coreidx];
	351	break;
	352
	353	case PCI_BUS:
	354	/* point bar0 window */
57d8cd23	355	pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN, addr);
a9533e7e HP	356	regs = sii->curmap;
a9533e7e HP	357	/* point bar0 2nd 4KB window */
57d8cd23	358	pci_write_config_dword(sii->osh->pdev, PCI_BAR0_WIN2, wrap);
a9533e7e HP	359	break;
	360
	361	#ifdef BCMSDIO
	362	case SPI_BUS:
	363	case SDIO_BUS:
	364	#endif /* BCMSDIO */
6ddcfdcf GKH	365	sii->curmap = regs = (void *)(unsigned long)addr;
6ddcfdcf GKH	366	sii->curwrap = (void *)(unsigned long)wrap;
a9533e7e HP	367	break;
	368
	369	default:
	370	ASSERT(0);
	371	regs = NULL;
	372	break;
	373	}
	374
	375	sii->curmap = regs;
	376	sii->curidx = coreidx;
	377
	378	return regs;
	379	}
	380
	381	/* Return the number of address spaces in current core */
7cc4a4c0	382	int ai_numaddrspaces(si_t *sih)
a9533e7e HP	383	{
	384	return 2;
	385	}
	386
	387	/* Return the address of the nth address space in the current core */
66cbd3ab	388	u32 ai_addrspace(si_t *sih, uint asidx)
a9533e7e HP	389	{
	390	si_info_t *sii;
	391	uint cidx;
	392
	393	sii = SI_INFO(sih);
	394	cidx = sii->curidx;
	395
	396	if (asidx == 0)
	397	return sii->coresba[cidx];
	398	else if (asidx == 1)
	399	return sii->coresba2[cidx];
	400	else {
	401	SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
	402	return 0;
	403	}
	404	}
	405
	406	/* Return the size of the nth address space in the current core */
66cbd3ab	407	u32 ai_addrspacesize(si_t *sih, uint asidx)
a9533e7e HP	408	{
	409	si_info_t *sii;
	410	uint cidx;
	411
	412	sii = SI_INFO(sih);
	413	cidx = sii->curidx;
	414
	415	if (asidx == 0)
	416	return sii->coresba_size[cidx];
	417	else if (asidx == 1)
	418	return sii->coresba2_size[cidx];
	419	else {
	420	SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
	421	return 0;
	422	}
	423	}
	424
7cc4a4c0	425	uint ai_flag(si_t *sih)
a9533e7e HP	426	{
	427	si_info_t *sii;
	428	aidmp_t *ai;
	429
	430	sii = SI_INFO(sih);
	431	if (BCM47162_DMP()) {
	432	SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
	433	return sii->curidx;
	434	}
	435	ai = sii->curwrap;
	436
90ea2296	437	return R_REG(sii->osh, &ai->oobselouta30) & 0x1f;
a9533e7e HP	438	}
a9533e7e HP	439
7cc4a4c0	440	void ai_setint(si_t *sih, int siflag)
a9533e7e HP	441	{
	442	}
	443
66cbd3ab	444	void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
a9533e7e HP	445	{
a9533e7e HP	446	si_info_t *sii = SI_INFO(sih);
66cbd3ab	447	u32 w = (u32 ) sii->curwrap;
a9533e7e HP	448	W_REG(sii->osh, w + (offset / 4), val);
	449	return;
	450	}
	451
7cc4a4c0	452	uint ai_corevendor(si_t *sih)
a9533e7e HP	453	{
a9533e7e HP	454	si_info_t *sii;
66cbd3ab	455	u32 cia;
a9533e7e HP	456
	457	sii = SI_INFO(sih);
	458	cia = sii->cia[sii->curidx];
90ea2296	459	return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
a9533e7e HP	460	}
a9533e7e HP	461
7cc4a4c0	462	uint ai_corerev(si_t *sih)
a9533e7e HP	463	{
a9533e7e HP	464	si_info_t *sii;
66cbd3ab	465	u32 cib;
a9533e7e HP	466
	467	sii = SI_INFO(sih);
	468	cib = sii->cib[sii->curidx];
90ea2296	469	return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
a9533e7e HP	470	}
a9533e7e HP	471
7cc4a4c0	472	bool ai_iscoreup(si_t *sih)
a9533e7e HP	473	{
	474	si_info_t *sii;
	475	aidmp_t *ai;
	476
	477	sii = SI_INFO(sih);
	478	ai = sii->curwrap;
	479
	480	return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC \| SICF_CLOCK_EN)) ==
	481	SICF_CLOCK_EN)
	482	&& ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
	483	}
	484
	485	/*
	486	* Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
	487	* switch back to the original core, and return the new value.
	488	*
	489	* When using the silicon backplane, no fiddling with interrupts or core switches is needed.
	490	*
	491	* Also, when using pci/pcie, we can optimize away the core switching for pci registers
	492	* and (on newer pci cores) chipcommon registers.
	493	*/
7cc4a4c0	494	uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
a9533e7e HP	495	{
a9533e7e HP	496	uint origidx = 0;
66cbd3ab	497	u32 *r = NULL;
a9533e7e HP	498	uint w;
a9533e7e HP	499	uint intr_val = 0;
0965ae88	500	bool fast = false;
a9533e7e HP	501	si_info_t *sii;
	502
	503	sii = SI_INFO(sih);
	504
	505	ASSERT(GOODIDX(coreidx));
	506	ASSERT(regoff < SI_CORE_SIZE);
	507	ASSERT((val & ~mask) == 0);
	508
	509	if (coreidx >= SI_MAXCORES)
	510	return 0;
	511
fa7a1db2	512	if (sih->bustype == SI_BUS) {
a9533e7e	513	/* If internal bus, we can always get at everything */
0f0881b0	514	fast = true;
a9533e7e HP	515	/* map if does not exist */
	516	if (!sii->regs[coreidx]) {
	517	sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
	518	SI_CORE_SIZE);
	519	ASSERT(GOODREGS(sii->regs[coreidx]));
	520	}
66cbd3ab	521	r = (u32 ) ((unsigned char ) sii->regs[coreidx] + regoff);
fa7a1db2	522	} else if (sih->bustype == PCI_BUS) {
a9533e7e HP	523	/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
	524
	525	if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
	526	/* Chipc registers are mapped at 12KB */
	527
0f0881b0	528	fast = true;
66cbd3ab	529	r = (u32 ) ((char )sii->curmap +
a9533e7e HP	530	PCI_16KB0_CCREGS_OFFSET + regoff);
	531	} else if (sii->pub.buscoreidx == coreidx) {
	532	/* pci registers are at either in the last 2KB of an 8KB window
	533	* or, in pcie and pci rev 13 at 8KB
	534	*/
0f0881b0	535	fast = true;
a9533e7e	536	if (SI_FAST(sii))
66cbd3ab	537	r = (u32 ) ((char )sii->curmap +
a9533e7e HP	538	PCI_16KB0_PCIREGS_OFFSET +
	539	regoff);
	540	else
66cbd3ab	541	r = (u32 ) ((char )sii->curmap +
a9533e7e HP	542	((regoff >= SBCONFIGOFF) ?
	543	PCI_BAR0_PCISBR_OFFSET :
	544	PCI_BAR0_PCIREGS_OFFSET) +
	545	regoff);
	546	}
	547	}
	548
	549	if (!fast) {
	550	INTR_OFF(sii, intr_val);
	551
	552	/* save current core index */
	553	origidx = si_coreidx(&sii->pub);
	554
	555	/* switch core */
66cbd3ab	556	r = (u32 ) ((unsigned char ) ai_setcoreidx(&sii->pub, coreidx) +
a9533e7e HP	557	regoff);
	558	}
	559	ASSERT(r != NULL);
	560
	561	/* mask and set */
	562	if (mask \|\| val) {
	563	w = (R_REG(sii->osh, r) & ~mask) \| val;
	564	W_REG(sii->osh, r, w);
	565	}
	566
	567	/* readback */
	568	w = R_REG(sii->osh, r);
	569
	570	if (!fast) {
	571	/* restore core index */
	572	if (origidx != coreidx)
	573	ai_setcoreidx(&sii->pub, origidx);
	574
	575	INTR_RESTORE(sii, intr_val);
	576	}
	577
90ea2296	578	return w;
a9533e7e HP	579	}
a9533e7e HP	580
66cbd3ab	581	void ai_core_disable(si_t *sih, u32 bits)
a9533e7e HP	582	{
a9533e7e HP	583	si_info_t *sii;
66cbd3ab	584	volatile u32 dummy;
a9533e7e HP	585	aidmp_t *ai;
	586
	587	sii = SI_INFO(sih);
	588
	589	ASSERT(GOODREGS(sii->curwrap));
	590	ai = sii->curwrap;
	591
	592	/* if core is already in reset, just return */
	593	if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
	594	return;
	595
	596	W_REG(sii->osh, &ai->ioctrl, bits);
	597	dummy = R_REG(sii->osh, &ai->ioctrl);
7383141b	598	udelay(10);
a9533e7e HP	599
a9533e7e HP	600	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
7383141b	601	udelay(1);
a9533e7e HP	602	}
	603
	604	/* reset and re-enable a core
	605	* inputs:
	606	* bits - core specific bits that are set during and after reset sequence
	607	* resetbits - core specific bits that are set only during reset sequence
	608	*/
66cbd3ab	609	void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
a9533e7e HP	610	{
	611	si_info_t *sii;
	612	aidmp_t *ai;
66cbd3ab	613	volatile u32 dummy;
a9533e7e HP	614
	615	sii = SI_INFO(sih);
	616	ASSERT(GOODREGS(sii->curwrap));
	617	ai = sii->curwrap;
	618
	619	/*
	620	* Must do the disable sequence first to work for arbitrary current core state.
	621	*/
	622	ai_core_disable(sih, (bits \| resetbits));
	623
	624	/*
	625	* Now do the initialization sequence.
	626	*/
	627	W_REG(sii->osh, &ai->ioctrl, (bits \| SICF_FGC \| SICF_CLOCK_EN));
	628	dummy = R_REG(sii->osh, &ai->ioctrl);
	629	W_REG(sii->osh, &ai->resetctrl, 0);
7383141b	630	udelay(1);
a9533e7e HP	631
	632	W_REG(sii->osh, &ai->ioctrl, (bits \| SICF_CLOCK_EN));
	633	dummy = R_REG(sii->osh, &ai->ioctrl);
7383141b	634	udelay(1);
a9533e7e HP	635	}
a9533e7e HP	636
66cbd3ab	637	void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
a9533e7e HP	638	{
	639	si_info_t *sii;
	640	aidmp_t *ai;
66cbd3ab	641	u32 w;
a9533e7e HP	642
	643	sii = SI_INFO(sih);
	644
	645	if (BCM47162_DMP()) {
	646	SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
	647	__func__));
	648	return;
	649	}
	650
	651	ASSERT(GOODREGS(sii->curwrap));
	652	ai = sii->curwrap;
	653
	654	ASSERT((val & ~mask) == 0);
	655
	656	if (mask \|\| val) {
	657	w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) \| val);
	658	W_REG(sii->osh, &ai->ioctrl, w);
	659	}
	660	}
	661
66cbd3ab	662	u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
a9533e7e HP	663	{
	664	si_info_t *sii;
	665	aidmp_t *ai;
66cbd3ab	666	u32 w;
a9533e7e HP	667
	668	sii = SI_INFO(sih);
	669	if (BCM47162_DMP()) {
	670	SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
	671	__func__));
	672	return 0;
	673	}
	674
	675	ASSERT(GOODREGS(sii->curwrap));
	676	ai = sii->curwrap;
	677
	678	ASSERT((val & ~mask) == 0);
	679
	680	if (mask \|\| val) {
	681	w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) \| val);
	682	W_REG(sii->osh, &ai->ioctrl, w);
	683	}
	684
	685	return R_REG(sii->osh, &ai->ioctrl);
	686	}
	687
66cbd3ab	688	u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
a9533e7e HP	689	{
	690	si_info_t *sii;
	691	aidmp_t *ai;
66cbd3ab	692	u32 w;
a9533e7e HP	693
	694	sii = SI_INFO(sih);
	695	if (BCM47162_DMP()) {
	696	SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
	697	return 0;
	698	}
	699
	700	ASSERT(GOODREGS(sii->curwrap));
	701	ai = sii->curwrap;
	702
	703	ASSERT((val & ~mask) == 0);
	704	ASSERT((mask & ~SISF_CORE_BITS) == 0);
	705
	706	if (mask \|\| val) {
	707	w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) \| val);
	708	W_REG(sii->osh, &ai->iostatus, w);
	709	}
	710
	711	return R_REG(sii->osh, &ai->iostatus);
	712	}
	713