[mirror_ubuntu-bionic-kernel.git] / drivers / staging / brcm80211 / util / aiutils.c

/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#include <linux/kernel.h>
#include <linux/string.h>
#include <bcmdefs.h>
#ifdef BRCM_FULLMAC
#include <linux/netdevice.h>
#endif
#include <osl.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <bcmutils.h>
#include <siutils.h>
#include <hndsoc.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <bcmdevs.h>

#define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \
		(CHIPREV(sih->chiprev) == 0) && \
		(sii->coreid[sii->curidx] == MIPS74K_CORE_ID))

/* EROM parsing */

static u32
get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
{
	u32 ent;
	uint inv = 0, nom = 0;

	while (true) {
		ent = R_REG(si_osh(sih), *eromptr);
		(*eromptr)++;

		if (mask == 0)
			break;

		if ((ent & ER_VALID) == 0) {
			inv++;
			continue;
		}

		if (ent == (ER_END | ER_VALID))
			break;

		if ((ent & mask) == match)
			break;

		nom++;
	}

	SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
	if (inv + nom) {
		SI_VMSG(("  after %d invalid and %d non-matching entries\n",
			 inv, nom));
	}
	return ent;
}

static u32
get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
	u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
{
	u32 asd, sz, szd;

	asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
	if (((asd & ER_TAG1) != ER_ADD) ||
	    (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
	    ((asd & AD_ST_MASK) != st)) {
		/* This is not what we want, "push" it back */
		(*eromptr)--;
		return 0;
	}
	*addrl = asd & AD_ADDR_MASK;
	if (asd & AD_AG32)
		*addrh = get_erom_ent(sih, eromptr, 0, 0);
	else
		*addrh = 0;
	*sizeh = 0;
	sz = asd & AD_SZ_MASK;
	if (sz == AD_SZ_SZD) {
		szd = get_erom_ent(sih, eromptr, 0, 0);
		*sizel = szd & SD_SZ_MASK;
		if (szd & SD_SG32)
			*sizeh = get_erom_ent(sih, eromptr, 0, 0);
	} else
		*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);

	SI_VMSG(("  SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
		 sp, ad, st, *sizeh, *sizel, *addrh, *addrl));

	return asd;
}

static void ai_hwfixup(si_info_t *sii)
{
}

/* parse the enumeration rom to identify all cores */
void ai_scan(si_t *sih, void *regs, uint devid)
{
	si_info_t *sii = SI_INFO(sih);
	chipcregs_t *cc = (chipcregs_t *) regs;
	u32 erombase, *eromptr, *eromlim;

	erombase = R_REG(sii->osh, &cc->eromptr);

	switch (BUSTYPE(sih->bustype)) {
	case SI_BUS:
		eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
		break;

	case PCI_BUS:
		/* Set wrappers address */
		sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);

		/* Now point the window at the erom */
		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
		eromptr = regs;
		break;

#ifdef BCMSDIO
	case SPI_BUS:
	case SDIO_BUS:
#endif				/* BCMSDIO */
		eromptr = (u32 *)(unsigned long)erombase;
		break;

	default:
		SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
			  sih->bustype));
		ASSERT(0);
		return;
	}
	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));

	SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
	while (eromptr < eromlim) {
		u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
		u32 mpd, asd, addrl, addrh, sizel, sizeh;
		u32 *base;
		uint i, j, idx;
		bool br;

		br = false;

		/* Grok a component */
		cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
		if (cia == (ER_END | ER_VALID)) {
			SI_VMSG(("Found END of erom after %d cores\n",
				 sii->numcores));
			ai_hwfixup(sii);
			return;
		}
		base = eromptr - 1;
		cib = get_erom_ent(sih, &eromptr, 0, 0);

		if ((cib & ER_TAG) != ER_CI) {
			SI_ERROR(("CIA not followed by CIB\n"));
			goto error;
		}

		cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
		mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
		crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
		nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
		nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
		nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
		nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;

		SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));

		if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
			continue;
		if ((nmw + nsw == 0)) {
			/* A component which is not a core */
			if (cid == OOB_ROUTER_CORE_ID) {
				asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
					      &addrl, &addrh, &sizel, &sizeh);
				if (asd != 0) {
					sii->oob_router = addrl;
				}
			}
			continue;
		}

		idx = sii->numcores;
/*		sii->eromptr[idx] = base; */
		sii->cia[idx] = cia;
		sii->cib[idx] = cib;
		sii->coreid[idx] = cid;

		for (i = 0; i < nmp; i++) {
			mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
			if ((mpd & ER_TAG) != ER_MP) {
				SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
				goto error;
			}
			SI_VMSG(("  Master port %d, mp: %d id: %d\n", i,
				 (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
				 (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
		}

		/* First Slave Address Descriptor should be port 0:
		 * the main register space for the core
		 */
		asd =
		    get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
			    &sizel, &sizeh);
		if (asd == 0) {
			/* Try again to see if it is a bridge */
			asd =
			    get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
				    &addrh, &sizel, &sizeh);
			if (asd != 0)
				br = true;
			else if ((addrh != 0) || (sizeh != 0)
				 || (sizel != SI_CORE_SIZE)) {
				SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
				goto error;
			}
		}
		sii->coresba[idx] = addrl;
		sii->coresba_size[idx] = sizel;
		/* Get any more ASDs in port 0 */
		j = 1;
		do {
			asd =
			    get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
				    &addrh, &sizel, &sizeh);
			if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
				sii->coresba2[idx] = addrl;
				sii->coresba2_size[idx] = sizel;
			}
			j++;
		} while (asd != 0);

		/* Go through the ASDs for other slave ports */
		for (i = 1; i < nsp; i++) {
			j = 0;
			do {
				asd =
				    get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
					    &addrl, &addrh, &sizel, &sizeh);
			} while (asd != 0);
			if (j == 0) {
				SI_ERROR((" SP %d has no address descriptors\n",
					  i));
				goto error;
			}
		}

		/* Now get master wrappers */
		for (i = 0; i < nmw; i++) {
			asd =
			    get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
				    &addrh, &sizel, &sizeh);
			if (asd == 0) {
				SI_ERROR(("Missing descriptor for MW %d\n", i));
				goto error;
			}
			if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
				SI_ERROR(("Master wrapper %d is not 4KB\n", i));
				goto error;
			}
			if (i == 0)
				sii->wrapba[idx] = addrl;
		}

		/* And finally slave wrappers */
		for (i = 0; i < nsw; i++) {
			uint fwp = (nsp == 1) ? 0 : 1;
			asd =
			    get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
				    &addrl, &addrh, &sizel, &sizeh);
			if (asd == 0) {
				SI_ERROR(("Missing descriptor for SW %d\n", i));
				goto error;
			}
			if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
				SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
				goto error;
			}
			if ((nmw == 0) && (i == 0))
				sii->wrapba[idx] = addrl;
		}

		/* Don't record bridges */
		if (br)
			continue;

		/* Done with core */
		sii->numcores++;
	}

	SI_ERROR(("Reached end of erom without finding END"));

 error:
	sii->numcores = 0;
	return;
}

/* This function changes the logical "focus" to the indicated core.
 * Return the current core's virtual address.
 */
void *ai_setcoreidx(si_t *sih, uint coreidx)
{
	si_info_t *sii = SI_INFO(sih);
	u32 addr = sii->coresba[coreidx];
	u32 wrap = sii->wrapba[coreidx];
	void *regs;

	if (coreidx >= sii->numcores)
		return NULL;

	/*
	 * If the user has provided an interrupt mask enabled function,
	 * then assert interrupts are disabled before switching the core.
	 */
	ASSERT((sii->intrsenabled_fn == NULL)
	       || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));

	switch (BUSTYPE(sih->bustype)) {
	case SI_BUS:
		/* map new one */
		if (!sii->regs[coreidx]) {
			sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
			ASSERT(GOODREGS(sii->regs[coreidx]));
		}
		sii->curmap = regs = sii->regs[coreidx];
		if (!sii->wrappers[coreidx]) {
			sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
			ASSERT(GOODREGS(sii->wrappers[coreidx]));
		}
		sii->curwrap = sii->wrappers[coreidx];
		break;

	case PCI_BUS:
		/* point bar0 window */
		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
		regs = sii->curmap;
		/* point bar0 2nd 4KB window */
		OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
		break;

#ifdef BCMSDIO
	case SPI_BUS:
	case SDIO_BUS:
#endif				/* BCMSDIO */
		sii->curmap = regs = (void *)(unsigned long)addr;
		sii->curwrap = (void *)(unsigned long)wrap;
		break;

	default:
		ASSERT(0);
		regs = NULL;
		break;
	}

	sii->curmap = regs;
	sii->curidx = coreidx;

	return regs;
}

/* Return the number of address spaces in current core */
int ai_numaddrspaces(si_t *sih)
{
	return 2;
}

/* Return the address of the nth address space in the current core */
u32 ai_addrspace(si_t *sih, uint asidx)
{
	si_info_t *sii;
	uint cidx;

	sii = SI_INFO(sih);
	cidx = sii->curidx;

	if (asidx == 0)
		return sii->coresba[cidx];
	else if (asidx == 1)
		return sii->coresba2[cidx];
	else {
		SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
		return 0;
	}
}

/* Return the size of the nth address space in the current core */
u32 ai_addrspacesize(si_t *sih, uint asidx)
{
	si_info_t *sii;
	uint cidx;

	sii = SI_INFO(sih);
	cidx = sii->curidx;

	if (asidx == 0)
		return sii->coresba_size[cidx];
	else if (asidx == 1)
		return sii->coresba2_size[cidx];
	else {
		SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
		return 0;
	}
}

uint ai_flag(si_t *sih)
{
	si_info_t *sii;
	aidmp_t *ai;

	sii = SI_INFO(sih);
	if (BCM47162_DMP()) {
		SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
		return sii->curidx;
	}
	ai = sii->curwrap;

	return R_REG(sii->osh, &ai->oobselouta30) & 0x1f;
}

void ai_setint(si_t *sih, int siflag)
{
}

void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
{
	si_info_t *sii = SI_INFO(sih);
	u32 *w = (u32 *) sii->curwrap;
	W_REG(sii->osh, w + (offset / 4), val);
	return;
}

uint ai_corevendor(si_t *sih)
{
	si_info_t *sii;
	u32 cia;

	sii = SI_INFO(sih);
	cia = sii->cia[sii->curidx];
	return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
}

uint ai_corerev(si_t *sih)
{
	si_info_t *sii;
	u32 cib;

	sii = SI_INFO(sih);
	cib = sii->cib[sii->curidx];
	return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
}

bool ai_iscoreup(si_t *sih)
{
	si_info_t *sii;
	aidmp_t *ai;

	sii = SI_INFO(sih);
	ai = sii->curwrap;

	return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
		 SICF_CLOCK_EN)
		&& ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
}

/*
 * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
 * switch back to the original core, and return the new value.
 *
 * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
 *
 * Also, when using pci/pcie, we can optimize away the core switching for pci registers
 * and (on newer pci cores) chipcommon registers.
 */
uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
{
	uint origidx = 0;
	u32 *r = NULL;
	uint w;
	uint intr_val = 0;
	bool fast = false;
	si_info_t *sii;

	sii = SI_INFO(sih);

	ASSERT(GOODIDX(coreidx));
	ASSERT(regoff < SI_CORE_SIZE);
	ASSERT((val & ~mask) == 0);

	if (coreidx >= SI_MAXCORES)
		return 0;

	if (BUSTYPE(sih->bustype) == SI_BUS) {
		/* If internal bus, we can always get at everything */
		fast = true;
		/* map if does not exist */
		if (!sii->regs[coreidx]) {
			sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
						     SI_CORE_SIZE);
			ASSERT(GOODREGS(sii->regs[coreidx]));
		}
		r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
	} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
		/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */

		if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
			/* Chipc registers are mapped at 12KB */

			fast = true;
			r = (u32 *) ((char *)sii->curmap +
					PCI_16KB0_CCREGS_OFFSET + regoff);
		} else if (sii->pub.buscoreidx == coreidx) {
			/* pci registers are at either in the last 2KB of an 8KB window
			 * or, in pcie and pci rev 13 at 8KB
			 */
			fast = true;
			if (SI_FAST(sii))
				r = (u32 *) ((char *)sii->curmap +
						PCI_16KB0_PCIREGS_OFFSET +
						regoff);
			else
				r = (u32 *) ((char *)sii->curmap +
						((regoff >= SBCONFIGOFF) ?
						 PCI_BAR0_PCISBR_OFFSET :
						 PCI_BAR0_PCIREGS_OFFSET) +
						regoff);
		}
	}

	if (!fast) {
		INTR_OFF(sii, intr_val);

		/* save current core index */
		origidx = si_coreidx(&sii->pub);

		/* switch core */
		r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
				regoff);
	}
	ASSERT(r != NULL);

	/* mask and set */
	if (mask || val) {
		w = (R_REG(sii->osh, r) & ~mask) | val;
		W_REG(sii->osh, r, w);
	}

	/* readback */
	w = R_REG(sii->osh, r);

	if (!fast) {
		/* restore core index */
		if (origidx != coreidx)
			ai_setcoreidx(&sii->pub, origidx);

		INTR_RESTORE(sii, intr_val);
	}

	return w;
}

void ai_core_disable(si_t *sih, u32 bits)
{
	si_info_t *sii;
	volatile u32 dummy;
	aidmp_t *ai;

	sii = SI_INFO(sih);

	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	/* if core is already in reset, just return */
	if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
		return;

	W_REG(sii->osh, &ai->ioctrl, bits);
	dummy = R_REG(sii->osh, &ai->ioctrl);
	udelay(10);

	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
	udelay(1);
}

/* reset and re-enable a core
 * inputs:
 * bits - core specific bits that are set during and after reset sequence
 * resetbits - core specific bits that are set only during reset sequence
 */
void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
{
	si_info_t *sii;
	aidmp_t *ai;
	volatile u32 dummy;

	sii = SI_INFO(sih);
	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	/*
	 * Must do the disable sequence first to work for arbitrary current core state.
	 */
	ai_core_disable(sih, (bits | resetbits));

	/*
	 * Now do the initialization sequence.
	 */
	W_REG(sii->osh, &ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
	dummy = R_REG(sii->osh, &ai->ioctrl);
	W_REG(sii->osh, &ai->resetctrl, 0);
	udelay(1);

	W_REG(sii->osh, &ai->ioctrl, (bits | SICF_CLOCK_EN));
	dummy = R_REG(sii->osh, &ai->ioctrl);
	udelay(1);
}

void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
{
	si_info_t *sii;
	aidmp_t *ai;
	u32 w;

	sii = SI_INFO(sih);

	if (BCM47162_DMP()) {
		SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
			  __func__));
		return;
	}

	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	ASSERT((val & ~mask) == 0);

	if (mask || val) {
		w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
		W_REG(sii->osh, &ai->ioctrl, w);
	}
}

u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
{
	si_info_t *sii;
	aidmp_t *ai;
	u32 w;

	sii = SI_INFO(sih);
	if (BCM47162_DMP()) {
		SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
			  __func__));
		return 0;
	}

	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	ASSERT((val & ~mask) == 0);

	if (mask || val) {
		w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) | val);
		W_REG(sii->osh, &ai->ioctrl, w);
	}

	return R_REG(sii->osh, &ai->ioctrl);
}

u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
{
	si_info_t *sii;
	aidmp_t *ai;
	u32 w;

	sii = SI_INFO(sih);
	if (BCM47162_DMP()) {
		SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
		return 0;
	}

	ASSERT(GOODREGS(sii->curwrap));
	ai = sii->curwrap;

	ASSERT((val & ~mask) == 0);
	ASSERT((mask & ~SISF_CORE_BITS) == 0);

	if (mask || val) {
		w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) | val);
		W_REG(sii->osh, &ai->iostatus, w);
	}

	return R_REG(sii->osh, &ai->iostatus);
}
Commit	Line	Data
a9533e7e HP	1	/*
	2	* Copyright (c) 2010 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
3327989a BR	17	#include <linux/kernel.h>
3327989a BR	18	#include <linux/string.h>
a1c16ed2	19	#include <bcmdefs.h>
c6ac24e9 BR	20	#ifdef BRCM_FULLMAC
	21	#include <linux/netdevice.h>
	22	#endif
a1c16ed2	23	#include <osl.h>
c6ac24e9 BR	24	#include <linux/module.h>
c6ac24e9 BR	25	#include <linux/pci.h>
a9533e7e HP	26	#include <bcmutils.h>
	27	#include <siutils.h>
	28	#include <hndsoc.h>
	29	#include <sbchipc.h>
	30	#include <pcicfg.h>
	31	#include <bcmdevs.h>
	32
	33	#define BCM47162_DMP() ((CHIPID(sih->chip) == BCM47162_CHIP_ID) && \
	34	(CHIPREV(sih->chiprev) == 0) && \
	35	(sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
	36
	37	/* EROM parsing */
	38
66cbd3ab GKH	39	static u32
66cbd3ab GKH	40	get_erom_ent(si_t sih, u32 *eromptr, u32 mask, u32 match)
a9533e7e	41	{
66cbd3ab	42	u32 ent;
a9533e7e HP	43	uint inv = 0, nom = 0;
a9533e7e HP	44
0f0881b0	45	while (true) {
a9533e7e HP	46	ent = R_REG(si_osh(sih), *eromptr);
	47	(*eromptr)++;
	48
	49	if (mask == 0)
	50	break;
	51
	52	if ((ent & ER_VALID) == 0) {
	53	inv++;
	54	continue;
	55	}
	56
	57	if (ent == (ER_END \| ER_VALID))
	58	break;
	59
	60	if ((ent & mask) == match)
	61	break;
	62
	63	nom++;
	64	}
	65
	66	SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
	67	if (inv + nom) {
	68	SI_VMSG((" after %d invalid and %d non-matching entries\n",
	69	inv, nom));
	70	}
	71	return ent;
	72	}
	73
66cbd3ab GKH	74	static u32
	75	get_asd(si_t sih, u32 *eromptr, uint sp, uint ad, uint st,
	76	u32 addrl, u32 addrh, u32 sizel, u32 sizeh)
a9533e7e	77	{
66cbd3ab	78	u32 asd, sz, szd;
a9533e7e HP	79
	80	asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
	81	if (((asd & ER_TAG1) != ER_ADD) \|\|
	82	(((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) \|\|
	83	((asd & AD_ST_MASK) != st)) {
	84	/* This is not what we want, "push" it back */
	85	(*eromptr)--;
	86	return 0;
	87	}
	88	*addrl = asd & AD_ADDR_MASK;
	89	if (asd & AD_AG32)
	90	*addrh = get_erom_ent(sih, eromptr, 0, 0);
	91	else
	92	*addrh = 0;
	93	*sizeh = 0;
	94	sz = asd & AD_SZ_MASK;
	95	if (sz == AD_SZ_SZD) {
	96	szd = get_erom_ent(sih, eromptr, 0, 0);
	97	*sizel = szd & SD_SZ_MASK;
	98	if (szd & SD_SG32)
	99	*sizeh = get_erom_ent(sih, eromptr, 0, 0);
	100	} else
	101	*sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
	102
	103	SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
	104	sp, ad, st, sizeh, sizel, addrh, addrl));
	105
	106	return asd;
	107	}
	108
7cc4a4c0	109	static void ai_hwfixup(si_info_t *sii)
a9533e7e HP	110	{
	111	}
	112
	113	/* parse the enumeration rom to identify all cores */
0d2f0724	114	void ai_scan(si_t sih, void regs, uint devid)
a2627bc0	115	{
a9533e7e HP	116	si_info_t *sii = SI_INFO(sih);
a9533e7e HP	117	chipcregs_t cc = (chipcregs_t ) regs;
66cbd3ab	118	u32 erombase, eromptr, eromlim;
a9533e7e HP	119
	120	erombase = R_REG(sii->osh, &cc->eromptr);
	121
	122	switch (BUSTYPE(sih->bustype)) {
	123	case SI_BUS:
66cbd3ab	124	eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
a9533e7e HP	125	break;
	126
	127	case PCI_BUS:
	128	/* Set wrappers address */
f024c48a	129	sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);
a9533e7e HP	130
	131	/* Now point the window at the erom */
	132	OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, erombase);
	133	eromptr = regs;
	134	break;
	135
	136	#ifdef BCMSDIO
	137	case SPI_BUS:
	138	case SDIO_BUS:
	139	#endif /* BCMSDIO */
6ddcfdcf	140	eromptr = (u32 *)(unsigned long)erombase;
a9533e7e HP	141	break;
	142
	143	default:
	144	SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
	145	sih->bustype));
	146	ASSERT(0);
	147	return;
	148	}
66cbd3ab	149	eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
a9533e7e HP	150
	151	SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
	152	while (eromptr < eromlim) {
66cbd3ab GKH	153	u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
	154	u32 mpd, asd, addrl, addrh, sizel, sizeh;
	155	u32 *base;
a9533e7e HP	156	uint i, j, idx;
	157	bool br;
	158
0965ae88	159	br = false;
a9533e7e HP	160
	161	/* Grok a component */
	162	cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
	163	if (cia == (ER_END \| ER_VALID)) {
	164	SI_VMSG(("Found END of erom after %d cores\n",
	165	sii->numcores));
	166	ai_hwfixup(sii);
	167	return;
	168	}
	169	base = eromptr - 1;
	170	cib = get_erom_ent(sih, &eromptr, 0, 0);
	171
	172	if ((cib & ER_TAG) != ER_CI) {
	173	SI_ERROR(("CIA not followed by CIB\n"));
	174	goto error;
	175	}
	176
	177	cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
	178	mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
	179	crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
	180	nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
	181	nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
	182	nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
	183	nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
	184
	185	SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));
	186
	187	if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) \|\| (nsp == 0))
	188	continue;
	189	if ((nmw + nsw == 0)) {
	190	/* A component which is not a core */
	191	if (cid == OOB_ROUTER_CORE_ID) {
	192	asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
	193	&addrl, &addrh, &sizel, &sizeh);
	194	if (asd != 0) {
	195	sii->oob_router = addrl;
	196	}
	197	}
	198	continue;
	199	}
	200
	201	idx = sii->numcores;
	202	/* sii->eromptr[idx] = base; */
	203	sii->cia[idx] = cia;
	204	sii->cib[idx] = cib;
	205	sii->coreid[idx] = cid;
	206
	207	for (i = 0; i < nmp; i++) {
	208	mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
	209	if ((mpd & ER_TAG) != ER_MP) {
	210	SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
	211	goto error;
	212	}
	213	SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
	214	(mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
	215	(mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
	216	}
	217
	218	/* First Slave Address Descriptor should be port 0:
	219	* the main register space for the core
	220	*/
	221	asd =
	222	get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
	223	&sizel, &sizeh);
224	if (asd == 0) {
225	/* Try again to see if it is a bridge */
226	asd =
227	get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
228	&addrh, &sizel, &sizeh);
229	if (asd != 0)
0f0881b0	230	br = true;
a9533e7e HP	231	else if ((addrh != 0) \|\| (sizeh != 0)
	232	\|\| (sizel != SI_CORE_SIZE)) {
	233	SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
	234	goto error;
	235	}
	236	}
	237	sii->coresba[idx] = addrl;
	238	sii->coresba_size[idx] = sizel;
	239	/* Get any more ASDs in port 0 */
	240	j = 1;
	241	do {
	242	asd =
	243	get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
	244	&addrh, &sizel, &sizeh);
	245	if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
	246	sii->coresba2[idx] = addrl;
	247	sii->coresba2_size[idx] = sizel;
	248	}
	249	j++;
	250	} while (asd != 0);
	251
	252	/* Go through the ASDs for other slave ports */
	253	for (i = 1; i < nsp; i++) {
	254	j = 0;
	255	do {
	256	asd =
	257	get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
	258	&addrl, &addrh, &sizel, &sizeh);
	259	} while (asd != 0);
	260	if (j == 0) {
	261	SI_ERROR((" SP %d has no address descriptors\n",
	262	i));
	263	goto error;
	264	}
	265	}
	266
	267	/* Now get master wrappers */
	268	for (i = 0; i < nmw; i++) {
	269	asd =
	270	get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
	271	&addrh, &sizel, &sizeh);
	272	if (asd == 0) {
	273	SI_ERROR(("Missing descriptor for MW %d\n", i));
	274	goto error;
	275	}
	276	if ((sizeh != 0) \|\| (sizel != SI_CORE_SIZE)) {
	277	SI_ERROR(("Master wrapper %d is not 4KB\n", i));
	278	goto error;
	279	}
	280	if (i == 0)
	281	sii->wrapba[idx] = addrl;
	282	}
	283
	284	/* And finally slave wrappers */
	285	for (i = 0; i < nsw; i++) {
	286	uint fwp = (nsp == 1) ? 0 : 1;
	287	asd =
	288	get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
	289	&addrl, &addrh, &sizel, &sizeh);
	290	if (asd == 0) {
	291	SI_ERROR(("Missing descriptor for SW %d\n", i));
	292	goto error;
	293	}
	294	if ((sizeh != 0) \|\| (sizel != SI_CORE_SIZE)) {
295	SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
296	goto error;
297	}
298	if ((nmw == 0) && (i == 0))
299	sii->wrapba[idx] = addrl;
300	}
301
302	/* Don't record bridges */
303	if (br)
304	continue;
305
306	/* Done with core */
307	sii->numcores++;
308	}
309
310	SI_ERROR(("Reached end of erom without finding END"));
311
312	error:
313	sii->numcores = 0;
314	return;
315	}
316
317	/* This function changes the logical "focus" to the indicated core.
318	* Return the current core's virtual address.
319	*/
7cc4a4c0	320	void ai_setcoreidx(si_t sih, uint coreidx)
a9533e7e HP	321	{
a9533e7e HP	322	si_info_t *sii = SI_INFO(sih);
66cbd3ab GKH	323	u32 addr = sii->coresba[coreidx];
66cbd3ab GKH	324	u32 wrap = sii->wrapba[coreidx];
a9533e7e HP	325	void *regs;
	326
	327	if (coreidx >= sii->numcores)
90ea2296	328	return NULL;
a9533e7e HP	329
	330	/*
	331	* If the user has provided an interrupt mask enabled function,
	332	* then assert interrupts are disabled before switching the core.
	333	*/
	334	ASSERT((sii->intrsenabled_fn == NULL)
	335	\|\| !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));
	336
	337	switch (BUSTYPE(sih->bustype)) {
	338	case SI_BUS:
	339	/* map new one */
	340	if (!sii->regs[coreidx]) {
	341	sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
	342	ASSERT(GOODREGS(sii->regs[coreidx]));
	343	}
	344	sii->curmap = regs = sii->regs[coreidx];
	345	if (!sii->wrappers[coreidx]) {
	346	sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
	347	ASSERT(GOODREGS(sii->wrappers[coreidx]));
	348	}
	349	sii->curwrap = sii->wrappers[coreidx];
	350	break;
	351
	352	case PCI_BUS:
	353	/* point bar0 window */
	354	OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, addr);
	355	regs = sii->curmap;
	356	/* point bar0 2nd 4KB window */
	357	OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN2, 4, wrap);
	358	break;
	359
	360	#ifdef BCMSDIO
	361	case SPI_BUS:
	362	case SDIO_BUS:
	363	#endif /* BCMSDIO */
6ddcfdcf GKH	364	sii->curmap = regs = (void *)(unsigned long)addr;
6ddcfdcf GKH	365	sii->curwrap = (void *)(unsigned long)wrap;
a9533e7e HP	366	break;
	367
	368	default:
	369	ASSERT(0);
	370	regs = NULL;
	371	break;
	372	}
	373
	374	sii->curmap = regs;
	375	sii->curidx = coreidx;
	376
	377	return regs;
	378	}
	379
	380	/* Return the number of address spaces in current core */
7cc4a4c0	381	int ai_numaddrspaces(si_t *sih)
a9533e7e HP	382	{
	383	return 2;
	384	}
	385
	386	/* Return the address of the nth address space in the current core */
66cbd3ab	387	u32 ai_addrspace(si_t *sih, uint asidx)
a9533e7e HP	388	{
	389	si_info_t *sii;
	390	uint cidx;
	391
	392	sii = SI_INFO(sih);
	393	cidx = sii->curidx;
	394
	395	if (asidx == 0)
	396	return sii->coresba[cidx];
	397	else if (asidx == 1)
	398	return sii->coresba2[cidx];
	399	else {
	400	SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
	401	return 0;
	402	}
	403	}
	404
	405	/* Return the size of the nth address space in the current core */
66cbd3ab	406	u32 ai_addrspacesize(si_t *sih, uint asidx)
a9533e7e HP	407	{
	408	si_info_t *sii;
	409	uint cidx;
	410
	411	sii = SI_INFO(sih);
	412	cidx = sii->curidx;
	413
	414	if (asidx == 0)
	415	return sii->coresba_size[cidx];
	416	else if (asidx == 1)
	417	return sii->coresba2_size[cidx];
	418	else {
	419	SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
	420	return 0;
	421	}
	422	}
	423
7cc4a4c0	424	uint ai_flag(si_t *sih)
a9533e7e HP	425	{
	426	si_info_t *sii;
	427	aidmp_t *ai;
	428
	429	sii = SI_INFO(sih);
	430	if (BCM47162_DMP()) {
	431	SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
	432	return sii->curidx;
	433	}
	434	ai = sii->curwrap;
	435
90ea2296	436	return R_REG(sii->osh, &ai->oobselouta30) & 0x1f;
a9533e7e HP	437	}
a9533e7e HP	438
7cc4a4c0	439	void ai_setint(si_t *sih, int siflag)
a9533e7e HP	440	{
	441	}
	442
66cbd3ab	443	void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
a9533e7e HP	444	{
a9533e7e HP	445	si_info_t *sii = SI_INFO(sih);
66cbd3ab	446	u32 w = (u32 ) sii->curwrap;
a9533e7e HP	447	W_REG(sii->osh, w + (offset / 4), val);
	448	return;
	449	}
	450
7cc4a4c0	451	uint ai_corevendor(si_t *sih)
a9533e7e HP	452	{
a9533e7e HP	453	si_info_t *sii;
66cbd3ab	454	u32 cia;
a9533e7e HP	455
	456	sii = SI_INFO(sih);
	457	cia = sii->cia[sii->curidx];
90ea2296	458	return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
a9533e7e HP	459	}
a9533e7e HP	460
7cc4a4c0	461	uint ai_corerev(si_t *sih)
a9533e7e HP	462	{
a9533e7e HP	463	si_info_t *sii;
66cbd3ab	464	u32 cib;
a9533e7e HP	465
	466	sii = SI_INFO(sih);
	467	cib = sii->cib[sii->curidx];
90ea2296	468	return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
a9533e7e HP	469	}
a9533e7e HP	470
7cc4a4c0	471	bool ai_iscoreup(si_t *sih)
a9533e7e HP	472	{
	473	si_info_t *sii;
	474	aidmp_t *ai;
	475
	476	sii = SI_INFO(sih);
	477	ai = sii->curwrap;
	478
	479	return (((R_REG(sii->osh, &ai->ioctrl) & (SICF_FGC \| SICF_CLOCK_EN)) ==
	480	SICF_CLOCK_EN)
	481	&& ((R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET) == 0));
	482	}
	483
	484	/*
	485	* Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
	486	* switch back to the original core, and return the new value.
	487	*
	488	* When using the silicon backplane, no fiddling with interrupts or core switches is needed.
	489	*
	490	* Also, when using pci/pcie, we can optimize away the core switching for pci registers
	491	* and (on newer pci cores) chipcommon registers.
	492	*/
7cc4a4c0	493	uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
a9533e7e HP	494	{
a9533e7e HP	495	uint origidx = 0;
66cbd3ab	496	u32 *r = NULL;
a9533e7e HP	497	uint w;
a9533e7e HP	498	uint intr_val = 0;
0965ae88	499	bool fast = false;
a9533e7e HP	500	si_info_t *sii;
	501
	502	sii = SI_INFO(sih);
	503
	504	ASSERT(GOODIDX(coreidx));
	505	ASSERT(regoff < SI_CORE_SIZE);
	506	ASSERT((val & ~mask) == 0);
	507
	508	if (coreidx >= SI_MAXCORES)
	509	return 0;
	510
	511	if (BUSTYPE(sih->bustype) == SI_BUS) {
	512	/* If internal bus, we can always get at everything */
0f0881b0	513	fast = true;
a9533e7e HP	514	/* map if does not exist */
	515	if (!sii->regs[coreidx]) {
	516	sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
	517	SI_CORE_SIZE);
	518	ASSERT(GOODREGS(sii->regs[coreidx]));
	519	}
66cbd3ab	520	r = (u32 ) ((unsigned char ) sii->regs[coreidx] + regoff);
a9533e7e HP	521	} else if (BUSTYPE(sih->bustype) == PCI_BUS) {
	522	/* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
	523
	524	if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
	525	/* Chipc registers are mapped at 12KB */
	526
0f0881b0	527	fast = true;
66cbd3ab	528	r = (u32 ) ((char )sii->curmap +
a9533e7e HP	529	PCI_16KB0_CCREGS_OFFSET + regoff);
	530	} else if (sii->pub.buscoreidx == coreidx) {
	531	/* pci registers are at either in the last 2KB of an 8KB window
	532	* or, in pcie and pci rev 13 at 8KB
	533	*/
0f0881b0	534	fast = true;
a9533e7e	535	if (SI_FAST(sii))
66cbd3ab	536	r = (u32 ) ((char )sii->curmap +
a9533e7e HP	537	PCI_16KB0_PCIREGS_OFFSET +
	538	regoff);
	539	else
66cbd3ab	540	r = (u32 ) ((char )sii->curmap +
a9533e7e HP	541	((regoff >= SBCONFIGOFF) ?
	542	PCI_BAR0_PCISBR_OFFSET :
	543	PCI_BAR0_PCIREGS_OFFSET) +
	544	regoff);
	545	}
	546	}
	547
	548	if (!fast) {
	549	INTR_OFF(sii, intr_val);
	550
	551	/* save current core index */
	552	origidx = si_coreidx(&sii->pub);
	553
	554	/* switch core */
66cbd3ab	555	r = (u32 ) ((unsigned char ) ai_setcoreidx(&sii->pub, coreidx) +
a9533e7e HP	556	regoff);
	557	}
	558	ASSERT(r != NULL);
	559
	560	/* mask and set */
	561	if (mask \|\| val) {
	562	w = (R_REG(sii->osh, r) & ~mask) \| val;
	563	W_REG(sii->osh, r, w);
	564	}
	565
	566	/* readback */
	567	w = R_REG(sii->osh, r);
	568
	569	if (!fast) {
	570	/* restore core index */
	571	if (origidx != coreidx)
	572	ai_setcoreidx(&sii->pub, origidx);
	573
	574	INTR_RESTORE(sii, intr_val);
	575	}
	576
90ea2296	577	return w;
a9533e7e HP	578	}
a9533e7e HP	579
66cbd3ab	580	void ai_core_disable(si_t *sih, u32 bits)
a9533e7e HP	581	{
a9533e7e HP	582	si_info_t *sii;
66cbd3ab	583	volatile u32 dummy;
a9533e7e HP	584	aidmp_t *ai;
	585
	586	sii = SI_INFO(sih);
	587
	588	ASSERT(GOODREGS(sii->curwrap));
	589	ai = sii->curwrap;
	590
	591	/* if core is already in reset, just return */
	592	if (R_REG(sii->osh, &ai->resetctrl) & AIRC_RESET)
	593	return;
	594
	595	W_REG(sii->osh, &ai->ioctrl, bits);
	596	dummy = R_REG(sii->osh, &ai->ioctrl);
7383141b	597	udelay(10);
a9533e7e HP	598
a9533e7e HP	599	W_REG(sii->osh, &ai->resetctrl, AIRC_RESET);
7383141b	600	udelay(1);
a9533e7e HP	601	}
	602
	603	/* reset and re-enable a core
	604	* inputs:
	605	* bits - core specific bits that are set during and after reset sequence
	606	* resetbits - core specific bits that are set only during reset sequence
	607	*/
66cbd3ab	608	void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
a9533e7e HP	609	{
	610	si_info_t *sii;
	611	aidmp_t *ai;
66cbd3ab	612	volatile u32 dummy;
a9533e7e HP	613
	614	sii = SI_INFO(sih);
	615	ASSERT(GOODREGS(sii->curwrap));
	616	ai = sii->curwrap;
	617
	618	/*
	619	* Must do the disable sequence first to work for arbitrary current core state.
	620	*/
	621	ai_core_disable(sih, (bits \| resetbits));
	622
	623	/*
	624	* Now do the initialization sequence.
	625	*/
	626	W_REG(sii->osh, &ai->ioctrl, (bits \| SICF_FGC \| SICF_CLOCK_EN));
	627	dummy = R_REG(sii->osh, &ai->ioctrl);
	628	W_REG(sii->osh, &ai->resetctrl, 0);
7383141b	629	udelay(1);
a9533e7e HP	630
	631	W_REG(sii->osh, &ai->ioctrl, (bits \| SICF_CLOCK_EN));
	632	dummy = R_REG(sii->osh, &ai->ioctrl);
7383141b	633	udelay(1);
a9533e7e HP	634	}
a9533e7e HP	635
66cbd3ab	636	void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
a9533e7e HP	637	{
	638	si_info_t *sii;
	639	aidmp_t *ai;
66cbd3ab	640	u32 w;
a9533e7e HP	641
	642	sii = SI_INFO(sih);
	643
	644	if (BCM47162_DMP()) {
	645	SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
	646	__func__));
	647	return;
	648	}
	649
	650	ASSERT(GOODREGS(sii->curwrap));
	651	ai = sii->curwrap;
	652
	653	ASSERT((val & ~mask) == 0);
	654
	655	if (mask \|\| val) {
	656	w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) \| val);
	657	W_REG(sii->osh, &ai->ioctrl, w);
	658	}
	659	}
	660
66cbd3ab	661	u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
a9533e7e HP	662	{
	663	si_info_t *sii;
	664	aidmp_t *ai;
66cbd3ab	665	u32 w;
a9533e7e HP	666
	667	sii = SI_INFO(sih);
	668	if (BCM47162_DMP()) {
	669	SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
	670	__func__));
	671	return 0;
	672	}
	673
	674	ASSERT(GOODREGS(sii->curwrap));
	675	ai = sii->curwrap;
	676
	677	ASSERT((val & ~mask) == 0);
	678
	679	if (mask \|\| val) {
	680	w = ((R_REG(sii->osh, &ai->ioctrl) & ~mask) \| val);
	681	W_REG(sii->osh, &ai->ioctrl, w);
	682	}
	683
	684	return R_REG(sii->osh, &ai->ioctrl);
	685	}
	686
66cbd3ab	687	u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
a9533e7e HP	688	{
	689	si_info_t *sii;
	690	aidmp_t *ai;
66cbd3ab	691	u32 w;
a9533e7e HP	692
	693	sii = SI_INFO(sih);
	694	if (BCM47162_DMP()) {
	695	SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
	696	return 0;
	697	}
	698
	699	ASSERT(GOODREGS(sii->curwrap));
	700	ai = sii->curwrap;
	701
	702	ASSERT((val & ~mask) == 0);
	703	ASSERT((mask & ~SISF_CORE_BITS) == 0);
	704
	705	if (mask \|\| val) {
	706	w = ((R_REG(sii->osh, &ai->iostatus) & ~mask) \| val);
	707	W_REG(sii->osh, &ai->iostatus, w);
	708	}
	709
	710	return R_REG(sii->osh, &ai->iostatus);
	711	}
	712