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abefd674 GBY |
1 | /* |
2 | * Copyright (C) 2012-2017 ARM Limited or its affiliates. | |
c8f17865 | 3 | * |
abefd674 GBY |
4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
c8f17865 | 7 | * |
abefd674 GBY |
8 | * This program is distributed in the hope that it will be useful, |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
c8f17865 | 12 | * |
abefd674 GBY |
13 | * You should have received a copy of the GNU General Public License |
14 | * along with this program; if not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #ifndef __CC_HW_QUEUE_DEFS_H__ | |
18 | #define __CC_HW_QUEUE_DEFS_H__ | |
19 | ||
a1ab41eb GBY |
20 | #include <linux/types.h> |
21 | ||
abefd674 | 22 | #include "dx_crys_kernel.h" |
ed744391 | 23 | #include <linux/bitfield.h> |
abefd674 | 24 | |
abefd674 | 25 | /****************************************************************************** |
8b64e512 GBY |
26 | * DEFINITIONS |
27 | ******************************************************************************/ | |
abefd674 GBY |
28 | |
29 | #define HW_DESC_SIZE_WORDS 6 | |
30 | #define HW_QUEUE_SLOTS_MAX 15 /* Max. available slots in HW queue */ | |
31 | ||
8b64e512 GBY |
32 | #define CC_REG_NAME(word, name) DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name |
33 | ||
34 | #define CC_REG_LOW(word, name) \ | |
35 | (DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SHIFT) | |
36 | ||
37 | #define CC_REG_HIGH(word, name) \ | |
38 | (CC_REG_LOW(word, name) + \ | |
39 | DX_DSCRPTR_QUEUE_WORD ## word ## _ ## name ## _BIT_SIZE - 1) | |
40 | ||
41 | #define CC_GENMASK(word, name) \ | |
42 | GENMASK(CC_REG_HIGH(word, name), CC_REG_LOW(word, name)) | |
43 | ||
44 | #define WORD0_VALUE CC_GENMASK(0, VALUE) | |
45 | #define WORD1_DIN_CONST_VALUE CC_GENMASK(1, DIN_CONST_VALUE) | |
46 | #define WORD1_DIN_DMA_MODE CC_GENMASK(1, DIN_DMA_MODE) | |
47 | #define WORD1_DIN_SIZE CC_GENMASK(1, DIN_SIZE) | |
48 | #define WORD1_NOT_LAST CC_GENMASK(1, NOT_LAST) | |
49 | #define WORD1_NS_BIT CC_GENMASK(1, NS_BIT) | |
50 | #define WORD2_VALUE CC_GENMASK(2, VALUE) | |
51 | #define WORD3_DOUT_DMA_MODE CC_GENMASK(3, DOUT_DMA_MODE) | |
52 | #define WORD3_DOUT_LAST_IND CC_GENMASK(3, DOUT_LAST_IND) | |
53 | #define WORD3_DOUT_SIZE CC_GENMASK(3, DOUT_SIZE) | |
54 | #define WORD3_HASH_XOR_BIT CC_GENMASK(3, HASH_XOR_BIT) | |
55 | #define WORD3_NS_BIT CC_GENMASK(3, NS_BIT) | |
56 | #define WORD3_QUEUE_LAST_IND CC_GENMASK(3, QUEUE_LAST_IND) | |
57 | #define WORD4_ACK_NEEDED CC_GENMASK(4, ACK_NEEDED) | |
58 | #define WORD4_AES_SEL_N_HASH CC_GENMASK(4, AES_SEL_N_HASH) | |
59 | #define WORD4_BYTES_SWAP CC_GENMASK(4, BYTES_SWAP) | |
60 | #define WORD4_CIPHER_CONF0 CC_GENMASK(4, CIPHER_CONF0) | |
61 | #define WORD4_CIPHER_CONF1 CC_GENMASK(4, CIPHER_CONF1) | |
62 | #define WORD4_CIPHER_CONF2 CC_GENMASK(4, CIPHER_CONF2) | |
63 | #define WORD4_CIPHER_DO CC_GENMASK(4, CIPHER_DO) | |
64 | #define WORD4_CIPHER_MODE CC_GENMASK(4, CIPHER_MODE) | |
65 | #define WORD4_CMAC_SIZE0 CC_GENMASK(4, CMAC_SIZE0) | |
66 | #define WORD4_DATA_FLOW_MODE CC_GENMASK(4, DATA_FLOW_MODE) | |
67 | #define WORD4_KEY_SIZE CC_GENMASK(4, KEY_SIZE) | |
68 | #define WORD4_SETUP_OPERATION CC_GENMASK(4, SETUP_OPERATION) | |
69 | #define WORD5_DIN_ADDR_HIGH CC_GENMASK(5, DIN_ADDR_HIGH) | |
70 | #define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH) | |
71 | ||
abefd674 | 72 | /****************************************************************************** |
8b64e512 GBY |
73 | * TYPE DEFINITIONS |
74 | ******************************************************************************/ | |
abefd674 | 75 | |
8ca57f5c | 76 | struct cc_hw_desc { |
8b64e512 GBY |
77 | union { |
78 | u32 word[HW_DESC_SIZE_WORDS]; | |
79 | u16 hword[HW_DESC_SIZE_WORDS * 2]; | |
80 | }; | |
81 | }; | |
82 | ||
83 | enum cc_axi_sec { | |
84 | AXI_SECURE = 0, | |
85 | AXI_NOT_SECURE = 1 | |
8ca57f5c | 86 | }; |
abefd674 | 87 | |
8ca57f5c | 88 | enum cc_desc_direction { |
abefd674 GBY |
89 | DESC_DIRECTION_ILLEGAL = -1, |
90 | DESC_DIRECTION_ENCRYPT_ENCRYPT = 0, | |
91 | DESC_DIRECTION_DECRYPT_DECRYPT = 1, | |
92 | DESC_DIRECTION_DECRYPT_ENCRYPT = 3, | |
a1ab41eb | 93 | DESC_DIRECTION_END = S32_MAX, |
8ca57f5c | 94 | }; |
abefd674 | 95 | |
8ca57f5c | 96 | enum cc_dma_mode { |
abefd674 | 97 | DMA_MODE_NULL = -1, |
e3f25f79 | 98 | NO_DMA = 0, |
abefd674 GBY |
99 | DMA_SRAM = 1, |
100 | DMA_DLLI = 2, | |
101 | DMA_MLLI = 3, | |
e3f25f79 | 102 | DMA_MODE_END = S32_MAX, |
8ca57f5c | 103 | }; |
abefd674 | 104 | |
8ca57f5c | 105 | enum cc_flow_mode { |
abefd674 GBY |
106 | FLOW_MODE_NULL = -1, |
107 | /* data flows */ | |
e3f25f79 | 108 | BYPASS = 0, |
abefd674 GBY |
109 | DIN_AES_DOUT = 1, |
110 | AES_to_HASH = 2, | |
111 | AES_and_HASH = 3, | |
112 | DIN_DES_DOUT = 4, | |
113 | DES_to_HASH = 5, | |
114 | DES_and_HASH = 6, | |
115 | DIN_HASH = 7, | |
116 | DIN_HASH_and_BYPASS = 8, | |
117 | AESMAC_and_BYPASS = 9, | |
118 | AES_to_HASH_and_DOUT = 10, | |
119 | DIN_RC4_DOUT = 11, | |
120 | DES_to_HASH_and_DOUT = 12, | |
121 | AES_to_AES_to_HASH_and_DOUT = 13, | |
122 | AES_to_AES_to_HASH = 14, | |
123 | AES_to_HASH_and_AES = 15, | |
124 | DIN_MULTI2_DOUT = 16, | |
125 | DIN_AES_AESMAC = 17, | |
126 | HASH_to_DOUT = 18, | |
127 | /* setup flows */ | |
e3f25f79 | 128 | S_DIN_to_AES = 32, |
abefd674 GBY |
129 | S_DIN_to_AES2 = 33, |
130 | S_DIN_to_DES = 34, | |
131 | S_DIN_to_RC4 = 35, | |
e3f25f79 | 132 | S_DIN_to_MULTI2 = 36, |
abefd674 GBY |
133 | S_DIN_to_HASH = 37, |
134 | S_AES_to_DOUT = 38, | |
135 | S_AES2_to_DOUT = 39, | |
136 | S_RC4_to_DOUT = 41, | |
137 | S_DES_to_DOUT = 42, | |
138 | S_HASH_to_DOUT = 43, | |
139 | SET_FLOW_ID = 44, | |
8ca57f5c GBY |
140 | FLOW_MODE_END = S32_MAX, |
141 | }; | |
abefd674 | 142 | |
8ca57f5c | 143 | enum cc_tunnel_op { |
abefd674 GBY |
144 | TUNNEL_OP_INVALID = -1, |
145 | TUNNEL_OFF = 0, | |
146 | TUNNEL_ON = 1, | |
8ca57f5c GBY |
147 | TUNNEL_OP_END = S32_MAX, |
148 | }; | |
abefd674 | 149 | |
8ca57f5c | 150 | enum cc_setup_op { |
abefd674 GBY |
151 | SETUP_LOAD_NOP = 0, |
152 | SETUP_LOAD_STATE0 = 1, | |
153 | SETUP_LOAD_STATE1 = 2, | |
154 | SETUP_LOAD_STATE2 = 3, | |
155 | SETUP_LOAD_KEY0 = 4, | |
156 | SETUP_LOAD_XEX_KEY = 5, | |
c8f17865 | 157 | SETUP_WRITE_STATE0 = 8, |
abefd674 GBY |
158 | SETUP_WRITE_STATE1 = 9, |
159 | SETUP_WRITE_STATE2 = 10, | |
160 | SETUP_WRITE_STATE3 = 11, | |
8ca57f5c GBY |
161 | SETUP_OP_END = S32_MAX, |
162 | }; | |
abefd674 | 163 | |
8ca57f5c | 164 | enum cc_aes_mac_selector { |
abefd674 GBY |
165 | AES_SK = 1, |
166 | AES_CMAC_INIT = 2, | |
167 | AES_CMAC_SIZE0 = 3, | |
8ca57f5c | 168 | AES_MAC_END = S32_MAX, |
abefd674 GBY |
169 | }; |
170 | ||
e3f25f79 | 171 | #define HW_KEY_MASK_CIPHER_DO 0x3 |
abefd674 GBY |
172 | #define HW_KEY_SHIFT_CIPHER_CFG2 2 |
173 | ||
abefd674 GBY |
174 | /* HwCryptoKey[1:0] is mapped to cipher_do[1:0] */ |
175 | /* HwCryptoKey[2:3] is mapped to cipher_config2[1:0] */ | |
8ca57f5c | 176 | enum cc_hw_crypto_key { |
abefd674 GBY |
177 | USER_KEY = 0, /* 0x0000 */ |
178 | ROOT_KEY = 1, /* 0x0001 */ | |
179 | PROVISIONING_KEY = 2, /* 0x0010 */ /* ==KCP */ | |
180 | SESSION_KEY = 3, /* 0x0011 */ | |
181 | RESERVED_KEY = 4, /* NA */ | |
182 | PLATFORM_KEY = 5, /* 0x0101 */ | |
183 | CUSTOMER_KEY = 6, /* 0x0110 */ | |
184 | KFDE0_KEY = 7, /* 0x0111 */ | |
185 | KFDE1_KEY = 9, /* 0x1001 */ | |
186 | KFDE2_KEY = 10, /* 0x1010 */ | |
187 | KFDE3_KEY = 11, /* 0x1011 */ | |
a1ab41eb | 188 | END_OF_KEYS = S32_MAX, |
8ca57f5c | 189 | }; |
abefd674 | 190 | |
8ca57f5c | 191 | enum cc_hw_aes_key_size { |
abefd674 GBY |
192 | AES_128_KEY = 0, |
193 | AES_192_KEY = 1, | |
194 | AES_256_KEY = 2, | |
a1ab41eb | 195 | END_OF_AES_KEYS = S32_MAX, |
8ca57f5c | 196 | }; |
abefd674 | 197 | |
8ca57f5c | 198 | enum cc_hw_des_key_size { |
abefd674 GBY |
199 | DES_ONE_KEY = 0, |
200 | DES_TWO_KEYS = 1, | |
201 | DES_THREE_KEYS = 2, | |
a1ab41eb | 202 | END_OF_DES_KEYS = S32_MAX, |
8ca57f5c | 203 | }; |
abefd674 GBY |
204 | |
205 | /*****************************/ | |
206 | /* Descriptor packing macros */ | |
207 | /*****************************/ | |
208 | ||
8b64e512 GBY |
209 | /* |
210 | * Init a HW descriptor struct | |
211 | * @pdesc: pointer HW descriptor struct | |
212 | */ | |
213 | static inline void hw_desc_init(struct cc_hw_desc *pdesc) | |
214 | { | |
215 | memset(pdesc, 0, sizeof(struct cc_hw_desc)); | |
216 | } | |
abefd674 | 217 | |
8b64e512 GBY |
218 | /* |
219 | * Indicates the end of current HW descriptors flow and release the HW engines. | |
c8f17865 | 220 | * |
8b64e512 | 221 | * @pdesc: pointer HW descriptor struct |
abefd674 | 222 | */ |
8b64e512 GBY |
223 | static inline void set_queue_last_ind(struct cc_hw_desc *pdesc) |
224 | { | |
225 | pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); | |
226 | } | |
abefd674 | 227 | |
8b64e512 GBY |
228 | /* |
229 | * Set the DIN field of a HW descriptors | |
c8f17865 | 230 | * |
8b64e512 GBY |
231 | * @pdesc: pointer HW descriptor struct |
232 | * @dma_mode: dmaMode The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT | |
233 | * @addr: dinAdr DIN address | |
234 | * @size: Data size in bytes | |
235 | * @axi_sec: AXI secure bit | |
236 | */ | |
237 | static inline void set_din_type(struct cc_hw_desc *pdesc, | |
238 | enum cc_dma_mode dma_mode, dma_addr_t addr, | |
239 | u32 size, enum cc_axi_sec axi_sec) | |
240 | { | |
241 | pdesc->word[0] = (u32)addr; | |
242 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
243 | pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32))); | |
244 | #endif | |
245 | pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | | |
246 | FIELD_PREP(WORD1_DIN_SIZE, size) | | |
247 | FIELD_PREP(WORD1_NS_BIT, axi_sec); | |
248 | } | |
abefd674 | 249 | |
8b64e512 GBY |
250 | /* |
251 | * Set the DIN field of a HW descriptors to NO DMA mode. | |
252 | * Used for NOP descriptor, register patches and other special modes. | |
c8f17865 | 253 | * |
8b64e512 GBY |
254 | * @pdesc: pointer HW descriptor struct |
255 | * @addr: DIN address | |
256 | * @size: Data size in bytes | |
abefd674 | 257 | */ |
8b64e512 GBY |
258 | static inline void set_din_no_dma(struct cc_hw_desc *pdesc, u32 addr, u32 size) |
259 | { | |
260 | pdesc->word[0] = addr; | |
261 | pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); | |
262 | } | |
abefd674 | 263 | |
8b64e512 GBY |
264 | /* |
265 | * Set the DIN field of a HW descriptors to SRAM mode. | |
c8f17865 TI |
266 | * Note: No need to check SRAM alignment since host requests do not use SRAM and |
267 | * adaptor will enforce alignment check. | |
268 | * | |
8b64e512 GBY |
269 | * @pdesc: pointer HW descriptor struct |
270 | * @addr: DIN address | |
271 | * @size Data size in bytes | |
abefd674 | 272 | */ |
8b64e512 GBY |
273 | static inline void set_din_sram(struct cc_hw_desc *pdesc, dma_addr_t addr, |
274 | u32 size) | |
275 | { | |
276 | pdesc->word[0] = (u32)addr; | |
277 | pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | | |
278 | FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM); | |
279 | } | |
abefd674 | 280 | |
8b64e512 GBY |
281 | /* |
282 | * Set the DIN field of a HW descriptors to CONST mode | |
c8f17865 | 283 | * |
8b64e512 GBY |
284 | * @pdesc: pointer HW descriptor struct |
285 | * @val: DIN const value | |
286 | * @size: Data size in bytes | |
abefd674 | 287 | */ |
8b64e512 GBY |
288 | static inline void set_din_const(struct cc_hw_desc *pdesc, u32 val, u32 size) |
289 | { | |
290 | pdesc->word[0] = val; | |
291 | pdesc->word[1] |= FIELD_PREP(WORD1_DIN_CONST_VALUE, 1) | | |
292 | FIELD_PREP(WORD1_DIN_DMA_MODE, DMA_SRAM) | | |
293 | FIELD_PREP(WORD1_DIN_SIZE, size); | |
294 | } | |
abefd674 | 295 | |
8b64e512 GBY |
296 | /* |
297 | * Set the DIN not last input data indicator | |
c8f17865 | 298 | * |
8b64e512 | 299 | * @pdesc: pointer HW descriptor struct |
abefd674 | 300 | */ |
8b64e512 GBY |
301 | static inline void set_din_not_last_indication(struct cc_hw_desc *pdesc) |
302 | { | |
303 | pdesc->word[1] |= FIELD_PREP(WORD1_NOT_LAST, 1); | |
304 | } | |
abefd674 | 305 | |
8b64e512 GBY |
306 | /* |
307 | * Set the DOUT field of a HW descriptors | |
c8f17865 | 308 | * |
8b64e512 GBY |
309 | * @pdesc: pointer HW descriptor struct |
310 | * @dma_mode: The DMA mode: NO_DMA, SRAM, DLLI, MLLI, CONSTANT | |
311 | * @addr: DOUT address | |
312 | * @size: Data size in bytes | |
313 | * @axi_sec: AXI secure bit | |
abefd674 | 314 | */ |
8b64e512 GBY |
315 | static inline void set_dout_type(struct cc_hw_desc *pdesc, |
316 | enum cc_dma_mode dma_mode, dma_addr_t addr, | |
317 | u32 size, enum cc_axi_sec axi_sec) | |
318 | { | |
319 | pdesc->word[2] = (u32)addr; | |
320 | #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT | |
321 | pdesc->word[5] |= FIELD_PREP(WORD5_DOUT_ADDR_HIGH, ((u16)(addr >> 32))); | |
322 | #endif | |
323 | pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, dma_mode) | | |
324 | FIELD_PREP(WORD3_DOUT_SIZE, size) | | |
325 | FIELD_PREP(WORD3_NS_BIT, axi_sec); | |
326 | } | |
abefd674 | 327 | |
8b64e512 GBY |
328 | /* |
329 | * Set the DOUT field of a HW descriptors to DLLI type | |
c8f17865 TI |
330 | * The LAST INDICATION is provided by the user |
331 | * | |
8b64e512 GBY |
332 | * @pdesc pointer HW descriptor struct |
333 | * @addr: DOUT address | |
334 | * @size: Data size in bytes | |
335 | * @last_ind: The last indication bit | |
336 | * @axi_sec: AXI secure bit | |
337 | */ | |
338 | static inline void set_dout_dlli(struct cc_hw_desc *pdesc, dma_addr_t addr, | |
339 | u32 size, enum cc_axi_sec axi_sec, | |
340 | u32 last_ind) | |
341 | { | |
342 | set_dout_type(pdesc, DMA_DLLI, addr, size, axi_sec); | |
343 | pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); | |
344 | } | |
abefd674 | 345 | |
8b64e512 GBY |
346 | /* |
347 | * Set the DOUT field of a HW descriptors to DLLI type | |
c8f17865 TI |
348 | * The LAST INDICATION is provided by the user |
349 | * | |
8b64e512 GBY |
350 | * @pdesc: pointer HW descriptor struct |
351 | * @addr: DOUT address | |
352 | * @size: Data size in bytes | |
353 | * @last_ind: The last indication bit | |
354 | * @axi_sec: AXI secure bit | |
355 | */ | |
356 | static inline void set_dout_mlli(struct cc_hw_desc *pdesc, dma_addr_t addr, | |
357 | u32 size, enum cc_axi_sec axi_sec, | |
358 | bool last_ind) | |
359 | { | |
360 | set_dout_type(pdesc, DMA_MLLI, addr, size, axi_sec); | |
361 | pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_LAST_IND, last_ind); | |
362 | } | |
abefd674 | 363 | |
8b64e512 GBY |
364 | /* |
365 | * Set the DOUT field of a HW descriptors to NO DMA mode. | |
366 | * Used for NOP descriptor, register patches and other special modes. | |
c8f17865 | 367 | * |
8b64e512 GBY |
368 | * @pdesc: pointer HW descriptor struct |
369 | * @addr: DOUT address | |
370 | * @size: Data size in bytes | |
371 | * @write_enable: Enables a write operation to a register | |
372 | */ | |
373 | static inline void set_dout_no_dma(struct cc_hw_desc *pdesc, u32 addr, | |
374 | u32 size, bool write_enable) | |
375 | { | |
376 | pdesc->word[2] = addr; | |
377 | pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_SIZE, size) | | |
378 | FIELD_PREP(WORD3_DOUT_LAST_IND, write_enable); | |
379 | } | |
abefd674 | 380 | |
8b64e512 GBY |
381 | /* |
382 | * Set the word for the XOR operation. | |
c8f17865 | 383 | * |
8b64e512 GBY |
384 | * @pdesc: pointer HW descriptor struct |
385 | * @val: xor data value | |
abefd674 | 386 | */ |
8b64e512 GBY |
387 | static inline void set_xor_val(struct cc_hw_desc *pdesc, u32 val) |
388 | { | |
389 | pdesc->word[2] = val; | |
390 | } | |
abefd674 | 391 | |
8b64e512 GBY |
392 | /* |
393 | * Sets the XOR indicator bit in the descriptor | |
c8f17865 | 394 | * |
8b64e512 | 395 | * @pdesc: pointer HW descriptor struct |
abefd674 | 396 | */ |
8b64e512 GBY |
397 | static inline void set_xor_active(struct cc_hw_desc *pdesc) |
398 | { | |
399 | pdesc->word[3] |= FIELD_PREP(WORD3_HASH_XOR_BIT, 1); | |
400 | } | |
abefd674 | 401 | |
8b64e512 GBY |
402 | /* |
403 | * Select the AES engine instead of HASH engine when setting up combined mode | |
404 | * with AES XCBC MAC | |
c8f17865 | 405 | * |
8b64e512 | 406 | * @pdesc: pointer HW descriptor struct |
abefd674 | 407 | */ |
8b64e512 GBY |
408 | static inline void set_aes_not_hash_mode(struct cc_hw_desc *pdesc) |
409 | { | |
410 | pdesc->word[4] |= FIELD_PREP(WORD4_AES_SEL_N_HASH, 1); | |
411 | } | |
abefd674 | 412 | |
8b64e512 GBY |
413 | /* |
414 | * Set the DOUT field of a HW descriptors to SRAM mode | |
c8f17865 TI |
415 | * Note: No need to check SRAM alignment since host requests do not use SRAM and |
416 | * adaptor will enforce alignment check. | |
417 | * | |
8b64e512 GBY |
418 | * @pdesc: pointer HW descriptor struct |
419 | * @addr: DOUT address | |
420 | * @size: Data size in bytes | |
abefd674 | 421 | */ |
8b64e512 GBY |
422 | static inline void set_dout_sram(struct cc_hw_desc *pdesc, u32 addr, u32 size) |
423 | { | |
424 | pdesc->word[2] = addr; | |
425 | pdesc->word[3] |= FIELD_PREP(WORD3_DOUT_DMA_MODE, DMA_SRAM) | | |
426 | FIELD_PREP(WORD3_DOUT_SIZE, size); | |
427 | } | |
abefd674 | 428 | |
8b64e512 GBY |
429 | /* |
430 | * Sets the data unit size for XEX mode in data_out_addr[15:0] | |
c8f17865 | 431 | * |
8b64e512 GBY |
432 | * @pdesc: pDesc pointer HW descriptor struct |
433 | * @size: data unit size for XEX mode | |
abefd674 | 434 | */ |
8b64e512 GBY |
435 | static inline void set_xex_data_unit_size(struct cc_hw_desc *pdesc, u32 size) |
436 | { | |
437 | pdesc->word[2] = size; | |
438 | } | |
abefd674 | 439 | |
8b64e512 GBY |
440 | /* |
441 | * Set the number of rounds for Multi2 in data_out_addr[15:0] | |
abefd674 | 442 | * |
8b64e512 GBY |
443 | * @pdesc: pointer HW descriptor struct |
444 | * @num: number of rounds for Multi2 | |
ed5210cb | 445 | */ |
8b64e512 GBY |
446 | static inline void set_multi2_num_rounds(struct cc_hw_desc *pdesc, u32 num) |
447 | { | |
448 | pdesc->word[2] = num; | |
449 | } | |
abefd674 | 450 | |
8b64e512 GBY |
451 | /* |
452 | * Set the flow mode. | |
abefd674 | 453 | * |
8b64e512 GBY |
454 | * @pdesc: pointer HW descriptor struct |
455 | * @mode: Any one of the modes defined in [CC7x-DESC] | |
ed5210cb | 456 | */ |
8b64e512 GBY |
457 | static inline void set_flow_mode(struct cc_hw_desc *pdesc, |
458 | enum cc_flow_mode mode) | |
459 | { | |
460 | pdesc->word[4] |= FIELD_PREP(WORD4_DATA_FLOW_MODE, mode); | |
461 | } | |
abefd674 | 462 | |
8b64e512 GBY |
463 | /* |
464 | * Set the cipher mode. | |
465 | * | |
466 | * @pdesc: pointer HW descriptor struct | |
467 | * @mode: Any one of the modes defined in [CC7x-DESC] | |
468 | */ | |
469 | static inline void set_cipher_mode(struct cc_hw_desc *pdesc, | |
470 | enum drv_cipher_mode mode) | |
471 | { | |
472 | pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_MODE, mode); | |
473 | } | |
abefd674 | 474 | |
8b64e512 GBY |
475 | /* |
476 | * Set the cipher configuration fields. | |
abefd674 | 477 | * |
8b64e512 GBY |
478 | * @pdesc: pointer HW descriptor struct |
479 | * @mode: Any one of the modes defined in [CC7x-DESC] | |
ed5210cb | 480 | */ |
8b64e512 GBY |
481 | static inline void set_cipher_config0(struct cc_hw_desc *pdesc, |
482 | enum drv_crypto_direction mode) | |
483 | { | |
484 | pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF0, mode); | |
485 | } | |
abefd674 | 486 | |
8b64e512 GBY |
487 | /* |
488 | * Set the cipher configuration fields. | |
abefd674 | 489 | * |
8b64e512 GBY |
490 | * @pdesc: pointer HW descriptor struct |
491 | * @config: Any one of the modes defined in [CC7x-DESC] | |
ed5210cb | 492 | */ |
8b64e512 | 493 | static inline void set_cipher_config1(struct cc_hw_desc *pdesc, |
84d69a7b | 494 | enum cc_hash_conf_pad config) |
8b64e512 GBY |
495 | { |
496 | pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_CONF1, config); | |
497 | } | |
abefd674 | 498 | |
8b64e512 GBY |
499 | /* |
500 | * Set HW key configuration fields. | |
abefd674 | 501 | * |
8b64e512 GBY |
502 | * @pdesc: pointer HW descriptor struct |
503 | * @hw_key: The HW key slot asdefined in enum cc_hw_crypto_key | |
ed5210cb | 504 | */ |
8b64e512 GBY |
505 | static inline void set_hw_crypto_key(struct cc_hw_desc *pdesc, |
506 | enum cc_hw_crypto_key hw_key) | |
507 | { | |
508 | pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, | |
509 | (hw_key & HW_KEY_MASK_CIPHER_DO)) | | |
510 | FIELD_PREP(WORD4_CIPHER_CONF2, | |
511 | (hw_key >> HW_KEY_SHIFT_CIPHER_CFG2)); | |
512 | } | |
abefd674 | 513 | |
8b64e512 GBY |
514 | /* |
515 | * Set byte order of all setup-finalize descriptors. | |
abefd674 | 516 | * |
8b64e512 GBY |
517 | * @pdesc: pointer HW descriptor struct |
518 | * @config: Any one of the modes defined in [CC7x-DESC] | |
ed5210cb | 519 | */ |
8b64e512 GBY |
520 | static inline void set_bytes_swap(struct cc_hw_desc *pdesc, bool config) |
521 | { | |
522 | pdesc->word[4] |= FIELD_PREP(WORD4_BYTES_SWAP, config); | |
523 | } | |
abefd674 | 524 | |
8b64e512 GBY |
525 | /* |
526 | * Set CMAC_SIZE0 mode. | |
abefd674 | 527 | * |
8b64e512 | 528 | * @pdesc: pointer HW descriptor struct |
ed5210cb | 529 | */ |
8b64e512 GBY |
530 | static inline void set_cmac_size0_mode(struct cc_hw_desc *pdesc) |
531 | { | |
532 | pdesc->word[4] |= FIELD_PREP(WORD4_CMAC_SIZE0, 1); | |
533 | } | |
abefd674 | 534 | |
8b64e512 GBY |
535 | /* |
536 | * Set key size descriptor field. | |
abefd674 | 537 | * |
8b64e512 GBY |
538 | * @pdesc: pointer HW descriptor struct |
539 | * @size: key size in bytes (NOT size code) | |
ed5210cb | 540 | */ |
8b64e512 GBY |
541 | static inline void set_key_size(struct cc_hw_desc *pdesc, u32 size) |
542 | { | |
543 | pdesc->word[4] |= FIELD_PREP(WORD4_KEY_SIZE, size); | |
544 | } | |
abefd674 | 545 | |
8b64e512 GBY |
546 | /* |
547 | * Set AES key size. | |
abefd674 | 548 | * |
8b64e512 GBY |
549 | * @pdesc: pointer HW descriptor struct |
550 | * @size: key size in bytes (NOT size code) | |
ed5210cb | 551 | */ |
8b64e512 GBY |
552 | static inline void set_key_size_aes(struct cc_hw_desc *pdesc, u32 size) |
553 | { | |
554 | set_key_size(pdesc, ((size >> 3) - 2)); | |
555 | } | |
abefd674 | 556 | |
8b64e512 GBY |
557 | /* |
558 | * Set DES key size. | |
abefd674 | 559 | * |
8b64e512 GBY |
560 | * @pdesc: pointer HW descriptor struct |
561 | * @size: key size in bytes (NOT size code) | |
ed5210cb | 562 | */ |
8b64e512 GBY |
563 | static inline void set_key_size_des(struct cc_hw_desc *pdesc, u32 size) |
564 | { | |
565 | set_key_size(pdesc, ((size >> 3) - 1)); | |
566 | } | |
abefd674 | 567 | |
8b64e512 GBY |
568 | /* |
569 | * Set the descriptor setup mode | |
abefd674 | 570 | * |
8b64e512 GBY |
571 | * @pdesc: pointer HW descriptor struct |
572 | * @mode: Any one of the setup modes defined in [CC7x-DESC] | |
ed5210cb | 573 | */ |
8b64e512 GBY |
574 | static inline void set_setup_mode(struct cc_hw_desc *pdesc, |
575 | enum cc_setup_op mode) | |
576 | { | |
577 | pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, mode); | |
578 | } | |
abefd674 | 579 | |
8b64e512 GBY |
580 | /* |
581 | * Set the descriptor cipher DO | |
abefd674 | 582 | * |
8b64e512 GBY |
583 | * @pdesc: pointer HW descriptor struct |
584 | * @config: Any one of the cipher do defined in [CC7x-DESC] | |
ed5210cb | 585 | */ |
8b64e512 | 586 | static inline void set_cipher_do(struct cc_hw_desc *pdesc, |
84d69a7b | 587 | enum cc_hash_cipher_pad config) |
8b64e512 GBY |
588 | { |
589 | pdesc->word[4] |= FIELD_PREP(WORD4_CIPHER_DO, | |
590 | (config & HW_KEY_MASK_CIPHER_DO)); | |
591 | } | |
abefd674 | 592 | |
abefd674 | 593 | #endif /*__CC_HW_QUEUE_DEFS_H__*/ |