[mirror_ubuntu-hirsute-kernel.git] / drivers / staging / comedi / drivers / 8255_pci.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * COMEDI driver for generic PCI based 8255 digital i/o boards
 * Copyright (C) 2012 H Hartley Sweeten <hsweeten@visionengravers.com>
 *
 * Based on the tested adl_pci7296 driver written by:
 *	Jon Grierson <jd@renko.co.uk>
 * and the experimental cb_pcidio driver written by:
 *	Yoshiya Matsuzaka
 *
 * COMEDI - Linux Control and Measurement Device Interface
 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
 */

/*
 * Driver: 8255_pci
 * Description: Generic PCI based 8255 Digital I/O boards
 * Devices: [ADLink] PCI-7224 (adl_pci-7224), PCI-7248 (adl_pci-7248),
 *   PCI-7296 (adl_pci-7296),
 *   [Measurement Computing] PCI-DIO24 (cb_pci-dio24),
 *   PCI-DIO24H (cb_pci-dio24h), PCI-DIO48H (cb_pci-dio48h),
 *   PCI-DIO96H (cb_pci-dio96h),
 *   [National Instruments] PCI-DIO-96 (ni_pci-dio-96),
 *   PCI-DIO-96B (ni_pci-dio-96b), PXI-6508 (ni_pxi-6508),
 *   PCI-6503 (ni_pci-6503), PCI-6503B (ni_pci-6503b),
 *   PCI-6503X (ni_pci-6503x), PXI-6503 (ni_pxi-6503)
 * Author: H Hartley Sweeten <hsweeten@visionengravers.com>
 * Updated: Wed, 12 Sep 2012 11:52:01 -0700
 * Status: untested
 *
 * These boards have one or more 8255 digital I/O chips, each of which
 * is supported as a separate 24-channel DIO subdevice.
 *
 * Boards with 24 DIO channels (1 DIO subdevice):
 *
 *   PCI-7224, PCI-DIO24, PCI-DIO24H, PCI-6503, PCI-6503B, PCI-6503X,
 *   PXI-6503
 *
 * Boards with 48 DIO channels (2 DIO subdevices):
 *
 *   PCI-7248, PCI-DIO48H
 *
 * Boards with 96 DIO channels (4 DIO subdevices):
 *
 *   PCI-7296, PCI-DIO96H, PCI-DIO-96, PCI-DIO-96B, PXI-6508
 *
 * Some of these boards also have an 8254 programmable timer/counter
 * chip.  This chip is not currently supported by this driver.
 *
 * Interrupt support for these boards is also not currently supported.
 *
 * Configuration Options: not applicable, uses PCI auto config.
 */

#include <linux/module.h>

#include "../comedi_pci.h"

#include "8255.h"

enum pci_8255_boardid {
	BOARD_ADLINK_PCI7224,
	BOARD_ADLINK_PCI7248,
	BOARD_ADLINK_PCI7296,
	BOARD_CB_PCIDIO24,
	BOARD_CB_PCIDIO24H,
	BOARD_CB_PCIDIO48H_OLD,
	BOARD_CB_PCIDIO48H_NEW,
	BOARD_CB_PCIDIO96H,
	BOARD_NI_PCIDIO96,
	BOARD_NI_PCIDIO96B,
	BOARD_NI_PXI6508,
	BOARD_NI_PCI6503,
	BOARD_NI_PCI6503B,
	BOARD_NI_PCI6503X,
	BOARD_NI_PXI_6503,
};

struct pci_8255_boardinfo {
	const char *name;
	int dio_badr;
	int n_8255;
	unsigned int has_mite:1;
};

static const struct pci_8255_boardinfo pci_8255_boards[] = {
	[BOARD_ADLINK_PCI7224] = {
		.name		= "adl_pci-7224",
		.dio_badr	= 2,
		.n_8255		= 1,
	},
	[BOARD_ADLINK_PCI7248] = {
		.name		= "adl_pci-7248",
		.dio_badr	= 2,
		.n_8255		= 2,
	},
	[BOARD_ADLINK_PCI7296] = {
		.name		= "adl_pci-7296",
		.dio_badr	= 2,
		.n_8255		= 4,
	},
	[BOARD_CB_PCIDIO24] = {
		.name		= "cb_pci-dio24",
		.dio_badr	= 2,
		.n_8255		= 1,
	},
	[BOARD_CB_PCIDIO24H] = {
		.name		= "cb_pci-dio24h",
		.dio_badr	= 2,
		.n_8255		= 1,
	},
	[BOARD_CB_PCIDIO48H_OLD] = {
		.name		= "cb_pci-dio48h",
		.dio_badr	= 1,
		.n_8255		= 2,
	},
	[BOARD_CB_PCIDIO48H_NEW] = {
		.name		= "cb_pci-dio48h",
		.dio_badr	= 2,
		.n_8255		= 2,
	},
	[BOARD_CB_PCIDIO96H] = {
		.name		= "cb_pci-dio96h",
		.dio_badr	= 2,
		.n_8255		= 4,
	},
	[BOARD_NI_PCIDIO96] = {
		.name		= "ni_pci-dio-96",
		.dio_badr	= 1,
		.n_8255		= 4,
		.has_mite	= 1,
	},
	[BOARD_NI_PCIDIO96B] = {
		.name		= "ni_pci-dio-96b",
		.dio_badr	= 1,
		.n_8255		= 4,
		.has_mite	= 1,
	},
	[BOARD_NI_PXI6508] = {
		.name		= "ni_pxi-6508",
		.dio_badr	= 1,
		.n_8255		= 4,
		.has_mite	= 1,
	},
	[BOARD_NI_PCI6503] = {
		.name		= "ni_pci-6503",
		.dio_badr	= 1,
		.n_8255		= 1,
		.has_mite	= 1,
	},
	[BOARD_NI_PCI6503B] = {
		.name		= "ni_pci-6503b",
		.dio_badr	= 1,
		.n_8255		= 1,
		.has_mite	= 1,
	},
	[BOARD_NI_PCI6503X] = {
		.name		= "ni_pci-6503x",
		.dio_badr	= 1,
		.n_8255		= 1,
		.has_mite	= 1,
	},
	[BOARD_NI_PXI_6503] = {
		.name		= "ni_pxi-6503",
		.dio_badr	= 1,
		.n_8255		= 1,
		.has_mite	= 1,
	},
};

/* ripped from mite.h and mite_setup2() to avoid mite dependency */
#define MITE_IODWBSR	0xc0	/* IO Device Window Base Size Register */
#define WENAB		BIT(7)	/* window enable */

static int pci_8255_mite_init(struct pci_dev *pcidev)
{
	void __iomem *mite_base;
	u32 main_phys_addr;

	/* ioremap the MITE registers (BAR 0) temporarily */
	mite_base = pci_ioremap_bar(pcidev, 0);
	if (!mite_base)
		return -ENOMEM;

	/* set data window to main registers (BAR 1) */
	main_phys_addr = pci_resource_start(pcidev, 1);
	writel(main_phys_addr | WENAB, mite_base + MITE_IODWBSR);

	/* finished with MITE registers */
	iounmap(mite_base);
	return 0;
}

static int pci_8255_auto_attach(struct comedi_device *dev,
				unsigned long context)
{
	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
	const struct pci_8255_boardinfo *board = NULL;
	struct comedi_subdevice *s;
	int ret;
	int i;

	if (context < ARRAY_SIZE(pci_8255_boards))
		board = &pci_8255_boards[context];
	if (!board)
		return -ENODEV;
	dev->board_ptr = board;
	dev->board_name = board->name;

	ret = comedi_pci_enable(dev);
	if (ret)
		return ret;

	if (board->has_mite) {
		ret = pci_8255_mite_init(pcidev);
		if (ret)
			return ret;
	}

	if ((pci_resource_flags(pcidev, board->dio_badr) & IORESOURCE_MEM)) {
		dev->mmio = pci_ioremap_bar(pcidev, board->dio_badr);
		if (!dev->mmio)
			return -ENOMEM;
	} else {
		dev->iobase = pci_resource_start(pcidev, board->dio_badr);
	}

	/*
	 * One, two, or four subdevices are setup by this driver depending
	 * on the number of channels provided by the board. Each subdevice
	 * has 24 channels supported by the 8255 module.
	 */
	ret = comedi_alloc_subdevices(dev, board->n_8255);
	if (ret)
		return ret;

	for (i = 0; i < board->n_8255; i++) {
		s = &dev->subdevices[i];
		if (dev->mmio)
			ret = subdev_8255_mm_init(dev, s, NULL, i * I8255_SIZE);
		else
			ret = subdev_8255_init(dev, s, NULL, i * I8255_SIZE);
		if (ret)
			return ret;
	}

	return 0;
}

static struct comedi_driver pci_8255_driver = {
	.driver_name	= "8255_pci",
	.module		= THIS_MODULE,
	.auto_attach	= pci_8255_auto_attach,
	.detach		= comedi_pci_detach,
};

static int pci_8255_pci_probe(struct pci_dev *dev,
			      const struct pci_device_id *id)
{
	return comedi_pci_auto_config(dev, &pci_8255_driver, id->driver_data);
}

static const struct pci_device_id pci_8255_pci_table[] = {
	{ PCI_VDEVICE(ADLINK, 0x7224), BOARD_ADLINK_PCI7224 },
	{ PCI_VDEVICE(ADLINK, 0x7248), BOARD_ADLINK_PCI7248 },
	{ PCI_VDEVICE(ADLINK, 0x7296), BOARD_ADLINK_PCI7296 },
	{ PCI_VDEVICE(CB, 0x0028), BOARD_CB_PCIDIO24 },
	{ PCI_VDEVICE(CB, 0x0014), BOARD_CB_PCIDIO24H },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CB, 0x000b, 0x0000, 0x0000),
	  .driver_data = BOARD_CB_PCIDIO48H_OLD },
	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CB, 0x000b, PCI_VENDOR_ID_CB, 0x000b),
	  .driver_data = BOARD_CB_PCIDIO48H_NEW },
	{ PCI_VDEVICE(CB, 0x0017), BOARD_CB_PCIDIO96H },
	{ PCI_VDEVICE(NI, 0x0160), BOARD_NI_PCIDIO96 },
	{ PCI_VDEVICE(NI, 0x1630), BOARD_NI_PCIDIO96B },
	{ PCI_VDEVICE(NI, 0x13c0), BOARD_NI_PXI6508 },
	{ PCI_VDEVICE(NI, 0x0400), BOARD_NI_PCI6503 },
	{ PCI_VDEVICE(NI, 0x1250), BOARD_NI_PCI6503B },
	{ PCI_VDEVICE(NI, 0x17d0), BOARD_NI_PCI6503X },
	{ PCI_VDEVICE(NI, 0x1800), BOARD_NI_PXI_6503 },
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, pci_8255_pci_table);

static struct pci_driver pci_8255_pci_driver = {
	.name		= "8255_pci",
	.id_table	= pci_8255_pci_table,
	.probe		= pci_8255_pci_probe,
	.remove		= comedi_pci_auto_unconfig,
};
module_comedi_pci_driver(pci_8255_driver, pci_8255_pci_driver);

MODULE_DESCRIPTION("COMEDI - Generic PCI based 8255 Digital I/O boards");
MODULE_AUTHOR("Comedi https://www.comedi.org");
MODULE_LICENSE("GPL");
Commit	Line	Data
e184e2be	1	// SPDX-License-Identifier: GPL-2.0+
bb71f8b3	2	/*
f7c22868 HS	3	* COMEDI driver for generic PCI based 8255 digital i/o boards
	4	* Copyright (C) 2012 H Hartley Sweeten <hsweeten@visionengravers.com>
	5	*
	6	* Based on the tested adl_pci7296 driver written by:
	7	* Jon Grierson <jd@renko.co.uk>
df1a3f87 HS	8	* and the experimental cb_pcidio driver written by:
df1a3f87 HS	9	* Yoshiya Matsuzaka
32bb1544 HS	10	*
	11	* COMEDI - Linux Control and Measurement Device Interface
	12	* Copyright (C) 2000 David A. Schleef <ds@schleef.org>
32bb1544	13	*/
bb71f8b3	14
bb71f8b3	15	/*
1308a487 IA	16	* Driver: 8255_pci
	17	* Description: Generic PCI based 8255 Digital I/O boards
	18	* Devices: [ADLink] PCI-7224 (adl_pci-7224), PCI-7248 (adl_pci-7248),
	19	* PCI-7296 (adl_pci-7296),
	20	* [Measurement Computing] PCI-DIO24 (cb_pci-dio24),
	21	* PCI-DIO24H (cb_pci-dio24h), PCI-DIO48H (cb_pci-dio48h),
	22	* PCI-DIO96H (cb_pci-dio96h),
	23	* [National Instruments] PCI-DIO-96 (ni_pci-dio-96),
	24	* PCI-DIO-96B (ni_pci-dio-96b), PXI-6508 (ni_pxi-6508),
	25	* PCI-6503 (ni_pci-6503), PCI-6503B (ni_pci-6503b),
	26	* PCI-6503X (ni_pci-6503x), PXI-6503 (ni_pxi-6503)
	27	* Author: H Hartley Sweeten <hsweeten@visionengravers.com>
	28	* Updated: Wed, 12 Sep 2012 11:52:01 -0700
	29	* Status: untested
	30	*
	31	* These boards have one or more 8255 digital I/O chips, each of which
	32	* is supported as a separate 24-channel DIO subdevice.
	33	*
	34	* Boards with 24 DIO channels (1 DIO subdevice):
	35	*
	36	* PCI-7224, PCI-DIO24, PCI-DIO24H, PCI-6503, PCI-6503B, PCI-6503X,
	37	* PXI-6503
	38	*
	39	* Boards with 48 DIO channels (2 DIO subdevices):
	40	*
	41	* PCI-7248, PCI-DIO48H
	42	*
	43	* Boards with 96 DIO channels (4 DIO subdevices):
	44	*
	45	* PCI-7296, PCI-DIO96H, PCI-DIO-96, PCI-DIO-96B, PXI-6508
	46	*
	47	* Some of these boards also have an 8254 programmable timer/counter
	48	* chip. This chip is not currently supported by this driver.
	49	*
	50	* Interrupt support for these boards is also not currently supported.
	51	*
	52	* Configuration Options: not applicable, uses PCI auto config.
	53	*/
bb71f8b3	54
ce157f80	55	#include <linux/module.h>
33782dd5	56
7215a284	57	#include "../comedi_pci.h"
bb71f8b3	58
bb71f8b3	59	#include "8255.h"
bb71f8b3	60
af48bd8c HS	61	enum pci_8255_boardid {
	62	BOARD_ADLINK_PCI7224,
	63	BOARD_ADLINK_PCI7248,
	64	BOARD_ADLINK_PCI7296,
	65	BOARD_CB_PCIDIO24,
	66	BOARD_CB_PCIDIO24H,
0283f7a1 IA	67	BOARD_CB_PCIDIO48H_OLD,
0283f7a1 IA	68	BOARD_CB_PCIDIO48H_NEW,
af48bd8c HS	69	BOARD_CB_PCIDIO96H,
	70	BOARD_NI_PCIDIO96,
	71	BOARD_NI_PCIDIO96B,
	72	BOARD_NI_PXI6508,
	73	BOARD_NI_PCI6503,
	74	BOARD_NI_PCI6503B,
	75	BOARD_NI_PCI6503X,
	76	BOARD_NI_PXI_6503,
	77	};
b37c1aee	78
f7c22868	79	struct pci_8255_boardinfo {
32bb1544	80	const char *name;
df1a3f87	81	int dio_badr;
f7c22868	82	int n_8255;
268d1e79	83	unsigned int has_mite:1;
32bb1544	84	};
bb71f8b3	85
f7c22868	86	static const struct pci_8255_boardinfo pci_8255_boards[] = {
af48bd8c	87	[BOARD_ADLINK_PCI7224] = {
f7c22868	88	.name = "adl_pci-7224",
df1a3f87	89	.dio_badr = 2,
f7c22868	90	.n_8255 = 1,
af48bd8c HS	91	},
af48bd8c HS	92	[BOARD_ADLINK_PCI7248] = {
f7c22868	93	.name = "adl_pci-7248",
df1a3f87	94	.dio_badr = 2,
f7c22868	95	.n_8255 = 2,
af48bd8c HS	96	},
af48bd8c HS	97	[BOARD_ADLINK_PCI7296] = {
f7c22868	98	.name = "adl_pci-7296",
df1a3f87	99	.dio_badr = 2,
f7c22868	100	.n_8255 = 4,
af48bd8c HS	101	},
af48bd8c HS	102	[BOARD_CB_PCIDIO24] = {
df1a3f87	103	.name = "cb_pci-dio24",
df1a3f87 HS	104	.dio_badr = 2,
df1a3f87 HS	105	.n_8255 = 1,
af48bd8c HS	106	},
af48bd8c HS	107	[BOARD_CB_PCIDIO24H] = {
df1a3f87	108	.name = "cb_pci-dio24h",
df1a3f87 HS	109	.dio_badr = 2,
df1a3f87 HS	110	.n_8255 = 1,
af48bd8c	111	},
0283f7a1	112	[BOARD_CB_PCIDIO48H_OLD] = {
df1a3f87	113	.name = "cb_pci-dio48h",
df1a3f87 HS	114	.dio_badr = 1,
df1a3f87 HS	115	.n_8255 = 2,
af48bd8c	116	},
0283f7a1 IA	117	[BOARD_CB_PCIDIO48H_NEW] = {
	118	.name = "cb_pci-dio48h",
	119	.dio_badr = 2,
	120	.n_8255 = 2,
	121	},
af48bd8c	122	[BOARD_CB_PCIDIO96H] = {
606b0470	123	.name = "cb_pci-dio96h",
606b0470 HS	124	.dio_badr = 2,
606b0470 HS	125	.n_8255 = 4,
af48bd8c HS	126	},
af48bd8c HS	127	[BOARD_NI_PCIDIO96] = {
b37c1aee	128	.name = "ni_pci-dio-96",
b37c1aee	129	.dio_badr = 1,
b37c1aee	130	.n_8255 = 4,
268d1e79	131	.has_mite = 1,
af48bd8c HS	132	},
af48bd8c HS	133	[BOARD_NI_PCIDIO96B] = {
b37c1aee	134	.name = "ni_pci-dio-96b",
b37c1aee	135	.dio_badr = 1,
b37c1aee	136	.n_8255 = 4,
268d1e79	137	.has_mite = 1,
af48bd8c HS	138	},
af48bd8c HS	139	[BOARD_NI_PXI6508] = {
b37c1aee	140	.name = "ni_pxi-6508",
b37c1aee	141	.dio_badr = 1,
b37c1aee	142	.n_8255 = 4,
268d1e79	143	.has_mite = 1,
af48bd8c HS	144	},
af48bd8c HS	145	[BOARD_NI_PCI6503] = {
b37c1aee	146	.name = "ni_pci-6503",
b37c1aee	147	.dio_badr = 1,
b37c1aee	148	.n_8255 = 1,
268d1e79	149	.has_mite = 1,
af48bd8c HS	150	},
af48bd8c HS	151	[BOARD_NI_PCI6503B] = {
b37c1aee	152	.name = "ni_pci-6503b",
b37c1aee	153	.dio_badr = 1,
b37c1aee	154	.n_8255 = 1,
268d1e79	155	.has_mite = 1,
af48bd8c HS	156	},
af48bd8c HS	157	[BOARD_NI_PCI6503X] = {
b37c1aee	158	.name = "ni_pci-6503x",
b37c1aee	159	.dio_badr = 1,
b37c1aee	160	.n_8255 = 1,
268d1e79	161	.has_mite = 1,
af48bd8c HS	162	},
af48bd8c HS	163	[BOARD_NI_PXI_6503] = {
b37c1aee	164	.name = "ni_pxi-6503",
b37c1aee	165	.dio_badr = 1,
b37c1aee	166	.n_8255 = 1,
268d1e79	167	.has_mite = 1,
32bb1544 HS	168	},
32bb1544 HS	169	};
bb71f8b3	170
9949595c	171	/* ripped from mite.h and mite_setup2() to avoid mite dependency */
1da66175 HS	172	#define MITE_IODWBSR 0xc0 /* IO Device Window Base Size Register */
1da66175 HS	173	#define WENAB BIT(7) /* window enable */
e2f1036a	174
268d1e79 IA	175	static int pci_8255_mite_init(struct pci_dev *pcidev)
	176	{
	177	void __iomem *mite_base;
	178	u32 main_phys_addr;
	179
	180	/* ioremap the MITE registers (BAR 0) temporarily */
	181	mite_base = pci_ioremap_bar(pcidev, 0);
	182	if (!mite_base)
	183	return -ENOMEM;
	184
	185	/* set data window to main registers (BAR 1) */
	186	main_phys_addr = pci_resource_start(pcidev, 1);
	187	writel(main_phys_addr \| WENAB, mite_base + MITE_IODWBSR);
	188
	189	/* finished with MITE registers */
	190	iounmap(mite_base);
	191	return 0;
	192	}
	193
a690b7e5	194	static int pci_8255_auto_attach(struct comedi_device *dev,
af48bd8c	195	unsigned long context)
bb71f8b3	196	{
750af5e5	197	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
af48bd8c	198	const struct pci_8255_boardinfo *board = NULL;
34c43922	199	struct comedi_subdevice *s;
bb71f8b3	200	int ret;
32bb1544	201	int i;
bb71f8b3	202
af48bd8c HS	203	if (context < ARRAY_SIZE(pci_8255_boards))
af48bd8c HS	204	board = &pci_8255_boards[context];
32bb1544 HS	205	if (!board)
	206	return -ENODEV;
	207	dev->board_ptr = board;
	208	dev->board_name = board->name;
bb71f8b3	209
818f569f	210	ret = comedi_pci_enable(dev);
8b6c5694 HS	211	if (ret)
8b6c5694 HS	212	return ret;
77f17d37	213
268d1e79 IA	214	if (board->has_mite) {
	215	ret = pci_8255_mite_init(pcidev);
	216	if (ret)
	217	return ret;
	218	}
	219
5c19084b	220	if ((pci_resource_flags(pcidev, board->dio_badr) & IORESOURCE_MEM)) {
78b46938 HS	221	dev->mmio = pci_ioremap_bar(pcidev, board->dio_badr);
78b46938 HS	222	if (!dev->mmio)
77f17d37	223	return -ENOMEM;
43535526 HS	224	} else {
43535526 HS	225	dev->iobase = pci_resource_start(pcidev, board->dio_badr);
77f17d37	226	}
262ea0d4	227
32bb1544 HS	228	/*
	229	* One, two, or four subdevices are setup by this driver depending
	230	* on the number of channels provided by the board. Each subdevice
	231	* has 24 channels supported by the 8255 module.
	232	*/
f7c22868	233	ret = comedi_alloc_subdevices(dev, board->n_8255);
32bb1544	234	if (ret)
262ea0d4 HS	235	return ret;
262ea0d4 HS	236
f7c22868	237	for (i = 0; i < board->n_8255; i++) {
630b713b	238	s = &dev->subdevices[i];
5c19084b	239	if (dev->mmio)
f0162091	240	ret = subdev_8255_mm_init(dev, s, NULL, i * I8255_SIZE);
4085e93b	241	else
f0162091	242	ret = subdev_8255_init(dev, s, NULL, i * I8255_SIZE);
32bb1544 HS	243	if (ret)
	244	return ret;
	245	}
262ea0d4	246
262ea0d4	247	return 0;
bb71f8b3 JG	248	}
bb71f8b3 JG	249
f7c22868 HS	250	static struct comedi_driver pci_8255_driver = {
f7c22868 HS	251	.driver_name = "8255_pci",
db0eaeed	252	.module = THIS_MODULE,
750af5e5	253	.auto_attach = pci_8255_auto_attach,
aac307f9	254	.detach = comedi_pci_detach,
db0eaeed HS	255	};
db0eaeed HS	256
a690b7e5	257	static int pci_8255_pci_probe(struct pci_dev *dev,
b8f4ac23	258	const struct pci_device_id *id)
727b286b	259	{
b8f4ac23	260	return comedi_pci_auto_config(dev, &pci_8255_driver, id->driver_data);
727b286b AT	261	}
727b286b AT	262
41e043fc	263	static const struct pci_device_id pci_8255_pci_table[] = {
af48bd8c HS	264	{ PCI_VDEVICE(ADLINK, 0x7224), BOARD_ADLINK_PCI7224 },
	265	{ PCI_VDEVICE(ADLINK, 0x7248), BOARD_ADLINK_PCI7248 },
	266	{ PCI_VDEVICE(ADLINK, 0x7296), BOARD_ADLINK_PCI7296 },
	267	{ PCI_VDEVICE(CB, 0x0028), BOARD_CB_PCIDIO24 },
	268	{ PCI_VDEVICE(CB, 0x0014), BOARD_CB_PCIDIO24H },
0283f7a1 IA	269	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CB, 0x000b, 0x0000, 0x0000),
	270	.driver_data = BOARD_CB_PCIDIO48H_OLD },
	271	{ PCI_DEVICE_SUB(PCI_VENDOR_ID_CB, 0x000b, PCI_VENDOR_ID_CB, 0x000b),
	272	.driver_data = BOARD_CB_PCIDIO48H_NEW },
af48bd8c HS	273	{ PCI_VDEVICE(CB, 0x0017), BOARD_CB_PCIDIO96H },
	274	{ PCI_VDEVICE(NI, 0x0160), BOARD_NI_PCIDIO96 },
	275	{ PCI_VDEVICE(NI, 0x1630), BOARD_NI_PCIDIO96B },
	276	{ PCI_VDEVICE(NI, 0x13c0), BOARD_NI_PXI6508 },
	277	{ PCI_VDEVICE(NI, 0x0400), BOARD_NI_PCI6503 },
	278	{ PCI_VDEVICE(NI, 0x1250), BOARD_NI_PCI6503B },
	279	{ PCI_VDEVICE(NI, 0x17d0), BOARD_NI_PCI6503X },
	280	{ PCI_VDEVICE(NI, 0x1800), BOARD_NI_PXI_6503 },
75e6301b	281	{ 0 }
db0eaeed	282	};
f7c22868	283	MODULE_DEVICE_TABLE(pci, pci_8255_pci_table);
db0eaeed	284
f7c22868 HS	285	static struct pci_driver pci_8255_pci_driver = {
	286	.name = "8255_pci",
	287	.id_table = pci_8255_pci_table,
	288	.probe = pci_8255_pci_probe,
9901a4d7	289	.remove = comedi_pci_auto_unconfig,
727b286b	290	};
f7c22868	291	module_comedi_pci_driver(pci_8255_driver, pci_8255_pci_driver);
90f703d3	292
f7c22868	293	MODULE_DESCRIPTION("COMEDI - Generic PCI based 8255 Digital I/O boards");
13d8b1f3	294	MODULE_AUTHOR("Comedi https://www.comedi.org");
90f703d3	295	MODULE_LICENSE("GPL");