[mirror_ubuntu-bionic-kernel.git] / drivers / staging / comedi / drivers / addi_apci_2032.c

/*
 * addi_apci_2032.c
 * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
 * Project manager: Eric Stolz
 *
 *	ADDI-DATA GmbH
 *	Dieselstrasse 3
 *	D-77833 Ottersweier
 *	Tel: +19(0)7223/9493-0
 *	Fax: +49(0)7223/9493-92
 *	http://www.addi-data.com
 *	info@addi-data.com
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along
 * with this program; if not, write to the Free Software Foundation, Inc.,
 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 * You should also find the complete GPL in the COPYING file accompanying
 * this source code.
 */

#include "../comedidev.h"
#include "comedi_fc.h"

/*
 * PCI bar 1 I/O Register map
 */
#define APCI2032_DO_REG			0x00
#define APCI2032_INT_CTRL_REG		0x04
#define APCI2032_INT_CTRL_VCC_ENA	(1 << 0)
#define APCI2032_INT_CTRL_CC_ENA	(1 << 1)
#define APCI2032_INT_STATUS_REG		0x08
#define APCI2032_INT_STATUS_VCC		(1 << 0)
#define APCI2032_INT_STATUS_CC		(1 << 1)
#define APCI2032_STATUS_REG		0x0c
#define APCI2032_STATUS_IRQ		(1 << 0)
#define APCI2032_WDOG_REG		0x10
#define APCI2032_WDOG_RELOAD_REG	0x14
#define APCI2032_WDOG_TIMEBASE		0x18
#define APCI2032_WDOG_CTRL_REG		0x1c
#define APCI2032_WDOG_CTRL_ENABLE	(1 << 0)
#define APCI2032_WDOG_CTRL_SW_TRIG	(1 << 9)
#define APCI2032_WDOG_STATUS_REG	0x20
#define APCI2032_WDOG_STATUS_ENABLED	(1 << 0)
#define APCI2032_WDOG_STATUS_SW_TRIG	(1 << 1)

struct apci2032_private {
	unsigned int wdog_ctrl;
};

struct apci2032_int_private {
	spinlock_t spinlock;
	unsigned int stop_count;
	bool active;
	unsigned char enabled_isns;
};

static int apci2032_do_insn_bits(struct comedi_device *dev,
				 struct comedi_subdevice *s,
				 struct comedi_insn *insn,
				 unsigned int *data)
{
	unsigned int mask = data[0];
	unsigned int bits = data[1];

	s->state = inl(dev->iobase + APCI2032_DO_REG);
	if (mask) {
		s->state &= ~mask;
		s->state |= (bits & mask);

		outl(s->state, dev->iobase + APCI2032_DO_REG);
	}

	data[1] = s->state;

	return insn->n;
}

/*
 * The watchdog subdevice is configured with two INSN_CONFIG instructions:
 *
 * Enable the watchdog and set the reload timeout:
 *	data[0] = INSN_CONFIG_ARM
 *	data[1] = timeout reload value
 *
 * Disable the watchdog:
 *	data[0] = INSN_CONFIG_DISARM
 */
static int apci2032_wdog_insn_config(struct comedi_device *dev,
				     struct comedi_subdevice *s,
				     struct comedi_insn *insn,
				     unsigned int *data)
{
	struct apci2032_private *devpriv = dev->private;
	unsigned int reload;

	switch (data[0]) {
	case INSN_CONFIG_ARM:
		devpriv->wdog_ctrl = APCI2032_WDOG_CTRL_ENABLE;
		reload = data[1] & s->maxdata;
		outw(reload, dev->iobase + APCI2032_WDOG_RELOAD_REG);

		/* Time base is 20ms, let the user know the timeout */
		dev_info(dev->class_dev, "watchdog enabled, timeout:%dms\n",
			20 * reload + 20);
		break;
	case INSN_CONFIG_DISARM:
		devpriv->wdog_ctrl = 0;
		break;
	default:
		return -EINVAL;
	}

	outw(devpriv->wdog_ctrl, dev->iobase + APCI2032_WDOG_CTRL_REG);

	return insn->n;
}

static int apci2032_wdog_insn_write(struct comedi_device *dev,
				    struct comedi_subdevice *s,
				    struct comedi_insn *insn,
				    unsigned int *data)
{
	struct apci2032_private *devpriv = dev->private;
	int i;

	if (devpriv->wdog_ctrl == 0) {
		dev_warn(dev->class_dev, "watchdog is disabled\n");
		return -EINVAL;
	}

	/* "ping" the watchdog */
	for (i = 0; i < insn->n; i++) {
		outw(devpriv->wdog_ctrl | APCI2032_WDOG_CTRL_SW_TRIG,
			dev->iobase + APCI2032_WDOG_CTRL_REG);
	}

	return insn->n;
}

static int apci2032_wdog_insn_read(struct comedi_device *dev,
				   struct comedi_subdevice *s,
				   struct comedi_insn *insn,
				   unsigned int *data)
{
	int i;

	for (i = 0; i < insn->n; i++)
		data[i] = inl(dev->iobase + APCI2032_WDOG_STATUS_REG);

	return insn->n;
}

static int apci2032_int_insn_bits(struct comedi_device *dev,
				  struct comedi_subdevice *s,
				  struct comedi_insn *insn,
				  unsigned int *data)
{
	data[1] = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3;
	return insn->n;
}

static void apci2032_int_stop(struct comedi_device *dev,
			      struct comedi_subdevice *s)
{
	struct apci2032_int_private *subpriv = s->private;

	subpriv->active = false;
	subpriv->enabled_isns = 0;
	outl(0x0, dev->iobase + APCI2032_INT_CTRL_REG);
}

static bool apci2032_int_start(struct comedi_device *dev,
			       struct comedi_subdevice *s,
			       unsigned char enabled_isns)
{
	struct apci2032_int_private *subpriv = s->private;
	struct comedi_cmd *cmd = &s->async->cmd;
	bool do_event;

	subpriv->enabled_isns = enabled_isns;
	subpriv->stop_count = cmd->stop_arg;
	if (cmd->stop_src == TRIG_COUNT && subpriv->stop_count == 0) {
		/* An empty acquisition! */
		s->async->events |= COMEDI_CB_EOA;
		subpriv->active = false;
		do_event = true;
	} else {
		subpriv->active = true;
		outl(enabled_isns, dev->iobase + APCI2032_INT_CTRL_REG);
		do_event = false;
	}

	return do_event;
}

static int apci2032_int_cmdtest(struct comedi_device *dev,
				struct comedi_subdevice *s,
				struct comedi_cmd *cmd)
{
	int err = 0;

	/* Step 1 : check if triggers are trivially valid */

	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);

	if (err)
		return 1;

	/* Step 2a : make sure trigger sources are unique */
	err |= cfc_check_trigger_is_unique(cmd->stop_src);

	/* Step 2b : and mutually compatible */

	if (err)
		return 2;

	/* Step 3: check if arguments are trivially valid */

	err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
	if (cmd->stop_src == TRIG_NONE)
		err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);

	if (err)
		return 3;

	/* step 4: ignored */

	if (err)
		return 4;

	return 0;
}

static int apci2032_int_cmd(struct comedi_device *dev,
			    struct comedi_subdevice *s)
{
	struct comedi_cmd *cmd = &s->async->cmd;
	struct apci2032_int_private *subpriv = s->private;
	unsigned char enabled_isns;
	unsigned int n;
	unsigned long flags;
	bool do_event;

	enabled_isns = 0;
	for (n = 0; n < cmd->chanlist_len; n++)
		enabled_isns |= 1 << CR_CHAN(cmd->chanlist[n]);

	spin_lock_irqsave(&subpriv->spinlock, flags);
	do_event = apci2032_int_start(dev, s, enabled_isns);
	spin_unlock_irqrestore(&subpriv->spinlock, flags);

	if (do_event)
		comedi_event(dev, s);

	return 0;
}

static int apci2032_int_cancel(struct comedi_device *dev,
			       struct comedi_subdevice *s)
{
	struct apci2032_int_private *subpriv = s->private;
	unsigned long flags;

	spin_lock_irqsave(&subpriv->spinlock, flags);
	if (subpriv->active)
		apci2032_int_stop(dev, s);
	spin_unlock_irqrestore(&subpriv->spinlock, flags);

	return 0;
}

static irqreturn_t apci2032_interrupt(int irq, void *d)
{
	struct comedi_device *dev = d;
	struct comedi_subdevice *s = dev->read_subdev;
	struct apci2032_int_private *subpriv;
	unsigned int val;
	bool do_event = false;

	if (!dev->attached)
		return IRQ_NONE;

	/* Check if VCC OR CC interrupt has occurred */
	val = inl(dev->iobase + APCI2032_STATUS_REG) & APCI2032_STATUS_IRQ;
	if (!val)
		return IRQ_NONE;

	subpriv = s->private;
	spin_lock(&subpriv->spinlock);

	val = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3;
	/* Disable triggered interrupt sources. */
	outl(~val & 3, dev->iobase + APCI2032_INT_CTRL_REG);
	/*
	 * Note: We don't reenable the triggered interrupt sources because they
	 * are level-sensitive, hardware error status interrupt sources and
	 * they'd keep triggering interrupts repeatedly.
	 */

	if (subpriv->active && (val & subpriv->enabled_isns) != 0) {
		unsigned short bits;
		unsigned int n, len;
		unsigned int *chanlist;

		/* Bits in scan data correspond to indices in channel list. */
		bits = 0;
		len = s->async->cmd.chanlist_len;
		chanlist = &s->async->cmd.chanlist[0];
		for (n = 0; n < len; n++)
			if ((val & (1U << CR_CHAN(chanlist[n]))) != 0)
				bits |= 1U << n;

		if (comedi_buf_put(s->async, bits)) {
			s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
			if (s->async->cmd.stop_src == TRIG_COUNT &&
			    subpriv->stop_count > 0) {
				subpriv->stop_count--;
				if (subpriv->stop_count == 0) {
					/* end of acquisition */
					s->async->events |= COMEDI_CB_EOA;
					apci2032_int_stop(dev, s);
				}
			}
		} else {
			apci2032_int_stop(dev, s);
			s->async->events |= COMEDI_CB_OVERFLOW;
		}
		do_event = true;
	}

	spin_unlock(&subpriv->spinlock);
	if (do_event)
		comedi_event(dev, s);

	return IRQ_HANDLED;
}

static int apci2032_reset(struct comedi_device *dev)
{
	outl(0x0, dev->iobase + APCI2032_DO_REG);
	outl(0x0, dev->iobase + APCI2032_INT_CTRL_REG);
	outl(0x0, dev->iobase + APCI2032_WDOG_CTRL_REG);
	outl(0x0, dev->iobase + APCI2032_WDOG_RELOAD_REG);

	return 0;
}

static int apci2032_auto_attach(struct comedi_device *dev,
				unsigned long context_unused)
{
	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
	struct apci2032_private *devpriv;
	struct comedi_subdevice *s;
	int ret;

	dev->board_name = dev->driver->driver_name;

	devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
	if (!devpriv)
		return -ENOMEM;
	dev->private = devpriv;

	ret = comedi_pci_enable(pcidev, dev->board_name);
	if (ret)
		return ret;
	dev->iobase = pci_resource_start(pcidev, 1);
	apci2032_reset(dev);

	if (pcidev->irq > 0) {
		ret = request_irq(pcidev->irq, apci2032_interrupt,
				  IRQF_SHARED, dev->board_name, dev);
		if (ret == 0)
			dev->irq = pcidev->irq;
	}

	ret = comedi_alloc_subdevices(dev, 3);
	if (ret)
		return ret;

	/* Initialize the digital output subdevice */
	s = &dev->subdevices[0];
	s->type		= COMEDI_SUBD_DO;
	s->subdev_flags	= SDF_WRITEABLE;
	s->n_chan	= 32;
	s->maxdata	= 1;
	s->range_table	= &range_digital;
	s->insn_bits	= apci2032_do_insn_bits;

	/* Initialize the watchdog subdevice */
	s = &dev->subdevices[1];
	s->type		= COMEDI_SUBD_TIMER;
	s->subdev_flags	= SDF_WRITEABLE;
	s->n_chan	= 1;
	s->maxdata	= 0xff;
	s->insn_write	= apci2032_wdog_insn_write;
	s->insn_read	= apci2032_wdog_insn_read;
	s->insn_config	= apci2032_wdog_insn_config;

	/* Initialize the interrupt subdevice */
	s = &dev->subdevices[2];
	s->type		= COMEDI_SUBD_DI;
	s->subdev_flags	= SDF_READABLE;
	s->n_chan	= 2;
	s->maxdata	= 1;
	s->range_table	= &range_digital;
	s->insn_bits	= apci2032_int_insn_bits;
	if (dev->irq) {
		struct apci2032_int_private *subpriv;

		dev->read_subdev = s;
		subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
		if (!subpriv)
			return -ENOMEM;
		spin_lock_init(&subpriv->spinlock);
		s->private	= subpriv;
		s->subdev_flags	= SDF_READABLE | SDF_CMD_READ;
		s->len_chanlist = 2;
		s->do_cmdtest	= apci2032_int_cmdtest;
		s->do_cmd	= apci2032_int_cmd;
		s->cancel	= apci2032_int_cancel;
	}

	return 0;
}

static void apci2032_detach(struct comedi_device *dev)
{
	struct pci_dev *pcidev = comedi_to_pci_dev(dev);

	if (dev->iobase)
		apci2032_reset(dev);
	if (dev->irq)
		free_irq(dev->irq, dev);
	if (dev->read_subdev)
		kfree(dev->read_subdev->private);
	if (pcidev) {
		if (dev->iobase)
			comedi_pci_disable(pcidev);
	}
}

static struct comedi_driver apci2032_driver = {
	.driver_name	= "addi_apci_2032",
	.module		= THIS_MODULE,
	.auto_attach	= apci2032_auto_attach,
	.detach		= apci2032_detach,
};

static int apci2032_pci_probe(struct pci_dev *dev,
					const struct pci_device_id *ent)
{
	return comedi_pci_auto_config(dev, &apci2032_driver);
}

static void apci2032_pci_remove(struct pci_dev *dev)
{
	comedi_pci_auto_unconfig(dev);
}

static DEFINE_PCI_DEVICE_TABLE(apci2032_pci_table) = {
	{ PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1004) },
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, apci2032_pci_table);

static struct pci_driver apci2032_pci_driver = {
	.name		= "addi_apci_2032",
	.id_table	= apci2032_pci_table,
	.probe		= apci2032_pci_probe,
	.remove		= apci2032_pci_remove,
};
module_comedi_pci_driver(apci2032_driver, apci2032_pci_driver);

MODULE_AUTHOR("Comedi http://www.comedi.org");
MODULE_DESCRIPTION("Comedi low-level driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d02178b7 HS	1	/*
	2	* addi_apci_2032.c
	3	* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
	4	* Project manager: Eric Stolz
	5	*
	6	* ADDI-DATA GmbH
	7	* Dieselstrasse 3
	8	* D-77833 Ottersweier
	9	* Tel: +19(0)7223/9493-0
	10	* Fax: +49(0)7223/9493-92
	11	* http://www.addi-data.com
	12	* info@addi-data.com
	13	*
	14	* This program is free software; you can redistribute it and/or modify it
	15	* under the terms of the GNU General Public License as published by the
	16	* Free Software Foundation; either version 2 of the License, or (at your
	17	* option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
	23	*
	24	* You should have received a copy of the GNU General Public License along
	25	* with this program; if not, write to the Free Software Foundation, Inc.,
	26	* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	27	*
	28	* You should also find the complete GPL in the COPYING file accompanying
	29	* this source code.
	30	*/
	31
3d41c443 HS	32	#include "../comedidev.h"
	33	#include "comedi_fc.h"
	34
d02178b7 HS	35	/*
	36	* PCI bar 1 I/O Register map
	37	*/
7180eb30 HS	38	#define APCI2032_DO_REG 0x00
	39	#define APCI2032_INT_CTRL_REG 0x04
	40	#define APCI2032_INT_CTRL_VCC_ENA (1 << 0)
	41	#define APCI2032_INT_CTRL_CC_ENA (1 << 1)
	42	#define APCI2032_INT_STATUS_REG 0x08
	43	#define APCI2032_INT_STATUS_VCC (1 << 0)
	44	#define APCI2032_INT_STATUS_CC (1 << 1)
	45	#define APCI2032_STATUS_REG 0x0c
	46	#define APCI2032_STATUS_IRQ (1 << 0)
	47	#define APCI2032_WDOG_REG 0x10
	48	#define APCI2032_WDOG_RELOAD_REG 0x14
	49	#define APCI2032_WDOG_TIMEBASE 0x18
	50	#define APCI2032_WDOG_CTRL_REG 0x1c
	51	#define APCI2032_WDOG_CTRL_ENABLE (1 << 0)
	52	#define APCI2032_WDOG_CTRL_SW_TRIG (1 << 9)
	53	#define APCI2032_WDOG_STATUS_REG 0x20
	54	#define APCI2032_WDOG_STATUS_ENABLED (1 << 0)
	55	#define APCI2032_WDOG_STATUS_SW_TRIG (1 << 1)
d02178b7	56
23fb1747 HS	57	struct apci2032_private {
	58	unsigned int wdog_ctrl;
	59	};
	60
5c2d4cba IA	61	struct apci2032_int_private {
5c2d4cba IA	62	spinlock_t spinlock;
215caceb	63	unsigned int stop_count;
5c2d4cba IA	64	bool active;
	65	unsigned char enabled_isns;
	66	};
	67
d02178b7 HS	68	static int apci2032_do_insn_bits(struct comedi_device *dev,
	69	struct comedi_subdevice *s,
	70	struct comedi_insn *insn,
	71	unsigned int *data)
	72	{
	73	unsigned int mask = data[0];
	74	unsigned int bits = data[1];
	75
7180eb30	76	s->state = inl(dev->iobase + APCI2032_DO_REG);
d02178b7 HS	77	if (mask) {
	78	s->state &= ~mask;
	79	s->state \|= (bits & mask);
	80
7180eb30	81	outl(s->state, dev->iobase + APCI2032_DO_REG);
d02178b7 HS	82	}
	83
	84	data[1] = s->state;
	85
	86	return insn->n;
	87	}
	88
23fb1747 HS	89	/*
	90	* The watchdog subdevice is configured with two INSN_CONFIG instructions:
	91	*
	92	* Enable the watchdog and set the reload timeout:
	93	* data[0] = INSN_CONFIG_ARM
	94	* data[1] = timeout reload value
	95	*
	96	* Disable the watchdog:
	97	* data[0] = INSN_CONFIG_DISARM
	98	*/
	99	static int apci2032_wdog_insn_config(struct comedi_device *dev,
d02178b7 HS	100	struct comedi_subdevice *s,
	101	struct comedi_insn *insn,
	102	unsigned int *data)
	103	{
23fb1747 HS	104	struct apci2032_private *devpriv = dev->private;
	105	unsigned int reload;
	106
	107	switch (data[0]) {
	108	case INSN_CONFIG_ARM:
	109	devpriv->wdog_ctrl = APCI2032_WDOG_CTRL_ENABLE;
	110	reload = data[1] & s->maxdata;
	111	outw(reload, dev->iobase + APCI2032_WDOG_RELOAD_REG);
	112
	113	/* Time base is 20ms, let the user know the timeout */
	114	dev_info(dev->class_dev, "watchdog enabled, timeout:%dms\n",
	115	20 * reload + 20);
	116	break;
	117	case INSN_CONFIG_DISARM:
	118	devpriv->wdog_ctrl = 0;
	119	break;
	120	default:
d02178b7 HS	121	return -EINVAL;
	122	}
	123
23fb1747 HS	124	outw(devpriv->wdog_ctrl, dev->iobase + APCI2032_WDOG_CTRL_REG);
23fb1747 HS	125
d02178b7 HS	126	return insn->n;
	127	}
	128
23fb1747 HS	129	static int apci2032_wdog_insn_write(struct comedi_device *dev,
	130	struct comedi_subdevice *s,
	131	struct comedi_insn *insn,
	132	unsigned int *data)
d02178b7	133	{
23fb1747 HS	134	struct apci2032_private *devpriv = dev->private;
	135	int i;
	136
	137	if (devpriv->wdog_ctrl == 0) {
	138	dev_warn(dev->class_dev, "watchdog is disabled\n");
d02178b7 HS	139	return -EINVAL;
d02178b7 HS	140	}
23fb1747 HS	141
	142	/* "ping" the watchdog */
	143	for (i = 0; i < insn->n; i++) {
	144	outw(devpriv->wdog_ctrl \| APCI2032_WDOG_CTRL_SW_TRIG,
	145	dev->iobase + APCI2032_WDOG_CTRL_REG);
	146	}
	147
d02178b7 HS	148	return insn->n;
	149	}
	150
23fb1747	151	static int apci2032_wdog_insn_read(struct comedi_device *dev,
d02178b7 HS	152	struct comedi_subdevice *s,
	153	struct comedi_insn *insn,
	154	unsigned int *data)
	155	{
7b5dd1cc HS	156	int i;
	157
	158	for (i = 0; i < insn->n; i++)
	159	data[i] = inl(dev->iobase + APCI2032_WDOG_STATUS_REG);
	160
d02178b7 HS	161	return insn->n;
	162	}
	163
05fcdced HS	164	static int apci2032_int_insn_bits(struct comedi_device *dev,
	165	struct comedi_subdevice *s,
	166	struct comedi_insn *insn,
	167	unsigned int *data)
b3b7dab7	168	{
b652bd83	169	data[1] = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3;
05fcdced HS	170	return insn->n;
05fcdced HS	171	}
b3b7dab7	172
5c2d4cba IA	173	static void apci2032_int_stop(struct comedi_device *dev,
	174	struct comedi_subdevice *s)
	175	{
	176	struct apci2032_int_private *subpriv = s->private;
	177
	178	subpriv->active = false;
	179	subpriv->enabled_isns = 0;
	180	outl(0x0, dev->iobase + APCI2032_INT_CTRL_REG);
	181	}
	182
215caceb IA	183	static bool apci2032_int_start(struct comedi_device *dev,
	184	struct comedi_subdevice *s,
	185	unsigned char enabled_isns)
	186	{
	187	struct apci2032_int_private *subpriv = s->private;
	188	struct comedi_cmd *cmd = &s->async->cmd;
	189	bool do_event;
	190
	191	subpriv->enabled_isns = enabled_isns;
	192	subpriv->stop_count = cmd->stop_arg;
	193	if (cmd->stop_src == TRIG_COUNT && subpriv->stop_count == 0) {
	194	/* An empty acquisition! */
	195	s->async->events \|= COMEDI_CB_EOA;
	196	subpriv->active = false;
	197	do_event = true;
	198	} else {
	199	subpriv->active = true;
	200	outl(enabled_isns, dev->iobase + APCI2032_INT_CTRL_REG);
	201	do_event = false;
	202	}
	203
	204	return do_event;
	205	}
	206
05fcdced HS	207	static int apci2032_int_cmdtest(struct comedi_device *dev,
	208	struct comedi_subdevice *s,
	209	struct comedi_cmd *cmd)
	210	{
	211	int err = 0;
b3b7dab7	212
05fcdced	213	/* Step 1 : check if triggers are trivially valid */
b3b7dab7	214
05fcdced	215	err \|= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
5c2d4cba IA	216	err \|= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
5c2d4cba IA	217	err \|= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
05fcdced	218	err \|= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
215caceb	219	err \|= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT \| TRIG_NONE);
b3b7dab7	220
05fcdced HS	221	if (err)
05fcdced HS	222	return 1;
b3b7dab7	223
05fcdced	224	/* Step 2a : make sure trigger sources are unique */
215caceb IA	225	err \|= cfc_check_trigger_is_unique(cmd->stop_src);
215caceb IA	226
05fcdced HS	227	/* Step 2b : and mutually compatible */
	228
	229	if (err)
	230	return 2;
	231
	232	/* Step 3: check if arguments are trivially valid */
	233
	234	err \|= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
5c2d4cba	235	err \|= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
05fcdced	236	err \|= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
5c2d4cba	237	err \|= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
215caceb IA	238	if (cmd->stop_src == TRIG_NONE)
215caceb IA	239	err \|= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
05fcdced HS	240
	241	if (err)
	242	return 3;
	243
	244	/* step 4: ignored */
	245
	246	if (err)
	247	return 4;
	248
	249	return 0;
b3b7dab7 HS	250	}
b3b7dab7 HS	251
05fcdced HS	252	static int apci2032_int_cmd(struct comedi_device *dev,
05fcdced HS	253	struct comedi_subdevice *s)
d02178b7	254	{
05fcdced	255	struct comedi_cmd *cmd = &s->async->cmd;
5c2d4cba IA	256	struct apci2032_int_private *subpriv = s->private;
	257	unsigned char enabled_isns;
	258	unsigned int n;
	259	unsigned long flags;
215caceb	260	bool do_event;
5c2d4cba IA	261
	262	enabled_isns = 0;
	263	for (n = 0; n < cmd->chanlist_len; n++)
	264	enabled_isns \|= 1 << CR_CHAN(cmd->chanlist[n]);
05fcdced	265
5c2d4cba	266	spin_lock_irqsave(&subpriv->spinlock, flags);
215caceb	267	do_event = apci2032_int_start(dev, s, enabled_isns);
5c2d4cba	268	spin_unlock_irqrestore(&subpriv->spinlock, flags);
05fcdced	269
215caceb IA	270	if (do_event)
	271	comedi_event(dev, s);
	272
05fcdced	273	return 0;
d02178b7	274	}
7180eb30	275
05fcdced HS	276	static int apci2032_int_cancel(struct comedi_device *dev,
05fcdced HS	277	struct comedi_subdevice *s)
d02178b7	278	{
5c2d4cba IA	279	struct apci2032_int_private *subpriv = s->private;
	280	unsigned long flags;
	281
	282	spin_lock_irqsave(&subpriv->spinlock, flags);
	283	if (subpriv->active)
	284	apci2032_int_stop(dev, s);
	285	spin_unlock_irqrestore(&subpriv->spinlock, flags);
d02178b7	286
05fcdced	287	return 0;
d02178b7	288	}
317285d7	289
05fcdced	290	static irqreturn_t apci2032_interrupt(int irq, void *d)
25adf2cc	291	{
05fcdced HS	292	struct comedi_device *dev = d;
05fcdced HS	293	struct comedi_subdevice *s = dev->read_subdev;
5c2d4cba	294	struct apci2032_int_private *subpriv;
05fcdced	295	unsigned int val;
5c2d4cba	296	bool do_event = false;
05fcdced	297
0774c2b5 IA	298	if (!dev->attached)
	299	return IRQ_NONE;
	300
05fcdced HS	301	/* Check if VCC OR CC interrupt has occurred */
	302	val = inl(dev->iobase + APCI2032_STATUS_REG) & APCI2032_STATUS_IRQ;
	303	if (!val)
	304	return IRQ_NONE;
	305
5c2d4cba IA	306	subpriv = s->private;
	307	spin_lock(&subpriv->spinlock);
	308
b652bd83	309	val = inl(dev->iobase + APCI2032_INT_STATUS_REG) & 3;
ef6543db IA	310	/* Disable triggered interrupt sources. */
	311	outl(~val & 3, dev->iobase + APCI2032_INT_CTRL_REG);
	312	/*
	313	* Note: We don't reenable the triggered interrupt sources because they
	314	* are level-sensitive, hardware error status interrupt sources and
	315	* they'd keep triggering interrupts repeatedly.
	316	*/
05fcdced	317
5c2d4cba IA	318	if (subpriv->active && (val & subpriv->enabled_isns) != 0) {
	319	unsigned short bits;
	320	unsigned int n, len;
	321	unsigned int *chanlist;
	322
	323	/* Bits in scan data correspond to indices in channel list. */
	324	bits = 0;
	325	len = s->async->cmd.chanlist_len;
	326	chanlist = &s->async->cmd.chanlist[0];
	327	for (n = 0; n < len; n++)
	328	if ((val & (1U << CR_CHAN(chanlist[n]))) != 0)
	329	bits \|= 1U << n;
	330
	331	if (comedi_buf_put(s->async, bits)) {
	332	s->async->events \|= COMEDI_CB_BLOCK \| COMEDI_CB_EOS;
215caceb IA	333	if (s->async->cmd.stop_src == TRIG_COUNT &&
	334	subpriv->stop_count > 0) {
	335	subpriv->stop_count--;
	336	if (subpriv->stop_count == 0) {
	337	/* end of acquisition */
	338	s->async->events \|= COMEDI_CB_EOA;
	339	apci2032_int_stop(dev, s);
	340	}
	341	}
5c2d4cba IA	342	} else {
	343	apci2032_int_stop(dev, s);
	344	s->async->events \|= COMEDI_CB_OVERFLOW;
	345	}
	346	do_event = true;
	347	}
	348
	349	spin_unlock(&subpriv->spinlock);
	350	if (do_event)
	351	comedi_event(dev, s);
05fcdced HS	352
05fcdced HS	353	return IRQ_HANDLED;
25adf2cc HS	354	}
25adf2cc HS	355
791c9792	356	static int apci2032_reset(struct comedi_device *dev)
25adf2cc	357	{
7180eb30 HS	358	outl(0x0, dev->iobase + APCI2032_DO_REG);
	359	outl(0x0, dev->iobase + APCI2032_INT_CTRL_REG);
	360	outl(0x0, dev->iobase + APCI2032_WDOG_CTRL_REG);
	361	outl(0x0, dev->iobase + APCI2032_WDOG_RELOAD_REG);
25adf2cc	362
25adf2cc HS	363	return 0;
	364	}
	365
25adf2cc HS	366	static int apci2032_auto_attach(struct comedi_device *dev,
	367	unsigned long context_unused)
	368	{
	369	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
23fb1747	370	struct apci2032_private *devpriv;
25adf2cc	371	struct comedi_subdevice *s;
0c33bdd0	372	int ret;
25adf2cc	373
c0c3c7df	374	dev->board_name = dev->driver->driver_name;
25adf2cc	375
23fb1747 HS	376	devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
	377	if (!devpriv)
	378	return -ENOMEM;
	379	dev->private = devpriv;
	380
25adf2cc HS	381	ret = comedi_pci_enable(pcidev, dev->board_name);
	382	if (ret)
	383	return ret;
70ff4065	384	dev->iobase = pci_resource_start(pcidev, 1);
0774c2b5	385	apci2032_reset(dev);
25adf2cc	386
25adf2cc	387	if (pcidev->irq > 0) {
05fcdced HS	388	ret = request_irq(pcidev->irq, apci2032_interrupt,
05fcdced HS	389	IRQF_SHARED, dev->board_name, dev);
25adf2cc HS	390	if (ret == 0)
	391	dev->irq = pcidev->irq;
	392	}
	393
05fcdced	394	ret = comedi_alloc_subdevices(dev, 3);
25adf2cc HS	395	if (ret)
	396	return ret;
	397
0c33bdd0	398	/* Initialize the digital output subdevice */
25adf2cc	399	s = &dev->subdevices[0];
cf110882 HS	400	s->type = COMEDI_SUBD_DO;
	401	s->subdev_flags = SDF_WRITEABLE;
	402	s->n_chan = 32;
	403	s->maxdata = 1;
	404	s->range_table = &range_digital;
cf110882	405	s->insn_bits = apci2032_do_insn_bits;
25adf2cc	406
0c33bdd0 HS	407	/* Initialize the watchdog subdevice */
0c33bdd0 HS	408	s = &dev->subdevices[1];
cf110882 HS	409	s->type = COMEDI_SUBD_TIMER;
	410	s->subdev_flags = SDF_WRITEABLE;
	411	s->n_chan = 1;
	412	s->maxdata = 0xff;
cf110882 HS	413	s->insn_write = apci2032_wdog_insn_write;
	414	s->insn_read = apci2032_wdog_insn_read;
	415	s->insn_config = apci2032_wdog_insn_config;
25adf2cc	416
05fcdced HS	417	/* Initialize the interrupt subdevice */
05fcdced HS	418	s = &dev->subdevices[2];
5f6c2a95 IA	419	s->type = COMEDI_SUBD_DI;
	420	s->subdev_flags = SDF_READABLE;
	421	s->n_chan = 2;
	422	s->maxdata = 1;
	423	s->range_table = &range_digital;
	424	s->insn_bits = apci2032_int_insn_bits;
05fcdced	425	if (dev->irq) {
5c2d4cba IA	426	struct apci2032_int_private *subpriv;
5c2d4cba IA	427
05fcdced	428	dev->read_subdev = s;
5c2d4cba IA	429	subpriv = kzalloc(sizeof(*subpriv), GFP_KERNEL);
	430	if (!subpriv)
	431	return -ENOMEM;
	432	spin_lock_init(&subpriv->spinlock);
	433	s->private = subpriv;
b82fe57c	434	s->subdev_flags = SDF_READABLE \| SDF_CMD_READ;
5c2d4cba	435	s->len_chanlist = 2;
05fcdced HS	436	s->do_cmdtest = apci2032_int_cmdtest;
	437	s->do_cmd = apci2032_int_cmd;
	438	s->cancel = apci2032_int_cancel;
05fcdced HS	439	}
05fcdced HS	440
25adf2cc HS	441	return 0;
	442	}
	443
	444	static void apci2032_detach(struct comedi_device *dev)
	445	{
	446	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
25adf2cc	447
dce10abc HS	448	if (dev->iobase)
	449	apci2032_reset(dev);
	450	if (dev->irq)
	451	free_irq(dev->irq, dev);
5c2d4cba IA	452	if (dev->read_subdev)
5c2d4cba IA	453	kfree(dev->read_subdev->private);
25adf2cc HS	454	if (pcidev) {
	455	if (dev->iobase)
	456	comedi_pci_disable(pcidev);
	457	}
	458	}
	459
20a22b70 HS	460	static struct comedi_driver apci2032_driver = {
	461	.driver_name = "addi_apci_2032",
	462	.module = THIS_MODULE,
25adf2cc HS	463	.auto_attach = apci2032_auto_attach,
25adf2cc HS	464	.detach = apci2032_detach,
20a22b70 HS	465	};
20a22b70 HS	466
a690b7e5	467	static int apci2032_pci_probe(struct pci_dev *dev,
20a22b70 HS	468	const struct pci_device_id *ent)
	469	{
	470	return comedi_pci_auto_config(dev, &apci2032_driver);
	471	}
	472
53b80019	473	static void apci2032_pci_remove(struct pci_dev *dev)
20a22b70 HS	474	{
	475	comedi_pci_auto_unconfig(dev);
	476	}
	477
	478	static DEFINE_PCI_DEVICE_TABLE(apci2032_pci_table) = {
317285d7 HS	479	{ PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1004) },
	480	{ 0 }
	481	};
20a22b70	482	MODULE_DEVICE_TABLE(pci, apci2032_pci_table);
317285d7	483
20a22b70 HS	484	static struct pci_driver apci2032_pci_driver = {
	485	.name = "addi_apci_2032",
	486	.id_table = apci2032_pci_table,
	487	.probe = apci2032_pci_probe,
a471eace	488	.remove = apci2032_pci_remove,
20a22b70 HS	489	};
20a22b70 HS	490	module_comedi_pci_driver(apci2032_driver, apci2032_pci_driver);
90f703d3 AT	491
	492	MODULE_AUTHOR("Comedi http://www.comedi.org");
	493	MODULE_DESCRIPTION("Comedi low-level driver");
	494	MODULE_LICENSE("GPL");