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Commit | Line | Data |
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124b13b2 | 1 | /* |
31922394 HS |
2 | * comedi/drivers/ni_labpc.c |
3 | * Driver for National Instruments Lab-PC series boards and compatibles | |
4 | * Copyright (C) 2001-2003 Frank Mori Hess <fmhess@users.sourceforge.net> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
31922394 | 15 | */ |
124b13b2 FMH |
16 | |
17 | /* | |
31922394 HS |
18 | * Driver: ni_labpc |
19 | * Description: National Instruments Lab-PC (& compatibles) | |
20 | * Devices: (National Instruments) Lab-PC-1200 [lab-pc-1200] | |
21 | * (National Instruments) Lab-PC-1200AI [lab-pc-1200ai] | |
22 | * (National Instruments) Lab-PC+ [lab-pc+] | |
31922394 HS |
23 | * Author: Frank Mori Hess <fmhess@users.sourceforge.net> |
24 | * Status: works | |
25 | * | |
26 | * Configuration options - ISA boards: | |
27 | * [0] - I/O port base address | |
28 | * [1] - IRQ (optional, required for timed or externally triggered | |
29 | * conversions) | |
30 | * [2] - DMA channel (optional) | |
31 | * | |
31922394 HS |
32 | * Tested with lab-pc-1200. For the older Lab-PC+, not all input |
33 | * ranges and analog references will work, the available ranges/arefs | |
34 | * will depend on how you have configured the jumpers on your board | |
35 | * (see your owner's manual). | |
36 | * | |
37 | * Kernel-level ISA plug-and-play support for the lab-pc-1200 boards | |
38 | * has not yet been added to the driver, mainly due to the fact that | |
39 | * I don't know the device id numbers. If you have one of these boards, | |
40 | * please file a bug report at http://comedi.org/ so I can get the | |
41 | * necessary information from you. | |
42 | * | |
43 | * The 1200 series boards have onboard calibration dacs for correcting | |
44 | * analog input/output offsets and gains. The proper settings for these | |
45 | * caldacs are stored on the board's eeprom. To read the caldac values | |
46 | * from the eeprom and store them into a file that can be then be used | |
47 | * by comedilib, use the comedi_calibrate program. | |
48 | * | |
49 | * The Lab-pc+ has quirky chanlist requirements when scanning multiple | |
50 | * channels. Multiple channel scan sequence must start at highest channel, | |
51 | * then decrement down to channel 0. The rest of the cards can scan down | |
52 | * like lab-pc+ or scan up from channel zero. Chanlists consisting of all | |
53 | * one channel are also legal, and allow you to pace conversions in bursts. | |
54 | * | |
55 | * NI manuals: | |
56 | * 341309a (labpc-1200 register manual) | |
31922394 HS |
57 | * 320502b (lab-pc+) |
58 | */ | |
124b13b2 | 59 | |
25436dc9 | 60 | #include <linux/interrupt.h> |
5a0e3ad6 | 61 | #include <linux/slab.h> |
845d131e | 62 | #include <linux/io.h> |
33782dd5 HS |
63 | #include <linux/delay.h> |
64 | ||
124b13b2 FMH |
65 | #include "../comedidev.h" |
66 | ||
124b13b2 FMH |
67 | #include <asm/dma.h> |
68 | ||
69 | #include "8253.h" | |
70 | #include "8255.h" | |
124b13b2 FMH |
71 | #include "comedi_fc.h" |
72 | #include "ni_labpc.h" | |
73 | ||
42cb6a82 HS |
74 | /* |
75 | * Register map (all registers are 8-bit) | |
76 | */ | |
77 | #define STAT1_REG 0x00 /* R: Status 1 reg */ | |
78 | #define STAT1_DAVAIL (1 << 0) | |
79 | #define STAT1_OVERRUN (1 << 1) | |
80 | #define STAT1_OVERFLOW (1 << 2) | |
81 | #define STAT1_CNTINT (1 << 3) | |
82 | #define STAT1_GATA0 (1 << 5) | |
83 | #define STAT1_EXTGATA0 (1 << 6) | |
84 | #define CMD1_REG 0x00 /* W: Command 1 reg */ | |
85 | #define CMD1_MA(x) (((x) & 0x7) << 0) | |
86 | #define CMD1_TWOSCMP (1 << 3) | |
5e763f7b | 87 | #define CMD1_GAIN(x) (((x) & 0x7) << 4) |
42cb6a82 HS |
88 | #define CMD1_SCANEN (1 << 7) |
89 | #define CMD2_REG 0x01 /* W: Command 2 reg */ | |
90 | #define CMD2_PRETRIG (1 << 0) | |
91 | #define CMD2_HWTRIG (1 << 1) | |
92 | #define CMD2_SWTRIG (1 << 2) | |
93 | #define CMD2_TBSEL (1 << 3) | |
94 | #define CMD2_2SDAC0 (1 << 4) | |
95 | #define CMD2_2SDAC1 (1 << 5) | |
96 | #define CMD2_LDAC(x) (1 << (6 + (x))) | |
97 | #define CMD3_REG 0x02 /* W: Command 3 reg */ | |
98 | #define CMD3_DMAEN (1 << 0) | |
99 | #define CMD3_DIOINTEN (1 << 1) | |
100 | #define CMD3_DMATCINTEN (1 << 2) | |
101 | #define CMD3_CNTINTEN (1 << 3) | |
102 | #define CMD3_ERRINTEN (1 << 4) | |
103 | #define CMD3_FIFOINTEN (1 << 5) | |
104 | #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */ | |
105 | #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */ | |
106 | #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */ | |
107 | #define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */ | |
108 | #define ADC_FIFO_REG 0x0a /* R: A/D FIFO reg */ | |
109 | #define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */ | |
110 | #define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */ | |
111 | #define CMD6_REG 0x0e /* W: Command 6 reg */ | |
112 | #define CMD6_NRSE (1 << 0) | |
113 | #define CMD6_ADCUNI (1 << 1) | |
114 | #define CMD6_DACUNI(x) (1 << (2 + (x))) | |
115 | #define CMD6_HFINTEN (1 << 5) | |
116 | #define CMD6_DQINTEN (1 << 6) | |
117 | #define CMD6_SCANUP (1 << 7) | |
118 | #define CMD4_REG 0x0f /* W: Command 3 reg */ | |
119 | #define CMD4_INTSCAN (1 << 0) | |
120 | #define CMD4_EOIRCV (1 << 1) | |
121 | #define CMD4_ECLKDRV (1 << 2) | |
122 | #define CMD4_SEDIFF (1 << 3) | |
123 | #define CMD4_ECLKRCV (1 << 4) | |
124 | #define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */ | |
125 | #define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */ | |
42cb6a82 HS |
126 | #define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */ |
127 | #define CMD5_REG 0x1c /* W: Command 5 reg */ | |
128 | #define CMD5_WRTPRT (1 << 2) | |
129 | #define CMD5_DITHEREN (1 << 3) | |
130 | #define CMD5_CALDACLD (1 << 4) | |
131 | #define CMD5_SCLK (1 << 5) | |
132 | #define CMD5_SDATA (1 << 6) | |
133 | #define CMD5_EEPROMCS (1 << 7) | |
134 | #define STAT2_REG 0x1d /* R: Status 2 reg */ | |
135 | #define STAT2_PROMOUT (1 << 0) | |
136 | #define STAT2_OUTA1 (1 << 1) | |
137 | #define STAT2_FIFONHF (1 << 2) | |
138 | #define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */ | |
139 | #define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */ | |
124b13b2 | 140 | |
488ec9f1 HS |
141 | #define LABPC_SIZE 0x20 /* size of ISA io region */ |
142 | #define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ | |
810c73c7 HS |
143 | #define LABPC_ADC_TIMEOUT 1000 |
144 | ||
6f73fbce IA |
145 | enum scan_mode { |
146 | MODE_SINGLE_CHAN, | |
147 | MODE_SINGLE_CHAN_INTERVAL, | |
148 | MODE_MULT_CHAN_UP, | |
149 | MODE_MULT_CHAN_DOWN, | |
150 | }; | |
151 | ||
9ced1de6 | 152 | static const struct comedi_lrange range_labpc_plus_ai = { |
1b3e0c80 HS |
153 | 16, { |
154 | BIP_RANGE(5), | |
155 | BIP_RANGE(4), | |
156 | BIP_RANGE(2.5), | |
157 | BIP_RANGE(1), | |
158 | BIP_RANGE(0.5), | |
159 | BIP_RANGE(0.25), | |
160 | BIP_RANGE(0.1), | |
161 | BIP_RANGE(0.05), | |
162 | UNI_RANGE(10), | |
163 | UNI_RANGE(8), | |
164 | UNI_RANGE(5), | |
165 | UNI_RANGE(2), | |
166 | UNI_RANGE(1), | |
167 | UNI_RANGE(0.5), | |
168 | UNI_RANGE(0.2), | |
169 | UNI_RANGE(0.1) | |
170 | } | |
124b13b2 FMH |
171 | }; |
172 | ||
70d52bce | 173 | static const struct comedi_lrange range_labpc_1200_ai = { |
1b3e0c80 HS |
174 | 14, { |
175 | BIP_RANGE(5), | |
176 | BIP_RANGE(2.5), | |
177 | BIP_RANGE(1), | |
178 | BIP_RANGE(0.5), | |
179 | BIP_RANGE(0.25), | |
180 | BIP_RANGE(0.1), | |
181 | BIP_RANGE(0.05), | |
182 | UNI_RANGE(10), | |
183 | UNI_RANGE(5), | |
184 | UNI_RANGE(2), | |
185 | UNI_RANGE(1), | |
186 | UNI_RANGE(0.5), | |
187 | UNI_RANGE(0.2), | |
188 | UNI_RANGE(0.1) | |
189 | } | |
124b13b2 FMH |
190 | }; |
191 | ||
9ced1de6 | 192 | static const struct comedi_lrange range_labpc_ao = { |
1b3e0c80 HS |
193 | 2, { |
194 | BIP_RANGE(5), | |
195 | UNI_RANGE(10) | |
196 | } | |
124b13b2 FMH |
197 | }; |
198 | ||
199 | /* functions that do inb/outb and readb/writeb so we can use | |
200 | * function pointers to decide which to use */ | |
201 | static inline unsigned int labpc_inb(unsigned long address) | |
202 | { | |
203 | return inb(address); | |
204 | } | |
0a85b6f0 | 205 | |
124b13b2 FMH |
206 | static inline void labpc_outb(unsigned int byte, unsigned long address) |
207 | { | |
208 | outb(byte, address); | |
209 | } | |
0a85b6f0 | 210 | |
124b13b2 FMH |
211 | static inline unsigned int labpc_readb(unsigned long address) |
212 | { | |
5743aaac | 213 | return readb((void __iomem *)address); |
124b13b2 | 214 | } |
0a85b6f0 | 215 | |
124b13b2 FMH |
216 | static inline void labpc_writeb(unsigned int byte, unsigned long address) |
217 | { | |
5743aaac | 218 | writeb(byte, (void __iomem *)address); |
124b13b2 FMH |
219 | } |
220 | ||
a0eeed40 | 221 | #if IS_ENABLED(CONFIG_COMEDI_NI_LABPC_ISA) |
f65d971d | 222 | static const struct labpc_boardinfo labpc_boards[] = { |
124b13b2 | 223 | { |
f2c447ca | 224 | .name = "lab-pc-1200", |
63d6ba20 | 225 | .ai_speed = 10000, |
f2c447ca | 226 | .ai_scan_up = 1, |
63d6ba20 HS |
227 | .has_ao = 1, |
228 | .is_labpc1200 = 1, | |
f2c447ca HS |
229 | }, { |
230 | .name = "lab-pc-1200ai", | |
63d6ba20 | 231 | .ai_speed = 10000, |
f2c447ca | 232 | .ai_scan_up = 1, |
63d6ba20 | 233 | .is_labpc1200 = 1, |
f2c447ca HS |
234 | }, { |
235 | .name = "lab-pc+", | |
63d6ba20 HS |
236 | .ai_speed = 12000, |
237 | .has_ao = 1, | |
f2c447ca | 238 | }, |
124b13b2 | 239 | }; |
fa3cb219 | 240 | #endif |
124b13b2 | 241 | |
e41a6f6d SR |
242 | /* size in bytes of dma buffer */ |
243 | static const int dma_buffer_size = 0xff00; | |
244 | /* 2 bytes per sample */ | |
245 | static const int sample_size = 2; | |
124b13b2 | 246 | |
fbca05d6 HS |
247 | static int labpc_counter_load(struct comedi_device *dev, |
248 | unsigned long base_address, | |
249 | unsigned int counter_number, | |
250 | unsigned int count, unsigned int mode) | |
251 | { | |
252 | const struct labpc_boardinfo *board = comedi_board(dev); | |
253 | ||
254 | if (board->has_mmio) | |
255 | return i8254_mm_load((void __iomem *)base_address, 0, | |
256 | counter_number, count, mode); | |
257 | else | |
258 | return i8254_load(base_address, 0, counter_number, count, mode); | |
259 | } | |
260 | ||
463f9304 HS |
261 | static int labpc_counter_set_mode(struct comedi_device *dev, |
262 | unsigned long base_address, | |
263 | unsigned int counter_number, | |
264 | unsigned int mode) | |
265 | { | |
266 | const struct labpc_boardinfo *board = comedi_board(dev); | |
267 | ||
268 | if (board->has_mmio) | |
269 | return i8254_mm_set_mode((void __iomem *)base_address, 0, | |
270 | counter_number, mode); | |
271 | else | |
272 | return i8254_set_mode(base_address, 0, counter_number, mode); | |
273 | } | |
274 | ||
43a9411a HS |
275 | static bool labpc_range_is_unipolar(struct comedi_subdevice *s, |
276 | unsigned int range) | |
277 | { | |
43d092c6 | 278 | return s->range_table->range[range].min >= 0; |
43a9411a HS |
279 | } |
280 | ||
8a498667 HS |
281 | static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
282 | { | |
283 | struct labpc_private *devpriv = dev->private; | |
284 | unsigned long flags; | |
285 | ||
286 | spin_lock_irqsave(&dev->spinlock, flags); | |
42cb6a82 HS |
287 | devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); |
288 | devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); | |
8a498667 HS |
289 | spin_unlock_irqrestore(&dev->spinlock, flags); |
290 | ||
291 | devpriv->cmd3 = 0; | |
42cb6a82 | 292 | devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); |
8a498667 HS |
293 | |
294 | return 0; | |
295 | } | |
296 | ||
8c2bc333 HS |
297 | static void labpc_ai_set_chan_and_gain(struct comedi_device *dev, |
298 | enum scan_mode mode, | |
299 | unsigned int chan, | |
300 | unsigned int range, | |
301 | unsigned int aref) | |
302 | { | |
303 | const struct labpc_boardinfo *board = comedi_board(dev); | |
304 | struct labpc_private *devpriv = dev->private; | |
305 | ||
5e763f7b HS |
306 | if (board->is_labpc1200) { |
307 | /* | |
308 | * The LabPC-1200 boards do not have a gain | |
309 | * of '0x10'. Skip the range values that would | |
310 | * result in this gain. | |
311 | */ | |
312 | range += (range > 0) + (range > 7); | |
313 | } | |
314 | ||
8c2bc333 HS |
315 | /* munge channel bits for differential/scan disabled mode */ |
316 | if ((mode == MODE_SINGLE_CHAN || mode == MODE_SINGLE_CHAN_INTERVAL) && | |
317 | aref == AREF_DIFF) | |
318 | chan *= 2; | |
42cb6a82 | 319 | devpriv->cmd1 = CMD1_MA(chan); |
5e763f7b | 320 | devpriv->cmd1 |= CMD1_GAIN(range); |
8c2bc333 | 321 | |
42cb6a82 | 322 | devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); |
8c2bc333 HS |
323 | } |
324 | ||
359553bb HS |
325 | static void labpc_setup_cmd6_reg(struct comedi_device *dev, |
326 | struct comedi_subdevice *s, | |
327 | enum scan_mode mode, | |
328 | enum transfer_type xfer, | |
329 | unsigned int range, | |
330 | unsigned int aref, | |
331 | bool ena_intr) | |
332 | { | |
333 | const struct labpc_boardinfo *board = comedi_board(dev); | |
334 | struct labpc_private *devpriv = dev->private; | |
335 | ||
63d6ba20 | 336 | if (!board->is_labpc1200) |
359553bb HS |
337 | return; |
338 | ||
339 | /* reference inputs to ground or common? */ | |
340 | if (aref != AREF_GROUND) | |
42cb6a82 | 341 | devpriv->cmd6 |= CMD6_NRSE; |
359553bb | 342 | else |
42cb6a82 | 343 | devpriv->cmd6 &= ~CMD6_NRSE; |
359553bb HS |
344 | |
345 | /* bipolar or unipolar range? */ | |
346 | if (labpc_range_is_unipolar(s, range)) | |
42cb6a82 | 347 | devpriv->cmd6 |= CMD6_ADCUNI; |
359553bb | 348 | else |
42cb6a82 | 349 | devpriv->cmd6 &= ~CMD6_ADCUNI; |
359553bb HS |
350 | |
351 | /* interrupt on fifo half full? */ | |
352 | if (xfer == fifo_half_full_transfer) | |
42cb6a82 | 353 | devpriv->cmd6 |= CMD6_HFINTEN; |
359553bb | 354 | else |
42cb6a82 | 355 | devpriv->cmd6 &= ~CMD6_HFINTEN; |
359553bb HS |
356 | |
357 | /* enable interrupt on counter a1 terminal count? */ | |
358 | if (ena_intr) | |
42cb6a82 | 359 | devpriv->cmd6 |= CMD6_DQINTEN; |
359553bb | 360 | else |
42cb6a82 | 361 | devpriv->cmd6 &= ~CMD6_DQINTEN; |
359553bb HS |
362 | |
363 | /* are we scanning up or down through channels? */ | |
364 | if (mode == MODE_MULT_CHAN_UP) | |
42cb6a82 | 365 | devpriv->cmd6 |= CMD6_SCANUP; |
359553bb | 366 | else |
42cb6a82 | 367 | devpriv->cmd6 &= ~CMD6_SCANUP; |
359553bb | 368 | |
42cb6a82 | 369 | devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); |
359553bb HS |
370 | } |
371 | ||
3c4dfac8 HS |
372 | static unsigned int labpc_read_adc_fifo(struct comedi_device *dev) |
373 | { | |
374 | struct labpc_private *devpriv = dev->private; | |
375 | unsigned int lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
376 | unsigned int msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
377 | ||
378 | return (msb << 8) | lsb; | |
379 | } | |
380 | ||
381 | static void labpc_clear_adc_fifo(struct comedi_device *dev) | |
124b13b2 | 382 | { |
9a1a6cf8 | 383 | struct labpc_private *devpriv = dev->private; |
78110bb8 | 384 | |
42cb6a82 | 385 | devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); |
3c4dfac8 | 386 | labpc_read_adc_fifo(dev); |
dd2aef64 | 387 | } |
124b13b2 | 388 | |
810c73c7 HS |
389 | static int labpc_ai_wait_for_data(struct comedi_device *dev, |
390 | int timeout) | |
391 | { | |
392 | struct labpc_private *devpriv = dev->private; | |
393 | int i; | |
394 | ||
395 | for (i = 0; i < timeout; i++) { | |
42cb6a82 HS |
396 | devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); |
397 | if (devpriv->stat1 & STAT1_DAVAIL) | |
810c73c7 HS |
398 | return 0; |
399 | udelay(1); | |
400 | } | |
401 | return -ETIME; | |
402 | } | |
403 | ||
28a10930 HS |
404 | static int labpc_ai_insn_read(struct comedi_device *dev, |
405 | struct comedi_subdevice *s, | |
406 | struct comedi_insn *insn, | |
407 | unsigned int *data) | |
dd2aef64 HS |
408 | { |
409 | struct labpc_private *devpriv = dev->private; | |
73f2b1d2 HS |
410 | unsigned int chan = CR_CHAN(insn->chanspec); |
411 | unsigned int range = CR_RANGE(insn->chanspec); | |
412 | unsigned int aref = CR_AREF(insn->chanspec); | |
810c73c7 HS |
413 | int ret; |
414 | int i; | |
124b13b2 | 415 | |
8a498667 HS |
416 | /* disable timed conversions, interrupt generation and dma */ |
417 | labpc_cancel(dev, s); | |
124b13b2 | 418 | |
8c2bc333 | 419 | labpc_ai_set_chan_and_gain(dev, MODE_SINGLE_CHAN, chan, range, aref); |
124b13b2 | 420 | |
359553bb HS |
421 | labpc_setup_cmd6_reg(dev, s, MODE_SINGLE_CHAN, fifo_not_empty_transfer, |
422 | range, aref, false); | |
423 | ||
74df5760 HS |
424 | /* setup cmd4 register */ |
425 | devpriv->cmd4 = 0; | |
42cb6a82 | 426 | devpriv->cmd4 |= CMD4_ECLKRCV; |
af81f093 | 427 | /* single-ended/differential */ |
73f2b1d2 | 428 | if (aref == AREF_DIFF) |
42cb6a82 HS |
429 | devpriv->cmd4 |= CMD4_SEDIFF; |
430 | devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); | |
124b13b2 | 431 | |
463f9304 | 432 | /* initialize pacer counter to prevent any problems */ |
f06563f0 HS |
433 | ret = labpc_counter_set_mode(dev, dev->iobase + COUNTER_A_BASE_REG, |
434 | 0, I8254_MODE2); | |
435 | if (ret) | |
436 | return ret; | |
7e2716cd | 437 | |
af81f093 | 438 | labpc_clear_adc_fifo(dev); |
7e2716cd | 439 | |
810c73c7 | 440 | for (i = 0; i < insn->n; i++) { |
af81f093 | 441 | /* trigger conversion */ |
42cb6a82 | 442 | devpriv->write_byte(0x1, dev->iobase + ADC_START_CONVERT_REG); |
7e2716cd | 443 | |
810c73c7 HS |
444 | ret = labpc_ai_wait_for_data(dev, LABPC_ADC_TIMEOUT); |
445 | if (ret) | |
446 | return ret; | |
447 | ||
448 | data[i] = labpc_read_adc_fifo(dev); | |
dd2aef64 | 449 | } |
9a1a6cf8 | 450 | |
810c73c7 | 451 | return insn->n; |
af81f093 | 452 | } |
124b13b2 | 453 | |
af81f093 HS |
454 | #ifdef CONFIG_ISA_DMA_API |
455 | /* utility function that suggests a dma transfer size in bytes */ | |
456 | static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd) | |
457 | { | |
458 | unsigned int size; | |
459 | unsigned int freq; | |
124b13b2 | 460 | |
af81f093 HS |
461 | if (cmd->convert_src == TRIG_TIMER) |
462 | freq = 1000000000 / cmd->convert_arg; | |
463 | /* return some default value */ | |
464 | else | |
465 | freq = 0xffffffff; | |
124b13b2 | 466 | |
af81f093 HS |
467 | /* make buffer fill in no more than 1/3 second */ |
468 | size = (freq / 3) * sample_size; | |
124b13b2 | 469 | |
af81f093 HS |
470 | /* set a minimum and maximum size allowed */ |
471 | if (size > dma_buffer_size) | |
472 | size = dma_buffer_size - dma_buffer_size % sample_size; | |
473 | else if (size < sample_size) | |
474 | size = sample_size; | |
124b13b2 | 475 | |
af81f093 | 476 | return size; |
124b13b2 | 477 | } |
af81f093 | 478 | #endif |
124b13b2 | 479 | |
63a93381 HS |
480 | static bool labpc_use_continuous_mode(const struct comedi_cmd *cmd, |
481 | enum scan_mode mode) | |
124b13b2 | 482 | { |
63a93381 HS |
483 | if (mode == MODE_SINGLE_CHAN || cmd->scan_begin_src == TRIG_FOLLOW) |
484 | return true; | |
124b13b2 | 485 | |
63a93381 | 486 | return false; |
124b13b2 FMH |
487 | } |
488 | ||
6f73fbce IA |
489 | static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd, |
490 | enum scan_mode mode) | |
124b13b2 FMH |
491 | { |
492 | if (cmd->convert_src != TRIG_TIMER) | |
493 | return 0; | |
494 | ||
6f73fbce | 495 | if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER) |
124b13b2 FMH |
496 | return cmd->scan_begin_arg; |
497 | ||
498 | return cmd->convert_arg; | |
499 | } | |
500 | ||
6f73fbce IA |
501 | static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, |
502 | enum scan_mode mode, unsigned int ns) | |
124b13b2 FMH |
503 | { |
504 | if (cmd->convert_src != TRIG_TIMER) | |
505 | return; | |
506 | ||
6f73fbce | 507 | if (mode == MODE_SINGLE_CHAN && |
0a85b6f0 | 508 | cmd->scan_begin_src == TRIG_TIMER) { |
124b13b2 FMH |
509 | cmd->scan_begin_arg = ns; |
510 | if (cmd->convert_arg > cmd->scan_begin_arg) | |
511 | cmd->convert_arg = cmd->scan_begin_arg; | |
512 | } else | |
513 | cmd->convert_arg = ns; | |
514 | } | |
515 | ||
6f73fbce IA |
516 | static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd, |
517 | enum scan_mode mode) | |
124b13b2 FMH |
518 | { |
519 | if (cmd->scan_begin_src != TRIG_TIMER) | |
520 | return 0; | |
521 | ||
6f73fbce | 522 | if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) |
124b13b2 FMH |
523 | return 0; |
524 | ||
525 | return cmd->scan_begin_arg; | |
526 | } | |
527 | ||
af81f093 HS |
528 | static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, |
529 | enum scan_mode mode, unsigned int ns) | |
530 | { | |
531 | if (cmd->scan_begin_src != TRIG_TIMER) | |
532 | return; | |
533 | ||
534 | if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) | |
535 | return; | |
536 | ||
537 | cmd->scan_begin_arg = ns; | |
538 | } | |
539 | ||
540 | /* figures out what counter values to use based on command */ | |
541 | static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd, | |
542 | enum scan_mode mode) | |
543 | { | |
544 | struct labpc_private *devpriv = dev->private; | |
545 | /* max value for 16 bit counter in mode 2 */ | |
546 | const int max_counter_value = 0x10000; | |
547 | /* min value for 16 bit counter in mode 2 */ | |
548 | const int min_counter_value = 2; | |
549 | unsigned int base_period; | |
550 | unsigned int scan_period; | |
551 | unsigned int convert_period; | |
552 | ||
553 | /* | |
554 | * if both convert and scan triggers are TRIG_TIMER, then they | |
555 | * both rely on counter b0 | |
556 | */ | |
557 | convert_period = labpc_ai_convert_period(cmd, mode); | |
558 | scan_period = labpc_ai_scan_period(cmd, mode); | |
559 | if (convert_period && scan_period) { | |
560 | /* | |
561 | * pick the lowest b0 divisor value we can (for maximum input | |
562 | * clock speed on convert and scan counters) | |
563 | */ | |
564 | devpriv->divisor_b0 = (scan_period - 1) / | |
565 | (LABPC_TIMER_BASE * max_counter_value) + 1; | |
566 | if (devpriv->divisor_b0 < min_counter_value) | |
567 | devpriv->divisor_b0 = min_counter_value; | |
568 | if (devpriv->divisor_b0 > max_counter_value) | |
569 | devpriv->divisor_b0 = max_counter_value; | |
570 | ||
571 | base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; | |
572 | ||
573 | /* set a0 for conversion frequency and b1 for scan frequency */ | |
574 | switch (cmd->flags & TRIG_ROUND_MASK) { | |
575 | default: | |
576 | case TRIG_ROUND_NEAREST: | |
577 | devpriv->divisor_a0 = | |
578 | (convert_period + (base_period / 2)) / base_period; | |
579 | devpriv->divisor_b1 = | |
580 | (scan_period + (base_period / 2)) / base_period; | |
581 | break; | |
582 | case TRIG_ROUND_UP: | |
583 | devpriv->divisor_a0 = | |
584 | (convert_period + (base_period - 1)) / base_period; | |
585 | devpriv->divisor_b1 = | |
586 | (scan_period + (base_period - 1)) / base_period; | |
587 | break; | |
588 | case TRIG_ROUND_DOWN: | |
589 | devpriv->divisor_a0 = convert_period / base_period; | |
590 | devpriv->divisor_b1 = scan_period / base_period; | |
591 | break; | |
592 | } | |
593 | /* make sure a0 and b1 values are acceptable */ | |
594 | if (devpriv->divisor_a0 < min_counter_value) | |
595 | devpriv->divisor_a0 = min_counter_value; | |
596 | if (devpriv->divisor_a0 > max_counter_value) | |
597 | devpriv->divisor_a0 = max_counter_value; | |
598 | if (devpriv->divisor_b1 < min_counter_value) | |
599 | devpriv->divisor_b1 = min_counter_value; | |
600 | if (devpriv->divisor_b1 > max_counter_value) | |
601 | devpriv->divisor_b1 = max_counter_value; | |
602 | /* write corrected timings to command */ | |
603 | labpc_set_ai_convert_period(cmd, mode, | |
604 | base_period * devpriv->divisor_a0); | |
605 | labpc_set_ai_scan_period(cmd, mode, | |
606 | base_period * devpriv->divisor_b1); | |
607 | /* | |
608 | * if only one TRIG_TIMER is used, we can employ the generic | |
609 | * cascaded timing functions | |
610 | */ | |
611 | } else if (scan_period) { | |
612 | /* | |
613 | * calculate cascaded counter values | |
614 | * that give desired scan timing | |
615 | */ | |
616 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, | |
617 | &(devpriv->divisor_b1), | |
618 | &(devpriv->divisor_b0), | |
619 | &scan_period, | |
620 | cmd->flags & TRIG_ROUND_MASK); | |
621 | labpc_set_ai_scan_period(cmd, mode, scan_period); | |
622 | } else if (convert_period) { | |
623 | /* | |
624 | * calculate cascaded counter values | |
625 | * that give desired conversion timing | |
626 | */ | |
627 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, | |
628 | &(devpriv->divisor_a0), | |
629 | &(devpriv->divisor_b0), | |
630 | &convert_period, | |
631 | cmd->flags & TRIG_ROUND_MASK); | |
632 | labpc_set_ai_convert_period(cmd, mode, convert_period); | |
633 | } | |
634 | } | |
635 | ||
636 | static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) | |
637 | { | |
638 | if (cmd->chanlist_len == 1) | |
639 | return MODE_SINGLE_CHAN; | |
640 | ||
641 | /* chanlist may be NULL during cmdtest. */ | |
642 | if (cmd->chanlist == NULL) | |
643 | return MODE_MULT_CHAN_UP; | |
644 | ||
645 | if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) | |
646 | return MODE_SINGLE_CHAN_INTERVAL; | |
647 | ||
648 | if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) | |
649 | return MODE_MULT_CHAN_UP; | |
650 | ||
651 | if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) | |
652 | return MODE_MULT_CHAN_DOWN; | |
653 | ||
654 | pr_err("ni_labpc: bug! cannot determine AI scan mode\n"); | |
655 | return 0; | |
656 | } | |
657 | ||
658 | static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, | |
659 | const struct comedi_cmd *cmd, | |
660 | enum scan_mode mode) | |
661 | { | |
662 | int channel, range, aref, i; | |
663 | ||
664 | if (cmd->chanlist == NULL) | |
665 | return 0; | |
666 | ||
667 | if (mode == MODE_SINGLE_CHAN) | |
668 | return 0; | |
669 | ||
670 | if (mode == MODE_SINGLE_CHAN_INTERVAL) { | |
671 | if (cmd->chanlist_len > 0xff) { | |
672 | comedi_error(dev, | |
673 | "ni_labpc: chanlist too long for single channel interval mode\n"); | |
674 | return 1; | |
675 | } | |
676 | } | |
677 | ||
678 | channel = CR_CHAN(cmd->chanlist[0]); | |
679 | range = CR_RANGE(cmd->chanlist[0]); | |
680 | aref = CR_AREF(cmd->chanlist[0]); | |
681 | ||
682 | for (i = 0; i < cmd->chanlist_len; i++) { | |
683 | ||
684 | switch (mode) { | |
685 | case MODE_SINGLE_CHAN_INTERVAL: | |
686 | if (CR_CHAN(cmd->chanlist[i]) != channel) { | |
687 | comedi_error(dev, | |
688 | "channel scanning order specified in chanlist is not supported by hardware.\n"); | |
689 | return 1; | |
690 | } | |
691 | break; | |
692 | case MODE_MULT_CHAN_UP: | |
693 | if (CR_CHAN(cmd->chanlist[i]) != i) { | |
694 | comedi_error(dev, | |
695 | "channel scanning order specified in chanlist is not supported by hardware.\n"); | |
696 | return 1; | |
697 | } | |
698 | break; | |
699 | case MODE_MULT_CHAN_DOWN: | |
700 | if (CR_CHAN(cmd->chanlist[i]) != | |
701 | cmd->chanlist_len - i - 1) { | |
702 | comedi_error(dev, | |
703 | "channel scanning order specified in chanlist is not supported by hardware.\n"); | |
704 | return 1; | |
705 | } | |
706 | break; | |
707 | default: | |
708 | dev_err(dev->class_dev, | |
709 | "ni_labpc: bug! in chanlist check\n"); | |
710 | return 1; | |
711 | break; | |
712 | } | |
713 | ||
714 | if (CR_RANGE(cmd->chanlist[i]) != range) { | |
715 | comedi_error(dev, | |
716 | "entries in chanlist must all have the same range\n"); | |
717 | return 1; | |
718 | } | |
124b13b2 | 719 | |
af81f093 HS |
720 | if (CR_AREF(cmd->chanlist[i]) != aref) { |
721 | comedi_error(dev, | |
722 | "entries in chanlist must all have the same reference\n"); | |
723 | return 1; | |
724 | } | |
725 | } | |
124b13b2 | 726 | |
af81f093 | 727 | return 0; |
124b13b2 FMH |
728 | } |
729 | ||
0a85b6f0 MT |
730 | static int labpc_ai_cmdtest(struct comedi_device *dev, |
731 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
124b13b2 | 732 | { |
d0baa0c1 | 733 | const struct labpc_boardinfo *board = comedi_board(dev); |
124b13b2 FMH |
734 | int err = 0; |
735 | int tmp, tmp2; | |
27020ffe | 736 | unsigned int stop_mask; |
6f73fbce | 737 | enum scan_mode mode; |
124b13b2 | 738 | |
27020ffe | 739 | /* Step 1 : check if triggers are trivially valid */ |
124b13b2 | 740 | |
27020ffe HS |
741 | err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); |
742 | err |= cfc_check_trigger_src(&cmd->scan_begin_src, | |
743 | TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); | |
744 | err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT); | |
745 | err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
124b13b2 | 746 | |
124b13b2 | 747 | stop_mask = TRIG_COUNT | TRIG_NONE; |
63d6ba20 | 748 | if (board->is_labpc1200) |
124b13b2 | 749 | stop_mask |= TRIG_EXT; |
27020ffe | 750 | err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask); |
124b13b2 FMH |
751 | |
752 | if (err) | |
753 | return 1; | |
754 | ||
27020ffe | 755 | /* Step 2a : make sure trigger sources are unique */ |
124b13b2 | 756 | |
27020ffe HS |
757 | err |= cfc_check_trigger_is_unique(cmd->start_src); |
758 | err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); | |
759 | err |= cfc_check_trigger_is_unique(cmd->convert_src); | |
760 | err |= cfc_check_trigger_is_unique(cmd->stop_src); | |
761 | ||
762 | /* Step 2b : and mutually compatible */ | |
124b13b2 | 763 | |
e41a6f6d | 764 | /* can't have external stop and start triggers at once */ |
124b13b2 FMH |
765 | if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) |
766 | err++; | |
767 | ||
768 | if (err) | |
769 | return 2; | |
770 | ||
88c79301 | 771 | /* Step 3: check if arguments are trivially valid */ |
124b13b2 | 772 | |
88c79301 HS |
773 | if (cmd->start_arg == TRIG_NOW) |
774 | err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); | |
124b13b2 | 775 | |
412bd046 | 776 | if (!cmd->chanlist_len) |
88c79301 HS |
777 | err |= -EINVAL; |
778 | err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); | |
412bd046 | 779 | |
88c79301 HS |
780 | if (cmd->convert_src == TRIG_TIMER) |
781 | err |= cfc_check_trigger_arg_min(&cmd->convert_arg, | |
d0baa0c1 | 782 | board->ai_speed); |
124b13b2 | 783 | |
e41a6f6d | 784 | /* make sure scan timing is not too fast */ |
124b13b2 | 785 | if (cmd->scan_begin_src == TRIG_TIMER) { |
88c79301 HS |
786 | if (cmd->convert_src == TRIG_TIMER) |
787 | err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, | |
788 | cmd->convert_arg * cmd->chanlist_len); | |
789 | err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, | |
d0baa0c1 | 790 | board->ai_speed * cmd->chanlist_len); |
124b13b2 | 791 | } |
88c79301 | 792 | |
124b13b2 FMH |
793 | switch (cmd->stop_src) { |
794 | case TRIG_COUNT: | |
88c79301 | 795 | err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); |
124b13b2 FMH |
796 | break; |
797 | case TRIG_NONE: | |
88c79301 | 798 | err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); |
124b13b2 | 799 | break; |
1309e617 MD |
800 | /* |
801 | * TRIG_EXT doesn't care since it doesn't | |
802 | * trigger off a numbered channel | |
803 | */ | |
124b13b2 FMH |
804 | default: |
805 | break; | |
806 | } | |
807 | ||
808 | if (err) | |
809 | return 3; | |
810 | ||
811 | /* step 4: fix up any arguments */ | |
812 | ||
813 | tmp = cmd->convert_arg; | |
814 | tmp2 = cmd->scan_begin_arg; | |
6f73fbce IA |
815 | mode = labpc_ai_scan_mode(cmd); |
816 | labpc_adc_timing(dev, cmd, mode); | |
124b13b2 FMH |
817 | if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) |
818 | err++; | |
819 | ||
820 | if (err) | |
821 | return 4; | |
822 | ||
6f73fbce | 823 | if (labpc_ai_chanlist_invalid(dev, cmd, mode)) |
124b13b2 FMH |
824 | return 5; |
825 | ||
826 | return 0; | |
827 | } | |
828 | ||
da91b269 | 829 | static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
124b13b2 | 830 | { |
d0baa0c1 | 831 | const struct labpc_boardinfo *board = comedi_board(dev); |
9a1a6cf8 | 832 | struct labpc_private *devpriv = dev->private; |
d163679c | 833 | struct comedi_async *async = s->async; |
ea6d0d4c | 834 | struct comedi_cmd *cmd = &async->cmd; |
8a67a67f HS |
835 | enum scan_mode mode = labpc_ai_scan_mode(cmd); |
836 | unsigned int chanspec = (mode == MODE_MULT_CHAN_UP) | |
837 | ? cmd->chanlist[cmd->chanlist_len - 1] | |
838 | : cmd->chanlist[0]; | |
839 | unsigned int chan = CR_CHAN(chanspec); | |
840 | unsigned int range = CR_RANGE(chanspec); | |
841 | unsigned int aref = CR_AREF(chanspec); | |
124b13b2 FMH |
842 | enum transfer_type xfer; |
843 | unsigned long flags; | |
8a67a67f | 844 | int ret; |
124b13b2 | 845 | |
25985edc | 846 | /* make sure board is disabled before setting up acquisition */ |
8a498667 | 847 | labpc_cancel(dev, s); |
124b13b2 | 848 | |
f6b49620 | 849 | /* initialize software conversion count */ |
412bd046 | 850 | if (cmd->stop_src == TRIG_COUNT) |
124b13b2 | 851 | devpriv->count = cmd->stop_arg * cmd->chanlist_len; |
65d6d26c | 852 | |
f6b49620 | 853 | /* setup hardware conversion counter */ |
124b13b2 | 854 | if (cmd->stop_src == TRIG_EXT) { |
1309e617 MD |
855 | /* |
856 | * load counter a1 with count of 3 | |
857 | * (pc+ manual says this is minimum allowed) using mode 0 | |
858 | */ | |
124b13b2 | 859 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
fbca05d6 | 860 | 1, 3, I8254_MODE0); |
463f9304 HS |
861 | } else { |
862 | /* just put counter a1 in mode 0 to set its output low */ | |
f06563f0 HS |
863 | ret = labpc_counter_set_mode(dev, |
864 | dev->iobase + COUNTER_A_BASE_REG, | |
865 | 1, I8254_MODE0); | |
866 | } | |
867 | if (ret) { | |
868 | comedi_error(dev, "error loading counter a1"); | |
869 | return ret; | |
463f9304 | 870 | } |
124b13b2 | 871 | |
3297d6c7 | 872 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 BP |
873 | /* figure out what method we will use to transfer data */ |
874 | if (devpriv->dma_chan && /* need a dma channel allocated */ | |
1309e617 MD |
875 | /* |
876 | * dma unsafe at RT priority, | |
877 | * and too much setup time for TRIG_WAKE_EOS for | |
878 | */ | |
3a0a73b3 | 879 | (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0) { |
124b13b2 | 880 | xfer = isa_dma_transfer; |
1309e617 | 881 | /* pc-plus has no fifo-half full interrupt */ |
3297d6c7 RD |
882 | } else |
883 | #endif | |
63d6ba20 | 884 | if (board->is_labpc1200 && |
0a85b6f0 MT |
885 | /* wake-end-of-scan should interrupt on fifo not empty */ |
886 | (cmd->flags & TRIG_WAKE_EOS) == 0 && | |
887 | /* make sure we are taking more than just a few points */ | |
888 | (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { | |
124b13b2 FMH |
889 | xfer = fifo_half_full_transfer; |
890 | } else | |
891 | xfer = fifo_not_empty_transfer; | |
892 | devpriv->current_transfer = xfer; | |
893 | ||
8c2bc333 HS |
894 | labpc_ai_set_chan_and_gain(dev, mode, chan, range, aref); |
895 | ||
359553bb HS |
896 | labpc_setup_cmd6_reg(dev, s, mode, xfer, range, aref, |
897 | (cmd->stop_src == TRIG_EXT)); | |
898 | ||
e41a6f6d | 899 | /* manual says to set scan enable bit on second pass */ |
6f73fbce | 900 | if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) { |
42cb6a82 | 901 | devpriv->cmd1 |= CMD1_SCANEN; |
e41a6f6d SR |
902 | /* need a brief delay before enabling scan, or scan |
903 | * list will get screwed when you switch | |
124b13b2 | 904 | * between scan up to scan down mode - dunno why */ |
5f74ea14 | 905 | udelay(1); |
42cb6a82 | 906 | devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); |
124b13b2 | 907 | } |
124b13b2 FMH |
908 | |
909 | devpriv->write_byte(cmd->chanlist_len, | |
0a85b6f0 | 910 | dev->iobase + INTERVAL_COUNT_REG); |
f6b49620 | 911 | /* load count */ |
42cb6a82 | 912 | devpriv->write_byte(0x1, dev->iobase + INTERVAL_STROBE_REG); |
124b13b2 | 913 | |
d5c8d9c4 HS |
914 | if (cmd->convert_src == TRIG_TIMER || |
915 | cmd->scan_begin_src == TRIG_TIMER) { | |
f6b49620 | 916 | /* set up pacing */ |
6f73fbce | 917 | labpc_adc_timing(dev, cmd, mode); |
f6b49620 | 918 | /* load counter b0 in mode 3 */ |
124b13b2 | 919 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
fbca05d6 | 920 | 0, devpriv->divisor_b0, I8254_MODE3); |
124b13b2 FMH |
921 | if (ret < 0) { |
922 | comedi_error(dev, "error loading counter b0"); | |
923 | return -1; | |
924 | } | |
925 | } | |
f6b49620 | 926 | /* set up conversion pacing */ |
6f73fbce | 927 | if (labpc_ai_convert_period(cmd, mode)) { |
f6b49620 | 928 | /* load counter a0 in mode 2 */ |
124b13b2 | 929 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
fbca05d6 | 930 | 0, devpriv->divisor_a0, I8254_MODE2); |
463f9304 HS |
931 | } else { |
932 | /* initialize pacer counter to prevent any problems */ | |
f06563f0 HS |
933 | ret = labpc_counter_set_mode(dev, |
934 | dev->iobase + COUNTER_A_BASE_REG, | |
935 | 0, I8254_MODE2); | |
936 | } | |
937 | if (ret) { | |
938 | comedi_error(dev, "error loading counter a0"); | |
939 | return ret; | |
463f9304 | 940 | } |
124b13b2 | 941 | |
f6b49620 | 942 | /* set up scan pacing */ |
6f73fbce | 943 | if (labpc_ai_scan_period(cmd, mode)) { |
f6b49620 | 944 | /* load counter b1 in mode 2 */ |
124b13b2 | 945 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
fbca05d6 | 946 | 1, devpriv->divisor_b1, I8254_MODE2); |
124b13b2 FMH |
947 | if (ret < 0) { |
948 | comedi_error(dev, "error loading counter b1"); | |
949 | return -1; | |
950 | } | |
951 | } | |
952 | ||
953 | labpc_clear_adc_fifo(dev); | |
954 | ||
3297d6c7 | 955 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 | 956 | /* set up dma transfer */ |
124b13b2 | 957 | if (xfer == isa_dma_transfer) { |
fe7fc72a HS |
958 | unsigned long irq_flags; |
959 | ||
124b13b2 FMH |
960 | irq_flags = claim_dma_lock(); |
961 | disable_dma(devpriv->dma_chan); | |
962 | /* clear flip-flop to make sure 2-byte registers for | |
963 | * count and address get set correctly */ | |
964 | clear_dma_ff(devpriv->dma_chan); | |
1581a035 | 965 | set_dma_addr(devpriv->dma_chan, devpriv->dma_addr); |
f6b49620 | 966 | /* set appropriate size of transfer */ |
62fea8c8 | 967 | devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd); |
124b13b2 | 968 | if (cmd->stop_src == TRIG_COUNT && |
0a85b6f0 | 969 | devpriv->count * sample_size < devpriv->dma_transfer_size) { |
124b13b2 | 970 | devpriv->dma_transfer_size = |
0a85b6f0 | 971 | devpriv->count * sample_size; |
124b13b2 FMH |
972 | } |
973 | set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); | |
974 | enable_dma(devpriv->dma_chan); | |
975 | release_dma_lock(irq_flags); | |
f6b49620 | 976 | /* enable board's dma */ |
42cb6a82 | 977 | devpriv->cmd3 |= (CMD3_DMAEN | CMD3_DMATCINTEN); |
124b13b2 | 978 | } else |
42cb6a82 | 979 | devpriv->cmd3 &= ~(CMD3_DMAEN | CMD3_DMATCINTEN); |
3297d6c7 | 980 | #endif |
124b13b2 | 981 | |
f6b49620 | 982 | /* enable error interrupts */ |
42cb6a82 | 983 | devpriv->cmd3 |= CMD3_ERRINTEN; |
f6b49620 | 984 | /* enable fifo not empty interrupt? */ |
124b13b2 | 985 | if (xfer == fifo_not_empty_transfer) |
42cb6a82 | 986 | devpriv->cmd3 |= CMD3_FIFOINTEN; |
124b13b2 | 987 | else |
42cb6a82 HS |
988 | devpriv->cmd3 &= ~CMD3_FIFOINTEN; |
989 | devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); | |
124b13b2 | 990 | |
74df5760 HS |
991 | /* setup any external triggering/pacing (cmd4 register) */ |
992 | devpriv->cmd4 = 0; | |
22056e2b | 993 | if (cmd->convert_src != TRIG_EXT) |
42cb6a82 | 994 | devpriv->cmd4 |= CMD4_ECLKRCV; |
22056e2b IA |
995 | /* XXX should discard first scan when using interval scanning |
996 | * since manual says it is not synced with scan clock */ | |
63a93381 | 997 | if (!labpc_use_continuous_mode(cmd, mode)) { |
42cb6a82 | 998 | devpriv->cmd4 |= CMD4_INTSCAN; |
22056e2b | 999 | if (cmd->scan_begin_src == TRIG_EXT) |
42cb6a82 | 1000 | devpriv->cmd4 |= CMD4_EOIRCV; |
22056e2b IA |
1001 | } |
1002 | /* single-ended/differential */ | |
1003 | if (aref == AREF_DIFF) | |
42cb6a82 HS |
1004 | devpriv->cmd4 |= CMD4_SEDIFF; |
1005 | devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); | |
22056e2b | 1006 | |
25985edc | 1007 | /* startup acquisition */ |
124b13b2 | 1008 | |
5f74ea14 | 1009 | spin_lock_irqsave(&dev->spinlock, flags); |
58cd9b91 HS |
1010 | |
1011 | /* use 2 cascaded counters for pacing */ | |
42cb6a82 | 1012 | devpriv->cmd2 |= CMD2_TBSEL; |
58cd9b91 HS |
1013 | |
1014 | devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); | |
1015 | if (cmd->start_src == TRIG_EXT) | |
42cb6a82 | 1016 | devpriv->cmd2 |= CMD2_HWTRIG; |
58cd9b91 | 1017 | else |
42cb6a82 | 1018 | devpriv->cmd2 |= CMD2_SWTRIG; |
58cd9b91 | 1019 | if (cmd->stop_src == TRIG_EXT) |
42cb6a82 | 1020 | devpriv->cmd2 |= (CMD2_HWTRIG | CMD2_PRETRIG); |
58cd9b91 | 1021 | |
42cb6a82 | 1022 | devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); |
58cd9b91 | 1023 | |
5f74ea14 | 1024 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1025 | |
1026 | return 0; | |
1027 | } | |
1028 | ||
571e06c1 HS |
1029 | #ifdef CONFIG_ISA_DMA_API |
1030 | static void labpc_drain_dma(struct comedi_device *dev) | |
1031 | { | |
1032 | struct labpc_private *devpriv = dev->private; | |
1033 | struct comedi_subdevice *s = dev->read_subdev; | |
1034 | struct comedi_async *async = s->async; | |
1035 | int status; | |
1036 | unsigned long flags; | |
1037 | unsigned int max_points, num_points, residue, leftover; | |
1038 | int i; | |
1039 | ||
74df5760 | 1040 | status = devpriv->stat1; |
571e06c1 HS |
1041 | |
1042 | flags = claim_dma_lock(); | |
1043 | disable_dma(devpriv->dma_chan); | |
1044 | /* clear flip-flop to make sure 2-byte registers for | |
1045 | * count and address get set correctly */ | |
1046 | clear_dma_ff(devpriv->dma_chan); | |
1047 | ||
1048 | /* figure out how many points to read */ | |
1049 | max_points = devpriv->dma_transfer_size / sample_size; | |
1050 | /* residue is the number of points left to be done on the dma | |
1051 | * transfer. It should always be zero at this point unless | |
1052 | * the stop_src is set to external triggering. | |
1053 | */ | |
1054 | residue = get_dma_residue(devpriv->dma_chan) / sample_size; | |
1055 | num_points = max_points - residue; | |
1056 | if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) | |
1057 | num_points = devpriv->count; | |
1058 | ||
1059 | /* figure out how many points will be stored next time */ | |
1060 | leftover = 0; | |
1061 | if (async->cmd.stop_src != TRIG_COUNT) { | |
1062 | leftover = devpriv->dma_transfer_size / sample_size; | |
1063 | } else if (devpriv->count > num_points) { | |
1064 | leftover = devpriv->count - num_points; | |
1065 | if (leftover > max_points) | |
1066 | leftover = max_points; | |
1067 | } | |
1068 | ||
1069 | /* write data to comedi buffer */ | |
1070 | for (i = 0; i < num_points; i++) | |
1071 | cfc_write_to_buffer(s, devpriv->dma_buffer[i]); | |
1072 | ||
1073 | if (async->cmd.stop_src == TRIG_COUNT) | |
1074 | devpriv->count -= num_points; | |
1075 | ||
1076 | /* set address and count for next transfer */ | |
1581a035 | 1077 | set_dma_addr(devpriv->dma_chan, devpriv->dma_addr); |
571e06c1 HS |
1078 | set_dma_count(devpriv->dma_chan, leftover * sample_size); |
1079 | release_dma_lock(flags); | |
1080 | ||
1081 | async->events |= COMEDI_CB_BLOCK; | |
1082 | } | |
1083 | ||
1084 | static void handle_isa_dma(struct comedi_device *dev) | |
1085 | { | |
1086 | struct labpc_private *devpriv = dev->private; | |
1087 | ||
1088 | labpc_drain_dma(dev); | |
1089 | ||
1090 | enable_dma(devpriv->dma_chan); | |
1091 | ||
1092 | /* clear dma tc interrupt */ | |
1093 | devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); | |
1094 | } | |
1095 | #endif | |
1096 | ||
1097 | /* read all available samples from ai fifo */ | |
1098 | static int labpc_drain_fifo(struct comedi_device *dev) | |
1099 | { | |
1100 | struct labpc_private *devpriv = dev->private; | |
571e06c1 HS |
1101 | short data; |
1102 | struct comedi_async *async = dev->read_subdev->async; | |
1103 | const int timeout = 10000; | |
1104 | unsigned int i; | |
1105 | ||
42cb6a82 | 1106 | devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); |
571e06c1 | 1107 | |
42cb6a82 | 1108 | for (i = 0; (devpriv->stat1 & STAT1_DAVAIL) && i < timeout; |
571e06c1 HS |
1109 | i++) { |
1110 | /* quit if we have all the data we want */ | |
1111 | if (async->cmd.stop_src == TRIG_COUNT) { | |
1112 | if (devpriv->count == 0) | |
1113 | break; | |
1114 | devpriv->count--; | |
1115 | } | |
3c4dfac8 | 1116 | data = labpc_read_adc_fifo(dev); |
571e06c1 | 1117 | cfc_write_to_buffer(dev->read_subdev, data); |
42cb6a82 | 1118 | devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); |
571e06c1 HS |
1119 | } |
1120 | if (i == timeout) { | |
1121 | comedi_error(dev, "ai timeout, fifo never empties"); | |
1122 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
1123 | return -1; | |
1124 | } | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
1129 | /* makes sure all data acquired by board is transferred to comedi (used | |
1130 | * when acquisition is terminated by stop_src == TRIG_EXT). */ | |
1131 | static void labpc_drain_dregs(struct comedi_device *dev) | |
1132 | { | |
1133 | #ifdef CONFIG_ISA_DMA_API | |
1134 | struct labpc_private *devpriv = dev->private; | |
1135 | ||
1136 | if (devpriv->current_transfer == isa_dma_transfer) | |
1137 | labpc_drain_dma(dev); | |
1138 | #endif | |
1139 | ||
1140 | labpc_drain_fifo(dev); | |
1141 | } | |
1142 | ||
1143 | /* interrupt service routine */ | |
1144 | static irqreturn_t labpc_interrupt(int irq, void *d) | |
1145 | { | |
1146 | struct comedi_device *dev = d; | |
d0baa0c1 | 1147 | const struct labpc_boardinfo *board = comedi_board(dev); |
571e06c1 HS |
1148 | struct labpc_private *devpriv = dev->private; |
1149 | struct comedi_subdevice *s = dev->read_subdev; | |
1150 | struct comedi_async *async; | |
1151 | struct comedi_cmd *cmd; | |
1152 | ||
1153 | if (!dev->attached) { | |
1154 | comedi_error(dev, "premature interrupt"); | |
1155 | return IRQ_HANDLED; | |
1156 | } | |
1157 | ||
1158 | async = s->async; | |
1159 | cmd = &async->cmd; | |
1160 | async->events = 0; | |
1161 | ||
1162 | /* read board status */ | |
42cb6a82 | 1163 | devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); |
63d6ba20 | 1164 | if (board->is_labpc1200) |
42cb6a82 | 1165 | devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG); |
571e06c1 | 1166 | |
42cb6a82 HS |
1167 | if ((devpriv->stat1 & (STAT1_GATA0 | STAT1_CNTINT | STAT1_OVERFLOW | |
1168 | STAT1_OVERRUN | STAT1_DAVAIL)) == 0 | |
1169 | && (devpriv->stat2 & STAT2_OUTA1) == 0 | |
1170 | && (devpriv->stat2 & STAT2_FIFONHF)) { | |
571e06c1 HS |
1171 | return IRQ_NONE; |
1172 | } | |
1173 | ||
42cb6a82 | 1174 | if (devpriv->stat1 & STAT1_OVERRUN) { |
571e06c1 | 1175 | /* clear error interrupt */ |
42cb6a82 | 1176 | devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); |
571e06c1 HS |
1177 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; |
1178 | comedi_event(dev, s); | |
1179 | comedi_error(dev, "overrun"); | |
1180 | return IRQ_HANDLED; | |
1181 | } | |
1182 | ||
1183 | #ifdef CONFIG_ISA_DMA_API | |
1184 | if (devpriv->current_transfer == isa_dma_transfer) { | |
1185 | /* | |
1186 | * if a dma terminal count of external stop trigger | |
1187 | * has occurred | |
1188 | */ | |
42cb6a82 | 1189 | if (devpriv->stat1 & STAT1_GATA0 || |
63d6ba20 | 1190 | (board->is_labpc1200 && devpriv->stat2 & STAT2_OUTA1)) { |
571e06c1 HS |
1191 | handle_isa_dma(dev); |
1192 | } | |
1193 | } else | |
1194 | #endif | |
1195 | labpc_drain_fifo(dev); | |
1196 | ||
42cb6a82 | 1197 | if (devpriv->stat1 & STAT1_CNTINT) { |
571e06c1 HS |
1198 | comedi_error(dev, "handled timer interrupt?"); |
1199 | /* clear it */ | |
1200 | devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); | |
1201 | } | |
1202 | ||
42cb6a82 | 1203 | if (devpriv->stat1 & STAT1_OVERFLOW) { |
571e06c1 | 1204 | /* clear error interrupt */ |
42cb6a82 | 1205 | devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); |
571e06c1 HS |
1206 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; |
1207 | comedi_event(dev, s); | |
1208 | comedi_error(dev, "overflow"); | |
1209 | return IRQ_HANDLED; | |
1210 | } | |
1211 | /* handle external stop trigger */ | |
1212 | if (cmd->stop_src == TRIG_EXT) { | |
42cb6a82 | 1213 | if (devpriv->stat2 & STAT2_OUTA1) { |
571e06c1 HS |
1214 | labpc_drain_dregs(dev); |
1215 | labpc_cancel(dev, s); | |
1216 | async->events |= COMEDI_CB_EOA; | |
1217 | } | |
1218 | } | |
1219 | ||
1220 | /* TRIG_COUNT end of acquisition */ | |
1221 | if (cmd->stop_src == TRIG_COUNT) { | |
1222 | if (devpriv->count == 0) { | |
1223 | labpc_cancel(dev, s); | |
1224 | async->events |= COMEDI_CB_EOA; | |
1225 | } | |
1226 | } | |
1227 | ||
1228 | comedi_event(dev, s); | |
1229 | return IRQ_HANDLED; | |
1230 | } | |
1231 | ||
28a10930 HS |
1232 | static int labpc_ao_insn_write(struct comedi_device *dev, |
1233 | struct comedi_subdevice *s, | |
1234 | struct comedi_insn *insn, | |
1235 | unsigned int *data) | |
8913491d | 1236 | { |
d0baa0c1 | 1237 | const struct labpc_boardinfo *board = comedi_board(dev); |
8913491d HS |
1238 | struct labpc_private *devpriv = dev->private; |
1239 | int channel, range; | |
1240 | unsigned long flags; | |
1241 | int lsb, msb; | |
1242 | ||
1243 | channel = CR_CHAN(insn->chanspec); | |
1244 | ||
1245 | /* turn off pacing of analog output channel */ | |
1246 | /* note: hardware bug in daqcard-1200 means pacing cannot | |
1247 | * be independently enabled/disabled for its the two channels */ | |
1248 | spin_lock_irqsave(&dev->spinlock, flags); | |
42cb6a82 HS |
1249 | devpriv->cmd2 &= ~CMD2_LDAC(channel); |
1250 | devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); | |
8913491d HS |
1251 | spin_unlock_irqrestore(&dev->spinlock, flags); |
1252 | ||
1253 | /* set range */ | |
63d6ba20 | 1254 | if (board->is_labpc1200) { |
8913491d | 1255 | range = CR_RANGE(insn->chanspec); |
43a9411a | 1256 | if (labpc_range_is_unipolar(s, range)) |
42cb6a82 | 1257 | devpriv->cmd6 |= CMD6_DACUNI(channel); |
8913491d | 1258 | else |
42cb6a82 | 1259 | devpriv->cmd6 &= ~CMD6_DACUNI(channel); |
8913491d | 1260 | /* write to register */ |
42cb6a82 | 1261 | devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); |
8913491d HS |
1262 | } |
1263 | /* send data */ | |
1264 | lsb = data[0] & 0xff; | |
1265 | msb = (data[0] >> 8) & 0xff; | |
1266 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); | |
1267 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); | |
1268 | ||
1269 | /* remember value for readback */ | |
1270 | devpriv->ao_value[channel] = data[0]; | |
1271 | ||
1272 | return 1; | |
1273 | } | |
1274 | ||
28a10930 HS |
1275 | static int labpc_ao_insn_read(struct comedi_device *dev, |
1276 | struct comedi_subdevice *s, | |
1277 | struct comedi_insn *insn, | |
1278 | unsigned int *data) | |
8913491d HS |
1279 | { |
1280 | struct labpc_private *devpriv = dev->private; | |
1281 | ||
1282 | data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; | |
1283 | ||
1284 | return 1; | |
1285 | } | |
1286 | ||
370c8e1f | 1287 | static int labpc_8255_mmio(int dir, int port, int data, unsigned long iobase) |
124b13b2 FMH |
1288 | { |
1289 | if (dir) { | |
5743aaac | 1290 | writeb(data, (void __iomem *)(iobase + port)); |
124b13b2 FMH |
1291 | return 0; |
1292 | } else { | |
5743aaac | 1293 | return readb((void __iomem *)(iobase + port)); |
124b13b2 FMH |
1294 | } |
1295 | } | |
1296 | ||
f6b49620 | 1297 | /* lowlevel write to eeprom/dac */ |
da91b269 | 1298 | static void labpc_serial_out(struct comedi_device *dev, unsigned int value, |
0a85b6f0 | 1299 | unsigned int value_width) |
124b13b2 | 1300 | { |
9a1a6cf8 | 1301 | struct labpc_private *devpriv = dev->private; |
124b13b2 FMH |
1302 | int i; |
1303 | ||
1304 | for (i = 1; i <= value_width; i++) { | |
f6b49620 | 1305 | /* clear serial clock */ |
42cb6a82 | 1306 | devpriv->cmd5 &= ~CMD5_SCLK; |
f6b49620 | 1307 | /* send bits most significant bit first */ |
124b13b2 | 1308 | if (value & (1 << (value_width - i))) |
42cb6a82 | 1309 | devpriv->cmd5 |= CMD5_SDATA; |
124b13b2 | 1310 | else |
42cb6a82 | 1311 | devpriv->cmd5 &= ~CMD5_SDATA; |
5f74ea14 | 1312 | udelay(1); |
42cb6a82 | 1313 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
f6b49620 | 1314 | /* set clock to load bit */ |
42cb6a82 | 1315 | devpriv->cmd5 |= CMD5_SCLK; |
5f74ea14 | 1316 | udelay(1); |
42cb6a82 | 1317 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 FMH |
1318 | } |
1319 | } | |
1320 | ||
f6b49620 | 1321 | /* lowlevel read from eeprom */ |
da91b269 | 1322 | static unsigned int labpc_serial_in(struct comedi_device *dev) |
124b13b2 | 1323 | { |
9a1a6cf8 | 1324 | struct labpc_private *devpriv = dev->private; |
124b13b2 FMH |
1325 | unsigned int value = 0; |
1326 | int i; | |
f6b49620 | 1327 | const int value_width = 8; /* number of bits wide values are */ |
124b13b2 FMH |
1328 | |
1329 | for (i = 1; i <= value_width; i++) { | |
f6b49620 | 1330 | /* set serial clock */ |
42cb6a82 | 1331 | devpriv->cmd5 |= CMD5_SCLK; |
5f74ea14 | 1332 | udelay(1); |
42cb6a82 | 1333 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
f6b49620 | 1334 | /* clear clock bit */ |
42cb6a82 | 1335 | devpriv->cmd5 &= ~CMD5_SCLK; |
5f74ea14 | 1336 | udelay(1); |
42cb6a82 | 1337 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
f6b49620 | 1338 | /* read bits most significant bit first */ |
5f74ea14 | 1339 | udelay(1); |
42cb6a82 HS |
1340 | devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG); |
1341 | if (devpriv->stat2 & STAT2_PROMOUT) | |
124b13b2 | 1342 | value |= 1 << (value_width - i); |
124b13b2 FMH |
1343 | } |
1344 | ||
1345 | return value; | |
1346 | } | |
1347 | ||
0a85b6f0 MT |
1348 | static unsigned int labpc_eeprom_read(struct comedi_device *dev, |
1349 | unsigned int address) | |
124b13b2 | 1350 | { |
9a1a6cf8 | 1351 | struct labpc_private *devpriv = dev->private; |
124b13b2 | 1352 | unsigned int value; |
e41a6f6d SR |
1353 | /* bits to tell eeprom to expect a read */ |
1354 | const int read_instruction = 0x3; | |
1355 | /* 8 bit write lengths to eeprom */ | |
1356 | const int write_length = 8; | |
124b13b2 | 1357 | |
f6b49620 | 1358 | /* enable read/write to eeprom */ |
42cb6a82 | 1359 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
5f74ea14 | 1360 | udelay(1); |
42cb6a82 HS |
1361 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1362 | devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); | |
5f74ea14 | 1363 | udelay(1); |
42cb6a82 | 1364 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1365 | |
f6b49620 | 1366 | /* send read instruction */ |
124b13b2 | 1367 | labpc_serial_out(dev, read_instruction, write_length); |
f6b49620 | 1368 | /* send 8 bit address to read from */ |
124b13b2 | 1369 | labpc_serial_out(dev, address, write_length); |
f6b49620 | 1370 | /* read result */ |
124b13b2 FMH |
1371 | value = labpc_serial_in(dev); |
1372 | ||
f6b49620 | 1373 | /* disable read/write to eeprom */ |
42cb6a82 | 1374 | devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); |
5f74ea14 | 1375 | udelay(1); |
42cb6a82 | 1376 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 FMH |
1377 | |
1378 | return value; | |
1379 | } | |
1380 | ||
bc3fc446 HS |
1381 | static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) |
1382 | { | |
1383 | struct labpc_private *devpriv = dev->private; | |
1384 | unsigned int value; | |
1385 | const int read_status_instruction = 0x5; | |
1386 | const int write_length = 8; /* 8 bit write lengths to eeprom */ | |
1387 | ||
1388 | /* enable read/write to eeprom */ | |
42cb6a82 | 1389 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
bc3fc446 | 1390 | udelay(1); |
42cb6a82 HS |
1391 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1392 | devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); | |
bc3fc446 | 1393 | udelay(1); |
42cb6a82 | 1394 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
bc3fc446 HS |
1395 | |
1396 | /* send read status instruction */ | |
1397 | labpc_serial_out(dev, read_status_instruction, write_length); | |
1398 | /* read result */ | |
1399 | value = labpc_serial_in(dev); | |
1400 | ||
1401 | /* disable read/write to eeprom */ | |
42cb6a82 | 1402 | devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); |
bc3fc446 | 1403 | udelay(1); |
42cb6a82 | 1404 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
bc3fc446 HS |
1405 | |
1406 | return value; | |
1407 | } | |
1408 | ||
d6269644 JL |
1409 | static int labpc_eeprom_write(struct comedi_device *dev, |
1410 | unsigned int address, unsigned int value) | |
124b13b2 | 1411 | { |
9a1a6cf8 | 1412 | struct labpc_private *devpriv = dev->private; |
124b13b2 FMH |
1413 | const int write_enable_instruction = 0x6; |
1414 | const int write_instruction = 0x2; | |
f6b49620 | 1415 | const int write_length = 8; /* 8 bit write lengths to eeprom */ |
124b13b2 FMH |
1416 | const int write_in_progress_bit = 0x1; |
1417 | const int timeout = 10000; | |
1418 | int i; | |
1419 | ||
f6b49620 | 1420 | /* make sure there isn't already a write in progress */ |
124b13b2 FMH |
1421 | for (i = 0; i < timeout; i++) { |
1422 | if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == | |
0a85b6f0 | 1423 | 0) |
124b13b2 FMH |
1424 | break; |
1425 | } | |
1426 | if (i == timeout) { | |
1427 | comedi_error(dev, "eeprom write timed out"); | |
1428 | return -ETIME; | |
1429 | } | |
f6b49620 | 1430 | /* update software copy of eeprom */ |
124b13b2 FMH |
1431 | devpriv->eeprom_data[address] = value; |
1432 | ||
f6b49620 | 1433 | /* enable read/write to eeprom */ |
42cb6a82 | 1434 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
5f74ea14 | 1435 | udelay(1); |
42cb6a82 HS |
1436 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1437 | devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); | |
5f74ea14 | 1438 | udelay(1); |
42cb6a82 | 1439 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1440 | |
f6b49620 | 1441 | /* send write_enable instruction */ |
124b13b2 | 1442 | labpc_serial_out(dev, write_enable_instruction, write_length); |
42cb6a82 | 1443 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
5f74ea14 | 1444 | udelay(1); |
42cb6a82 | 1445 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1446 | |
f6b49620 | 1447 | /* send write instruction */ |
42cb6a82 | 1448 | devpriv->cmd5 |= CMD5_EEPROMCS; |
5f74ea14 | 1449 | udelay(1); |
42cb6a82 | 1450 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1451 | labpc_serial_out(dev, write_instruction, write_length); |
f6b49620 | 1452 | /* send 8 bit address to write to */ |
124b13b2 | 1453 | labpc_serial_out(dev, address, write_length); |
f6b49620 | 1454 | /* write value */ |
124b13b2 | 1455 | labpc_serial_out(dev, value, write_length); |
42cb6a82 | 1456 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
5f74ea14 | 1457 | udelay(1); |
42cb6a82 | 1458 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1459 | |
f6b49620 | 1460 | /* disable read/write to eeprom */ |
42cb6a82 | 1461 | devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); |
5f74ea14 | 1462 | udelay(1); |
42cb6a82 | 1463 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 FMH |
1464 | |
1465 | return 0; | |
1466 | } | |
1467 | ||
f6b49620 | 1468 | /* writes to 8 bit calibration dacs */ |
da91b269 | 1469 | static void write_caldac(struct comedi_device *dev, unsigned int channel, |
0a85b6f0 | 1470 | unsigned int value) |
124b13b2 | 1471 | { |
9a1a6cf8 HS |
1472 | struct labpc_private *devpriv = dev->private; |
1473 | ||
124b13b2 FMH |
1474 | if (value == devpriv->caldac[channel]) |
1475 | return; | |
1476 | devpriv->caldac[channel] = value; | |
1477 | ||
f6b49620 | 1478 | /* clear caldac load bit and make sure we don't write to eeprom */ |
42cb6a82 | 1479 | devpriv->cmd5 &= ~(CMD5_CALDACLD | CMD5_EEPROMCS | CMD5_WRTPRT); |
5f74ea14 | 1480 | udelay(1); |
42cb6a82 | 1481 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1482 | |
f6b49620 | 1483 | /* write 4 bit channel */ |
124b13b2 | 1484 | labpc_serial_out(dev, channel, 4); |
f6b49620 | 1485 | /* write 8 bit caldac value */ |
124b13b2 FMH |
1486 | labpc_serial_out(dev, value, 8); |
1487 | ||
f6b49620 | 1488 | /* set and clear caldac bit to load caldac value */ |
42cb6a82 | 1489 | devpriv->cmd5 |= CMD5_CALDACLD; |
5f74ea14 | 1490 | udelay(1); |
42cb6a82 HS |
1491 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1492 | devpriv->cmd5 &= ~CMD5_CALDACLD; | |
5f74ea14 | 1493 | udelay(1); |
42cb6a82 | 1494 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 FMH |
1495 | } |
1496 | ||
28a10930 | 1497 | static int labpc_calib_insn_write(struct comedi_device *dev, |
bc3fc446 | 1498 | struct comedi_subdevice *s, |
28a10930 HS |
1499 | struct comedi_insn *insn, |
1500 | unsigned int *data) | |
bc3fc446 | 1501 | { |
7c00782b | 1502 | unsigned int chan = CR_CHAN(insn->chanspec); |
bc3fc446 | 1503 | |
7c00782b HS |
1504 | /* |
1505 | * Only write the last data value to the caldac. Preceding | |
1506 | * data would be overwritten anyway. | |
1507 | */ | |
1508 | if (insn->n > 0) | |
1509 | write_caldac(dev, chan, data[insn->n - 1]); | |
1510 | ||
1511 | return insn->n; | |
bc3fc446 HS |
1512 | } |
1513 | ||
28a10930 | 1514 | static int labpc_calib_insn_read(struct comedi_device *dev, |
bc3fc446 | 1515 | struct comedi_subdevice *s, |
28a10930 HS |
1516 | struct comedi_insn *insn, |
1517 | unsigned int *data) | |
bc3fc446 HS |
1518 | { |
1519 | struct labpc_private *devpriv = dev->private; | |
198ac9dc HS |
1520 | unsigned int chan = CR_CHAN(insn->chanspec); |
1521 | int i; | |
bc3fc446 | 1522 | |
198ac9dc HS |
1523 | for (i = 0; i < insn->n; i++) |
1524 | data[i] = devpriv->caldac[chan]; | |
bc3fc446 | 1525 | |
198ac9dc | 1526 | return insn->n; |
bc3fc446 HS |
1527 | } |
1528 | ||
28a10930 | 1529 | static int labpc_eeprom_insn_write(struct comedi_device *dev, |
bc3fc446 | 1530 | struct comedi_subdevice *s, |
28a10930 HS |
1531 | struct comedi_insn *insn, |
1532 | unsigned int *data) | |
bc3fc446 | 1533 | { |
e7a1aa62 | 1534 | unsigned int chan = CR_CHAN(insn->chanspec); |
bc3fc446 HS |
1535 | int ret; |
1536 | ||
e7a1aa62 HS |
1537 | /* only allow writes to user area of eeprom */ |
1538 | if (chan < 16 || chan > 127) | |
bc3fc446 | 1539 | return -EINVAL; |
bc3fc446 | 1540 | |
e7a1aa62 HS |
1541 | /* |
1542 | * Only write the last data value to the eeprom. Preceding | |
1543 | * data would be overwritten anyway. | |
1544 | */ | |
1545 | if (insn->n > 0) { | |
1546 | ret = labpc_eeprom_write(dev, chan, data[insn->n - 1]); | |
1547 | if (ret) | |
1548 | return ret; | |
1549 | } | |
bc3fc446 | 1550 | |
e7a1aa62 | 1551 | return insn->n; |
bc3fc446 HS |
1552 | } |
1553 | ||
28a10930 | 1554 | static int labpc_eeprom_insn_read(struct comedi_device *dev, |
bc3fc446 | 1555 | struct comedi_subdevice *s, |
28a10930 HS |
1556 | struct comedi_insn *insn, |
1557 | unsigned int *data) | |
bc3fc446 HS |
1558 | { |
1559 | struct labpc_private *devpriv = dev->private; | |
1330af4c HS |
1560 | unsigned int chan = CR_CHAN(insn->chanspec); |
1561 | int i; | |
bc3fc446 | 1562 | |
1330af4c HS |
1563 | for (i = 0; i < insn->n; i++) |
1564 | data[i] = devpriv->eeprom_data[chan]; | |
bc3fc446 | 1565 | |
1330af4c | 1566 | return insn->n; |
bc3fc446 HS |
1567 | } |
1568 | ||
de024b3d | 1569 | int labpc_common_attach(struct comedi_device *dev, |
3e034797 | 1570 | unsigned int irq, unsigned long isr_flags) |
dd2aef64 | 1571 | { |
d0baa0c1 | 1572 | const struct labpc_boardinfo *board = comedi_board(dev); |
dd2aef64 HS |
1573 | struct labpc_private *devpriv = dev->private; |
1574 | struct comedi_subdevice *s; | |
dd2aef64 | 1575 | int ret; |
cacedd0c | 1576 | int i; |
dd2aef64 | 1577 | |
4d3cc8ab | 1578 | if (board->has_mmio) { |
dd2aef64 HS |
1579 | devpriv->read_byte = labpc_readb; |
1580 | devpriv->write_byte = labpc_writeb; | |
1581 | } else { | |
1582 | devpriv->read_byte = labpc_inb; | |
1583 | devpriv->write_byte = labpc_outb; | |
1584 | } | |
83d75eff | 1585 | |
dd2aef64 | 1586 | /* initialize board's command registers */ |
42cb6a82 HS |
1587 | devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); |
1588 | devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); | |
1589 | devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); | |
1590 | devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); | |
63d6ba20 | 1591 | if (board->is_labpc1200) { |
42cb6a82 HS |
1592 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1593 | devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); | |
dd2aef64 HS |
1594 | } |
1595 | ||
dd2aef64 | 1596 | if (irq) { |
0229979a HS |
1597 | ret = request_irq(irq, labpc_interrupt, isr_flags, |
1598 | dev->board_name, dev); | |
1599 | if (ret == 0) | |
1600 | dev->irq = irq; | |
dd2aef64 | 1601 | } |
dd2aef64 | 1602 | |
dd2aef64 HS |
1603 | ret = comedi_alloc_subdevices(dev, 5); |
1604 | if (ret) | |
1605 | return ret; | |
1606 | ||
1607 | /* analog input subdevice */ | |
1608 | s = &dev->subdevices[0]; | |
9bffb75d HS |
1609 | s->type = COMEDI_SUBD_AI; |
1610 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF; | |
1611 | s->n_chan = 8; | |
1612 | s->len_chanlist = 8; | |
1613 | s->maxdata = 0x0fff; | |
70d52bce HS |
1614 | s->range_table = board->is_labpc1200 |
1615 | ? &range_labpc_1200_ai : &range_labpc_plus_ai; | |
9bffb75d HS |
1616 | s->insn_read = labpc_ai_insn_read; |
1617 | if (dev->irq) { | |
1618 | dev->read_subdev = s; | |
1619 | s->subdev_flags |= SDF_CMD_READ; | |
1620 | s->do_cmd = labpc_ai_cmd; | |
1621 | s->do_cmdtest = labpc_ai_cmdtest; | |
1622 | s->cancel = labpc_cancel; | |
1623 | } | |
dd2aef64 HS |
1624 | |
1625 | /* analog output */ | |
1626 | s = &dev->subdevices[1]; | |
d0baa0c1 | 1627 | if (board->has_ao) { |
7d47f0f4 HS |
1628 | s->type = COMEDI_SUBD_AO; |
1629 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; | |
1630 | s->n_chan = NUM_AO_CHAN; | |
1631 | s->maxdata = 0x0fff; | |
1632 | s->range_table = &range_labpc_ao; | |
1633 | s->insn_read = labpc_ao_insn_read; | |
1634 | s->insn_write = labpc_ao_insn_write; | |
1635 | ||
dd2aef64 HS |
1636 | /* initialize analog outputs to a known value */ |
1637 | for (i = 0; i < s->n_chan; i++) { | |
7d47f0f4 HS |
1638 | short lsb, msb; |
1639 | ||
dd2aef64 HS |
1640 | devpriv->ao_value[i] = s->maxdata / 2; |
1641 | lsb = devpriv->ao_value[i] & 0xff; | |
1642 | msb = (devpriv->ao_value[i] >> 8) & 0xff; | |
1643 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); | |
1644 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); | |
1645 | } | |
1646 | } else { | |
7d47f0f4 | 1647 | s->type = COMEDI_SUBD_UNUSED; |
dd2aef64 HS |
1648 | } |
1649 | ||
1650 | /* 8255 dio */ | |
1651 | s = &dev->subdevices[2]; | |
370c8e1f HS |
1652 | ret = subdev_8255_init(dev, s, |
1653 | (board->has_mmio) ? labpc_8255_mmio : NULL, | |
1654 | dev->iobase + DIO_BASE_REG); | |
1655 | if (ret) | |
1656 | return ret; | |
dd2aef64 HS |
1657 | |
1658 | /* calibration subdevices for boards that have one */ | |
1659 | s = &dev->subdevices[3]; | |
63d6ba20 | 1660 | if (board->is_labpc1200) { |
7d47f0f4 HS |
1661 | s->type = COMEDI_SUBD_CALIB; |
1662 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; | |
1663 | s->n_chan = 16; | |
1664 | s->maxdata = 0xff; | |
1665 | s->insn_read = labpc_calib_insn_read; | |
1666 | s->insn_write = labpc_calib_insn_write; | |
dd2aef64 HS |
1667 | |
1668 | for (i = 0; i < s->n_chan; i++) | |
1669 | write_caldac(dev, i, s->maxdata / 2); | |
1670 | } else | |
7d47f0f4 | 1671 | s->type = COMEDI_SUBD_UNUSED; |
dd2aef64 HS |
1672 | |
1673 | /* EEPROM */ | |
1674 | s = &dev->subdevices[4]; | |
63d6ba20 | 1675 | if (board->is_labpc1200) { |
7d47f0f4 HS |
1676 | s->type = COMEDI_SUBD_MEMORY; |
1677 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; | |
1678 | s->n_chan = EEPROM_SIZE; | |
1679 | s->maxdata = 0xff; | |
1680 | s->insn_read = labpc_eeprom_insn_read; | |
1681 | s->insn_write = labpc_eeprom_insn_write; | |
1682 | ||
1683 | for (i = 0; i < s->n_chan; i++) | |
dd2aef64 HS |
1684 | devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); |
1685 | } else | |
7d47f0f4 | 1686 | s->type = COMEDI_SUBD_UNUSED; |
dd2aef64 HS |
1687 | |
1688 | return 0; | |
1689 | } | |
1690 | EXPORT_SYMBOL_GPL(labpc_common_attach); | |
1691 | ||
a0eeed40 | 1692 | #if IS_ENABLED(CONFIG_COMEDI_NI_LABPC_ISA) |
dd2aef64 HS |
1693 | static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) |
1694 | { | |
dd2aef64 | 1695 | struct labpc_private *devpriv; |
fa3cb219 HS |
1696 | unsigned int irq = it->options[1]; |
1697 | unsigned int dma_chan = it->options[2]; | |
5b365a8a | 1698 | int ret; |
dd2aef64 HS |
1699 | |
1700 | devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); | |
1701 | if (!devpriv) | |
1702 | return -ENOMEM; | |
1703 | dev->private = devpriv; | |
1704 | ||
fa3cb219 | 1705 | ret = comedi_request_region(dev, it->options[0], LABPC_SIZE); |
dd2aef64 HS |
1706 | if (ret) |
1707 | return ret; | |
1708 | ||
3e034797 | 1709 | ret = labpc_common_attach(dev, irq, 0); |
76730884 HS |
1710 | if (ret) |
1711 | return ret; | |
1712 | ||
1713 | #ifdef CONFIG_ISA_DMA_API | |
1714 | if (dev->irq && (dma_chan == 1 || dma_chan == 3)) { | |
1715 | devpriv->dma_buffer = kmalloc(dma_buffer_size, | |
1716 | GFP_KERNEL | GFP_DMA); | |
1717 | if (devpriv->dma_buffer) { | |
1718 | ret = request_dma(dma_chan, dev->board_name); | |
1719 | if (ret == 0) { | |
1720 | unsigned long dma_flags; | |
1721 | ||
1722 | devpriv->dma_chan = dma_chan; | |
1581a035 HS |
1723 | devpriv->dma_addr = |
1724 | virt_to_bus(devpriv->dma_buffer); | |
1725 | ||
76730884 HS |
1726 | dma_flags = claim_dma_lock(); |
1727 | disable_dma(devpriv->dma_chan); | |
1728 | set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); | |
1729 | release_dma_lock(dma_flags); | |
1730 | } else { | |
1731 | kfree(devpriv->dma_buffer); | |
1732 | } | |
1733 | } | |
1734 | } | |
1735 | #endif | |
1736 | ||
1737 | return 0; | |
dd2aef64 HS |
1738 | } |
1739 | ||
a0eeed40 | 1740 | static void labpc_detach(struct comedi_device *dev) |
dd2aef64 | 1741 | { |
dd2aef64 | 1742 | struct labpc_private *devpriv = dev->private; |
dd2aef64 | 1743 | |
fa3cb219 HS |
1744 | if (devpriv) { |
1745 | kfree(devpriv->dma_buffer); | |
1746 | if (devpriv->dma_chan) | |
1747 | free_dma(devpriv->dma_chan); | |
3d1fe3f7 | 1748 | } |
fa3cb219 | 1749 | comedi_legacy_detach(dev); |
dd2aef64 | 1750 | } |
dd2aef64 | 1751 | |
5e51f0db | 1752 | static struct comedi_driver labpc_driver = { |
147a85d7 | 1753 | .driver_name = "ni_labpc", |
6e8bddf2 HS |
1754 | .module = THIS_MODULE, |
1755 | .attach = labpc_attach, | |
fa3cb219 | 1756 | .detach = labpc_detach, |
6e8bddf2 HS |
1757 | .num_names = ARRAY_SIZE(labpc_boards), |
1758 | .board_name = &labpc_boards[0].name, | |
1759 | .offset = sizeof(struct labpc_boardinfo), | |
5e51f0db | 1760 | }; |
fa3cb219 HS |
1761 | module_comedi_driver(labpc_driver); |
1762 | #else | |
1763 | static int __init labpc_common_init(void) | |
727b286b | 1764 | { |
fa3cb219 | 1765 | return 0; |
727b286b | 1766 | } |
fa3cb219 | 1767 | module_init(labpc_common_init); |
727b286b | 1768 | |
fa3cb219 HS |
1769 | static void __exit labpc_common_exit(void) |
1770 | { | |
1771 | } | |
1772 | module_exit(labpc_common_exit); | |
124b13b2 FMH |
1773 | #endif |
1774 | ||
90f703d3 AT |
1775 | MODULE_AUTHOR("Comedi http://www.comedi.org"); |
1776 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
1777 | MODULE_LICENSE("GPL"); |