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c4beb34e DS |
1 | /* |
2 | comedi/drivers/ni_pcimio.c | |
3 | Hardware driver for NI PCI-MIO E series cards | |
4 | ||
5 | COMEDI - Linux Control and Measurement Device Interface | |
6 | Copyright (C) 1997-8 David A. Schleef <ds@schleef.org> | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | /* | |
23 | Driver: ni_pcimio | |
24 | Description: National Instruments PCI-MIO-E series and M series (all boards) | |
25 | Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans, | |
26 | Herman Bruyninckx, Terry Barnaby | |
27 | Status: works | |
28 | Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio), | |
29 | PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E, | |
30 | PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E, | |
31 | PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E, | |
51e290fd IA |
32 | PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225, |
33 | PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259, | |
c4beb34e DS |
34 | PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289, |
35 | PCI-6711, PXI-6711, PCI-6713, PXI-6713, | |
36 | PXI-6071E, PCI-6070E, PXI-6070E, | |
37 | PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733, | |
38 | PCI-6143, PXI-6143 | |
51e290fd | 39 | Updated: Wed, 03 Dec 2008 10:51:47 +0000 |
c4beb34e DS |
40 | |
41 | These boards are almost identical to the AT-MIO E series, except that | |
42 | they use the PCI bus instead of ISA (i.e., AT). See the notes for | |
43 | the ni_atmio.o driver for additional information about these boards. | |
44 | ||
45 | Autocalibration is supported on many of the devices, using the | |
46 | comedi_calibrate (or comedi_soft_calibrate for m-series) utility. | |
47 | M-Series boards do analog input and analog output calibration entirely | |
48 | in software. The software calibration corrects | |
49 | the analog input for offset, gain and | |
50 | nonlinearity. The analog outputs are corrected for offset and gain. | |
51 | See the comedilib documentation on comedi_get_softcal_converter() for | |
52 | more information. | |
53 | ||
54 | By default, the driver uses DMA to transfer analog input data to | |
55 | memory. When DMA is enabled, not all triggering features are | |
56 | supported. | |
57 | ||
58 | Digital I/O may not work on 673x. | |
59 | ||
60 | Note that the PCI-6143 is a simultaineous sampling device with 8 convertors. | |
61 | With this board all of the convertors perform one simultaineous sample during | |
62 | a scan interval. The period for a scan is used for the convert time in a | |
63 | Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default. | |
64 | ||
65 | The RTSI trigger bus is supported on these cards on | |
66 | subdevice 10. See the comedilib documentation for details. | |
67 | ||
68 | Information (number of channels, bits, etc.) for some devices may be | |
69 | incorrect. Please check this and submit a bug if there are problems | |
70 | for your device. | |
71 | ||
72 | SCXI is probably broken for m-series boards. | |
73 | ||
74 | Bugs: | |
75 | - When DMA is enabled, COMEDI_EV_CONVERT does | |
76 | not work correctly. | |
77 | ||
78 | */ | |
79 | /* | |
80 | The PCI-MIO E series driver was originally written by | |
81 | Tomasz Motylewski <...>, and ported to comedi by ds. | |
82 | ||
83 | References: | |
84 | ||
85 | 341079b.pdf PCI E Series Register-Level Programmer Manual | |
86 | 340934b.pdf DAQ-STC reference manual | |
87 | ||
88 | 322080b.pdf 6711/6713/6715 User Manual | |
89 | ||
90 | 320945c.pdf PCI E Series User Manual | |
91 | 322138a.pdf PCI-6052E and DAQPad-6052E User Manual | |
92 | ||
93 | ISSUES: | |
94 | ||
95 | need to deal with external reference for DAC, and other DAC | |
96 | properties in board properties | |
97 | ||
98 | deal with at-mio-16de-10 revision D to N changes, etc. | |
99 | ||
100 | need to add other CALDAC type | |
101 | ||
102 | need to slow down DAC loading. I don't trust NI's claim that | |
103 | two writes to the PCI bus slows IO enough. I would prefer to | |
5f74ea14 | 104 | use udelay(). Timing specs: (clock) |
c4beb34e DS |
105 | AD8522 30ns |
106 | DAC8043 120ns | |
107 | DAC8800 60ns | |
108 | MB88341 ? | |
109 | ||
110 | */ | |
111 | ||
112 | #include "../comedidev.h" | |
113 | ||
f8db88ef | 114 | #include <asm/byteorder.h> |
c4beb34e DS |
115 | #include <linux/delay.h> |
116 | ||
117 | #include "ni_stc.h" | |
118 | #include "mite.h" | |
119 | ||
2696fb57 | 120 | /* #define PCI_DEBUG */ |
c4beb34e DS |
121 | |
122 | #define PCIDMA | |
123 | ||
124 | #define PCIMIO 1 | |
125 | #undef ATMIO | |
126 | ||
127 | #define MAX_N_CALDACS (16+16+2) | |
128 | ||
129 | #define DRV_NAME "ni_pcimio" | |
130 | ||
131 | /* The following two tables must be in the same order */ | |
132 | static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = { | |
0a85b6f0 MT |
133 | { |
134 | PCI_VENDOR_ID_NATINST, 0x0162, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
135 | PCI_VENDOR_ID_NATINST, 0x1170, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
136 | PCI_VENDOR_ID_NATINST, 0x1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
137 | PCI_VENDOR_ID_NATINST, 0x1190, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
138 | PCI_VENDOR_ID_NATINST, 0x11b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
139 | PCI_VENDOR_ID_NATINST, 0x11c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
140 | PCI_VENDOR_ID_NATINST, 0x11d0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
141 | PCI_VENDOR_ID_NATINST, 0x1270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
142 | PCI_VENDOR_ID_NATINST, 0x1330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
143 | PCI_VENDOR_ID_NATINST, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
144 | PCI_VENDOR_ID_NATINST, 0x1350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
145 | PCI_VENDOR_ID_NATINST, 0x14e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
146 | PCI_VENDOR_ID_NATINST, 0x14f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
147 | PCI_VENDOR_ID_NATINST, 0x1580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
148 | PCI_VENDOR_ID_NATINST, 0x15b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
149 | PCI_VENDOR_ID_NATINST, 0x1880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
150 | PCI_VENDOR_ID_NATINST, 0x1870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
151 | PCI_VENDOR_ID_NATINST, 0x18b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
152 | PCI_VENDOR_ID_NATINST, 0x18c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
153 | PCI_VENDOR_ID_NATINST, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
154 | PCI_VENDOR_ID_NATINST, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
155 | PCI_VENDOR_ID_NATINST, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
156 | PCI_VENDOR_ID_NATINST, 0x2890, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
157 | PCI_VENDOR_ID_NATINST, 0x28c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
158 | PCI_VENDOR_ID_NATINST, 0x2a60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
159 | PCI_VENDOR_ID_NATINST, 0x2a70, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
160 | PCI_VENDOR_ID_NATINST, 0x2a80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
161 | PCI_VENDOR_ID_NATINST, 0x2ab0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
162 | PCI_VENDOR_ID_NATINST, 0x2b80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
163 | PCI_VENDOR_ID_NATINST, 0x2b90, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
164 | PCI_VENDOR_ID_NATINST, 0x2c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
165 | PCI_VENDOR_ID_NATINST, 0x2ca0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
166 | PCI_VENDOR_ID_NATINST, 0x70aa, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
167 | PCI_VENDOR_ID_NATINST, 0x70ab, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
168 | PCI_VENDOR_ID_NATINST, 0x70ac, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
169 | PCI_VENDOR_ID_NATINST, 0x70af, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
170 | PCI_VENDOR_ID_NATINST, 0x70b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
171 | PCI_VENDOR_ID_NATINST, 0x70b4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
172 | PCI_VENDOR_ID_NATINST, 0x70b6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
173 | PCI_VENDOR_ID_NATINST, 0x70b7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
174 | PCI_VENDOR_ID_NATINST, 0x70b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
175 | PCI_VENDOR_ID_NATINST, 0x70bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
176 | PCI_VENDOR_ID_NATINST, 0x70bd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
177 | PCI_VENDOR_ID_NATINST, 0x70bf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
178 | PCI_VENDOR_ID_NATINST, 0x70c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
179 | PCI_VENDOR_ID_NATINST, 0x70f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
180 | PCI_VENDOR_ID_NATINST, 0x710d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
181 | PCI_VENDOR_ID_NATINST, 0x716c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
182 | PCI_VENDOR_ID_NATINST, 0x717f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
183 | PCI_VENDOR_ID_NATINST, 0x71bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
184 | PCI_VENDOR_ID_NATINST, 0x717d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, { | |
185 | 0} | |
c4beb34e DS |
186 | }; |
187 | ||
188 | MODULE_DEVICE_TABLE(pci, ni_pci_table); | |
189 | ||
190 | /* These are not all the possible ao ranges for 628x boards. | |
191 | They can do OFFSET +- REFERENCE where OFFSET can be | |
192 | 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can | |
193 | be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's | |
194 | 63 different possibilities. An AO channel | |
195 | can not act as it's own OFFSET or REFERENCE. | |
196 | */ | |
9ced1de6 | 197 | static const struct comedi_lrange range_ni_M_628x_ao = { 8, { |
0a85b6f0 MT |
198 | RANGE(-10, 10), |
199 | RANGE(-5, 5), | |
200 | RANGE(-2, 2), | |
201 | RANGE(-1, 1), | |
202 | RANGE(-5, 15), | |
203 | RANGE(0, 10), | |
204 | RANGE(3, 7), | |
205 | RANGE(4, 6), | |
206 | RANGE_ext(-1, 1) | |
207 | } | |
c4beb34e | 208 | }; |
0a85b6f0 | 209 | |
9ced1de6 | 210 | static const struct comedi_lrange range_ni_M_625x_ao = { 3, { |
0a85b6f0 MT |
211 | RANGE(-10, 10), |
212 | RANGE(-5, 5), | |
213 | RANGE_ext(-1, 1) | |
214 | } | |
c4beb34e | 215 | }; |
0a85b6f0 | 216 | |
9ced1de6 | 217 | static const struct comedi_lrange range_ni_M_622x_ao = { 1, { |
0a85b6f0 MT |
218 | RANGE(-10, 10), |
219 | } | |
c4beb34e DS |
220 | }; |
221 | ||
8ab41df0 | 222 | static const struct ni_board_struct ni_boards[] = { |
c4beb34e | 223 | { |
0a85b6f0 MT |
224 | .device_id = 0x0162, /* NI also says 0x1620. typo? */ |
225 | .name = "pci-mio-16xe-50", | |
226 | .n_adchan = 16, | |
227 | .adbits = 16, | |
228 | .ai_fifo_depth = 2048, | |
229 | .alwaysdither = 1, | |
230 | .gainlkup = ai_gain_8, | |
231 | .ai_speed = 50000, | |
232 | .n_aochan = 2, | |
233 | .aobits = 12, | |
234 | .ao_fifo_depth = 0, | |
235 | .ao_range_table = &range_bipolar10, | |
236 | .ao_unipolar = 0, | |
237 | .ao_speed = 50000, | |
238 | .num_p0_dio_channels = 8, | |
239 | .caldac = {dac8800, dac8043}, | |
240 | .has_8255 = 0, | |
241 | }, | |
c4beb34e | 242 | { |
0a85b6f0 MT |
243 | .device_id = 0x1170, |
244 | .name = "pci-mio-16xe-10", /* aka pci-6030E */ | |
245 | .n_adchan = 16, | |
246 | .adbits = 16, | |
247 | .ai_fifo_depth = 512, | |
248 | .alwaysdither = 1, | |
249 | .gainlkup = ai_gain_14, | |
250 | .ai_speed = 10000, | |
251 | .n_aochan = 2, | |
252 | .aobits = 16, | |
253 | .ao_fifo_depth = 2048, | |
254 | .ao_range_table = &range_ni_E_ao_ext, | |
255 | .ao_unipolar = 1, | |
256 | .ao_speed = 10000, | |
257 | .num_p0_dio_channels = 8, | |
258 | .caldac = {dac8800, dac8043, ad8522}, | |
259 | .has_8255 = 0, | |
260 | }, | |
c4beb34e | 261 | { |
0a85b6f0 MT |
262 | .device_id = 0x28c0, |
263 | .name = "pci-6014", | |
264 | .n_adchan = 16, | |
265 | .adbits = 16, | |
266 | .ai_fifo_depth = 512, | |
267 | .alwaysdither = 1, | |
268 | .gainlkup = ai_gain_4, | |
269 | .ai_speed = 5000, | |
270 | .n_aochan = 2, | |
271 | .aobits = 16, | |
272 | .ao_fifo_depth = 0, | |
273 | .ao_range_table = &range_bipolar10, | |
274 | .ao_unipolar = 0, | |
275 | .ao_speed = 100000, | |
276 | .num_p0_dio_channels = 8, | |
277 | .caldac = {ad8804_debug}, | |
278 | .has_8255 = 0, | |
279 | }, | |
c4beb34e | 280 | { |
0a85b6f0 MT |
281 | .device_id = 0x11d0, |
282 | .name = "pxi-6030e", | |
283 | .n_adchan = 16, | |
284 | .adbits = 16, | |
285 | .ai_fifo_depth = 512, | |
286 | .alwaysdither = 1, | |
287 | .gainlkup = ai_gain_14, | |
288 | .ai_speed = 10000, | |
289 | .n_aochan = 2, | |
290 | .aobits = 16, | |
291 | .ao_fifo_depth = 2048, | |
292 | .ao_range_table = &range_ni_E_ao_ext, | |
293 | .ao_unipolar = 1, | |
294 | .ao_speed = 10000, | |
295 | .num_p0_dio_channels = 8, | |
296 | .caldac = {dac8800, dac8043, ad8522}, | |
297 | .has_8255 = 0, | |
298 | }, | |
c4beb34e | 299 | { |
0a85b6f0 MT |
300 | .device_id = 0x1180, |
301 | .name = "pci-mio-16e-1", /* aka pci-6070e */ | |
302 | .n_adchan = 16, | |
303 | .adbits = 12, | |
304 | .ai_fifo_depth = 512, | |
305 | .alwaysdither = 0, | |
306 | .gainlkup = ai_gain_16, | |
307 | .ai_speed = 800, | |
308 | .n_aochan = 2, | |
309 | .aobits = 12, | |
310 | .ao_fifo_depth = 2048, | |
311 | .ao_range_table = &range_ni_E_ao_ext, | |
312 | .ao_unipolar = 1, | |
313 | .ao_speed = 1000, | |
314 | .num_p0_dio_channels = 8, | |
315 | .caldac = {mb88341}, | |
316 | .has_8255 = 0, | |
317 | }, | |
c4beb34e | 318 | { |
0a85b6f0 MT |
319 | .device_id = 0x1190, |
320 | .name = "pci-mio-16e-4", /* aka pci-6040e */ | |
321 | .n_adchan = 16, | |
322 | .adbits = 12, | |
323 | .ai_fifo_depth = 512, | |
324 | .alwaysdither = 0, | |
325 | .gainlkup = ai_gain_16, | |
326 | /* .Note = there have been reported problems with full speed | |
327 | * on this board */ | |
328 | .ai_speed = 2000, | |
329 | .n_aochan = 2, | |
330 | .aobits = 12, | |
331 | .ao_fifo_depth = 512, | |
332 | .ao_range_table = &range_ni_E_ao_ext, | |
333 | .ao_unipolar = 1, | |
334 | .ao_speed = 1000, | |
335 | .num_p0_dio_channels = 8, | |
336 | .caldac = {ad8804_debug}, /* doc says mb88341 */ | |
337 | .has_8255 = 0, | |
338 | }, | |
c4beb34e | 339 | { |
0a85b6f0 MT |
340 | .device_id = 0x11c0, |
341 | .name = "pxi-6040e", | |
342 | .n_adchan = 16, | |
343 | .adbits = 12, | |
344 | .ai_fifo_depth = 512, | |
345 | .alwaysdither = 0, | |
346 | .gainlkup = ai_gain_16, | |
347 | .ai_speed = 2000, | |
348 | .n_aochan = 2, | |
349 | .aobits = 12, | |
350 | .ao_fifo_depth = 512, | |
351 | .ao_range_table = &range_ni_E_ao_ext, | |
352 | .ao_unipolar = 1, | |
353 | .ao_speed = 1000, | |
354 | .num_p0_dio_channels = 8, | |
355 | .caldac = {mb88341}, | |
356 | .has_8255 = 0, | |
357 | }, | |
c4beb34e DS |
358 | |
359 | { | |
0a85b6f0 MT |
360 | .device_id = 0x1330, |
361 | .name = "pci-6031e", | |
362 | .n_adchan = 64, | |
363 | .adbits = 16, | |
364 | .ai_fifo_depth = 512, | |
365 | .alwaysdither = 1, | |
366 | .gainlkup = ai_gain_14, | |
367 | .ai_speed = 10000, | |
368 | .n_aochan = 2, | |
369 | .aobits = 16, | |
370 | .ao_fifo_depth = 2048, | |
371 | .ao_range_table = &range_ni_E_ao_ext, | |
372 | .ao_unipolar = 1, | |
373 | .ao_speed = 10000, | |
374 | .num_p0_dio_channels = 8, | |
375 | .caldac = {dac8800, dac8043, ad8522}, | |
376 | .has_8255 = 0, | |
377 | }, | |
c4beb34e | 378 | { |
0a85b6f0 MT |
379 | .device_id = 0x1270, |
380 | .name = "pci-6032e", | |
381 | .n_adchan = 16, | |
382 | .adbits = 16, | |
383 | .ai_fifo_depth = 512, | |
384 | .alwaysdither = 1, | |
385 | .gainlkup = ai_gain_14, | |
386 | .ai_speed = 10000, | |
387 | .n_aochan = 0, | |
388 | .aobits = 0, | |
389 | .ao_fifo_depth = 0, | |
390 | .ao_unipolar = 0, | |
391 | .num_p0_dio_channels = 8, | |
392 | .caldac = {dac8800, dac8043, ad8522}, | |
393 | .has_8255 = 0, | |
394 | }, | |
c4beb34e | 395 | { |
0a85b6f0 MT |
396 | .device_id = 0x1340, |
397 | .name = "pci-6033e", | |
398 | .n_adchan = 64, | |
399 | .adbits = 16, | |
400 | .ai_fifo_depth = 512, | |
401 | .alwaysdither = 1, | |
402 | .gainlkup = ai_gain_14, | |
403 | .ai_speed = 10000, | |
404 | .n_aochan = 0, | |
405 | .aobits = 0, | |
406 | .ao_fifo_depth = 0, | |
407 | .ao_unipolar = 0, | |
408 | .num_p0_dio_channels = 8, | |
409 | .caldac = {dac8800, dac8043, ad8522}, | |
410 | .has_8255 = 0, | |
411 | }, | |
c4beb34e | 412 | { |
0a85b6f0 MT |
413 | .device_id = 0x1350, |
414 | .name = "pci-6071e", | |
415 | .n_adchan = 64, | |
416 | .adbits = 12, | |
417 | .ai_fifo_depth = 512, | |
418 | .alwaysdither = 1, | |
419 | .gainlkup = ai_gain_16, | |
420 | .ai_speed = 800, | |
421 | .n_aochan = 2, | |
422 | .aobits = 12, | |
423 | .ao_fifo_depth = 2048, | |
424 | .ao_range_table = &range_ni_E_ao_ext, | |
425 | .ao_unipolar = 1, | |
426 | .ao_speed = 1000, | |
427 | .num_p0_dio_channels = 8, | |
428 | .caldac = {ad8804_debug}, | |
429 | .has_8255 = 0, | |
430 | }, | |
c4beb34e | 431 | { |
0a85b6f0 MT |
432 | .device_id = 0x2a60, |
433 | .name = "pci-6023e", | |
434 | .n_adchan = 16, | |
435 | .adbits = 12, | |
436 | .ai_fifo_depth = 512, | |
437 | .alwaysdither = 0, | |
438 | .gainlkup = ai_gain_4, | |
439 | .ai_speed = 5000, | |
440 | .n_aochan = 0, | |
441 | .aobits = 0, | |
442 | .ao_unipolar = 0, | |
443 | .num_p0_dio_channels = 8, | |
444 | .caldac = {ad8804_debug}, /* manual is wrong */ | |
445 | .has_8255 = 0, | |
446 | }, | |
c4beb34e | 447 | { |
0a85b6f0 MT |
448 | .device_id = 0x2a70, |
449 | .name = "pci-6024e", | |
450 | .n_adchan = 16, | |
451 | .adbits = 12, | |
452 | .ai_fifo_depth = 512, | |
453 | .alwaysdither = 0, | |
454 | .gainlkup = ai_gain_4, | |
455 | .ai_speed = 5000, | |
456 | .n_aochan = 2, | |
457 | .aobits = 12, | |
458 | .ao_fifo_depth = 0, | |
459 | .ao_range_table = &range_bipolar10, | |
460 | .ao_unipolar = 0, | |
461 | .ao_speed = 100000, | |
462 | .num_p0_dio_channels = 8, | |
463 | .caldac = {ad8804_debug}, /* manual is wrong */ | |
464 | .has_8255 = 0, | |
465 | }, | |
c4beb34e | 466 | { |
0a85b6f0 MT |
467 | .device_id = 0x2a80, |
468 | .name = "pci-6025e", | |
469 | .n_adchan = 16, | |
470 | .adbits = 12, | |
471 | .ai_fifo_depth = 512, | |
472 | .alwaysdither = 0, | |
473 | .gainlkup = ai_gain_4, | |
474 | .ai_speed = 5000, | |
475 | .n_aochan = 2, | |
476 | .aobits = 12, | |
477 | .ao_fifo_depth = 0, | |
478 | .ao_range_table = &range_bipolar10, | |
479 | .ao_unipolar = 0, | |
480 | .ao_speed = 100000, | |
481 | .num_p0_dio_channels = 8, | |
482 | .caldac = {ad8804_debug}, /* manual is wrong */ | |
483 | .has_8255 = 1, | |
484 | }, | |
c4beb34e | 485 | { |
0a85b6f0 MT |
486 | .device_id = 0x2ab0, |
487 | .name = "pxi-6025e", | |
488 | .n_adchan = 16, | |
489 | .adbits = 12, | |
490 | .ai_fifo_depth = 512, | |
491 | .alwaysdither = 0, | |
492 | .gainlkup = ai_gain_4, | |
493 | .ai_speed = 5000, | |
494 | .n_aochan = 2, | |
495 | .aobits = 12, | |
496 | .ao_fifo_depth = 0, | |
497 | .ao_range_table = &range_ni_E_ao_ext, | |
498 | .ao_unipolar = 1, | |
499 | .ao_speed = 100000, | |
500 | .num_p0_dio_channels = 8, | |
501 | .caldac = {ad8804_debug}, /* manual is wrong */ | |
502 | .has_8255 = 1, | |
503 | }, | |
c4beb34e DS |
504 | |
505 | { | |
0a85b6f0 MT |
506 | .device_id = 0x2ca0, |
507 | .name = "pci-6034e", | |
508 | .n_adchan = 16, | |
509 | .adbits = 16, | |
510 | .ai_fifo_depth = 512, | |
511 | .alwaysdither = 1, | |
512 | .gainlkup = ai_gain_4, | |
513 | .ai_speed = 5000, | |
514 | .n_aochan = 0, | |
515 | .aobits = 0, | |
516 | .ao_fifo_depth = 0, | |
517 | .ao_unipolar = 0, | |
518 | .num_p0_dio_channels = 8, | |
519 | .caldac = {ad8804_debug}, | |
520 | .has_8255 = 0, | |
521 | }, | |
c4beb34e | 522 | { |
0a85b6f0 MT |
523 | .device_id = 0x2c80, |
524 | .name = "pci-6035e", | |
525 | .n_adchan = 16, | |
526 | .adbits = 16, | |
527 | .ai_fifo_depth = 512, | |
528 | .alwaysdither = 1, | |
529 | .gainlkup = ai_gain_4, | |
530 | .ai_speed = 5000, | |
531 | .n_aochan = 2, | |
532 | .aobits = 12, | |
533 | .ao_fifo_depth = 0, | |
534 | .ao_range_table = &range_bipolar10, | |
535 | .ao_unipolar = 0, | |
536 | .ao_speed = 100000, | |
537 | .num_p0_dio_channels = 8, | |
538 | .caldac = {ad8804_debug}, | |
539 | .has_8255 = 0, | |
540 | }, | |
c4beb34e | 541 | { |
0a85b6f0 MT |
542 | .device_id = 0x18b0, |
543 | .name = "pci-6052e", | |
544 | .n_adchan = 16, | |
545 | .adbits = 16, | |
546 | .ai_fifo_depth = 512, | |
547 | .alwaysdither = 1, | |
548 | .gainlkup = ai_gain_16, | |
549 | .ai_speed = 3000, | |
550 | .n_aochan = 2, | |
551 | .aobits = 16, | |
552 | .ao_unipolar = 1, | |
553 | .ao_fifo_depth = 2048, | |
554 | .ao_range_table = &range_ni_E_ao_ext, | |
555 | .ao_speed = 3000, | |
556 | .num_p0_dio_channels = 8, | |
557 | .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */ | |
558 | }, | |
c4beb34e | 559 | {.device_id = 0x14e0, |
0a85b6f0 MT |
560 | .name = "pci-6110", |
561 | .n_adchan = 4, | |
562 | .adbits = 12, | |
563 | .ai_fifo_depth = 8192, | |
564 | .alwaysdither = 0, | |
565 | .gainlkup = ai_gain_611x, | |
566 | .ai_speed = 200, | |
567 | .n_aochan = 2, | |
568 | .aobits = 16, | |
569 | .reg_type = ni_reg_611x, | |
570 | .ao_range_table = &range_bipolar10, | |
571 | .ao_unipolar = 0, | |
572 | .ao_fifo_depth = 2048, | |
573 | .ao_speed = 250, | |
574 | .num_p0_dio_channels = 8, | |
575 | .caldac = {ad8804, ad8804}, | |
576 | }, | |
c4beb34e | 577 | { |
0a85b6f0 MT |
578 | .device_id = 0x14f0, |
579 | .name = "pci-6111", | |
580 | .n_adchan = 2, | |
581 | .adbits = 12, | |
582 | .ai_fifo_depth = 8192, | |
583 | .alwaysdither = 0, | |
584 | .gainlkup = ai_gain_611x, | |
585 | .ai_speed = 200, | |
586 | .n_aochan = 2, | |
587 | .aobits = 16, | |
588 | .reg_type = ni_reg_611x, | |
589 | .ao_range_table = &range_bipolar10, | |
590 | .ao_unipolar = 0, | |
591 | .ao_fifo_depth = 2048, | |
592 | .ao_speed = 250, | |
593 | .num_p0_dio_channels = 8, | |
594 | .caldac = {ad8804, ad8804}, | |
595 | }, | |
c4beb34e DS |
596 | #if 0 |
597 | /* The 6115 boards probably need their own driver */ | |
598 | { | |
0a85b6f0 MT |
599 | .device_id = 0x2ed0, |
600 | .name = "pci-6115", | |
601 | .n_adchan = 4, | |
602 | .adbits = 12, | |
603 | .ai_fifo_depth = 8192, | |
604 | .alwaysdither = 0, | |
605 | .gainlkup = ai_gain_611x, | |
606 | .ai_speed = 100, | |
607 | .n_aochan = 2, | |
608 | .aobits = 16, | |
609 | .ao_671x = 1, | |
610 | .ao_unipolar = 0, | |
611 | .ao_fifo_depth = 2048, | |
612 | .ao_speed = 250, | |
613 | .num_p0_dio_channels = 8, | |
614 | .reg_611x = 1, | |
615 | .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */ | |
616 | }, | |
c4beb34e DS |
617 | #endif |
618 | #if 0 | |
619 | { | |
0a85b6f0 MT |
620 | .device_id = 0x0000, |
621 | .name = "pxi-6115", | |
622 | .n_adchan = 4, | |
623 | .adbits = 12, | |
624 | .ai_fifo_depth = 8192, | |
625 | .alwaysdither = 0, | |
626 | .gainlkup = ai_gain_611x, | |
627 | .ai_speed = 100, | |
628 | .n_aochan = 2, | |
629 | .aobits = 16, | |
630 | .ao_671x = 1, | |
631 | .ao_unipolar = 0, | |
632 | .ao_fifo_depth = 2048, | |
633 | .ao_speed = 250, | |
634 | .reg_611x = 1, | |
635 | .num_p0_dio_channels = 8, | |
636 | caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */ | |
637 | }, | |
c4beb34e DS |
638 | #endif |
639 | { | |
0a85b6f0 MT |
640 | .device_id = 0x1880, |
641 | .name = "pci-6711", | |
642 | .n_adchan = 0, /* no analog input */ | |
643 | .n_aochan = 4, | |
644 | .aobits = 12, | |
645 | .ao_unipolar = 0, | |
646 | .ao_fifo_depth = 16384, | |
647 | /* data sheet says 8192, but fifo really holds 16384 samples */ | |
648 | .ao_range_table = &range_bipolar10, | |
649 | .ao_speed = 1000, | |
650 | .num_p0_dio_channels = 8, | |
651 | .reg_type = ni_reg_6711, | |
652 | .caldac = {ad8804_debug}, | |
653 | }, | |
c4beb34e | 654 | { |
0a85b6f0 MT |
655 | .device_id = 0x2b90, |
656 | .name = "pxi-6711", | |
657 | .n_adchan = 0, /* no analog input */ | |
658 | .n_aochan = 4, | |
659 | .aobits = 12, | |
660 | .ao_unipolar = 0, | |
661 | .ao_fifo_depth = 16384, | |
662 | .ao_range_table = &range_bipolar10, | |
663 | .ao_speed = 1000, | |
664 | .num_p0_dio_channels = 8, | |
665 | .reg_type = ni_reg_6711, | |
666 | .caldac = {ad8804_debug}, | |
667 | }, | |
c4beb34e | 668 | { |
0a85b6f0 MT |
669 | .device_id = 0x1870, |
670 | .name = "pci-6713", | |
671 | .n_adchan = 0, /* no analog input */ | |
672 | .n_aochan = 8, | |
673 | .aobits = 12, | |
674 | .ao_unipolar = 0, | |
675 | .ao_fifo_depth = 16384, | |
676 | .ao_range_table = &range_bipolar10, | |
677 | .ao_speed = 1000, | |
678 | .num_p0_dio_channels = 8, | |
679 | .reg_type = ni_reg_6713, | |
680 | .caldac = {ad8804_debug, ad8804_debug}, | |
681 | }, | |
c4beb34e | 682 | { |
0a85b6f0 MT |
683 | .device_id = 0x2b80, |
684 | .name = "pxi-6713", | |
685 | .n_adchan = 0, /* no analog input */ | |
686 | .n_aochan = 8, | |
687 | .aobits = 12, | |
688 | .ao_unipolar = 0, | |
689 | .ao_fifo_depth = 16384, | |
690 | .ao_range_table = &range_bipolar10, | |
691 | .ao_speed = 1000, | |
692 | .num_p0_dio_channels = 8, | |
693 | .reg_type = ni_reg_6713, | |
694 | .caldac = {ad8804_debug, ad8804_debug}, | |
695 | }, | |
c4beb34e | 696 | { |
0a85b6f0 MT |
697 | .device_id = 0x2430, |
698 | .name = "pci-6731", | |
699 | .n_adchan = 0, /* no analog input */ | |
700 | .n_aochan = 4, | |
701 | .aobits = 16, | |
702 | .ao_unipolar = 0, | |
703 | .ao_fifo_depth = 8192, | |
704 | .ao_range_table = &range_bipolar10, | |
705 | .ao_speed = 1000, | |
706 | .num_p0_dio_channels = 8, | |
707 | .reg_type = ni_reg_6711, | |
708 | .caldac = {ad8804_debug}, | |
709 | }, | |
c4beb34e DS |
710 | #if 0 /* need device ids */ |
711 | { | |
0a85b6f0 MT |
712 | .device_id = 0x0, |
713 | .name = "pxi-6731", | |
714 | .n_adchan = 0, /* no analog input */ | |
715 | .n_aochan = 4, | |
716 | .aobits = 16, | |
717 | .ao_unipolar = 0, | |
718 | .ao_fifo_depth = 8192, | |
719 | .ao_range_table = &range_bipolar10, | |
720 | .num_p0_dio_channels = 8, | |
721 | .reg_type = ni_reg_6711, | |
722 | .caldac = {ad8804_debug}, | |
723 | }, | |
c4beb34e DS |
724 | #endif |
725 | { | |
0a85b6f0 MT |
726 | .device_id = 0x2410, |
727 | .name = "pci-6733", | |
728 | .n_adchan = 0, /* no analog input */ | |
729 | .n_aochan = 8, | |
730 | .aobits = 16, | |
731 | .ao_unipolar = 0, | |
732 | .ao_fifo_depth = 16384, | |
733 | .ao_range_table = &range_bipolar10, | |
734 | .ao_speed = 1000, | |
735 | .num_p0_dio_channels = 8, | |
736 | .reg_type = ni_reg_6713, | |
737 | .caldac = {ad8804_debug, ad8804_debug}, | |
738 | }, | |
c4beb34e | 739 | { |
0a85b6f0 MT |
740 | .device_id = 0x2420, |
741 | .name = "pxi-6733", | |
742 | .n_adchan = 0, /* no analog input */ | |
743 | .n_aochan = 8, | |
744 | .aobits = 16, | |
745 | .ao_unipolar = 0, | |
746 | .ao_fifo_depth = 16384, | |
747 | .ao_range_table = &range_bipolar10, | |
748 | .ao_speed = 1000, | |
749 | .num_p0_dio_channels = 8, | |
750 | .reg_type = ni_reg_6713, | |
751 | .caldac = {ad8804_debug, ad8804_debug}, | |
752 | }, | |
c4beb34e | 753 | { |
0a85b6f0 MT |
754 | .device_id = 0x15b0, |
755 | .name = "pxi-6071e", | |
756 | .n_adchan = 64, | |
757 | .adbits = 12, | |
758 | .ai_fifo_depth = 512, | |
759 | .alwaysdither = 1, | |
760 | .gainlkup = ai_gain_16, | |
761 | .ai_speed = 800, | |
762 | .n_aochan = 2, | |
763 | .aobits = 12, | |
764 | .ao_fifo_depth = 2048, | |
765 | .ao_range_table = &range_ni_E_ao_ext, | |
766 | .ao_unipolar = 1, | |
767 | .ao_speed = 1000, | |
768 | .num_p0_dio_channels = 8, | |
769 | .caldac = {ad8804_debug}, | |
770 | .has_8255 = 0, | |
771 | }, | |
c4beb34e | 772 | { |
0a85b6f0 MT |
773 | .device_id = 0x11b0, |
774 | .name = "pxi-6070e", | |
775 | .n_adchan = 16, | |
776 | .adbits = 12, | |
777 | .ai_fifo_depth = 512, | |
778 | .alwaysdither = 1, | |
779 | .gainlkup = ai_gain_16, | |
780 | .ai_speed = 800, | |
781 | .n_aochan = 2, | |
782 | .aobits = 12, | |
783 | .ao_fifo_depth = 2048, | |
784 | .ao_range_table = &range_ni_E_ao_ext, | |
785 | .ao_unipolar = 1, | |
786 | .ao_speed = 1000, | |
787 | .num_p0_dio_channels = 8, | |
788 | .caldac = {ad8804_debug}, | |
789 | .has_8255 = 0, | |
790 | }, | |
c4beb34e | 791 | { |
0a85b6f0 MT |
792 | .device_id = 0x18c0, |
793 | .name = "pxi-6052e", | |
794 | .n_adchan = 16, | |
795 | .adbits = 16, | |
796 | .ai_fifo_depth = 512, | |
797 | .alwaysdither = 1, | |
798 | .gainlkup = ai_gain_16, | |
799 | .ai_speed = 3000, | |
800 | .n_aochan = 2, | |
801 | .aobits = 16, | |
802 | .ao_unipolar = 1, | |
803 | .ao_fifo_depth = 2048, | |
804 | .ao_range_table = &range_ni_E_ao_ext, | |
805 | .ao_speed = 3000, | |
806 | .num_p0_dio_channels = 8, | |
807 | .caldac = {mb88341, mb88341, ad8522}, | |
808 | }, | |
c4beb34e | 809 | { |
0a85b6f0 MT |
810 | .device_id = 0x1580, |
811 | .name = "pxi-6031e", | |
812 | .n_adchan = 64, | |
813 | .adbits = 16, | |
814 | .ai_fifo_depth = 512, | |
815 | .alwaysdither = 1, | |
816 | .gainlkup = ai_gain_14, | |
817 | .ai_speed = 10000, | |
818 | .n_aochan = 2, | |
819 | .aobits = 16, | |
820 | .ao_fifo_depth = 2048, | |
821 | .ao_range_table = &range_ni_E_ao_ext, | |
822 | .ao_unipolar = 1, | |
823 | .ao_speed = 10000, | |
824 | .num_p0_dio_channels = 8, | |
825 | .caldac = {dac8800, dac8043, ad8522}, | |
826 | }, | |
c4beb34e | 827 | { |
0a85b6f0 MT |
828 | .device_id = 0x2890, |
829 | .name = "pci-6036e", | |
830 | .n_adchan = 16, | |
831 | .adbits = 16, | |
832 | .ai_fifo_depth = 512, | |
833 | .alwaysdither = 1, | |
834 | .gainlkup = ai_gain_4, | |
835 | .ai_speed = 5000, | |
836 | .n_aochan = 2, | |
837 | .aobits = 16, | |
838 | .ao_fifo_depth = 0, | |
839 | .ao_range_table = &range_bipolar10, | |
840 | .ao_unipolar = 0, | |
841 | .ao_speed = 100000, | |
842 | .num_p0_dio_channels = 8, | |
843 | .caldac = {ad8804_debug}, | |
844 | .has_8255 = 0, | |
845 | }, | |
c4beb34e | 846 | { |
0a85b6f0 MT |
847 | .device_id = 0x70b0, |
848 | .name = "pci-6220", | |
849 | .n_adchan = 16, | |
850 | .adbits = 16, | |
851 | .ai_fifo_depth = 512, | |
852 | /* .FIXME = guess */ | |
853 | .gainlkup = ai_gain_622x, | |
854 | .ai_speed = 4000, | |
855 | .n_aochan = 0, | |
856 | .aobits = 0, | |
857 | .ao_fifo_depth = 0, | |
858 | .num_p0_dio_channels = 8, | |
859 | .reg_type = ni_reg_622x, | |
860 | .ao_unipolar = 0, | |
861 | .caldac = {caldac_none}, | |
862 | .has_8255 = 0, | |
863 | }, | |
c4beb34e | 864 | { |
0a85b6f0 MT |
865 | .device_id = 0x70af, |
866 | .name = "pci-6221", | |
867 | .n_adchan = 16, | |
868 | .adbits = 16, | |
869 | .ai_fifo_depth = 4095, | |
870 | .gainlkup = ai_gain_622x, | |
871 | .ai_speed = 4000, | |
872 | .n_aochan = 2, | |
873 | .aobits = 16, | |
874 | .ao_fifo_depth = 8191, | |
875 | .ao_range_table = &range_ni_M_622x_ao, | |
876 | .reg_type = ni_reg_622x, | |
877 | .ao_unipolar = 0, | |
878 | .ao_speed = 1200, | |
879 | .num_p0_dio_channels = 8, | |
880 | .caldac = {caldac_none}, | |
881 | .has_8255 = 0, | |
882 | }, | |
c4beb34e | 883 | { |
0a85b6f0 MT |
884 | .device_id = 0x71bc, |
885 | .name = "pci-6221_37pin", | |
886 | .n_adchan = 16, | |
887 | .adbits = 16, | |
888 | .ai_fifo_depth = 4095, | |
889 | .gainlkup = ai_gain_622x, | |
890 | .ai_speed = 4000, | |
891 | .n_aochan = 2, | |
892 | .aobits = 16, | |
893 | .ao_fifo_depth = 8191, | |
894 | .ao_range_table = &range_ni_M_622x_ao, | |
895 | .reg_type = ni_reg_622x, | |
896 | .ao_unipolar = 0, | |
897 | .ao_speed = 1200, | |
898 | .num_p0_dio_channels = 8, | |
899 | .caldac = {caldac_none}, | |
900 | .has_8255 = 0, | |
901 | }, | |
c4beb34e | 902 | { |
0a85b6f0 MT |
903 | .device_id = 0x70f2, |
904 | .name = "pci-6224", | |
905 | .n_adchan = 32, | |
906 | .adbits = 16, | |
907 | .ai_fifo_depth = 4095, | |
908 | .gainlkup = ai_gain_622x, | |
909 | .ai_speed = 4000, | |
910 | .n_aochan = 0, | |
911 | .aobits = 0, | |
912 | .ao_fifo_depth = 0, | |
913 | .reg_type = ni_reg_622x, | |
914 | .ao_unipolar = 0, | |
915 | .num_p0_dio_channels = 32, | |
916 | .caldac = {caldac_none}, | |
917 | .has_8255 = 0, | |
918 | }, | |
51e290fd | 919 | { |
0a85b6f0 MT |
920 | .device_id = 0x70f3, |
921 | .name = "pxi-6224", | |
922 | .n_adchan = 32, | |
923 | .adbits = 16, | |
924 | .ai_fifo_depth = 4095, | |
925 | .gainlkup = ai_gain_622x, | |
926 | .ai_speed = 4000, | |
927 | .n_aochan = 0, | |
928 | .aobits = 0, | |
929 | .ao_fifo_depth = 0, | |
930 | .reg_type = ni_reg_622x, | |
931 | .ao_unipolar = 0, | |
932 | .num_p0_dio_channels = 32, | |
933 | .caldac = {caldac_none}, | |
934 | .has_8255 = 0, | |
935 | }, | |
c4beb34e | 936 | { |
0a85b6f0 MT |
937 | .device_id = 0x716c, |
938 | .name = "pci-6225", | |
939 | .n_adchan = 80, | |
940 | .adbits = 16, | |
941 | .ai_fifo_depth = 4095, | |
942 | .gainlkup = ai_gain_622x, | |
943 | .ai_speed = 4000, | |
944 | .n_aochan = 2, | |
945 | .aobits = 16, | |
946 | .ao_fifo_depth = 8191, | |
947 | .ao_range_table = &range_ni_M_622x_ao, | |
948 | .reg_type = ni_reg_622x, | |
949 | .ao_unipolar = 0, | |
950 | .ao_speed = 1200, | |
951 | .num_p0_dio_channels = 32, | |
952 | .caldac = {caldac_none}, | |
953 | .has_8255 = 0, | |
954 | }, | |
c4beb34e | 955 | { |
0a85b6f0 MT |
956 | .device_id = 0x70aa, |
957 | .name = "pci-6229", | |
958 | .n_adchan = 32, | |
959 | .adbits = 16, | |
960 | .ai_fifo_depth = 4095, | |
961 | .gainlkup = ai_gain_622x, | |
962 | .ai_speed = 4000, | |
963 | .n_aochan = 4, | |
964 | .aobits = 16, | |
965 | .ao_fifo_depth = 8191, | |
966 | .ao_range_table = &range_ni_M_622x_ao, | |
967 | .reg_type = ni_reg_622x, | |
968 | .ao_unipolar = 0, | |
969 | .ao_speed = 1200, | |
970 | .num_p0_dio_channels = 32, | |
971 | .caldac = {caldac_none}, | |
972 | .has_8255 = 0, | |
973 | }, | |
c4beb34e | 974 | { |
0a85b6f0 MT |
975 | .device_id = 0x70b4, |
976 | .name = "pci-6250", | |
977 | .n_adchan = 16, | |
978 | .adbits = 16, | |
979 | .ai_fifo_depth = 4095, | |
980 | .gainlkup = ai_gain_628x, | |
981 | .ai_speed = 800, | |
982 | .n_aochan = 0, | |
983 | .aobits = 0, | |
984 | .ao_fifo_depth = 0, | |
985 | .reg_type = ni_reg_625x, | |
986 | .ao_unipolar = 0, | |
987 | .num_p0_dio_channels = 8, | |
988 | .caldac = {caldac_none}, | |
989 | .has_8255 = 0, | |
990 | }, | |
c4beb34e | 991 | { |
0a85b6f0 MT |
992 | .device_id = 0x70b8, |
993 | .name = "pci-6251", | |
994 | .n_adchan = 16, | |
995 | .adbits = 16, | |
996 | .ai_fifo_depth = 4095, | |
997 | .gainlkup = ai_gain_628x, | |
998 | .ai_speed = 800, | |
999 | .n_aochan = 2, | |
1000 | .aobits = 16, | |
1001 | .ao_fifo_depth = 8191, | |
1002 | .ao_range_table = &range_ni_M_625x_ao, | |
1003 | .reg_type = ni_reg_625x, | |
1004 | .ao_unipolar = 0, | |
1005 | .ao_speed = 357, | |
1006 | .num_p0_dio_channels = 8, | |
1007 | .caldac = {caldac_none}, | |
1008 | .has_8255 = 0, | |
1009 | }, | |
c4beb34e | 1010 | { |
0a85b6f0 MT |
1011 | .device_id = 0x717d, |
1012 | .name = "pcie-6251", | |
1013 | .n_adchan = 16, | |
1014 | .adbits = 16, | |
1015 | .ai_fifo_depth = 4095, | |
1016 | .gainlkup = ai_gain_628x, | |
1017 | .ai_speed = 800, | |
1018 | .n_aochan = 2, | |
1019 | .aobits = 16, | |
1020 | .ao_fifo_depth = 8191, | |
1021 | .ao_range_table = &range_ni_M_625x_ao, | |
1022 | .reg_type = ni_reg_625x, | |
1023 | .ao_unipolar = 0, | |
1024 | .ao_speed = 357, | |
1025 | .num_p0_dio_channels = 8, | |
1026 | .caldac = {caldac_none}, | |
1027 | .has_8255 = 0, | |
1028 | }, | |
c4beb34e | 1029 | { |
0a85b6f0 MT |
1030 | .device_id = 0x70b7, |
1031 | .name = "pci-6254", | |
1032 | .n_adchan = 32, | |
1033 | .adbits = 16, | |
1034 | .ai_fifo_depth = 4095, | |
1035 | .gainlkup = ai_gain_628x, | |
1036 | .ai_speed = 800, | |
1037 | .n_aochan = 0, | |
1038 | .aobits = 0, | |
1039 | .ao_fifo_depth = 0, | |
1040 | .reg_type = ni_reg_625x, | |
1041 | .ao_unipolar = 0, | |
1042 | .num_p0_dio_channels = 32, | |
1043 | .caldac = {caldac_none}, | |
1044 | .has_8255 = 0, | |
1045 | }, | |
c4beb34e | 1046 | { |
0a85b6f0 MT |
1047 | .device_id = 0x70ab, |
1048 | .name = "pci-6259", | |
1049 | .n_adchan = 32, | |
1050 | .adbits = 16, | |
1051 | .ai_fifo_depth = 4095, | |
1052 | .gainlkup = ai_gain_628x, | |
1053 | .ai_speed = 800, | |
1054 | .n_aochan = 4, | |
1055 | .aobits = 16, | |
1056 | .ao_fifo_depth = 8191, | |
1057 | .ao_range_table = &range_ni_M_625x_ao, | |
1058 | .reg_type = ni_reg_625x, | |
1059 | .ao_unipolar = 0, | |
1060 | .ao_speed = 357, | |
1061 | .num_p0_dio_channels = 32, | |
1062 | .caldac = {caldac_none}, | |
1063 | .has_8255 = 0, | |
1064 | }, | |
c4beb34e | 1065 | { |
0a85b6f0 MT |
1066 | .device_id = 0x717f, |
1067 | .name = "pcie-6259", | |
1068 | .n_adchan = 32, | |
1069 | .adbits = 16, | |
1070 | .ai_fifo_depth = 4095, | |
1071 | .gainlkup = ai_gain_628x, | |
1072 | .ai_speed = 800, | |
1073 | .n_aochan = 4, | |
1074 | .aobits = 16, | |
1075 | .ao_fifo_depth = 8191, | |
1076 | .ao_range_table = &range_ni_M_625x_ao, | |
1077 | .reg_type = ni_reg_625x, | |
1078 | .ao_unipolar = 0, | |
1079 | .ao_speed = 357, | |
1080 | .num_p0_dio_channels = 32, | |
1081 | .caldac = {caldac_none}, | |
1082 | .has_8255 = 0, | |
1083 | }, | |
c4beb34e | 1084 | { |
0a85b6f0 MT |
1085 | .device_id = 0x70b6, |
1086 | .name = "pci-6280", | |
1087 | .n_adchan = 16, | |
1088 | .adbits = 18, | |
1089 | .ai_fifo_depth = 2047, | |
1090 | .gainlkup = ai_gain_628x, | |
1091 | .ai_speed = 1600, | |
1092 | .n_aochan = 0, | |
1093 | .aobits = 0, | |
1094 | .ao_fifo_depth = 8191, | |
1095 | .reg_type = ni_reg_628x, | |
1096 | .ao_unipolar = 0, | |
1097 | .num_p0_dio_channels = 8, | |
1098 | .caldac = {caldac_none}, | |
1099 | .has_8255 = 0, | |
1100 | }, | |
c4beb34e | 1101 | { |
0a85b6f0 MT |
1102 | .device_id = 0x70bd, |
1103 | .name = "pci-6281", | |
1104 | .n_adchan = 16, | |
1105 | .adbits = 18, | |
1106 | .ai_fifo_depth = 2047, | |
1107 | .gainlkup = ai_gain_628x, | |
1108 | .ai_speed = 1600, | |
1109 | .n_aochan = 2, | |
1110 | .aobits = 16, | |
1111 | .ao_fifo_depth = 8191, | |
1112 | .ao_range_table = &range_ni_M_628x_ao, | |
1113 | .reg_type = ni_reg_628x, | |
1114 | .ao_unipolar = 1, | |
1115 | .ao_speed = 357, | |
1116 | .num_p0_dio_channels = 8, | |
1117 | .caldac = {caldac_none}, | |
1118 | .has_8255 = 0, | |
1119 | }, | |
c4beb34e | 1120 | { |
0a85b6f0 MT |
1121 | .device_id = 0x70bf, |
1122 | .name = "pxi-6281", | |
1123 | .n_adchan = 16, | |
1124 | .adbits = 18, | |
1125 | .ai_fifo_depth = 2047, | |
1126 | .gainlkup = ai_gain_628x, | |
1127 | .ai_speed = 1600, | |
1128 | .n_aochan = 2, | |
1129 | .aobits = 16, | |
1130 | .ao_fifo_depth = 8191, | |
1131 | .ao_range_table = &range_ni_M_628x_ao, | |
1132 | .reg_type = ni_reg_628x, | |
1133 | .ao_unipolar = 1, | |
1134 | .ao_speed = 357, | |
1135 | .num_p0_dio_channels = 8, | |
1136 | .caldac = {caldac_none}, | |
1137 | .has_8255 = 0, | |
1138 | }, | |
c4beb34e | 1139 | { |
0a85b6f0 MT |
1140 | .device_id = 0x70bc, |
1141 | .name = "pci-6284", | |
1142 | .n_adchan = 32, | |
1143 | .adbits = 18, | |
1144 | .ai_fifo_depth = 2047, | |
1145 | .gainlkup = ai_gain_628x, | |
1146 | .ai_speed = 1600, | |
1147 | .n_aochan = 0, | |
1148 | .aobits = 0, | |
1149 | .ao_fifo_depth = 0, | |
1150 | .reg_type = ni_reg_628x, | |
1151 | .ao_unipolar = 0, | |
1152 | .num_p0_dio_channels = 32, | |
1153 | .caldac = {caldac_none}, | |
1154 | .has_8255 = 0, | |
1155 | }, | |
c4beb34e | 1156 | { |
0a85b6f0 MT |
1157 | .device_id = 0x70ac, |
1158 | .name = "pci-6289", | |
1159 | .n_adchan = 32, | |
1160 | .adbits = 18, | |
1161 | .ai_fifo_depth = 2047, | |
1162 | .gainlkup = ai_gain_628x, | |
1163 | .ai_speed = 1600, | |
1164 | .n_aochan = 4, | |
1165 | .aobits = 16, | |
1166 | .ao_fifo_depth = 8191, | |
1167 | .ao_range_table = &range_ni_M_628x_ao, | |
1168 | .reg_type = ni_reg_628x, | |
1169 | .ao_unipolar = 1, | |
1170 | .ao_speed = 357, | |
1171 | .num_p0_dio_channels = 32, | |
1172 | .caldac = {caldac_none}, | |
1173 | .has_8255 = 0, | |
1174 | }, | |
c4beb34e | 1175 | { |
0a85b6f0 MT |
1176 | .device_id = 0x70C0, |
1177 | .name = "pci-6143", | |
1178 | .n_adchan = 8, | |
1179 | .adbits = 16, | |
1180 | .ai_fifo_depth = 1024, | |
1181 | .alwaysdither = 0, | |
1182 | .gainlkup = ai_gain_6143, | |
1183 | .ai_speed = 4000, | |
1184 | .n_aochan = 0, | |
1185 | .aobits = 0, | |
1186 | .reg_type = ni_reg_6143, | |
1187 | .ao_unipolar = 0, | |
1188 | .ao_fifo_depth = 0, | |
1189 | .num_p0_dio_channels = 8, | |
1190 | .caldac = {ad8804_debug, ad8804_debug}, | |
1191 | }, | |
c4beb34e | 1192 | { |
0a85b6f0 MT |
1193 | .device_id = 0x710D, |
1194 | .name = "pxi-6143", | |
1195 | .n_adchan = 8, | |
1196 | .adbits = 16, | |
1197 | .ai_fifo_depth = 1024, | |
1198 | .alwaysdither = 0, | |
1199 | .gainlkup = ai_gain_6143, | |
1200 | .ai_speed = 4000, | |
1201 | .n_aochan = 0, | |
1202 | .aobits = 0, | |
1203 | .reg_type = ni_reg_6143, | |
1204 | .ao_unipolar = 0, | |
1205 | .ao_fifo_depth = 0, | |
1206 | .num_p0_dio_channels = 8, | |
1207 | .caldac = {ad8804_debug, ad8804_debug}, | |
1208 | }, | |
c4beb34e DS |
1209 | }; |
1210 | ||
1211 | #define n_pcimio_boards ((sizeof(ni_boards)/sizeof(ni_boards[0]))) | |
1212 | ||
0a85b6f0 MT |
1213 | static int pcimio_attach(struct comedi_device *dev, |
1214 | struct comedi_devconfig *it); | |
da91b269 | 1215 | static int pcimio_detach(struct comedi_device *dev); |
139dfbdf | 1216 | static struct comedi_driver driver_pcimio = { |
68c3dbff BP |
1217 | .driver_name = DRV_NAME, |
1218 | .module = THIS_MODULE, | |
1219 | .attach = pcimio_attach, | |
1220 | .detach = pcimio_detach, | |
c4beb34e DS |
1221 | }; |
1222 | ||
1223 | COMEDI_PCI_INITCLEANUP(driver_pcimio, ni_pci_table) | |
1224 | ||
3301cc76 | 1225 | struct ni_private { |
0a85b6f0 | 1226 | NI_PRIVATE_COMMON}; |
3301cc76 | 1227 | #define devpriv ((struct ni_private *)dev->private) |
c4beb34e DS |
1228 | |
1229 | /* How we access registers */ | |
1230 | ||
f7cbd7aa | 1231 | #define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b))) |
c4beb34e | 1232 | #define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a))) |
f7cbd7aa | 1233 | #define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b))) |
c4beb34e | 1234 | #define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a))) |
f7cbd7aa | 1235 | #define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b))) |
c4beb34e DS |
1236 | #define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a))) |
1237 | ||
1238 | /* How we access STC registers */ | |
1239 | ||
1240 | /* We automatically take advantage of STC registers that can be | |
1241 | * read/written directly in the I/O space of the board. Most | |
1242 | * PCIMIO devices map the low 8 STC registers to iobase+addr*2. | |
1243 | * The 611x devices map the write registers to iobase+addr*2, and | |
1244 | * the read registers to iobase+(addr-1)*2. */ | |
1245 | /* However, the 611x boards still aren't working, so I'm disabling | |
1246 | * non-windowed STC access temporarily */ | |
1247 | ||
da91b269 | 1248 | static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg) |
c4beb34e DS |
1249 | { |
1250 | unsigned long flags; | |
1251 | ||
5f74ea14 | 1252 | spin_lock_irqsave(&devpriv->window_lock, flags); |
c4beb34e DS |
1253 | ni_writew(reg, Window_Address); |
1254 | ni_writew(data, Window_Data); | |
5f74ea14 | 1255 | spin_unlock_irqrestore(&devpriv->window_lock, flags); |
c4beb34e DS |
1256 | } |
1257 | ||
da91b269 | 1258 | static uint16_t e_series_win_in(struct comedi_device *dev, int reg) |
c4beb34e DS |
1259 | { |
1260 | unsigned long flags; | |
1261 | uint16_t ret; | |
1262 | ||
5f74ea14 | 1263 | spin_lock_irqsave(&devpriv->window_lock, flags); |
c4beb34e DS |
1264 | ni_writew(reg, Window_Address); |
1265 | ret = ni_readw(Window_Data); | |
5f74ea14 | 1266 | spin_unlock_irqrestore(&devpriv->window_lock, flags); |
c4beb34e DS |
1267 | |
1268 | return ret; | |
1269 | } | |
1270 | ||
0a85b6f0 MT |
1271 | static void m_series_stc_writew(struct comedi_device *dev, uint16_t data, |
1272 | int reg) | |
c4beb34e DS |
1273 | { |
1274 | unsigned offset; | |
1275 | switch (reg) { | |
1276 | case ADC_FIFO_Clear: | |
1277 | offset = M_Offset_AI_FIFO_Clear; | |
1278 | break; | |
1279 | case AI_Command_1_Register: | |
1280 | offset = M_Offset_AI_Command_1; | |
1281 | break; | |
1282 | case AI_Command_2_Register: | |
1283 | offset = M_Offset_AI_Command_2; | |
1284 | break; | |
1285 | case AI_Mode_1_Register: | |
1286 | offset = M_Offset_AI_Mode_1; | |
1287 | break; | |
1288 | case AI_Mode_2_Register: | |
1289 | offset = M_Offset_AI_Mode_2; | |
1290 | break; | |
1291 | case AI_Mode_3_Register: | |
1292 | offset = M_Offset_AI_Mode_3; | |
1293 | break; | |
1294 | case AI_Output_Control_Register: | |
1295 | offset = M_Offset_AI_Output_Control; | |
1296 | break; | |
1297 | case AI_Personal_Register: | |
1298 | offset = M_Offset_AI_Personal; | |
1299 | break; | |
1300 | case AI_SI2_Load_A_Register: | |
2696fb57 | 1301 | /* this is actually a 32 bit register on m series boards */ |
c4beb34e DS |
1302 | ni_writel(data, M_Offset_AI_SI2_Load_A); |
1303 | return; | |
1304 | break; | |
1305 | case AI_SI2_Load_B_Register: | |
2696fb57 | 1306 | /* this is actually a 32 bit register on m series boards */ |
c4beb34e DS |
1307 | ni_writel(data, M_Offset_AI_SI2_Load_B); |
1308 | return; | |
1309 | break; | |
1310 | case AI_START_STOP_Select_Register: | |
1311 | offset = M_Offset_AI_START_STOP_Select; | |
1312 | break; | |
1313 | case AI_Trigger_Select_Register: | |
1314 | offset = M_Offset_AI_Trigger_Select; | |
1315 | break; | |
1316 | case Analog_Trigger_Etc_Register: | |
1317 | offset = M_Offset_Analog_Trigger_Etc; | |
1318 | break; | |
1319 | case AO_Command_1_Register: | |
1320 | offset = M_Offset_AO_Command_1; | |
1321 | break; | |
1322 | case AO_Command_2_Register: | |
1323 | offset = M_Offset_AO_Command_2; | |
1324 | break; | |
1325 | case AO_Mode_1_Register: | |
1326 | offset = M_Offset_AO_Mode_1; | |
1327 | break; | |
1328 | case AO_Mode_2_Register: | |
1329 | offset = M_Offset_AO_Mode_2; | |
1330 | break; | |
1331 | case AO_Mode_3_Register: | |
1332 | offset = M_Offset_AO_Mode_3; | |
1333 | break; | |
1334 | case AO_Output_Control_Register: | |
1335 | offset = M_Offset_AO_Output_Control; | |
1336 | break; | |
1337 | case AO_Personal_Register: | |
1338 | offset = M_Offset_AO_Personal; | |
1339 | break; | |
1340 | case AO_Start_Select_Register: | |
1341 | offset = M_Offset_AO_Start_Select; | |
1342 | break; | |
1343 | case AO_Trigger_Select_Register: | |
1344 | offset = M_Offset_AO_Trigger_Select; | |
1345 | break; | |
1346 | case Clock_and_FOUT_Register: | |
1347 | offset = M_Offset_Clock_and_FOUT; | |
1348 | break; | |
1349 | case Configuration_Memory_Clear: | |
1350 | offset = M_Offset_Configuration_Memory_Clear; | |
1351 | break; | |
1352 | case DAC_FIFO_Clear: | |
1353 | offset = M_Offset_AO_FIFO_Clear; | |
1354 | break; | |
1355 | case DIO_Control_Register: | |
5f74ea14 | 1356 | printk |
0a85b6f0 MT |
1357 | ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n", |
1358 | __func__, reg); | |
c4beb34e DS |
1359 | return; |
1360 | break; | |
1361 | case G_Autoincrement_Register(0): | |
1362 | offset = M_Offset_G0_Autoincrement; | |
1363 | break; | |
1364 | case G_Autoincrement_Register(1): | |
1365 | offset = M_Offset_G1_Autoincrement; | |
1366 | break; | |
1367 | case G_Command_Register(0): | |
1368 | offset = M_Offset_G0_Command; | |
1369 | break; | |
1370 | case G_Command_Register(1): | |
1371 | offset = M_Offset_G1_Command; | |
1372 | break; | |
1373 | case G_Input_Select_Register(0): | |
1374 | offset = M_Offset_G0_Input_Select; | |
1375 | break; | |
1376 | case G_Input_Select_Register(1): | |
1377 | offset = M_Offset_G1_Input_Select; | |
1378 | break; | |
1379 | case G_Mode_Register(0): | |
1380 | offset = M_Offset_G0_Mode; | |
1381 | break; | |
1382 | case G_Mode_Register(1): | |
1383 | offset = M_Offset_G1_Mode; | |
1384 | break; | |
1385 | case Interrupt_A_Ack_Register: | |
1386 | offset = M_Offset_Interrupt_A_Ack; | |
1387 | break; | |
1388 | case Interrupt_A_Enable_Register: | |
1389 | offset = M_Offset_Interrupt_A_Enable; | |
1390 | break; | |
1391 | case Interrupt_B_Ack_Register: | |
1392 | offset = M_Offset_Interrupt_B_Ack; | |
1393 | break; | |
1394 | case Interrupt_B_Enable_Register: | |
1395 | offset = M_Offset_Interrupt_B_Enable; | |
1396 | break; | |
1397 | case Interrupt_Control_Register: | |
1398 | offset = M_Offset_Interrupt_Control; | |
1399 | break; | |
1400 | case IO_Bidirection_Pin_Register: | |
1401 | offset = M_Offset_IO_Bidirection_Pin; | |
1402 | break; | |
1403 | case Joint_Reset_Register: | |
1404 | offset = M_Offset_Joint_Reset; | |
1405 | break; | |
1406 | case RTSI_Trig_A_Output_Register: | |
1407 | offset = M_Offset_RTSI_Trig_A_Output; | |
1408 | break; | |
1409 | case RTSI_Trig_B_Output_Register: | |
1410 | offset = M_Offset_RTSI_Trig_B_Output; | |
1411 | break; | |
1412 | case RTSI_Trig_Direction_Register: | |
1413 | offset = M_Offset_RTSI_Trig_Direction; | |
1414 | break; | |
1415 | /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit) | |
1416 | and M_Offset_SCXI_Serial_Data_Out (8 bit) */ | |
1417 | default: | |
5f74ea14 | 1418 | printk("%s: bug! unhandled register=0x%x in switch.\n", |
0a85b6f0 | 1419 | __func__, reg); |
c4beb34e DS |
1420 | BUG(); |
1421 | return; | |
1422 | break; | |
1423 | } | |
1424 | ni_writew(data, offset); | |
1425 | } | |
1426 | ||
da91b269 | 1427 | static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg) |
c4beb34e DS |
1428 | { |
1429 | unsigned offset; | |
1430 | switch (reg) { | |
1431 | case AI_Status_1_Register: | |
1432 | offset = M_Offset_AI_Status_1; | |
1433 | break; | |
1434 | case AO_Status_1_Register: | |
1435 | offset = M_Offset_AO_Status_1; | |
1436 | break; | |
1437 | case AO_Status_2_Register: | |
1438 | offset = M_Offset_AO_Status_2; | |
1439 | break; | |
1440 | case DIO_Serial_Input_Register: | |
1441 | return ni_readb(M_Offset_SCXI_Serial_Data_In); | |
1442 | break; | |
1443 | case Joint_Status_1_Register: | |
1444 | offset = M_Offset_Joint_Status_1; | |
1445 | break; | |
1446 | case Joint_Status_2_Register: | |
1447 | offset = M_Offset_Joint_Status_2; | |
1448 | break; | |
1449 | case G_Status_Register: | |
1450 | offset = M_Offset_G01_Status; | |
1451 | break; | |
1452 | default: | |
5f74ea14 | 1453 | printk("%s: bug! unhandled register=0x%x in switch.\n", |
0a85b6f0 | 1454 | __func__, reg); |
c4beb34e DS |
1455 | BUG(); |
1456 | return 0; | |
1457 | break; | |
1458 | } | |
1459 | return ni_readw(offset); | |
1460 | } | |
1461 | ||
0a85b6f0 MT |
1462 | static void m_series_stc_writel(struct comedi_device *dev, uint32_t data, |
1463 | int reg) | |
c4beb34e DS |
1464 | { |
1465 | unsigned offset; | |
1466 | switch (reg) { | |
1467 | case AI_SC_Load_A_Registers: | |
1468 | offset = M_Offset_AI_SC_Load_A; | |
1469 | break; | |
1470 | case AI_SI_Load_A_Registers: | |
1471 | offset = M_Offset_AI_SI_Load_A; | |
1472 | break; | |
1473 | case AO_BC_Load_A_Register: | |
1474 | offset = M_Offset_AO_BC_Load_A; | |
1475 | break; | |
1476 | case AO_UC_Load_A_Register: | |
1477 | offset = M_Offset_AO_UC_Load_A; | |
1478 | break; | |
1479 | case AO_UI_Load_A_Register: | |
1480 | offset = M_Offset_AO_UI_Load_A; | |
1481 | break; | |
1482 | case G_Load_A_Register(0): | |
1483 | offset = M_Offset_G0_Load_A; | |
1484 | break; | |
1485 | case G_Load_A_Register(1): | |
1486 | offset = M_Offset_G1_Load_A; | |
1487 | break; | |
1488 | case G_Load_B_Register(0): | |
1489 | offset = M_Offset_G0_Load_B; | |
1490 | break; | |
1491 | case G_Load_B_Register(1): | |
1492 | offset = M_Offset_G1_Load_B; | |
1493 | break; | |
1494 | default: | |
5f74ea14 | 1495 | printk("%s: bug! unhandled register=0x%x in switch.\n", |
0a85b6f0 | 1496 | __func__, reg); |
c4beb34e DS |
1497 | BUG(); |
1498 | return; | |
1499 | break; | |
1500 | } | |
1501 | ni_writel(data, offset); | |
1502 | } | |
1503 | ||
da91b269 | 1504 | static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg) |
c4beb34e DS |
1505 | { |
1506 | unsigned offset; | |
1507 | switch (reg) { | |
1508 | case G_HW_Save_Register(0): | |
1509 | offset = M_Offset_G0_HW_Save; | |
1510 | break; | |
1511 | case G_HW_Save_Register(1): | |
1512 | offset = M_Offset_G1_HW_Save; | |
1513 | break; | |
1514 | case G_Save_Register(0): | |
1515 | offset = M_Offset_G0_Save; | |
1516 | break; | |
1517 | case G_Save_Register(1): | |
1518 | offset = M_Offset_G1_Save; | |
1519 | break; | |
1520 | default: | |
5f74ea14 | 1521 | printk("%s: bug! unhandled register=0x%x in switch.\n", |
0a85b6f0 | 1522 | __func__, reg); |
c4beb34e DS |
1523 | BUG(); |
1524 | return 0; | |
1525 | break; | |
1526 | } | |
1527 | return ni_readl(offset); | |
1528 | } | |
1529 | ||
1530 | #define interrupt_pin(a) 0 | |
1531 | #define IRQ_POLARITY 1 | |
1532 | ||
1533 | #define NI_E_IRQ_FLAGS IRQF_SHARED | |
1534 | ||
1535 | #include "ni_mio_common.c" | |
1536 | ||
da91b269 | 1537 | static int pcimio_find_device(struct comedi_device *dev, int bus, int slot); |
0a85b6f0 MT |
1538 | static int pcimio_ai_change(struct comedi_device *dev, |
1539 | struct comedi_subdevice *s, unsigned long new_size); | |
1540 | static int pcimio_ao_change(struct comedi_device *dev, | |
1541 | struct comedi_subdevice *s, unsigned long new_size); | |
1542 | static int pcimio_gpct0_change(struct comedi_device *dev, | |
1543 | struct comedi_subdevice *s, | |
1544 | unsigned long new_size); | |
1545 | static int pcimio_gpct1_change(struct comedi_device *dev, | |
1546 | struct comedi_subdevice *s, | |
1547 | unsigned long new_size); | |
1548 | static int pcimio_dio_change(struct comedi_device *dev, | |
1549 | struct comedi_subdevice *s, | |
1550 | unsigned long new_size); | |
c4beb34e | 1551 | |
da91b269 | 1552 | static void m_series_init_eeprom_buffer(struct comedi_device *dev) |
c4beb34e DS |
1553 | { |
1554 | static const int Start_Cal_EEPROM = 0x400; | |
1555 | static const unsigned window_size = 10; | |
f8db88ef FMH |
1556 | static const int serial_number_eeprom_offset = 0x4; |
1557 | static const int serial_number_eeprom_length = 0x4; | |
c4beb34e DS |
1558 | unsigned old_iodwbsr_bits; |
1559 | unsigned old_iodwbsr1_bits; | |
1560 | unsigned old_iodwcr1_bits; | |
1561 | int i; | |
1562 | ||
1563 | old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR); | |
1564 | old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1); | |
1565 | old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1); | |
1566 | writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR); | |
1567 | writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr), | |
0a85b6f0 MT |
1568 | devpriv->mite->mite_io_addr + MITE_IODWBSR_1); |
1569 | writel(0x1 | old_iodwcr1_bits, | |
1570 | devpriv->mite->mite_io_addr + MITE_IODWCR_1); | |
c4beb34e DS |
1571 | writel(0xf, devpriv->mite->mite_io_addr + 0x30); |
1572 | ||
f8db88ef FMH |
1573 | BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number)); |
1574 | for (i = 0; i < serial_number_eeprom_length; ++i) { | |
0a85b6f0 | 1575 | char *byte_ptr = (char *)&devpriv->serial_number + i; |
f8db88ef FMH |
1576 | *byte_ptr = ni_readb(serial_number_eeprom_offset + i); |
1577 | } | |
1578 | devpriv->serial_number = be32_to_cpu(devpriv->serial_number); | |
1579 | ||
c4beb34e DS |
1580 | for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) { |
1581 | devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i); | |
1582 | } | |
1583 | ||
1584 | writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1); | |
1585 | writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR); | |
1586 | writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1); | |
1587 | writel(0x0, devpriv->mite->mite_io_addr + 0x30); | |
1588 | } | |
1589 | ||
da91b269 | 1590 | static void init_6143(struct comedi_device *dev) |
c4beb34e | 1591 | { |
2696fb57 | 1592 | /* Disable interrupts */ |
c4beb34e DS |
1593 | devpriv->stc_writew(dev, 0, Interrupt_Control_Register); |
1594 | ||
2696fb57 BP |
1595 | /* Initialise 6143 AI specific bits */ |
1596 | ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */ | |
1597 | ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */ | |
1598 | ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */ | |
c4beb34e | 1599 | |
2696fb57 | 1600 | ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Set the FIFO half full level */ |
c4beb34e | 1601 | |
2696fb57 | 1602 | /* Strobe Relay disable bit */ |
c4beb34e DS |
1603 | devpriv->ai_calib_source_enabled = 0; |
1604 | ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff, | |
0a85b6f0 | 1605 | Calibration_Channel_6143); |
c4beb34e DS |
1606 | ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143); |
1607 | } | |
1608 | ||
1609 | /* cleans up allocated resources */ | |
da91b269 | 1610 | static int pcimio_detach(struct comedi_device *dev) |
c4beb34e DS |
1611 | { |
1612 | mio_common_detach(dev); | |
1613 | if (dev->irq) { | |
5f74ea14 | 1614 | free_irq(dev->irq, dev); |
c4beb34e DS |
1615 | } |
1616 | if (dev->private) { | |
1617 | mite_free_ring(devpriv->ai_mite_ring); | |
1618 | mite_free_ring(devpriv->ao_mite_ring); | |
1619 | mite_free_ring(devpriv->cdo_mite_ring); | |
1620 | mite_free_ring(devpriv->gpct_mite_ring[0]); | |
1621 | mite_free_ring(devpriv->gpct_mite_ring[1]); | |
1622 | if (devpriv->mite) | |
1623 | mite_unsetup(devpriv->mite); | |
1624 | } | |
1625 | ||
1626 | return 0; | |
1627 | } | |
1628 | ||
da91b269 | 1629 | static int pcimio_attach(struct comedi_device *dev, struct comedi_devconfig *it) |
c4beb34e DS |
1630 | { |
1631 | int ret; | |
1632 | ||
1633 | printk("comedi%d: ni_pcimio:", dev->minor); | |
1634 | ||
1635 | ret = ni_alloc_private(dev); | |
1636 | if (ret < 0) | |
1637 | return ret; | |
1638 | ||
1639 | ret = pcimio_find_device(dev, it->options[0], it->options[1]); | |
1640 | if (ret < 0) | |
1641 | return ret; | |
1642 | ||
1643 | printk(" %s", boardtype.name); | |
1644 | dev->board_name = boardtype.name; | |
1645 | ||
1646 | if (boardtype.reg_type & ni_reg_m_series_mask) { | |
1647 | devpriv->stc_writew = &m_series_stc_writew; | |
1648 | devpriv->stc_readw = &m_series_stc_readw; | |
1649 | devpriv->stc_writel = &m_series_stc_writel; | |
1650 | devpriv->stc_readl = &m_series_stc_readl; | |
1651 | } else { | |
1652 | devpriv->stc_writew = &e_series_win_out; | |
1653 | devpriv->stc_readw = &e_series_win_in; | |
1654 | devpriv->stc_writel = &win_out2; | |
1655 | devpriv->stc_readl = &win_in2; | |
1656 | } | |
1657 | ||
1658 | ret = mite_setup(devpriv->mite); | |
1659 | if (ret < 0) { | |
1660 | printk(" error setting up mite\n"); | |
1661 | return ret; | |
1662 | } | |
1663 | comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev); | |
1664 | devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite); | |
1665 | if (devpriv->ai_mite_ring == NULL) | |
1666 | return -ENOMEM; | |
1667 | devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite); | |
1668 | if (devpriv->ao_mite_ring == NULL) | |
1669 | return -ENOMEM; | |
1670 | devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite); | |
1671 | if (devpriv->cdo_mite_ring == NULL) | |
1672 | return -ENOMEM; | |
1673 | devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite); | |
1674 | if (devpriv->gpct_mite_ring[0] == NULL) | |
1675 | return -ENOMEM; | |
1676 | devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite); | |
1677 | if (devpriv->gpct_mite_ring[1] == NULL) | |
1678 | return -ENOMEM; | |
1679 | ||
1680 | if (boardtype.reg_type & ni_reg_m_series_mask) | |
1681 | m_series_init_eeprom_buffer(dev); | |
1682 | if (boardtype.reg_type == ni_reg_6143) | |
1683 | init_6143(dev); | |
1684 | ||
1685 | dev->irq = mite_irq(devpriv->mite); | |
1686 | ||
1687 | if (dev->irq == 0) { | |
1688 | printk(" unknown irq (bad)\n"); | |
1689 | } else { | |
1690 | printk(" ( irq = %u )", dev->irq); | |
5f74ea14 GKH |
1691 | ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS, |
1692 | DRV_NAME, dev); | |
c3744138 | 1693 | if (ret < 0) { |
c4beb34e DS |
1694 | printk(" irq not available\n"); |
1695 | dev->irq = 0; | |
1696 | } | |
1697 | } | |
1698 | ||
1699 | ret = ni_E_init(dev, it); | |
1700 | if (ret < 0) | |
1701 | return ret; | |
1702 | ||
1703 | dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change; | |
1704 | dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change; | |
1705 | dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change; | |
1706 | dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change; | |
1707 | dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change; | |
1708 | ||
1709 | return ret; | |
1710 | } | |
1711 | ||
da91b269 | 1712 | static int pcimio_find_device(struct comedi_device *dev, int bus, int slot) |
c4beb34e DS |
1713 | { |
1714 | struct mite_struct *mite; | |
1715 | int i; | |
1716 | ||
1717 | for (mite = mite_devices; mite; mite = mite->next) { | |
1718 | if (mite->used) | |
1719 | continue; | |
1720 | if (bus || slot) { | |
1721 | if (bus != mite->pcidev->bus->number || | |
0a85b6f0 | 1722 | slot != PCI_SLOT(mite->pcidev->devfn)) |
c4beb34e DS |
1723 | continue; |
1724 | } | |
1725 | ||
1726 | for (i = 0; i < n_pcimio_boards; i++) { | |
1727 | if (mite_device_id(mite) == ni_boards[i].device_id) { | |
1728 | dev->board_ptr = ni_boards + i; | |
1729 | devpriv->mite = mite; | |
1730 | ||
1731 | return 0; | |
1732 | } | |
1733 | } | |
1734 | } | |
1735 | printk("no device found\n"); | |
1736 | mite_list_devices(); | |
1737 | return -EIO; | |
1738 | } | |
1739 | ||
0a85b6f0 MT |
1740 | static int pcimio_ai_change(struct comedi_device *dev, |
1741 | struct comedi_subdevice *s, unsigned long new_size) | |
c4beb34e DS |
1742 | { |
1743 | int ret; | |
1744 | ||
1745 | ret = mite_buf_change(devpriv->ai_mite_ring, s->async); | |
1746 | if (ret < 0) | |
1747 | return ret; | |
1748 | ||
1749 | return 0; | |
1750 | } | |
1751 | ||
0a85b6f0 MT |
1752 | static int pcimio_ao_change(struct comedi_device *dev, |
1753 | struct comedi_subdevice *s, unsigned long new_size) | |
c4beb34e DS |
1754 | { |
1755 | int ret; | |
1756 | ||
1757 | ret = mite_buf_change(devpriv->ao_mite_ring, s->async); | |
1758 | if (ret < 0) | |
1759 | return ret; | |
1760 | ||
1761 | return 0; | |
1762 | } | |
1763 | ||
0a85b6f0 MT |
1764 | static int pcimio_gpct0_change(struct comedi_device *dev, |
1765 | struct comedi_subdevice *s, | |
1766 | unsigned long new_size) | |
c4beb34e DS |
1767 | { |
1768 | int ret; | |
1769 | ||
1770 | ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async); | |
1771 | if (ret < 0) | |
1772 | return ret; | |
1773 | ||
1774 | return 0; | |
1775 | } | |
1776 | ||
0a85b6f0 MT |
1777 | static int pcimio_gpct1_change(struct comedi_device *dev, |
1778 | struct comedi_subdevice *s, | |
1779 | unsigned long new_size) | |
c4beb34e DS |
1780 | { |
1781 | int ret; | |
1782 | ||
1783 | ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async); | |
1784 | if (ret < 0) | |
1785 | return ret; | |
1786 | ||
1787 | return 0; | |
1788 | } | |
1789 | ||
0a85b6f0 MT |
1790 | static int pcimio_dio_change(struct comedi_device *dev, |
1791 | struct comedi_subdevice *s, unsigned long new_size) | |
c4beb34e DS |
1792 | { |
1793 | int ret; | |
1794 | ||
1795 | ret = mite_buf_change(devpriv->cdo_mite_ring, s->async); | |
1796 | if (ret < 0) | |
1797 | return ret; | |
1798 | ||
1799 | return 0; | |
1800 | } |