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3d9f0739 | 1 | /* |
9880d313 HS |
2 | * comedi/drivers/rtd520.c |
3 | * Comedi driver for Real Time Devices (RTD) PCI4520/DM7520 | |
4 | * | |
5 | * COMEDI - Linux Control and Measurement Device Interface | |
6 | * Copyright (C) 2001 David A. Schleef <ds@schleef.org> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
9880d313 | 17 | */ |
3d9f0739 | 18 | |
3d9f0739 | 19 | /* |
9880d313 HS |
20 | * Driver: rtd520 |
21 | * Description: Real Time Devices PCI4520/DM7520 | |
9c3ac117 IA |
22 | * Devices: [Real Time Devices] DM7520HR-1 (DM7520), DM7520HR-8, |
23 | * PCI4520 (PCI4520), PCI4520-8 | |
9880d313 HS |
24 | * Author: Dan Christian |
25 | * Status: Works. Only tested on DM7520-8. Not SMP safe. | |
26 | * | |
27 | * Configuration options: not applicable, uses PCI auto config | |
28 | */ | |
3d9f0739 | 29 | |
3d9f0739 | 30 | /* |
9880d313 HS |
31 | * Created by Dan Christian, NASA Ames Research Center. |
32 | * | |
33 | * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card. | |
34 | * Both have: | |
35 | * 8/16 12 bit ADC with FIFO and channel gain table | |
36 | * 8 bits high speed digital out (for external MUX) (or 8 in or 8 out) | |
37 | * 8 bits high speed digital in with FIFO and interrupt on change (or 8 IO) | |
38 | * 2 12 bit DACs with FIFOs | |
39 | * 2 bits output | |
40 | * 2 bits input | |
41 | * bus mastering DMA | |
42 | * timers: ADC sample, pacer, burst, about, delay, DA1, DA2 | |
43 | * sample counter | |
44 | * 3 user timer/counters (8254) | |
45 | * external interrupt | |
46 | * | |
47 | * The DM7520 has slightly fewer features (fewer gain steps). | |
48 | * | |
49 | * These boards can support external multiplexors and multi-board | |
50 | * synchronization, but this driver doesn't support that. | |
51 | * | |
52 | * Board docs: http://www.rtdusa.com/PC104/DM/analog%20IO/dm7520.htm | |
53 | * Data sheet: http://www.rtdusa.com/pdf/dm7520.pdf | |
54 | * Example source: http://www.rtdusa.com/examples/dm/dm7520.zip | |
55 | * Call them and ask for the register level manual. | |
56 | * PCI chip: http://www.plxtech.com/products/io/pci9080 | |
57 | * | |
58 | * Notes: | |
59 | * This board is memory mapped. There is some IO stuff, but it isn't needed. | |
60 | * | |
61 | * I use a pretty loose naming style within the driver (rtd_blah). | |
62 | * All externally visible names should be rtd520_blah. | |
63 | * I use camelCase for structures (and inside them). | |
64 | * I may also use upper CamelCase for function names (old habit). | |
65 | * | |
66 | * This board is somewhat related to the RTD PCI4400 board. | |
67 | * | |
68 | * I borrowed heavily from the ni_mio_common, ni_atmio16d, mite, and | |
69 | * das1800, since they have the best documented code. Driver cb_pcidas64.c | |
70 | * uses the same DMA controller. | |
71 | * | |
72 | * As far as I can tell, the About interrupt doesn't work if Sample is | |
73 | * also enabled. It turns out that About really isn't needed, since | |
74 | * we always count down samples read. | |
75 | * | |
76 | * There was some timer/counter code, but it didn't follow the right API. | |
77 | */ | |
3d9f0739 DC |
78 | |
79 | /* | |
9880d313 HS |
80 | * driver status: |
81 | * | |
82 | * Analog-In supports instruction and command mode. | |
83 | * | |
84 | * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2 | |
85 | * (single channel, 64K read buffer). I get random system lockups when | |
86 | * using DMA with ALI-15xx based systems. I haven't been able to test | |
87 | * any other chipsets. The lockups happen soon after the start of an | |
88 | * acquistion, not in the middle of a long run. | |
89 | * | |
90 | * Without DMA, you can do 620Khz sampling with 20% idle on a 400Mhz K6-2 | |
91 | * (with a 256K read buffer). | |
92 | * | |
93 | * Digital-IO and Analog-Out only support instruction mode. | |
94 | */ | |
3d9f0739 | 95 | |
ce157f80 | 96 | #include <linux/module.h> |
3d9f0739 | 97 | #include <linux/delay.h> |
33782dd5 | 98 | #include <linux/interrupt.h> |
3d9f0739 | 99 | |
9fca154c | 100 | #include "../comedi_pci.h" |
3d9f0739 | 101 | |
fe559c02 | 102 | #include "plx9080.h" |
27020ffe | 103 | |
f88bb22f HS |
104 | /* |
105 | * Local Address Space 0 Offsets | |
106 | */ | |
107 | #define LAS0_USER_IO 0x0008 /* User I/O */ | |
108 | #define LAS0_ADC 0x0010 /* FIFO Status/Software A/D Start */ | |
109 | #define FS_DAC1_NOT_EMPTY (1 << 0) /* DAC1 FIFO not empty */ | |
110 | #define FS_DAC1_HEMPTY (1 << 1) /* DAC1 FIFO half empty */ | |
111 | #define FS_DAC1_NOT_FULL (1 << 2) /* DAC1 FIFO not full */ | |
112 | #define FS_DAC2_NOT_EMPTY (1 << 4) /* DAC2 FIFO not empty */ | |
113 | #define FS_DAC2_HEMPTY (1 << 5) /* DAC2 FIFO half empty */ | |
114 | #define FS_DAC2_NOT_FULL (1 << 6) /* DAC2 FIFO not full */ | |
115 | #define FS_ADC_NOT_EMPTY (1 << 8) /* ADC FIFO not empty */ | |
116 | #define FS_ADC_HEMPTY (1 << 9) /* ADC FIFO half empty */ | |
117 | #define FS_ADC_NOT_FULL (1 << 10) /* ADC FIFO not full */ | |
118 | #define FS_DIN_NOT_EMPTY (1 << 12) /* DIN FIFO not empty */ | |
119 | #define FS_DIN_HEMPTY (1 << 13) /* DIN FIFO half empty */ | |
120 | #define FS_DIN_NOT_FULL (1 << 14) /* DIN FIFO not full */ | |
121 | #define LAS0_DAC1 0x0014 /* Software D/A1 Update (w) */ | |
122 | #define LAS0_DAC2 0x0018 /* Software D/A2 Update (w) */ | |
123 | #define LAS0_DAC 0x0024 /* Software Simultaneous Update (w) */ | |
124 | #define LAS0_PACER 0x0028 /* Software Pacer Start/Stop */ | |
125 | #define LAS0_TIMER 0x002c /* Timer Status/HDIN Software Trig. */ | |
126 | #define LAS0_IT 0x0030 /* Interrupt Status/Enable */ | |
127 | #define IRQM_ADC_FIFO_WRITE (1 << 0) /* ADC FIFO Write */ | |
128 | #define IRQM_CGT_RESET (1 << 1) /* Reset CGT */ | |
129 | #define IRQM_CGT_PAUSE (1 << 3) /* Pause CGT */ | |
130 | #define IRQM_ADC_ABOUT_CNT (1 << 4) /* About Counter out */ | |
131 | #define IRQM_ADC_DELAY_CNT (1 << 5) /* Delay Counter out */ | |
132 | #define IRQM_ADC_SAMPLE_CNT (1 << 6) /* ADC Sample Counter */ | |
133 | #define IRQM_DAC1_UCNT (1 << 7) /* DAC1 Update Counter */ | |
134 | #define IRQM_DAC2_UCNT (1 << 8) /* DAC2 Update Counter */ | |
135 | #define IRQM_UTC1 (1 << 9) /* User TC1 out */ | |
136 | #define IRQM_UTC1_INV (1 << 10) /* User TC1 out, inverted */ | |
137 | #define IRQM_UTC2 (1 << 11) /* User TC2 out */ | |
138 | #define IRQM_DIGITAL_IT (1 << 12) /* Digital Interrupt */ | |
139 | #define IRQM_EXTERNAL_IT (1 << 13) /* External Interrupt */ | |
140 | #define IRQM_ETRIG_RISING (1 << 14) /* Ext Trigger rising-edge */ | |
141 | #define IRQM_ETRIG_FALLING (1 << 15) /* Ext Trigger falling-edge */ | |
142 | #define LAS0_CLEAR 0x0034 /* Clear/Set Interrupt Clear Mask */ | |
143 | #define LAS0_OVERRUN 0x0038 /* Pending interrupts/Clear Overrun */ | |
144 | #define LAS0_PCLK 0x0040 /* Pacer Clock (24bit) */ | |
145 | #define LAS0_BCLK 0x0044 /* Burst Clock (10bit) */ | |
146 | #define LAS0_ADC_SCNT 0x0048 /* A/D Sample counter (10bit) */ | |
147 | #define LAS0_DAC1_UCNT 0x004c /* D/A1 Update counter (10 bit) */ | |
148 | #define LAS0_DAC2_UCNT 0x0050 /* D/A2 Update counter (10 bit) */ | |
149 | #define LAS0_DCNT 0x0054 /* Delay counter (16 bit) */ | |
150 | #define LAS0_ACNT 0x0058 /* About counter (16 bit) */ | |
151 | #define LAS0_DAC_CLK 0x005c /* DAC clock (16bit) */ | |
152 | #define LAS0_UTC0 0x0060 /* 8254 TC Counter 0 */ | |
153 | #define LAS0_UTC1 0x0064 /* 8254 TC Counter 1 */ | |
154 | #define LAS0_UTC2 0x0068 /* 8254 TC Counter 2 */ | |
155 | #define LAS0_UTC_CTRL 0x006c /* 8254 TC Control */ | |
156 | #define LAS0_DIO0 0x0070 /* Digital I/O Port 0 */ | |
157 | #define LAS0_DIO1 0x0074 /* Digital I/O Port 1 */ | |
158 | #define LAS0_DIO0_CTRL 0x0078 /* Digital I/O Control */ | |
159 | #define LAS0_DIO_STATUS 0x007c /* Digital I/O Status */ | |
160 | #define LAS0_BOARD_RESET 0x0100 /* Board reset */ | |
161 | #define LAS0_DMA0_SRC 0x0104 /* DMA 0 Sources select */ | |
162 | #define LAS0_DMA1_SRC 0x0108 /* DMA 1 Sources select */ | |
163 | #define LAS0_ADC_CONVERSION 0x010c /* A/D Conversion Signal select */ | |
164 | #define LAS0_BURST_START 0x0110 /* Burst Clock Start Trigger select */ | |
165 | #define LAS0_PACER_START 0x0114 /* Pacer Clock Start Trigger select */ | |
166 | #define LAS0_PACER_STOP 0x0118 /* Pacer Clock Stop Trigger select */ | |
167 | #define LAS0_ACNT_STOP_ENABLE 0x011c /* About Counter Stop Enable */ | |
168 | #define LAS0_PACER_REPEAT 0x0120 /* Pacer Start Trigger Mode select */ | |
169 | #define LAS0_DIN_START 0x0124 /* HiSpd DI Sampling Signal select */ | |
170 | #define LAS0_DIN_FIFO_CLEAR 0x0128 /* Digital Input FIFO Clear */ | |
171 | #define LAS0_ADC_FIFO_CLEAR 0x012c /* A/D FIFO Clear */ | |
172 | #define LAS0_CGT_WRITE 0x0130 /* Channel Gain Table Write */ | |
173 | #define LAS0_CGL_WRITE 0x0134 /* Channel Gain Latch Write */ | |
174 | #define LAS0_CG_DATA 0x0138 /* Digital Table Write */ | |
175 | #define LAS0_CGT_ENABLE 0x013c /* Channel Gain Table Enable */ | |
176 | #define LAS0_CG_ENABLE 0x0140 /* Digital Table Enable */ | |
177 | #define LAS0_CGT_PAUSE 0x0144 /* Table Pause Enable */ | |
178 | #define LAS0_CGT_RESET 0x0148 /* Reset Channel Gain Table */ | |
179 | #define LAS0_CGT_CLEAR 0x014c /* Clear Channel Gain Table */ | |
180 | #define LAS0_DAC1_CTRL 0x0150 /* D/A1 output type/range */ | |
181 | #define LAS0_DAC1_SRC 0x0154 /* D/A1 update source */ | |
182 | #define LAS0_DAC1_CYCLE 0x0158 /* D/A1 cycle mode */ | |
183 | #define LAS0_DAC1_RESET 0x015c /* D/A1 FIFO reset */ | |
184 | #define LAS0_DAC1_FIFO_CLEAR 0x0160 /* D/A1 FIFO clear */ | |
185 | #define LAS0_DAC2_CTRL 0x0164 /* D/A2 output type/range */ | |
186 | #define LAS0_DAC2_SRC 0x0168 /* D/A2 update source */ | |
187 | #define LAS0_DAC2_CYCLE 0x016c /* D/A2 cycle mode */ | |
188 | #define LAS0_DAC2_RESET 0x0170 /* D/A2 FIFO reset */ | |
189 | #define LAS0_DAC2_FIFO_CLEAR 0x0174 /* D/A2 FIFO clear */ | |
190 | #define LAS0_ADC_SCNT_SRC 0x0178 /* A/D Sample Counter Source select */ | |
191 | #define LAS0_PACER_SELECT 0x0180 /* Pacer Clock select */ | |
192 | #define LAS0_SBUS0_SRC 0x0184 /* SyncBus 0 Source select */ | |
193 | #define LAS0_SBUS0_ENABLE 0x0188 /* SyncBus 0 enable */ | |
194 | #define LAS0_SBUS1_SRC 0x018c /* SyncBus 1 Source select */ | |
195 | #define LAS0_SBUS1_ENABLE 0x0190 /* SyncBus 1 enable */ | |
196 | #define LAS0_SBUS2_SRC 0x0198 /* SyncBus 2 Source select */ | |
197 | #define LAS0_SBUS2_ENABLE 0x019c /* SyncBus 2 enable */ | |
198 | #define LAS0_ETRG_POLARITY 0x01a4 /* Ext. Trigger polarity select */ | |
199 | #define LAS0_EINT_POLARITY 0x01a8 /* Ext. Interrupt polarity select */ | |
200 | #define LAS0_UTC0_CLOCK 0x01ac /* UTC0 Clock select */ | |
201 | #define LAS0_UTC0_GATE 0x01b0 /* UTC0 Gate select */ | |
202 | #define LAS0_UTC1_CLOCK 0x01b4 /* UTC1 Clock select */ | |
203 | #define LAS0_UTC1_GATE 0x01b8 /* UTC1 Gate select */ | |
204 | #define LAS0_UTC2_CLOCK 0x01bc /* UTC2 Clock select */ | |
205 | #define LAS0_UTC2_GATE 0x01c0 /* UTC2 Gate select */ | |
206 | #define LAS0_UOUT0_SELECT 0x01c4 /* User Output 0 source select */ | |
207 | #define LAS0_UOUT1_SELECT 0x01c8 /* User Output 1 source select */ | |
208 | #define LAS0_DMA0_RESET 0x01cc /* DMA0 Request state machine reset */ | |
209 | #define LAS0_DMA1_RESET 0x01d0 /* DMA1 Request state machine reset */ | |
210 | ||
211 | /* | |
212 | * Local Address Space 1 Offsets | |
213 | */ | |
214 | #define LAS1_ADC_FIFO 0x0000 /* A/D FIFO (16bit) */ | |
215 | #define LAS1_HDIO_FIFO 0x0004 /* HiSpd DI FIFO (16bit) */ | |
216 | #define LAS1_DAC1_FIFO 0x0008 /* D/A1 FIFO (16bit) */ | |
217 | #define LAS1_DAC2_FIFO 0x000c /* D/A2 FIFO (16bit) */ | |
218 | ||
3d9f0739 DC |
219 | /*====================================================================== |
220 | Driver specific stuff (tunable) | |
221 | ======================================================================*/ | |
3d9f0739 DC |
222 | |
223 | /* We really only need 2 buffers. More than that means being much | |
224 | smarter about knowing which ones are full. */ | |
225 | #define DMA_CHAIN_COUNT 2 /* max DMA segments/buffers in a ring (min 2) */ | |
226 | ||
227 | /* Target period for periodic transfers. This sets the user read latency. */ | |
228 | /* Note: There are certain rates where we give this up and transfer 1/2 FIFO */ | |
229 | /* If this is too low, efficiency is poor */ | |
230 | #define TRANS_TARGET_PERIOD 10000000 /* 10 ms (in nanoseconds) */ | |
231 | ||
232 | /* Set a practical limit on how long a list to support (affects memory use) */ | |
233 | /* The board support a channel list up to the FIFO length (1K or 8K) */ | |
234 | #define RTD_MAX_CHANLIST 128 /* max channel list that we allow */ | |
235 | ||
3d9f0739 DC |
236 | /*====================================================================== |
237 | Board specific stuff | |
238 | ======================================================================*/ | |
239 | ||
3d9f0739 DC |
240 | #define RTD_CLOCK_RATE 8000000 /* 8Mhz onboard clock */ |
241 | #define RTD_CLOCK_BASE 125 /* clock period in ns */ | |
242 | ||
243 | /* Note: these speed are slower than the spec, but fit the counter resolution*/ | |
244 | #define RTD_MAX_SPEED 1625 /* when sampling, in nanoseconds */ | |
245 | /* max speed if we don't have to wait for settling */ | |
246 | #define RTD_MAX_SPEED_1 875 /* if single channel, in nanoseconds */ | |
247 | ||
248 | #define RTD_MIN_SPEED 2097151875 /* (24bit counter) in nanoseconds */ | |
249 | /* min speed when only 1 channel (no burst counter) */ | |
250 | #define RTD_MIN_SPEED_1 5000000 /* 200Hz, in nanoseconds */ | |
251 | ||
3d9f0739 DC |
252 | /* Setup continuous ring of 1/2 FIFO transfers. See RTD manual p91 */ |
253 | #define DMA_MODE_BITS (\ | |
254 | PLX_LOCAL_BUS_16_WIDE_BITS \ | |
255 | | PLX_DMA_EN_READYIN_BIT \ | |
256 | | PLX_DMA_LOCAL_BURST_EN_BIT \ | |
257 | | PLX_EN_CHAIN_BIT \ | |
258 | | PLX_DMA_INTR_PCI_BIT \ | |
259 | | PLX_LOCAL_ADDR_CONST_BIT \ | |
260 | | PLX_DEMAND_MODE_BIT) | |
261 | ||
262 | #define DMA_TRANSFER_BITS (\ | |
6e882d47 | 263 | /* descriptors in PCI memory*/ PLX_DESC_IN_PCI_BIT \ |
3d9f0739 DC |
264 | /* interrupt at end of block */ | PLX_INTR_TERM_COUNT \ |
265 | /* from board to PCI */ | PLX_XFER_LOCAL_TO_PCI) | |
266 | ||
267 | /*====================================================================== | |
268 | Comedi specific stuff | |
269 | ======================================================================*/ | |
270 | ||
271 | /* | |
feb153f3 HS |
272 | * The board has 3 input modes and the gains of 1,2,4,...32 (, 64, 128) |
273 | */ | |
274 | static const struct comedi_lrange rtd_ai_7520_range = { | |
275 | 18, { | |
276 | /* +-5V input range gain steps */ | |
277 | BIP_RANGE(5.0), | |
278 | BIP_RANGE(5.0 / 2), | |
279 | BIP_RANGE(5.0 / 4), | |
280 | BIP_RANGE(5.0 / 8), | |
281 | BIP_RANGE(5.0 / 16), | |
282 | BIP_RANGE(5.0 / 32), | |
283 | /* +-10V input range gain steps */ | |
284 | BIP_RANGE(10.0), | |
285 | BIP_RANGE(10.0 / 2), | |
286 | BIP_RANGE(10.0 / 4), | |
287 | BIP_RANGE(10.0 / 8), | |
288 | BIP_RANGE(10.0 / 16), | |
289 | BIP_RANGE(10.0 / 32), | |
290 | /* +10V input range gain steps */ | |
291 | UNI_RANGE(10.0), | |
292 | UNI_RANGE(10.0 / 2), | |
293 | UNI_RANGE(10.0 / 4), | |
294 | UNI_RANGE(10.0 / 8), | |
295 | UNI_RANGE(10.0 / 16), | |
296 | UNI_RANGE(10.0 / 32), | |
297 | } | |
3d9f0739 DC |
298 | }; |
299 | ||
300 | /* PCI4520 has two more gains (6 more entries) */ | |
feb153f3 HS |
301 | static const struct comedi_lrange rtd_ai_4520_range = { |
302 | 24, { | |
303 | /* +-5V input range gain steps */ | |
304 | BIP_RANGE(5.0), | |
305 | BIP_RANGE(5.0 / 2), | |
306 | BIP_RANGE(5.0 / 4), | |
307 | BIP_RANGE(5.0 / 8), | |
308 | BIP_RANGE(5.0 / 16), | |
309 | BIP_RANGE(5.0 / 32), | |
310 | BIP_RANGE(5.0 / 64), | |
311 | BIP_RANGE(5.0 / 128), | |
312 | /* +-10V input range gain steps */ | |
313 | BIP_RANGE(10.0), | |
314 | BIP_RANGE(10.0 / 2), | |
315 | BIP_RANGE(10.0 / 4), | |
316 | BIP_RANGE(10.0 / 8), | |
317 | BIP_RANGE(10.0 / 16), | |
318 | BIP_RANGE(10.0 / 32), | |
319 | BIP_RANGE(10.0 / 64), | |
320 | BIP_RANGE(10.0 / 128), | |
321 | /* +10V input range gain steps */ | |
322 | UNI_RANGE(10.0), | |
323 | UNI_RANGE(10.0 / 2), | |
324 | UNI_RANGE(10.0 / 4), | |
325 | UNI_RANGE(10.0 / 8), | |
326 | UNI_RANGE(10.0 / 16), | |
327 | UNI_RANGE(10.0 / 32), | |
328 | UNI_RANGE(10.0 / 64), | |
329 | UNI_RANGE(10.0 / 128), | |
330 | } | |
3d9f0739 DC |
331 | }; |
332 | ||
333 | /* Table order matches range values */ | |
feb153f3 HS |
334 | static const struct comedi_lrange rtd_ao_range = { |
335 | 4, { | |
336 | UNI_RANGE(5), | |
337 | UNI_RANGE(10), | |
338 | BIP_RANGE(5), | |
339 | BIP_RANGE(10), | |
340 | } | |
3d9f0739 DC |
341 | }; |
342 | ||
b3322d42 HS |
343 | enum rtd_boardid { |
344 | BOARD_DM7520, | |
345 | BOARD_PCI4520, | |
346 | }; | |
347 | ||
dcc2358f | 348 | struct rtd_boardinfo { |
3cdefc92 | 349 | const char *name; |
dcc2358f HS |
350 | int range_bip10; /* start of +-10V range */ |
351 | int range_uni10; /* start of +10V range */ | |
8a799460 | 352 | const struct comedi_lrange *ai_range; |
d80235ce | 353 | }; |
3d9f0739 | 354 | |
dcc2358f | 355 | static const struct rtd_boardinfo rtd520Boards[] = { |
b3322d42 | 356 | [BOARD_DM7520] = { |
3cdefc92 | 357 | .name = "DM7520", |
dcc2358f HS |
358 | .range_bip10 = 6, |
359 | .range_uni10 = 12, | |
8a799460 | 360 | .ai_range = &rtd_ai_7520_range, |
b3322d42 HS |
361 | }, |
362 | [BOARD_PCI4520] = { | |
3cdefc92 | 363 | .name = "PCI4520", |
dcc2358f HS |
364 | .range_bip10 = 8, |
365 | .range_uni10 = 16, | |
8a799460 | 366 | .ai_range = &rtd_ai_4520_range, |
3cdefc92 | 367 | }, |
3d9f0739 DC |
368 | }; |
369 | ||
4686a0e6 | 370 | struct rtd_private { |
3d9f0739 | 371 | /* memory mapped board structures */ |
54fe68a8 HS |
372 | void __iomem *las1; |
373 | void __iomem *lcfg; | |
3d9f0739 | 374 | |
8bc1bd1f | 375 | long ai_count; /* total transfer size (samples) */ |
2d7b8b94 | 376 | int xfer_count; /* # to transfer data. 0->1/2FIFO */ |
3d9f0739 | 377 | int flags; /* flag event modes */ |
cd5e2d06 | 378 | unsigned fifosz; |
d80235ce | 379 | }; |
3d9f0739 DC |
380 | |
381 | /* bit defines for "flags" */ | |
382 | #define SEND_EOS 0x01 /* send End Of Scan events */ | |
383 | #define DMA0_ACTIVE 0x02 /* DMA0 is active */ | |
384 | #define DMA1_ACTIVE 0x04 /* DMA1 is active */ | |
385 | ||
5bb196ad | 386 | /* |
c98d90fd HS |
387 | Given a desired period and the clock period (both in ns), |
388 | return the proper counter value (divider-1). | |
389 | Sets the original period to be the true value. | |
390 | Note: you have to check if the value is larger than the counter range! | |
391 | */ | |
3ff20ef3 | 392 | static int rtd_ns_to_timer_base(unsigned int *nanosec, |
a207c12f | 393 | unsigned int flags, int base) |
3ff20ef3 | 394 | { |
c98d90fd HS |
395 | int divider; |
396 | ||
2ed2182e IA |
397 | switch (flags & CMDF_ROUND_MASK) { |
398 | case CMDF_ROUND_NEAREST: | |
c98d90fd HS |
399 | default: |
400 | divider = (*nanosec + base / 2) / base; | |
401 | break; | |
2ed2182e | 402 | case CMDF_ROUND_DOWN: |
c98d90fd HS |
403 | divider = (*nanosec) / base; |
404 | break; | |
2ed2182e | 405 | case CMDF_ROUND_UP: |
c98d90fd HS |
406 | divider = (*nanosec + base - 1) / base; |
407 | break; | |
408 | } | |
409 | if (divider < 2) | |
410 | divider = 2; /* min is divide by 2 */ | |
411 | ||
412 | /* Note: we don't check for max, because different timers | |
413 | have different ranges */ | |
414 | ||
415 | *nanosec = base * divider; | |
416 | return divider - 1; /* countdown is divisor+1 */ | |
417 | } | |
3d9f0739 DC |
418 | |
419 | /* | |
c98d90fd HS |
420 | Given a desired period (in ns), |
421 | return the proper counter value (divider-1) for the internal clock. | |
422 | Sets the original period to be the true value. | |
423 | */ | |
a207c12f | 424 | static int rtd_ns_to_timer(unsigned int *ns, unsigned int flags) |
c98d90fd | 425 | { |
a207c12f | 426 | return rtd_ns_to_timer_base(ns, flags, RTD_CLOCK_BASE); |
c98d90fd | 427 | } |
3d9f0739 | 428 | |
c98d90fd HS |
429 | /* |
430 | Convert a single comedi channel-gain entry to a RTD520 table entry | |
431 | */ | |
b0ae4368 HS |
432 | static unsigned short rtd_convert_chan_gain(struct comedi_device *dev, |
433 | unsigned int chanspec, int index) | |
434 | { | |
3afadfa5 | 435 | const struct rtd_boardinfo *board = dev->board_ptr; |
b0ae4368 HS |
436 | unsigned int chan = CR_CHAN(chanspec); |
437 | unsigned int range = CR_RANGE(chanspec); | |
438 | unsigned int aref = CR_AREF(chanspec); | |
c98d90fd | 439 | unsigned short r = 0; |
3d9f0739 | 440 | |
c98d90fd | 441 | r |= chan & 0xf; |
3d9f0739 | 442 | |
c98d90fd | 443 | /* Note: we also setup the channel list bipolar flag array */ |
e9e7023c | 444 | if (range < board->range_bip10) { |
3ff20ef3 HS |
445 | /* +-5 range */ |
446 | r |= 0x000; | |
447 | r |= (range & 0x7) << 4; | |
e9e7023c | 448 | } else if (range < board->range_uni10) { |
3ff20ef3 HS |
449 | /* +-10 range */ |
450 | r |= 0x100; | |
e9e7023c | 451 | r |= ((range - board->range_bip10) & 0x7) << 4; |
3ff20ef3 HS |
452 | } else { |
453 | /* +10 range */ | |
454 | r |= 0x200; | |
e9e7023c | 455 | r |= ((range - board->range_uni10) & 0x7) << 4; |
c98d90fd | 456 | } |
3d9f0739 | 457 | |
c98d90fd HS |
458 | switch (aref) { |
459 | case AREF_GROUND: /* on-board ground */ | |
460 | break; | |
461 | ||
462 | case AREF_COMMON: | |
463 | r |= 0x80; /* ref external analog common */ | |
464 | break; | |
465 | ||
466 | case AREF_DIFF: | |
467 | r |= 0x400; /* differential inputs */ | |
468 | break; | |
469 | ||
470 | case AREF_OTHER: /* ??? */ | |
471 | break; | |
472 | } | |
c98d90fd HS |
473 | return r; |
474 | } | |
475 | ||
476 | /* | |
477 | Setup the channel-gain table from a comedi list | |
478 | */ | |
479 | static void rtd_load_channelgain_list(struct comedi_device *dev, | |
480 | unsigned int n_chan, unsigned int *list) | |
481 | { | |
482 | if (n_chan > 1) { /* setup channel gain table */ | |
483 | int ii; | |
67e50c6c | 484 | |
c5930d66 HS |
485 | writel(0, dev->mmio + LAS0_CGT_CLEAR); |
486 | writel(1, dev->mmio + LAS0_CGT_ENABLE); | |
c98d90fd | 487 | for (ii = 0; ii < n_chan; ii++) { |
b0ae4368 | 488 | writel(rtd_convert_chan_gain(dev, list[ii], ii), |
c5930d66 | 489 | dev->mmio + LAS0_CGT_WRITE); |
3d9f0739 | 490 | } |
c98d90fd | 491 | } else { /* just use the channel gain latch */ |
c5930d66 | 492 | writel(0, dev->mmio + LAS0_CGT_ENABLE); |
b0ae4368 | 493 | writel(rtd_convert_chan_gain(dev, list[0], 0), |
c5930d66 | 494 | dev->mmio + LAS0_CGL_WRITE); |
3d9f0739 | 495 | } |
c98d90fd HS |
496 | } |
497 | ||
498 | /* determine fifo size by doing adc conversions until the fifo half | |
499 | empty status flag clears */ | |
500 | static int rtd520_probe_fifo_depth(struct comedi_device *dev) | |
501 | { | |
502 | unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND); | |
503 | unsigned i; | |
504 | static const unsigned limit = 0x2000; | |
505 | unsigned fifo_size = 0; | |
506 | ||
c5930d66 | 507 | writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); |
c98d90fd | 508 | rtd_load_channelgain_list(dev, 1, &chanspec); |
9a1f7223 | 509 | /* ADC conversion trigger source: SOFTWARE */ |
c5930d66 | 510 | writel(0, dev->mmio + LAS0_ADC_CONVERSION); |
c98d90fd HS |
511 | /* convert samples */ |
512 | for (i = 0; i < limit; ++i) { | |
513 | unsigned fifo_status; | |
514 | /* trigger conversion */ | |
c5930d66 | 515 | writew(0, dev->mmio + LAS0_ADC); |
c98d90fd | 516 | udelay(1); |
c5930d66 | 517 | fifo_status = readl(dev->mmio + LAS0_ADC); |
c98d90fd HS |
518 | if ((fifo_status & FS_ADC_HEMPTY) == 0) { |
519 | fifo_size = 2 * i; | |
520 | break; | |
3d9f0739 | 521 | } |
c98d90fd HS |
522 | } |
523 | if (i == limit) { | |
4370e80f | 524 | dev_info(dev->class_dev, "failed to probe fifo size.\n"); |
3d9f0739 DC |
525 | return -EIO; |
526 | } | |
c5930d66 | 527 | writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); |
c98d90fd | 528 | if (fifo_size != 0x400 && fifo_size != 0x2000) { |
4370e80f YT |
529 | dev_info(dev->class_dev, |
530 | "unexpected fifo size of %i, expected 1024 or 8192.\n", | |
531 | fifo_size); | |
c98d90fd | 532 | return -EIO; |
3d9f0739 | 533 | } |
c98d90fd HS |
534 | return fifo_size; |
535 | } | |
3d9f0739 | 536 | |
051448c5 HS |
537 | static int rtd_ai_eoc(struct comedi_device *dev, |
538 | struct comedi_subdevice *s, | |
539 | struct comedi_insn *insn, | |
540 | unsigned long context) | |
541 | { | |
051448c5 HS |
542 | unsigned int status; |
543 | ||
c5930d66 | 544 | status = readl(dev->mmio + LAS0_ADC); |
051448c5 HS |
545 | if (status & FS_ADC_NOT_EMPTY) |
546 | return 0; | |
547 | return -EBUSY; | |
548 | } | |
bc8bf90a | 549 | |
c98d90fd HS |
550 | static int rtd_ai_rinsn(struct comedi_device *dev, |
551 | struct comedi_subdevice *s, struct comedi_insn *insn, | |
552 | unsigned int *data) | |
553 | { | |
4686a0e6 | 554 | struct rtd_private *devpriv = dev->private; |
c234566f | 555 | unsigned int range = CR_RANGE(insn->chanspec); |
051448c5 HS |
556 | int ret; |
557 | int n; | |
3d9f0739 | 558 | |
c98d90fd | 559 | /* clear any old fifo data */ |
c5930d66 | 560 | writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); |
3d9f0739 | 561 | |
c98d90fd HS |
562 | /* write channel to multiplexer and clear channel gain table */ |
563 | rtd_load_channelgain_list(dev, 1, &insn->chanspec); | |
3d9f0739 | 564 | |
9a1f7223 | 565 | /* ADC conversion trigger source: SOFTWARE */ |
c5930d66 | 566 | writel(0, dev->mmio + LAS0_ADC_CONVERSION); |
3d9f0739 | 567 | |
c98d90fd HS |
568 | /* convert n samples */ |
569 | for (n = 0; n < insn->n; n++) { | |
055a1e2c | 570 | unsigned short d; |
c98d90fd | 571 | /* trigger conversion */ |
c5930d66 | 572 | writew(0, dev->mmio + LAS0_ADC); |
c98d90fd | 573 | |
051448c5 HS |
574 | ret = comedi_timeout(dev, s, insn, rtd_ai_eoc, 0); |
575 | if (ret) | |
576 | return ret; | |
c98d90fd HS |
577 | |
578 | /* read data */ | |
d2e1aebe | 579 | d = readw(devpriv->las1 + LAS1_ADC_FIFO); |
f559108b | 580 | d >>= 3; /* low 3 bits are marker lines */ |
c234566f HS |
581 | |
582 | /* convert bipolar data to comedi unsigned data */ | |
583 | if (comedi_range_is_bipolar(s, range)) | |
055a1e2c | 584 | d = comedi_offset_munge(s, d); |
c234566f | 585 | |
055a1e2c | 586 | data[n] = d & s->maxdata; |
3d9f0739 DC |
587 | } |
588 | ||
c98d90fd HS |
589 | /* return the number of samples read/written */ |
590 | return n; | |
591 | } | |
3d9f0739 | 592 | |
c98d90fd HS |
593 | /* |
594 | Get what we know is there.... Fast! | |
595 | This uses 1/2 the bus cycles of read_dregs (below). | |
bc8bf90a | 596 | |
c98d90fd HS |
597 | The manual claims that we can do a lword read, but it doesn't work here. |
598 | */ | |
599 | static int ai_read_n(struct comedi_device *dev, struct comedi_subdevice *s, | |
600 | int count) | |
601 | { | |
4686a0e6 | 602 | struct rtd_private *devpriv = dev->private; |
0c8c1c0a HS |
603 | struct comedi_async *async = s->async; |
604 | struct comedi_cmd *cmd = &async->cmd; | |
c98d90fd | 605 | int ii; |
3d9f0739 | 606 | |
c98d90fd | 607 | for (ii = 0; ii < count; ii++) { |
c234566f | 608 | unsigned int range = CR_RANGE(cmd->chanlist[async->cur_chan]); |
055a1e2c | 609 | unsigned short d; |
bc8bf90a | 610 | |
8bc1bd1f | 611 | if (0 == devpriv->ai_count) { /* done */ |
d2e1aebe | 612 | d = readw(devpriv->las1 + LAS1_ADC_FIFO); |
c98d90fd HS |
613 | continue; |
614 | } | |
3d9f0739 | 615 | |
5133f127 | 616 | d = readw(devpriv->las1 + LAS1_ADC_FIFO); |
f559108b | 617 | d >>= 3; /* low 3 bits are marker lines */ |
c234566f HS |
618 | |
619 | /* convert bipolar data to comedi unsigned data */ | |
620 | if (comedi_range_is_bipolar(s, range)) | |
055a1e2c IA |
621 | d = comedi_offset_munge(s, d); |
622 | d &= s->maxdata; | |
3d9f0739 | 623 | |
5023a4bb | 624 | if (!comedi_buf_write_samples(s, &d, 1)) |
c98d90fd | 625 | return -1; |
3d9f0739 | 626 | |
8bc1bd1f HS |
627 | if (devpriv->ai_count > 0) /* < 0, means read forever */ |
628 | devpriv->ai_count--; | |
c98d90fd HS |
629 | } |
630 | return 0; | |
631 | } | |
3d9f0739 | 632 | |
c98d90fd HS |
633 | /* |
634 | Handle all rtd520 interrupts. | |
635 | Runs atomically and is never re-entered. | |
636 | This is a "slow handler"; other interrupts may be active. | |
637 | The data conversion may someday happen in a "bottom half". | |
638 | */ | |
2f021034 HS |
639 | static irqreturn_t rtd_interrupt(int irq, void *d) |
640 | { | |
f782a255 | 641 | struct comedi_device *dev = d; |
9eba3a27 | 642 | struct comedi_subdevice *s = dev->read_subdev; |
4686a0e6 | 643 | struct rtd_private *devpriv = dev->private; |
4c977b86 | 644 | u32 overrun; |
c98d90fd | 645 | u16 status; |
2f021034 | 646 | u16 fifo_status; |
bc8bf90a | 647 | |
c98d90fd HS |
648 | if (!dev->attached) |
649 | return IRQ_NONE; | |
bc8bf90a | 650 | |
c5930d66 | 651 | fifo_status = readl(dev->mmio + LAS0_ADC); |
c98d90fd | 652 | /* check for FIFO full, this automatically halts the ADC! */ |
2f021034 HS |
653 | if (!(fifo_status & FS_ADC_NOT_FULL)) /* 0 -> full */ |
654 | goto xfer_abort; | |
c98d90fd | 655 | |
c5930d66 | 656 | status = readw(dev->mmio + LAS0_IT); |
c98d90fd HS |
657 | /* if interrupt was not caused by our board, or handled above */ |
658 | if (0 == status) | |
659 | return IRQ_HANDLED; | |
660 | ||
661 | if (status & IRQM_ADC_ABOUT_CNT) { /* sample count -> read FIFO */ | |
3ff20ef3 HS |
662 | /* |
663 | * since the priority interrupt controller may have queued | |
664 | * a sample counter interrupt, even though we have already | |
665 | * finished, we must handle the possibility that there is | |
666 | * no data here | |
667 | */ | |
2f021034 | 668 | if (!(fifo_status & FS_ADC_HEMPTY)) { |
3ff20ef3 | 669 | /* FIFO half full */ |
cd5e2d06 | 670 | if (ai_read_n(dev, s, devpriv->fifosz / 2) < 0) |
2f021034 | 671 | goto xfer_abort; |
d62bc468 | 672 | |
8bc1bd1f | 673 | if (0 == devpriv->ai_count) |
2f021034 | 674 | goto xfer_done; |
2d7b8b94 | 675 | } else if (devpriv->xfer_count > 0) { |
2f021034 | 676 | if (fifo_status & FS_ADC_NOT_EMPTY) { |
3ff20ef3 | 677 | /* FIFO not empty */ |
2d7b8b94 | 678 | if (ai_read_n(dev, s, devpriv->xfer_count) < 0) |
2f021034 | 679 | goto xfer_abort; |
d62bc468 | 680 | |
8bc1bd1f | 681 | if (0 == devpriv->ai_count) |
2f021034 | 682 | goto xfer_done; |
c98d90fd | 683 | } |
3d9f0739 DC |
684 | } |
685 | } | |
3d9f0739 | 686 | |
c5930d66 | 687 | overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff; |
d62bc468 | 688 | if (overrun) |
2f021034 | 689 | goto xfer_abort; |
3d9f0739 | 690 | |
c98d90fd | 691 | /* clear the interrupt */ |
c5930d66 HS |
692 | writew(status, dev->mmio + LAS0_CLEAR); |
693 | readw(dev->mmio + LAS0_CLEAR); | |
a708e091 HS |
694 | |
695 | comedi_handle_events(dev, s); | |
696 | ||
c98d90fd | 697 | return IRQ_HANDLED; |
3d9f0739 | 698 | |
2f021034 | 699 | xfer_abort: |
c98d90fd | 700 | s->async->events |= COMEDI_CB_ERROR; |
3d9f0739 | 701 | |
2f021034 | 702 | xfer_done: |
a708e091 | 703 | s->async->events |= COMEDI_CB_EOA; |
3d9f0739 | 704 | |
c98d90fd | 705 | /* clear the interrupt */ |
c5930d66 HS |
706 | status = readw(dev->mmio + LAS0_IT); |
707 | writew(status, dev->mmio + LAS0_CLEAR); | |
708 | readw(dev->mmio + LAS0_CLEAR); | |
3d9f0739 | 709 | |
c5930d66 HS |
710 | fifo_status = readl(dev->mmio + LAS0_ADC); |
711 | overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff; | |
c98d90fd | 712 | |
a708e091 HS |
713 | comedi_handle_events(dev, s); |
714 | ||
c98d90fd | 715 | return IRQ_HANDLED; |
3d9f0739 DC |
716 | } |
717 | ||
c98d90fd HS |
718 | /* |
719 | cmdtest tests a particular command to see if it is valid. | |
720 | Using the cmdtest ioctl, a user can create a valid cmd | |
bff6c3e0 | 721 | and then have it executed by the cmd ioctl (asynchronously). |
c98d90fd HS |
722 | |
723 | cmdtest returns 1,2,3,4 or 0, depending on which tests | |
724 | the command passes. | |
725 | */ | |
726 | ||
727 | static int rtd_ai_cmdtest(struct comedi_device *dev, | |
728 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
3d9f0739 | 729 | { |
c98d90fd | 730 | int err = 0; |
3d6a4d11 | 731 | unsigned int arg; |
3d9f0739 | 732 | |
27020ffe | 733 | /* Step 1 : check if triggers are trivially valid */ |
c98d90fd | 734 | |
57fab5a2 IA |
735 | err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW); |
736 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, | |
27020ffe | 737 | TRIG_TIMER | TRIG_EXT); |
57fab5a2 IA |
738 | err |= comedi_check_trigger_src(&cmd->convert_src, |
739 | TRIG_TIMER | TRIG_EXT); | |
740 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
741 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); | |
c98d90fd HS |
742 | |
743 | if (err) | |
744 | return 1; | |
745 | ||
27020ffe | 746 | /* Step 2a : make sure trigger sources are unique */ |
3d9f0739 | 747 | |
57fab5a2 IA |
748 | err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); |
749 | err |= comedi_check_trigger_is_unique(cmd->convert_src); | |
750 | err |= comedi_check_trigger_is_unique(cmd->stop_src); | |
27020ffe HS |
751 | |
752 | /* Step 2b : and mutually compatible */ | |
3d9f0739 | 753 | |
c98d90fd HS |
754 | if (err) |
755 | return 2; | |
3d9f0739 | 756 | |
8a2b08ec | 757 | /* Step 3: check if arguments are trivially valid */ |
3d9f0739 | 758 | |
57fab5a2 | 759 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
3d9f0739 | 760 | |
c98d90fd HS |
761 | if (cmd->scan_begin_src == TRIG_TIMER) { |
762 | /* Note: these are time periods, not actual rates */ | |
763 | if (1 == cmd->chanlist_len) { /* no scanning */ | |
57fab5a2 IA |
764 | if (comedi_check_trigger_arg_min(&cmd->scan_begin_arg, |
765 | RTD_MAX_SPEED_1)) { | |
c98d90fd | 766 | rtd_ns_to_timer(&cmd->scan_begin_arg, |
2ed2182e | 767 | CMDF_ROUND_UP); |
8a2b08ec | 768 | err |= -EINVAL; |
c98d90fd | 769 | } |
57fab5a2 IA |
770 | if (comedi_check_trigger_arg_max(&cmd->scan_begin_arg, |
771 | RTD_MIN_SPEED_1)) { | |
c98d90fd | 772 | rtd_ns_to_timer(&cmd->scan_begin_arg, |
2ed2182e | 773 | CMDF_ROUND_DOWN); |
8a2b08ec | 774 | err |= -EINVAL; |
c98d90fd HS |
775 | } |
776 | } else { | |
57fab5a2 IA |
777 | if (comedi_check_trigger_arg_min(&cmd->scan_begin_arg, |
778 | RTD_MAX_SPEED)) { | |
c98d90fd | 779 | rtd_ns_to_timer(&cmd->scan_begin_arg, |
2ed2182e | 780 | CMDF_ROUND_UP); |
8a2b08ec | 781 | err |= -EINVAL; |
c98d90fd | 782 | } |
57fab5a2 IA |
783 | if (comedi_check_trigger_arg_max(&cmd->scan_begin_arg, |
784 | RTD_MIN_SPEED)) { | |
c98d90fd | 785 | rtd_ns_to_timer(&cmd->scan_begin_arg, |
2ed2182e | 786 | CMDF_ROUND_DOWN); |
8a2b08ec | 787 | err |= -EINVAL; |
c98d90fd | 788 | } |
3d9f0739 | 789 | } |
c98d90fd HS |
790 | } else { |
791 | /* external trigger */ | |
792 | /* should be level/edge, hi/lo specification here */ | |
793 | /* should specify multiple external triggers */ | |
57fab5a2 | 794 | err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9); |
c98d90fd | 795 | } |
8a2b08ec | 796 | |
c98d90fd HS |
797 | if (cmd->convert_src == TRIG_TIMER) { |
798 | if (1 == cmd->chanlist_len) { /* no scanning */ | |
57fab5a2 IA |
799 | if (comedi_check_trigger_arg_min(&cmd->convert_arg, |
800 | RTD_MAX_SPEED_1)) { | |
c98d90fd | 801 | rtd_ns_to_timer(&cmd->convert_arg, |
2ed2182e | 802 | CMDF_ROUND_UP); |
8a2b08ec | 803 | err |= -EINVAL; |
c98d90fd | 804 | } |
57fab5a2 IA |
805 | if (comedi_check_trigger_arg_max(&cmd->convert_arg, |
806 | RTD_MIN_SPEED_1)) { | |
c98d90fd | 807 | rtd_ns_to_timer(&cmd->convert_arg, |
2ed2182e | 808 | CMDF_ROUND_DOWN); |
8a2b08ec | 809 | err |= -EINVAL; |
c98d90fd HS |
810 | } |
811 | } else { | |
57fab5a2 IA |
812 | if (comedi_check_trigger_arg_min(&cmd->convert_arg, |
813 | RTD_MAX_SPEED)) { | |
c98d90fd | 814 | rtd_ns_to_timer(&cmd->convert_arg, |
2ed2182e | 815 | CMDF_ROUND_UP); |
8a2b08ec | 816 | err |= -EINVAL; |
c98d90fd | 817 | } |
57fab5a2 IA |
818 | if (comedi_check_trigger_arg_max(&cmd->convert_arg, |
819 | RTD_MIN_SPEED)) { | |
c98d90fd | 820 | rtd_ns_to_timer(&cmd->convert_arg, |
2ed2182e | 821 | CMDF_ROUND_DOWN); |
8a2b08ec | 822 | err |= -EINVAL; |
c98d90fd HS |
823 | } |
824 | } | |
825 | } else { | |
826 | /* external trigger */ | |
827 | /* see above */ | |
57fab5a2 | 828 | err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 9); |
c98d90fd HS |
829 | } |
830 | ||
57fab5a2 IA |
831 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
832 | cmd->chanlist_len); | |
f50cebb9 | 833 | |
8c602c49 | 834 | if (cmd->stop_src == TRIG_COUNT) |
57fab5a2 | 835 | err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); |
8c602c49 | 836 | else /* TRIG_NONE */ |
57fab5a2 | 837 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
bc8bf90a | 838 | |
c98d90fd HS |
839 | if (err) |
840 | return 3; | |
3d9f0739 | 841 | |
c98d90fd HS |
842 | /* step 4: fix up any arguments */ |
843 | ||
c98d90fd | 844 | if (cmd->scan_begin_src == TRIG_TIMER) { |
3d6a4d11 | 845 | arg = cmd->scan_begin_arg; |
a207c12f | 846 | rtd_ns_to_timer(&arg, cmd->flags); |
57fab5a2 | 847 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg); |
c98d90fd | 848 | } |
3d6a4d11 | 849 | |
c98d90fd | 850 | if (cmd->convert_src == TRIG_TIMER) { |
3d6a4d11 | 851 | arg = cmd->convert_arg; |
a207c12f | 852 | rtd_ns_to_timer(&arg, cmd->flags); |
57fab5a2 | 853 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg); |
3d6a4d11 HS |
854 | |
855 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
856 | arg = cmd->convert_arg * cmd->scan_end_arg; | |
57fab5a2 IA |
857 | err |= comedi_check_trigger_arg_min(&cmd-> |
858 | scan_begin_arg, | |
859 | arg); | |
3d9f0739 | 860 | } |
c98d90fd | 861 | } |
3d9f0739 | 862 | |
c98d90fd HS |
863 | if (err) |
864 | return 4; | |
3d9f0739 | 865 | |
3d9f0739 DC |
866 | return 0; |
867 | } | |
868 | ||
3d9f0739 | 869 | /* |
c98d90fd HS |
870 | Execute a analog in command with many possible triggering options. |
871 | The data get stored in the async structure of the subdevice. | |
872 | This is usually done by an interrupt handler. | |
873 | Userland gets to the data using read calls. | |
3d9f0739 | 874 | */ |
c98d90fd HS |
875 | static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
876 | { | |
4686a0e6 | 877 | struct rtd_private *devpriv = dev->private; |
c98d90fd HS |
878 | struct comedi_cmd *cmd = &s->async->cmd; |
879 | int timer; | |
3d9f0739 | 880 | |
c98d90fd | 881 | /* stop anything currently running */ |
9a1f7223 | 882 | /* pacer stop source: SOFTWARE */ |
c5930d66 HS |
883 | writel(0, dev->mmio + LAS0_PACER_STOP); |
884 | writel(0, dev->mmio + LAS0_PACER); /* stop pacer */ | |
885 | writel(0, dev->mmio + LAS0_ADC_CONVERSION); | |
886 | writew(0, dev->mmio + LAS0_IT); | |
887 | writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); | |
888 | writel(0, dev->mmio + LAS0_OVERRUN); | |
3d9f0739 | 889 | |
c98d90fd HS |
890 | /* start configuration */ |
891 | /* load channel list and reset CGT */ | |
892 | rtd_load_channelgain_list(dev, cmd->chanlist_len, cmd->chanlist); | |
3d9f0739 | 893 | |
c98d90fd HS |
894 | /* setup the common case and override if needed */ |
895 | if (cmd->chanlist_len > 1) { | |
9a1f7223 | 896 | /* pacer start source: SOFTWARE */ |
c5930d66 | 897 | writel(0, dev->mmio + LAS0_PACER_START); |
9a1f7223 | 898 | /* burst trigger source: PACER */ |
c5930d66 | 899 | writel(1, dev->mmio + LAS0_BURST_START); |
9a1f7223 | 900 | /* ADC conversion trigger source: BURST */ |
c5930d66 | 901 | writel(2, dev->mmio + LAS0_ADC_CONVERSION); |
c98d90fd | 902 | } else { /* single channel */ |
9a1f7223 | 903 | /* pacer start source: SOFTWARE */ |
c5930d66 | 904 | writel(0, dev->mmio + LAS0_PACER_START); |
9a1f7223 | 905 | /* ADC conversion trigger source: PACER */ |
c5930d66 | 906 | writel(1, dev->mmio + LAS0_ADC_CONVERSION); |
3d9f0739 | 907 | } |
c5930d66 | 908 | writel((devpriv->fifosz / 2 - 1) & 0xffff, dev->mmio + LAS0_ACNT); |
c98d90fd HS |
909 | |
910 | if (TRIG_TIMER == cmd->scan_begin_src) { | |
911 | /* scan_begin_arg is in nanoseconds */ | |
912 | /* find out how many samples to wait before transferring */ | |
6681d3da | 913 | if (cmd->flags & CMDF_WAKE_EOS) { |
3ff20ef3 HS |
914 | /* |
915 | * this may generate un-sustainable interrupt rates | |
916 | * the application is responsible for doing the | |
917 | * right thing | |
918 | */ | |
2d7b8b94 | 919 | devpriv->xfer_count = cmd->chanlist_len; |
c98d90fd HS |
920 | devpriv->flags |= SEND_EOS; |
921 | } else { | |
922 | /* arrange to transfer data periodically */ | |
2d7b8b94 | 923 | devpriv->xfer_count = |
c98d90fd HS |
924 | (TRANS_TARGET_PERIOD * cmd->chanlist_len) / |
925 | cmd->scan_begin_arg; | |
2d7b8b94 | 926 | if (devpriv->xfer_count < cmd->chanlist_len) { |
c98d90fd | 927 | /* transfer after each scan (and avoid 0) */ |
2d7b8b94 | 928 | devpriv->xfer_count = cmd->chanlist_len; |
c98d90fd | 929 | } else { /* make a multiple of scan length */ |
2d7b8b94 HS |
930 | devpriv->xfer_count = |
931 | (devpriv->xfer_count + | |
c98d90fd HS |
932 | cmd->chanlist_len - 1) |
933 | / cmd->chanlist_len; | |
2d7b8b94 | 934 | devpriv->xfer_count *= cmd->chanlist_len; |
c98d90fd HS |
935 | } |
936 | devpriv->flags |= SEND_EOS; | |
937 | } | |
cd5e2d06 | 938 | if (devpriv->xfer_count >= (devpriv->fifosz / 2)) { |
c98d90fd | 939 | /* out of counter range, use 1/2 fifo instead */ |
2d7b8b94 | 940 | devpriv->xfer_count = 0; |
c98d90fd HS |
941 | devpriv->flags &= ~SEND_EOS; |
942 | } else { | |
943 | /* interrupt for each transfer */ | |
2d7b8b94 | 944 | writel((devpriv->xfer_count - 1) & 0xffff, |
c5930d66 | 945 | dev->mmio + LAS0_ACNT); |
c98d90fd | 946 | } |
c98d90fd | 947 | } else { /* unknown timing, just use 1/2 FIFO */ |
2d7b8b94 | 948 | devpriv->xfer_count = 0; |
c98d90fd | 949 | devpriv->flags &= ~SEND_EOS; |
3d9f0739 | 950 | } |
9a1f7223 | 951 | /* pacer clock source: INTERNAL 8MHz */ |
c5930d66 | 952 | writel(1, dev->mmio + LAS0_PACER_SELECT); |
9a1f7223 | 953 | /* just interrupt, don't stop */ |
c5930d66 | 954 | writel(1, dev->mmio + LAS0_ACNT_STOP_ENABLE); |
3d9f0739 | 955 | |
c98d90fd | 956 | /* BUG??? these look like enumerated values, but they are bit fields */ |
3d9f0739 | 957 | |
c98d90fd HS |
958 | /* First, setup when to stop */ |
959 | switch (cmd->stop_src) { | |
960 | case TRIG_COUNT: /* stop after N scans */ | |
8bc1bd1f | 961 | devpriv->ai_count = cmd->stop_arg * cmd->chanlist_len; |
2d7b8b94 | 962 | if ((devpriv->xfer_count > 0) |
8bc1bd1f HS |
963 | && (devpriv->xfer_count > devpriv->ai_count)) { |
964 | devpriv->xfer_count = devpriv->ai_count; | |
c98d90fd HS |
965 | } |
966 | break; | |
3d9f0739 | 967 | |
c98d90fd | 968 | case TRIG_NONE: /* stop when cancel is called */ |
8bc1bd1f | 969 | devpriv->ai_count = -1; /* read forever */ |
c98d90fd | 970 | break; |
c98d90fd HS |
971 | } |
972 | ||
973 | /* Scan timing */ | |
974 | switch (cmd->scan_begin_src) { | |
975 | case TRIG_TIMER: /* periodic scanning */ | |
976 | timer = rtd_ns_to_timer(&cmd->scan_begin_arg, | |
2ed2182e | 977 | CMDF_ROUND_NEAREST); |
c98d90fd | 978 | /* set PACER clock */ |
c5930d66 | 979 | writel(timer & 0xffffff, dev->mmio + LAS0_PCLK); |
3d9f0739 | 980 | |
c98d90fd | 981 | break; |
bc8bf90a | 982 | |
c98d90fd | 983 | case TRIG_EXT: |
9a1f7223 | 984 | /* pacer start source: EXTERNAL */ |
c5930d66 | 985 | writel(1, dev->mmio + LAS0_PACER_START); |
c98d90fd | 986 | break; |
c98d90fd | 987 | } |
3d9f0739 | 988 | |
c98d90fd HS |
989 | /* Sample timing within a scan */ |
990 | switch (cmd->convert_src) { | |
991 | case TRIG_TIMER: /* periodic */ | |
3ff20ef3 HS |
992 | if (cmd->chanlist_len > 1) { |
993 | /* only needed for multi-channel */ | |
c98d90fd | 994 | timer = rtd_ns_to_timer(&cmd->convert_arg, |
2ed2182e | 995 | CMDF_ROUND_NEAREST); |
c98d90fd | 996 | /* setup BURST clock */ |
c5930d66 | 997 | writel(timer & 0x3ff, dev->mmio + LAS0_BCLK); |
3d9f0739 | 998 | } |
3d9f0739 | 999 | |
c98d90fd | 1000 | break; |
3d9f0739 | 1001 | |
c98d90fd | 1002 | case TRIG_EXT: /* external */ |
9a1f7223 | 1003 | /* burst trigger source: EXTERNAL */ |
c5930d66 | 1004 | writel(2, dev->mmio + LAS0_BURST_START); |
c98d90fd | 1005 | break; |
3d9f0739 | 1006 | } |
c98d90fd | 1007 | /* end configuration */ |
3d9f0739 | 1008 | |
c98d90fd HS |
1009 | /* This doesn't seem to work. There is no way to clear an interrupt |
1010 | that the priority controller has queued! */ | |
c5930d66 HS |
1011 | writew(~0, dev->mmio + LAS0_CLEAR); |
1012 | readw(dev->mmio + LAS0_CLEAR); | |
3d9f0739 | 1013 | |
c98d90fd | 1014 | /* TODO: allow multiple interrupt sources */ |
b15f0277 NMG |
1015 | /* transfer every N samples */ |
1016 | writew(IRQM_ADC_ABOUT_CNT, dev->mmio + LAS0_IT); | |
3d9f0739 | 1017 | |
c98d90fd HS |
1018 | /* BUG: start_src is ASSUMED to be TRIG_NOW */ |
1019 | /* BUG? it seems like things are running before the "start" */ | |
c5930d66 | 1020 | readl(dev->mmio + LAS0_PACER); /* start pacer */ |
c98d90fd HS |
1021 | return 0; |
1022 | } | |
3d9f0739 | 1023 | |
c98d90fd HS |
1024 | /* |
1025 | Stop a running data acquisition. | |
1026 | */ | |
1027 | static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) | |
1028 | { | |
4686a0e6 | 1029 | struct rtd_private *devpriv = dev->private; |
3d9f0739 | 1030 | |
9a1f7223 | 1031 | /* pacer stop source: SOFTWARE */ |
c5930d66 HS |
1032 | writel(0, dev->mmio + LAS0_PACER_STOP); |
1033 | writel(0, dev->mmio + LAS0_PACER); /* stop pacer */ | |
1034 | writel(0, dev->mmio + LAS0_ADC_CONVERSION); | |
1035 | writew(0, dev->mmio + LAS0_IT); | |
8bc1bd1f | 1036 | devpriv->ai_count = 0; /* stop and don't transfer any more */ |
351a7bff | 1037 | writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); |
c98d90fd | 1038 | return 0; |
3d9f0739 | 1039 | } |
3d9f0739 | 1040 | |
051448c5 HS |
1041 | static int rtd_ao_eoc(struct comedi_device *dev, |
1042 | struct comedi_subdevice *s, | |
1043 | struct comedi_insn *insn, | |
1044 | unsigned long context) | |
1045 | { | |
051448c5 HS |
1046 | unsigned int chan = CR_CHAN(insn->chanspec); |
1047 | unsigned int bit = (chan == 0) ? FS_DAC1_NOT_EMPTY : FS_DAC2_NOT_EMPTY; | |
1048 | unsigned int status; | |
1049 | ||
c5930d66 | 1050 | status = readl(dev->mmio + LAS0_ADC); |
051448c5 HS |
1051 | if (status & bit) |
1052 | return 0; | |
1053 | return -EBUSY; | |
1054 | } | |
1055 | ||
c98d90fd HS |
1056 | static int rtd_ao_winsn(struct comedi_device *dev, |
1057 | struct comedi_subdevice *s, struct comedi_insn *insn, | |
1058 | unsigned int *data) | |
3d9f0739 | 1059 | { |
4686a0e6 | 1060 | struct rtd_private *devpriv = dev->private; |
c98d90fd HS |
1061 | int i; |
1062 | int chan = CR_CHAN(insn->chanspec); | |
1063 | int range = CR_RANGE(insn->chanspec); | |
051448c5 | 1064 | int ret; |
bc8bf90a | 1065 | |
c98d90fd | 1066 | /* Configure the output range (table index matches the range values) */ |
c5930d66 HS |
1067 | writew(range & 7, |
1068 | dev->mmio + ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL)); | |
3d9f0739 | 1069 | |
c98d90fd HS |
1070 | /* Writing a list of values to an AO channel is probably not |
1071 | * very useful, but that's how the interface is defined. */ | |
1072 | for (i = 0; i < insn->n; ++i) { | |
1073 | int val = data[i] << 3; | |
3d9f0739 | 1074 | |
c98d90fd | 1075 | /* VERIFY: comedi range and offset conversions */ |
bc8bf90a | 1076 | |
c98d90fd HS |
1077 | if ((range > 1) /* bipolar */ |
1078 | && (data[i] < 2048)) { | |
1079 | /* offset and sign extend */ | |
1080 | val = (((int)data[i]) - 2048) << 3; | |
1081 | } else { /* unipolor */ | |
1082 | val = data[i] << 3; | |
1083 | } | |
3d9f0739 | 1084 | |
c98d90fd | 1085 | /* a typical programming sequence */ |
5f73c718 HS |
1086 | writew(val, devpriv->las1 + |
1087 | ((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO)); | |
c5930d66 | 1088 | writew(0, dev->mmio + ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2)); |
3d9f0739 | 1089 | |
3caaf7b7 | 1090 | s->readback[chan] = data[i]; |
3d9f0739 | 1091 | |
051448c5 HS |
1092 | ret = comedi_timeout(dev, s, insn, rtd_ao_eoc, 0); |
1093 | if (ret) | |
1094 | return ret; | |
3d9f0739 DC |
1095 | } |
1096 | ||
c98d90fd HS |
1097 | /* return the number of samples read/written */ |
1098 | return i; | |
1099 | } | |
3d9f0739 | 1100 | |
c98d90fd HS |
1101 | static int rtd_dio_insn_bits(struct comedi_device *dev, |
1102 | struct comedi_subdevice *s, | |
45b6937a HS |
1103 | struct comedi_insn *insn, |
1104 | unsigned int *data) | |
c98d90fd | 1105 | { |
97f4289a | 1106 | if (comedi_dio_update_state(s, data)) |
c5930d66 | 1107 | writew(s->state & 0xff, dev->mmio + LAS0_DIO0); |
45b6937a | 1108 | |
c5930d66 | 1109 | data[1] = readw(dev->mmio + LAS0_DIO0) & 0xff; |
3d9f0739 | 1110 | |
a2714e3e | 1111 | return insn->n; |
3d9f0739 DC |
1112 | } |
1113 | ||
c98d90fd HS |
1114 | static int rtd_dio_insn_config(struct comedi_device *dev, |
1115 | struct comedi_subdevice *s, | |
efa5b326 HS |
1116 | struct comedi_insn *insn, |
1117 | unsigned int *data) | |
3d9f0739 | 1118 | { |
ddf62f2c | 1119 | int ret; |
3d9f0739 | 1120 | |
ddf62f2c HS |
1121 | ret = comedi_dio_insn_config(dev, s, insn, data, 0); |
1122 | if (ret) | |
1123 | return ret; | |
3d9f0739 | 1124 | |
c98d90fd | 1125 | /* TODO support digital match interrupts and strobes */ |
360235af HS |
1126 | |
1127 | /* set direction */ | |
c5930d66 HS |
1128 | writew(0x01, dev->mmio + LAS0_DIO_STATUS); |
1129 | writew(s->io_bits & 0xff, dev->mmio + LAS0_DIO0_CTRL); | |
360235af HS |
1130 | |
1131 | /* clear interrupts */ | |
c5930d66 | 1132 | writew(0x00, dev->mmio + LAS0_DIO_STATUS); |
3d9f0739 | 1133 | |
c98d90fd | 1134 | /* port1 can only be all input or all output */ |
3d9f0739 | 1135 | |
c98d90fd | 1136 | /* there are also 2 user input lines and 2 user output lines */ |
3d9f0739 | 1137 | |
efa5b326 | 1138 | return insn->n; |
c98d90fd | 1139 | } |
3d9f0739 | 1140 | |
09d93a18 | 1141 | static void rtd_reset(struct comedi_device *dev) |
b155c5fa | 1142 | { |
4686a0e6 | 1143 | struct rtd_private *devpriv = dev->private; |
b155c5fa | 1144 | |
c5930d66 | 1145 | writel(0, dev->mmio + LAS0_BOARD_RESET); |
b155c5fa | 1146 | udelay(100); /* needed? */ |
2fb0e849 | 1147 | writel(0, devpriv->lcfg + PLX_INTRCS_REG); |
c5930d66 HS |
1148 | writew(0, dev->mmio + LAS0_IT); |
1149 | writew(~0, dev->mmio + LAS0_CLEAR); | |
1150 | readw(dev->mmio + LAS0_CLEAR); | |
09d93a18 HS |
1151 | } |
1152 | ||
1153 | /* | |
1154 | * initialize board, per RTD spec | |
1155 | * also, initialize shadow registers | |
1156 | */ | |
1157 | static void rtd_init_board(struct comedi_device *dev) | |
1158 | { | |
09d93a18 HS |
1159 | rtd_reset(dev); |
1160 | ||
c5930d66 HS |
1161 | writel(0, dev->mmio + LAS0_OVERRUN); |
1162 | writel(0, dev->mmio + LAS0_CGT_CLEAR); | |
1163 | writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); | |
1164 | writel(0, dev->mmio + LAS0_DAC1_RESET); | |
1165 | writel(0, dev->mmio + LAS0_DAC2_RESET); | |
b155c5fa | 1166 | /* clear digital IO fifo */ |
c5930d66 HS |
1167 | writew(0, dev->mmio + LAS0_DIO_STATUS); |
1168 | writeb((0 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL); | |
1169 | writeb((1 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL); | |
1170 | writeb((2 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL); | |
1171 | writeb((3 << 6) | 0x00, dev->mmio + LAS0_UTC_CTRL); | |
b155c5fa HS |
1172 | /* TODO: set user out source ??? */ |
1173 | } | |
1174 | ||
3d7e4416 HS |
1175 | /* The RTD driver does this */ |
1176 | static void rtd_pci_latency_quirk(struct comedi_device *dev, | |
1177 | struct pci_dev *pcidev) | |
1178 | { | |
1179 | unsigned char pci_latency; | |
3d7e4416 HS |
1180 | |
1181 | pci_read_config_byte(pcidev, PCI_LATENCY_TIMER, &pci_latency); | |
1182 | if (pci_latency < 32) { | |
1183 | dev_info(dev->class_dev, | |
6c7d2c8b HS |
1184 | "PCI latency changed from %d to %d\n", |
1185 | pci_latency, 32); | |
3d7e4416 | 1186 | pci_write_config_byte(pcidev, PCI_LATENCY_TIMER, 32); |
3d7e4416 | 1187 | } |
3d7e4416 HS |
1188 | } |
1189 | ||
a690b7e5 | 1190 | static int rtd_auto_attach(struct comedi_device *dev, |
b3322d42 | 1191 | unsigned long context) |
825ca08e | 1192 | { |
5df39540 | 1193 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
e9e7023c | 1194 | const struct rtd_boardinfo *board = NULL; |
4686a0e6 | 1195 | struct rtd_private *devpriv; |
c98d90fd | 1196 | struct comedi_subdevice *s; |
c98d90fd | 1197 | int ret; |
3d9f0739 | 1198 | |
b3322d42 | 1199 | if (context < ARRAY_SIZE(rtd520Boards)) |
e9e7023c HS |
1200 | board = &rtd520Boards[context]; |
1201 | if (!board) | |
825ca08e | 1202 | return -ENODEV; |
e9e7023c HS |
1203 | dev->board_ptr = board; |
1204 | dev->board_name = board->name; | |
825ca08e | 1205 | |
0bdab509 | 1206 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
c34fa261 HS |
1207 | if (!devpriv) |
1208 | return -ENOMEM; | |
3d9f0739 | 1209 | |
818f569f | 1210 | ret = comedi_pci_enable(dev); |
edecbd06 | 1211 | if (ret) |
c98d90fd | 1212 | return ret; |
a26f4dd0 | 1213 | |
c5930d66 | 1214 | dev->mmio = pci_ioremap_bar(pcidev, 2); |
dde4196e HS |
1215 | devpriv->las1 = pci_ioremap_bar(pcidev, 3); |
1216 | devpriv->lcfg = pci_ioremap_bar(pcidev, 0); | |
c5930d66 | 1217 | if (!dev->mmio || !devpriv->las1 || !devpriv->lcfg) |
c98d90fd | 1218 | return -ENOMEM; |
3d9f0739 | 1219 | |
3d7e4416 | 1220 | rtd_pci_latency_quirk(dev, pcidev); |
3d9f0739 | 1221 | |
90973498 HS |
1222 | if (pcidev->irq) { |
1223 | ret = request_irq(pcidev->irq, rtd_interrupt, IRQF_SHARED, | |
1224 | dev->board_name, dev); | |
1225 | if (ret == 0) | |
1226 | dev->irq = pcidev->irq; | |
1227 | } | |
1228 | ||
8b6c5694 HS |
1229 | ret = comedi_alloc_subdevices(dev, 4); |
1230 | if (ret) | |
1231 | return ret; | |
3d9f0739 | 1232 | |
58f20459 | 1233 | s = &dev->subdevices[0]; |
c98d90fd | 1234 | /* analog input subdevice */ |
37f97e50 HS |
1235 | s->type = COMEDI_SUBD_AI; |
1236 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF; | |
1237 | s->n_chan = 16; | |
1238 | s->maxdata = 0x0fff; | |
e9e7023c | 1239 | s->range_table = board->ai_range; |
37f97e50 HS |
1240 | s->len_chanlist = RTD_MAX_CHANLIST; |
1241 | s->insn_read = rtd_ai_rinsn; | |
90973498 HS |
1242 | if (dev->irq) { |
1243 | dev->read_subdev = s; | |
37f97e50 HS |
1244 | s->subdev_flags |= SDF_CMD_READ; |
1245 | s->do_cmd = rtd_ai_cmd; | |
1246 | s->do_cmdtest = rtd_ai_cmdtest; | |
1247 | s->cancel = rtd_ai_cancel; | |
90973498 | 1248 | } |
3d9f0739 | 1249 | |
58f20459 | 1250 | s = &dev->subdevices[1]; |
c98d90fd | 1251 | /* analog output subdevice */ |
37f97e50 HS |
1252 | s->type = COMEDI_SUBD_AO; |
1253 | s->subdev_flags = SDF_WRITABLE; | |
1254 | s->n_chan = 2; | |
1255 | s->maxdata = 0x0fff; | |
1256 | s->range_table = &rtd_ao_range; | |
1257 | s->insn_write = rtd_ao_winsn; | |
3caaf7b7 HS |
1258 | |
1259 | ret = comedi_alloc_subdev_readback(s); | |
1260 | if (ret) | |
1261 | return ret; | |
3d9f0739 | 1262 | |
58f20459 | 1263 | s = &dev->subdevices[2]; |
c98d90fd | 1264 | /* digital i/o subdevice */ |
37f97e50 HS |
1265 | s->type = COMEDI_SUBD_DIO; |
1266 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE; | |
c98d90fd | 1267 | /* we only support port 0 right now. Ignoring port 1 and user IO */ |
37f97e50 HS |
1268 | s->n_chan = 8; |
1269 | s->maxdata = 1; | |
1270 | s->range_table = &range_digital; | |
1271 | s->insn_bits = rtd_dio_insn_bits; | |
1272 | s->insn_config = rtd_dio_insn_config; | |
3d9f0739 | 1273 | |
c98d90fd | 1274 | /* timer/counter subdevices (not currently supported) */ |
58f20459 | 1275 | s = &dev->subdevices[3]; |
37f97e50 HS |
1276 | s->type = COMEDI_SUBD_COUNTER; |
1277 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE; | |
1278 | s->n_chan = 3; | |
1279 | s->maxdata = 0xffff; | |
3d9f0739 | 1280 | |
b155c5fa | 1281 | rtd_init_board(dev); |
3d9f0739 | 1282 | |
c98d90fd HS |
1283 | ret = rtd520_probe_fifo_depth(dev); |
1284 | if (ret < 0) | |
1285 | return ret; | |
cd5e2d06 | 1286 | devpriv->fifosz = ret; |
c98d90fd | 1287 | |
a5ca9475 | 1288 | if (dev->irq) |
2fb0e849 | 1289 | writel(ICS_PIE | ICS_PLIE, devpriv->lcfg + PLX_INTRCS_REG); |
bc8bf90a | 1290 | |
edecbd06 | 1291 | return 0; |
3d9f0739 DC |
1292 | } |
1293 | ||
c98d90fd | 1294 | static void rtd_detach(struct comedi_device *dev) |
3d9f0739 | 1295 | { |
4686a0e6 | 1296 | struct rtd_private *devpriv = dev->private; |
3d9f0739 | 1297 | |
c98d90fd HS |
1298 | if (devpriv) { |
1299 | /* Shut down any board ops by resetting it */ | |
c5930d66 | 1300 | if (dev->mmio && devpriv->lcfg) |
09d93a18 | 1301 | rtd_reset(dev); |
b7d6b43b | 1302 | if (dev->irq) |
c98d90fd | 1303 | free_irq(dev->irq, dev); |
c5930d66 HS |
1304 | if (dev->mmio) |
1305 | iounmap(dev->mmio); | |
c98d90fd HS |
1306 | if (devpriv->las1) |
1307 | iounmap(devpriv->las1); | |
1308 | if (devpriv->lcfg) | |
1309 | iounmap(devpriv->lcfg); | |
843c042d | 1310 | } |
7f072f54 | 1311 | comedi_pci_disable(dev); |
3d9f0739 DC |
1312 | } |
1313 | ||
75e6301b HS |
1314 | static struct comedi_driver rtd520_driver = { |
1315 | .driver_name = "rtd520", | |
6beb8160 | 1316 | .module = THIS_MODULE, |
5df39540 | 1317 | .auto_attach = rtd_auto_attach, |
6beb8160 HS |
1318 | .detach = rtd_detach, |
1319 | }; | |
1320 | ||
a690b7e5 | 1321 | static int rtd520_pci_probe(struct pci_dev *dev, |
b8f4ac23 | 1322 | const struct pci_device_id *id) |
727b286b | 1323 | { |
b8f4ac23 | 1324 | return comedi_pci_auto_config(dev, &rtd520_driver, id->driver_data); |
727b286b AT |
1325 | } |
1326 | ||
41e043fc | 1327 | static const struct pci_device_id rtd520_pci_table[] = { |
b3322d42 HS |
1328 | { PCI_VDEVICE(RTD, 0x7520), BOARD_DM7520 }, |
1329 | { PCI_VDEVICE(RTD, 0x4520), BOARD_PCI4520 }, | |
6beb8160 HS |
1330 | { 0 } |
1331 | }; | |
1332 | MODULE_DEVICE_TABLE(pci, rtd520_pci_table); | |
1333 | ||
75e6301b HS |
1334 | static struct pci_driver rtd520_pci_driver = { |
1335 | .name = "rtd520", | |
6beb8160 | 1336 | .id_table = rtd520_pci_table, |
75e6301b | 1337 | .probe = rtd520_pci_probe, |
9901a4d7 | 1338 | .remove = comedi_pci_auto_unconfig, |
727b286b | 1339 | }; |
75e6301b | 1340 | module_comedi_pci_driver(rtd520_driver, rtd520_pci_driver); |
90f703d3 AT |
1341 | |
1342 | MODULE_AUTHOR("Comedi http://www.comedi.org"); | |
1343 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
1344 | MODULE_LICENSE("GPL"); |