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Commit | Line | Data |
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11e865c1 | 1 | /* |
7f32c7c4 IA |
2 | * comedi/drivers/s626.c |
3 | * Sensoray s626 Comedi driver | |
4 | * | |
5 | * COMEDI - Linux Control and Measurement Device Interface | |
6 | * Copyright (C) 2000 David A. Schleef <ds@schleef.org> | |
7 | * | |
8 | * Based on Sensoray Model 626 Linux driver Version 0.2 | |
9 | * Copyright (C) 2002-2004 Sensoray Co., Inc. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | */ | |
11e865c1 GP |
21 | |
22 | /* | |
7f32c7c4 IA |
23 | * Driver: s626 |
24 | * Description: Sensoray 626 driver | |
25 | * Devices: [Sensoray] 626 (s626) | |
26 | * Authors: Gianluca Palli <gpalli@deis.unibo.it>, | |
27 | * Updated: Fri, 15 Feb 2008 10:28:42 +0000 | |
28 | * Status: experimental | |
29 | ||
30 | * Configuration options: not applicable, uses PCI auto config | |
31 | ||
32 | * INSN_CONFIG instructions: | |
33 | * analog input: | |
34 | * none | |
35 | * | |
36 | * analog output: | |
37 | * none | |
38 | * | |
39 | * digital channel: | |
40 | * s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels | |
41 | * supported configuration options: | |
42 | * INSN_CONFIG_DIO_QUERY | |
43 | * COMEDI_INPUT | |
44 | * COMEDI_OUTPUT | |
45 | * | |
46 | * encoder: | |
47 | * Every channel must be configured before reading. | |
48 | * | |
49 | * Example code | |
50 | * | |
51 | * insn.insn=INSN_CONFIG; //configuration instruction | |
52 | * insn.n=1; //number of operation (must be 1) | |
53 | * insn.data=&initialvalue; //initial value loaded into encoder | |
54 | * //during configuration | |
55 | * insn.subdev=5; //encoder subdevice | |
56 | * insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel | |
57 | * //to configure | |
58 | * | |
59 | * comedi_do_insn(cf,&insn); //executing configuration | |
60 | */ | |
11e865c1 | 61 | |
ce157f80 HS |
62 | #include <linux/module.h> |
63 | #include <linux/delay.h> | |
25436dc9 | 64 | #include <linux/interrupt.h> |
11e865c1 GP |
65 | #include <linux/kernel.h> |
66 | #include <linux/types.h> | |
67 | ||
6ab38b05 | 68 | #include "../comedi_pci.h" |
11e865c1 | 69 | |
11e865c1 GP |
70 | #include "s626.h" |
71 | ||
dbb263f5 | 72 | struct s626_buffer_dma { |
8e06d662 IA |
73 | dma_addr_t physical_base; |
74 | void *logical_base; | |
75 | }; | |
76 | ||
427fda4e TH |
77 | /** |
78 | * struct s626_private - Working data for s626 driver. | |
79 | * @ai_cmd_running: non-zero if ai_cmd is running. | |
80 | * @ai_sample_timer: time between samples in units of the timer. | |
81 | * @ai_convert_count: conversion counter. | |
82 | * @ai_convert_timer: time between conversion in units of the timer. | |
83 | * @counter_int_enabs: counter interrupt enable mask for MISC2 register. | |
84 | * @adc_items: number of items in ADC poll list. | |
85 | * @rps_buf: DMA buffer used to hold ADC (RPS1) program. | |
86 | * @ana_buf: DMA buffer used to receive ADC data and hold DAC data. | |
87 | * @dac_wbuf: pointer to logical adrs of DMA buffer used to hold DAC data. | |
88 | * @dacpol: image of DAC polarity register. | |
89 | * @trim_setpoint: images of TrimDAC setpoints. | |
90 | * @i2c_adrs: I2C device address for onboard EEPROM (board rev dependent) | |
91 | */ | |
eb5e029e | 92 | struct s626_private { |
427fda4e TH |
93 | u8 ai_cmd_running; |
94 | unsigned int ai_sample_timer; | |
95 | int ai_convert_count; | |
96 | unsigned int ai_convert_timer; | |
97 | u16 counter_int_enabs; | |
98 | u8 adc_items; | |
99 | struct s626_buffer_dma rps_buf; | |
100 | struct s626_buffer_dma ana_buf; | |
101 | u32 *dac_wbuf; | |
102 | u16 dacpol; | |
103 | u8 trim_setpoint[12]; | |
104 | u32 i2c_adrs; | |
eb5e029e | 105 | }; |
11e865c1 | 106 | |
8ee52611 | 107 | /* Counter overflow/index event flag masks for RDMISC2. */ |
676921c9 IA |
108 | #define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4))) |
109 | #define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10))) | |
11e865c1 | 110 | |
ddd9813e HS |
111 | /* |
112 | * Enable/disable a function or test status bit(s) that are accessed | |
113 | * through Main Control Registers 1 or 2. | |
114 | */ | |
115 | static void s626_mc_enable(struct comedi_device *dev, | |
116 | unsigned int cmd, unsigned int reg) | |
117 | { | |
ddd9813e HS |
118 | unsigned int val = (cmd << 16) | cmd; |
119 | ||
bb49cddc | 120 | mmiowb(); |
de9cd5ca | 121 | writel(val, dev->mmio + reg); |
ddd9813e | 122 | } |
11e865c1 | 123 | |
c5cf4606 HS |
124 | static void s626_mc_disable(struct comedi_device *dev, |
125 | unsigned int cmd, unsigned int reg) | |
126 | { | |
ddd54d65 | 127 | writel(cmd << 16, dev->mmio + reg); |
bb49cddc | 128 | mmiowb(); |
c5cf4606 | 129 | } |
11e865c1 | 130 | |
95bb7982 HS |
131 | static bool s626_mc_test(struct comedi_device *dev, |
132 | unsigned int cmd, unsigned int reg) | |
133 | { | |
95bb7982 HS |
134 | unsigned int val; |
135 | ||
de9cd5ca | 136 | val = readl(dev->mmio + reg); |
95bb7982 HS |
137 | |
138 | return (val & cmd) ? true : false; | |
139 | } | |
11e865c1 | 140 | |
676921c9 | 141 | #define S626_BUGFIX_STREG(REGADRS) ((REGADRS) - 4) |
11e865c1 | 142 | |
8ee52611 | 143 | /* Write a time slot control record to TSL2. */ |
d8515652 | 144 | #define S626_VECTPORT(VECTNUM) (S626_P_TSL2 + ((VECTNUM) << 2)) |
11e865c1 | 145 | |
90d54ff2 HS |
146 | static const struct comedi_lrange s626_range_table = { |
147 | 2, { | |
148 | BIP_RANGE(5), | |
481ac510 | 149 | BIP_RANGE(10) |
90d54ff2 | 150 | } |
11e865c1 GP |
151 | }; |
152 | ||
8ee52611 IA |
153 | /* |
154 | * Execute a DEBI transfer. This must be called from within a critical section. | |
155 | */ | |
31de1948 | 156 | static void s626_debi_transfer(struct comedi_device *dev) |
6b387b70 | 157 | { |
59a32a46 CS |
158 | static const int timeout = 10000; |
159 | int i; | |
7f2f7e05 | 160 | |
ddd9813e | 161 | /* Initiate upload of shadow RAM to DEBI control register */ |
d8515652 | 162 | s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2); |
6b387b70 | 163 | |
95bb7982 HS |
164 | /* |
165 | * Wait for completion of upload from shadow RAM to | |
166 | * DEBI control register. | |
167 | */ | |
59a32a46 CS |
168 | for (i = 0; i < timeout; i++) { |
169 | if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2)) | |
170 | break; | |
171 | udelay(1); | |
172 | } | |
173 | if (i == timeout) | |
cefe9336 HS |
174 | dev_err(dev->class_dev, |
175 | "Timeout while uploading to DEBI control register\n"); | |
6b387b70 | 176 | |
be008602 | 177 | /* Wait until DEBI transfer is done */ |
59a32a46 | 178 | for (i = 0; i < timeout; i++) { |
de9cd5ca | 179 | if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S)) |
59a32a46 CS |
180 | break; |
181 | udelay(1); | |
182 | } | |
183 | if (i == timeout) | |
cefe9336 | 184 | dev_err(dev->class_dev, "DEBI transfer timeout\n"); |
6b387b70 HS |
185 | } |
186 | ||
8ee52611 IA |
187 | /* |
188 | * Read a value from a gate array register. | |
189 | */ | |
0bc45380 | 190 | static u16 s626_debi_read(struct comedi_device *dev, u16 addr) |
6b387b70 | 191 | { |
25f8fd5e | 192 | /* Set up DEBI control register value in shadow RAM */ |
de9cd5ca | 193 | writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); |
6b387b70 HS |
194 | |
195 | /* Execute the DEBI transfer. */ | |
31de1948 | 196 | s626_debi_transfer(dev); |
6b387b70 | 197 | |
de9cd5ca | 198 | return readl(dev->mmio + S626_P_DEBIAD); |
6b387b70 HS |
199 | } |
200 | ||
8ee52611 IA |
201 | /* |
202 | * Write a value to a gate array register. | |
203 | */ | |
0bc45380 SR |
204 | static void s626_debi_write(struct comedi_device *dev, u16 addr, |
205 | u16 wdata) | |
6b387b70 | 206 | { |
25f8fd5e | 207 | /* Set up DEBI control register value in shadow RAM */ |
de9cd5ca HS |
208 | writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); |
209 | writel(wdata, dev->mmio + S626_P_DEBIAD); | |
6b387b70 HS |
210 | |
211 | /* Execute the DEBI transfer. */ | |
31de1948 | 212 | s626_debi_transfer(dev); |
6b387b70 HS |
213 | } |
214 | ||
8ee52611 IA |
215 | /* |
216 | * Replace the specified bits in a gate array register. Imports: mask | |
6b387b70 HS |
217 | * specifies bits that are to be preserved, wdata is new value to be |
218 | * or'd with the masked original. | |
219 | */ | |
31de1948 IA |
220 | static void s626_debi_replace(struct comedi_device *dev, unsigned int addr, |
221 | unsigned int mask, unsigned int wdata) | |
6b387b70 | 222 | { |
be008602 | 223 | unsigned int val; |
6b387b70 | 224 | |
12f4e2f2 | 225 | addr &= 0xffff; |
de9cd5ca | 226 | writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); |
31de1948 | 227 | s626_debi_transfer(dev); |
6b387b70 | 228 | |
de9cd5ca HS |
229 | writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); |
230 | val = readl(dev->mmio + S626_P_DEBIAD); | |
be008602 HS |
231 | val &= mask; |
232 | val |= wdata; | |
de9cd5ca | 233 | writel(val & 0xffff, dev->mmio + S626_P_DEBIAD); |
31de1948 | 234 | s626_debi_transfer(dev); |
6b387b70 HS |
235 | } |
236 | ||
982e3d11 HS |
237 | /* ************** EEPROM ACCESS FUNCTIONS ************** */ |
238 | ||
571845c6 | 239 | static int s626_i2c_handshake_eoc(struct comedi_device *dev, |
6c7d2c8b HS |
240 | struct comedi_subdevice *s, |
241 | struct comedi_insn *insn, | |
242 | unsigned long context) | |
571845c6 CS |
243 | { |
244 | bool status; | |
245 | ||
246 | status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2); | |
247 | if (status) | |
248 | return 0; | |
249 | return -EBUSY; | |
250 | } | |
251 | ||
b13db6bf | 252 | static int s626_i2c_handshake(struct comedi_device *dev, u32 val) |
982e3d11 | 253 | { |
be008602 | 254 | unsigned int ctrl; |
571845c6 | 255 | int ret; |
7f2f7e05 | 256 | |
25f8fd5e | 257 | /* Write I2C command to I2C Transfer Control shadow register */ |
de9cd5ca | 258 | writel(val, dev->mmio + S626_P_I2CCTRL); |
982e3d11 | 259 | |
ddd9813e HS |
260 | /* |
261 | * Upload I2C shadow registers into working registers and | |
262 | * wait for upload confirmation. | |
263 | */ | |
d8515652 | 264 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
571845c6 CS |
265 | ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0); |
266 | if (ret) | |
267 | return ret; | |
982e3d11 | 268 | |
be008602 HS |
269 | /* Wait until I2C bus transfer is finished or an error occurs */ |
270 | do { | |
de9cd5ca | 271 | ctrl = readl(dev->mmio + S626_P_I2CCTRL); |
d8515652 | 272 | } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY); |
982e3d11 | 273 | |
be008602 | 274 | /* Return non-zero if I2C error occurred */ |
d8515652 | 275 | return ctrl & S626_I2C_ERR; |
982e3d11 HS |
276 | } |
277 | ||
d9f9600b SR |
278 | /* Read u8 from EEPROM. */ |
279 | static u8 s626_i2c_read(struct comedi_device *dev, u8 addr) | |
982e3d11 | 280 | { |
7f2f7e05 | 281 | struct s626_private *devpriv = dev->private; |
982e3d11 | 282 | |
8ee52611 IA |
283 | /* |
284 | * Send EEPROM target address: | |
285 | * Byte2 = I2C command: write to I2C EEPROM device. | |
286 | * Byte1 = EEPROM internal target address. | |
287 | * Byte0 = Not sent. | |
288 | */ | |
d8515652 IA |
289 | if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, |
290 | devpriv->i2c_adrs) | | |
291 | S626_I2C_B1(S626_I2C_ATTRSTOP, addr) | | |
292 | S626_I2C_B0(S626_I2C_ATTRNOP, 0))) | |
8ee52611 | 293 | /* Abort function and declare error if handshake failed. */ |
982e3d11 | 294 | return 0; |
982e3d11 | 295 | |
8ee52611 IA |
296 | /* |
297 | * Execute EEPROM read: | |
298 | * Byte2 = I2C command: read from I2C EEPROM device. | |
299 | * Byte1 receives uint8_t from EEPROM. | |
300 | * Byte0 = Not sent. | |
301 | */ | |
d8515652 | 302 | if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART, |
6c7d2c8b | 303 | (devpriv->i2c_adrs | 1)) | |
d8515652 IA |
304 | S626_I2C_B1(S626_I2C_ATTRSTOP, 0) | |
305 | S626_I2C_B0(S626_I2C_ATTRNOP, 0))) | |
8ee52611 | 306 | /* Abort function and declare error if handshake failed. */ |
982e3d11 | 307 | return 0; |
be008602 | 308 | |
de9cd5ca | 309 | return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff; |
982e3d11 HS |
310 | } |
311 | ||
95414729 HS |
312 | /* *********** DAC FUNCTIONS *********** */ |
313 | ||
8ee52611 | 314 | /* TrimDac LogicalChan-to-PhysicalChan mapping table. */ |
d9f9600b | 315 | static const u8 s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 }; |
95414729 | 316 | |
8ee52611 | 317 | /* TrimDac LogicalChan-to-EepromAdrs mapping table. */ |
d9f9600b | 318 | static const u8 s626_trimadrs[] = { |
8ee52611 IA |
319 | 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 |
320 | }; | |
95414729 | 321 | |
59a32a46 CS |
322 | enum { |
323 | s626_send_dac_wait_not_mc1_a2out, | |
324 | s626_send_dac_wait_ssr_af2_out, | |
325 | s626_send_dac_wait_fb_buffer2_msb_00, | |
326 | s626_send_dac_wait_fb_buffer2_msb_ff | |
327 | }; | |
328 | ||
329 | static int s626_send_dac_eoc(struct comedi_device *dev, | |
330 | struct comedi_subdevice *s, | |
331 | struct comedi_insn *insn, | |
332 | unsigned long context) | |
333 | { | |
59a32a46 CS |
334 | unsigned int status; |
335 | ||
336 | switch (context) { | |
337 | case s626_send_dac_wait_not_mc1_a2out: | |
de9cd5ca | 338 | status = readl(dev->mmio + S626_P_MC1); |
59a32a46 CS |
339 | if (!(status & S626_MC1_A2OUT)) |
340 | return 0; | |
341 | break; | |
342 | case s626_send_dac_wait_ssr_af2_out: | |
de9cd5ca | 343 | status = readl(dev->mmio + S626_P_SSR); |
59a32a46 CS |
344 | if (status & S626_SSR_AF2_OUT) |
345 | return 0; | |
346 | break; | |
347 | case s626_send_dac_wait_fb_buffer2_msb_00: | |
de9cd5ca | 348 | status = readl(dev->mmio + S626_P_FB_BUFFER2); |
59a32a46 CS |
349 | if (!(status & 0xff000000)) |
350 | return 0; | |
351 | break; | |
352 | case s626_send_dac_wait_fb_buffer2_msb_ff: | |
de9cd5ca | 353 | status = readl(dev->mmio + S626_P_FB_BUFFER2); |
59a32a46 CS |
354 | if (status & 0xff000000) |
355 | return 0; | |
356 | break; | |
357 | default: | |
358 | return -EINVAL; | |
359 | } | |
360 | return -EBUSY; | |
361 | } | |
362 | ||
8ee52611 IA |
363 | /* |
364 | * Private helper function: Transmit serial data to DAC via Audio | |
95414729 | 365 | * channel 2. Assumes: (1) TSL2 slot records initialized, and (2) |
07a36d66 | 366 | * dacpol contains valid target image. |
95414729 | 367 | */ |
b13db6bf | 368 | static int s626_send_dac(struct comedi_device *dev, u32 val) |
95414729 | 369 | { |
7f2f7e05 | 370 | struct s626_private *devpriv = dev->private; |
59a32a46 | 371 | int ret; |
95414729 HS |
372 | |
373 | /* START THE SERIAL CLOCK RUNNING ------------- */ | |
374 | ||
8ee52611 IA |
375 | /* |
376 | * Assert DAC polarity control and enable gating of DAC serial clock | |
95414729 HS |
377 | * and audio bit stream signals. At this point in time we must be |
378 | * assured of being in time slot 0. If we are not in slot 0, the | |
379 | * serial clock and audio stream signals will be disabled; this is | |
31de1948 IA |
380 | * because the following s626_debi_write statement (which enables |
381 | * signals to be passed through the gate array) would execute before | |
382 | * the trailing edge of WS1/WS3 (which turns off the signals), thus | |
95414729 HS |
383 | * causing the signals to be inactive during the DAC write. |
384 | */ | |
d8515652 | 385 | s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol); |
95414729 HS |
386 | |
387 | /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */ | |
388 | ||
389 | /* Copy DAC setpoint value to DAC's output DMA buffer. */ | |
de9cd5ca | 390 | /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */ |
07a36d66 | 391 | *devpriv->dac_wbuf = val; |
95414729 | 392 | |
ddd9813e HS |
393 | /* |
394 | * Enable the output DMA transfer. This will cause the DMAC to copy | |
395 | * the DAC's data value to A2's output FIFO. The DMA transfer will | |
95414729 HS |
396 | * then immediately terminate because the protection address is |
397 | * reached upon transfer of the first DWORD value. | |
398 | */ | |
d8515652 | 399 | s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1); |
95414729 | 400 | |
8ee52611 | 401 | /* While the DMA transfer is executing ... */ |
95414729 | 402 | |
25f8fd5e HS |
403 | /* |
404 | * Reset Audio2 output FIFO's underflow flag (along with any | |
405 | * other FIFO underflow/overflow flags). When set, this flag | |
406 | * will indicate that we have emerged from slot 0. | |
95414729 | 407 | */ |
de9cd5ca | 408 | writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR); |
95414729 | 409 | |
8ee52611 IA |
410 | /* |
411 | * Wait for the DMA transfer to finish so that there will be data | |
95414729 HS |
412 | * available in the FIFO when time slot 1 tries to transfer a DWORD |
413 | * from the FIFO to the output buffer register. We test for DMA | |
414 | * Done by polling the DMAC enable flag; this flag is automatically | |
415 | * cleared when the transfer has finished. | |
416 | */ | |
59a32a46 CS |
417 | ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc, |
418 | s626_send_dac_wait_not_mc1_a2out); | |
a7aa94ce | 419 | if (ret) { |
cefe9336 | 420 | dev_err(dev->class_dev, "DMA transfer timeout\n"); |
a7aa94ce CS |
421 | return ret; |
422 | } | |
95414729 HS |
423 | |
424 | /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */ | |
425 | ||
8ee52611 IA |
426 | /* |
427 | * FIFO data is now available, so we enable execution of time slots | |
95414729 HS |
428 | * 1 and higher by clearing the EOS flag in slot 0. Note that SD3 |
429 | * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list | |
430 | * detection. | |
431 | */ | |
d8515652 | 432 | writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2, |
de9cd5ca | 433 | dev->mmio + S626_VECTPORT(0)); |
95414729 | 434 | |
8ee52611 IA |
435 | /* |
436 | * Wait for slot 1 to execute to ensure that the Packet will be | |
95414729 HS |
437 | * transmitted. This is detected by polling the Audio2 output FIFO |
438 | * underflow flag, which will be set when slot 1 execution has | |
439 | * finished transferring the DAC's data DWORD from the output FIFO | |
440 | * to the output buffer register. | |
441 | */ | |
59a32a46 CS |
442 | ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc, |
443 | s626_send_dac_wait_ssr_af2_out); | |
a7aa94ce | 444 | if (ret) { |
cefe9336 HS |
445 | dev_err(dev->class_dev, |
446 | "TSL timeout waiting for slot 1 to execute\n"); | |
a7aa94ce CS |
447 | return ret; |
448 | } | |
95414729 | 449 | |
8ee52611 IA |
450 | /* |
451 | * Set up to trap execution at slot 0 when the TSL sequencer cycles | |
95414729 HS |
452 | * back to slot 0 after executing the EOS in slot 5. Also, |
453 | * simultaneously shift out and in the 0x00 that is ALWAYS the value | |
454 | * stored in the last byte to be shifted out of the FIFO's DWORD | |
455 | * buffer register. | |
456 | */ | |
d8515652 | 457 | writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS, |
de9cd5ca | 458 | dev->mmio + S626_VECTPORT(0)); |
95414729 HS |
459 | |
460 | /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */ | |
461 | ||
8ee52611 IA |
462 | /* |
463 | * Wait for the TSL to finish executing all time slots before | |
95414729 HS |
464 | * exiting this function. We must do this so that the next DAC |
465 | * write doesn't start, thereby enabling clock/chip select signals: | |
466 | * | |
467 | * 1. Before the TSL sequence cycles back to slot 0, which disables | |
468 | * the clock/cs signal gating and traps slot // list execution. | |
469 | * we have not yet finished slot 5 then the clock/cs signals are | |
470 | * still gated and we have not finished transmitting the stream. | |
471 | * | |
472 | * 2. While slots 2-5 are executing due to a late slot 0 trap. In | |
473 | * this case, the slot sequence is currently repeating, but with | |
474 | * clock/cs signals disabled. We must wait for slot 0 to trap | |
475 | * execution before setting up the next DAC setpoint DMA transfer | |
476 | * and enabling the clock/cs signals. To detect the end of slot 5, | |
477 | * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If | |
478 | * the TSL has not yet finished executing slot 5 ... | |
479 | */ | |
de9cd5ca | 480 | if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) { |
8ee52611 IA |
481 | /* |
482 | * The trap was set on time and we are still executing somewhere | |
95414729 HS |
483 | * in slots 2-5, so we now wait for slot 0 to execute and trap |
484 | * TSL execution. This is detected when FB_BUFFER2 MSB changes | |
485 | * from 0xFF to 0x00, which slot 0 causes to happen by shifting | |
486 | * out/in on SD2 the 0x00 that is always referenced by slot 5. | |
487 | */ | |
59a32a46 CS |
488 | ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc, |
489 | s626_send_dac_wait_fb_buffer2_msb_00); | |
a7aa94ce | 490 | if (ret) { |
cefe9336 HS |
491 | dev_err(dev->class_dev, |
492 | "TSL timeout waiting for slot 0 to execute\n"); | |
a7aa94ce CS |
493 | return ret; |
494 | } | |
95414729 | 495 | } |
8ee52611 IA |
496 | /* |
497 | * Either (1) we were too late setting the slot 0 trap; the TSL | |
95414729 HS |
498 | * sequencer restarted slot 0 before we could set the EOS trap flag, |
499 | * or (2) we were not late and execution is now trapped at slot 0. | |
500 | * In either case, we must now change slot 0 so that it will store | |
501 | * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes. | |
502 | * In order to do this, we reprogram slot 0 so that it will shift in | |
503 | * SD3, which is driven only by a pull-up resistor. | |
504 | */ | |
d8515652 | 505 | writel(S626_RSD3 | S626_SIB_A2 | S626_EOS, |
de9cd5ca | 506 | dev->mmio + S626_VECTPORT(0)); |
95414729 | 507 | |
8ee52611 IA |
508 | /* |
509 | * Wait for slot 0 to execute, at which time the TSL is setup for | |
95414729 HS |
510 | * the next DAC write. This is detected when FB_BUFFER2 MSB changes |
511 | * from 0x00 to 0xFF. | |
512 | */ | |
59a32a46 CS |
513 | ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc, |
514 | s626_send_dac_wait_fb_buffer2_msb_ff); | |
a7aa94ce | 515 | if (ret) { |
cefe9336 HS |
516 | dev_err(dev->class_dev, |
517 | "TSL timeout waiting for slot 0 to execute\n"); | |
a7aa94ce CS |
518 | return ret; |
519 | } | |
520 | return 0; | |
95414729 HS |
521 | } |
522 | ||
8ee52611 IA |
523 | /* |
524 | * Private helper function: Write setpoint to an application DAC channel. | |
525 | */ | |
6c7d2c8b | 526 | static int s626_set_dac(struct comedi_device *dev, |
0bc45380 | 527 | u16 chan, int16_t dacdata) |
95414729 | 528 | { |
7f2f7e05 | 529 | struct s626_private *devpriv = dev->private; |
0bc45380 | 530 | u16 signmask; |
b13db6bf SR |
531 | u32 ws_image; |
532 | u32 val; | |
95414729 | 533 | |
8ee52611 IA |
534 | /* |
535 | * Adjust DAC data polarity and set up Polarity Control Register image. | |
536 | */ | |
95414729 HS |
537 | signmask = 1 << chan; |
538 | if (dacdata < 0) { | |
539 | dacdata = -dacdata; | |
07a36d66 | 540 | devpriv->dacpol |= signmask; |
8ee52611 | 541 | } else { |
07a36d66 | 542 | devpriv->dacpol &= ~signmask; |
8ee52611 | 543 | } |
95414729 | 544 | |
8ee52611 | 545 | /* Limit DAC setpoint value to valid range. */ |
0bc45380 | 546 | if ((u16)dacdata > 0x1FFF) |
95414729 HS |
547 | dacdata = 0x1FFF; |
548 | ||
8ee52611 IA |
549 | /* |
550 | * Set up TSL2 records (aka "vectors") for DAC update. Vectors V2 | |
95414729 HS |
551 | * and V3 transmit the setpoint to the target DAC. V4 and V5 send |
552 | * data to a non-existent TrimDac channel just to keep the clock | |
553 | * running after sending data to the target DAC. This is necessary | |
554 | * to eliminate the clock glitch that would otherwise occur at the | |
555 | * end of the target DAC's serial data stream. When the sequence | |
556 | * restarts at V0 (after executing V5), the gate array automatically | |
557 | * disables gating for the DAC clock and all DAC chip selects. | |
558 | */ | |
559 | ||
25f8fd5e | 560 | /* Choose DAC chip select to be asserted */ |
d8515652 | 561 | ws_image = (chan & 2) ? S626_WS1 : S626_WS2; |
25f8fd5e | 562 | /* Slot 2: Transmit high data byte to target DAC */ |
d8515652 | 563 | writel(S626_XSD2 | S626_XFIFO_1 | ws_image, |
de9cd5ca | 564 | dev->mmio + S626_VECTPORT(2)); |
25f8fd5e | 565 | /* Slot 3: Transmit low data byte to target DAC */ |
d8515652 | 566 | writel(S626_XSD2 | S626_XFIFO_0 | ws_image, |
de9cd5ca | 567 | dev->mmio + S626_VECTPORT(3)); |
95414729 | 568 | /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */ |
d8515652 | 569 | writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3, |
de9cd5ca | 570 | dev->mmio + S626_VECTPORT(4)); |
25f8fd5e | 571 | /* Slot 5: running after writing target DAC's low data byte */ |
d8515652 | 572 | writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS, |
de9cd5ca | 573 | dev->mmio + S626_VECTPORT(5)); |
95414729 | 574 | |
8ee52611 IA |
575 | /* |
576 | * Construct and transmit target DAC's serial packet: | |
577 | * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>, | |
95414729 HS |
578 | * and D<12:0> is the DAC setpoint. Append a WORD value (that writes |
579 | * to a non-existent TrimDac channel) that serves to keep the clock | |
580 | * running after the packet has been sent to the target DAC. | |
581 | */ | |
8ee52611 | 582 | val = 0x0F000000; /* Continue clock after target DAC data |
3137139a | 583 | * (write to non-existent trimdac). |
584 | */ | |
8ee52611 | 585 | val |= 0x00004000; /* Address the two main dual-DAC devices |
3137139a | 586 | * (TSL's chip select enables target device). |
587 | */ | |
b13db6bf | 588 | val |= ((u32)(chan & 1) << 15); /* Address the DAC channel |
3137139a | 589 | * within the device. |
590 | */ | |
b13db6bf | 591 | val |= (u32)dacdata; /* Include DAC setpoint data. */ |
a7aa94ce | 592 | return s626_send_dac(dev, val); |
95414729 HS |
593 | } |
594 | ||
6c7d2c8b | 595 | static int s626_write_trim_dac(struct comedi_device *dev, |
d9f9600b | 596 | u8 logical_chan, u8 dac_data) |
95414729 | 597 | { |
7f2f7e05 | 598 | struct s626_private *devpriv = dev->private; |
b13db6bf | 599 | u32 chan; |
95414729 | 600 | |
8ee52611 IA |
601 | /* |
602 | * Save the new setpoint in case the application needs to read it back | |
603 | * later. | |
604 | */ | |
a2be0626 | 605 | devpriv->trim_setpoint[logical_chan] = dac_data; |
95414729 | 606 | |
8ee52611 | 607 | /* Map logical channel number to physical channel number. */ |
31de1948 | 608 | chan = s626_trimchan[logical_chan]; |
95414729 | 609 | |
8ee52611 IA |
610 | /* |
611 | * Set up TSL2 records for TrimDac write operation. All slots shift | |
95414729 HS |
612 | * 0xFF in from pulled-up SD3 so that the end of the slot sequence |
613 | * can be detected. | |
614 | */ | |
615 | ||
25f8fd5e | 616 | /* Slot 2: Send high uint8_t to target TrimDac */ |
d8515652 | 617 | writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3, |
de9cd5ca | 618 | dev->mmio + S626_VECTPORT(2)); |
25f8fd5e | 619 | /* Slot 3: Send low uint8_t to target TrimDac */ |
d8515652 | 620 | writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3, |
de9cd5ca | 621 | dev->mmio + S626_VECTPORT(3)); |
25f8fd5e | 622 | /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */ |
d8515652 | 623 | writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1, |
de9cd5ca | 624 | dev->mmio + S626_VECTPORT(4)); |
25f8fd5e | 625 | /* Slot 5: Send NOP low uint8_t to DAC0 */ |
d8515652 | 626 | writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS, |
de9cd5ca | 627 | dev->mmio + S626_VECTPORT(5)); |
95414729 | 628 | |
8ee52611 IA |
629 | /* |
630 | * Construct and transmit target DAC's serial packet: | |
631 | * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the | |
95414729 HS |
632 | * DAC channel's address, and D<7:0> is the DAC setpoint. Append a |
633 | * WORD value (that writes a channel 0 NOP command to a non-existent | |
634 | * main DAC channel) that serves to keep the clock running after the | |
635 | * packet has been sent to the target DAC. | |
636 | */ | |
637 | ||
8ee52611 IA |
638 | /* |
639 | * Address the DAC channel within the trimdac device. | |
640 | * Include DAC setpoint data. | |
641 | */ | |
a7aa94ce | 642 | return s626_send_dac(dev, (chan << 8) | dac_data); |
95414729 HS |
643 | } |
644 | ||
a7aa94ce | 645 | static int s626_load_trim_dacs(struct comedi_device *dev) |
95414729 | 646 | { |
d9f9600b | 647 | u8 i; |
a7aa94ce | 648 | int ret; |
95414729 | 649 | |
8ee52611 | 650 | /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */ |
a7aa94ce CS |
651 | for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) { |
652 | ret = s626_write_trim_dac(dev, i, | |
6c7d2c8b | 653 | s626_i2c_read(dev, s626_trimadrs[i])); |
a7aa94ce CS |
654 | if (ret) |
655 | return ret; | |
656 | } | |
657 | return 0; | |
95414729 HS |
658 | } |
659 | ||
e3eb08d0 | 660 | /* ****** COUNTER FUNCTIONS ******* */ |
8ee52611 IA |
661 | |
662 | /* | |
663 | * All counter functions address a specific counter by means of the | |
e3eb08d0 HS |
664 | * "Counter" argument, which is a logical counter number. The Counter |
665 | * argument may have any of the following legal values: 0=0A, 1=1A, | |
666 | * 2=2A, 3=0B, 4=1B, 5=2B. | |
667 | */ | |
668 | ||
8ee52611 IA |
669 | /* |
670 | * Return/set a counter pair's latch trigger source. 0: On read | |
e3eb08d0 HS |
671 | * access, 1: A index latches A, 2: B index latches B, 3: A overflow |
672 | * latches B. | |
673 | */ | |
31de1948 | 674 | static void s626_set_latch_source(struct comedi_device *dev, |
0bc45380 | 675 | unsigned int chan, u16 value) |
e3eb08d0 | 676 | { |
0c9a057c | 677 | s626_debi_replace(dev, S626_LP_CRB(chan), |
d8515652 | 678 | ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC), |
0830ada5 | 679 | S626_SET_CRB_LATCHSRC(value)); |
e3eb08d0 HS |
680 | } |
681 | ||
8ee52611 IA |
682 | /* |
683 | * Write value into counter preload register. | |
684 | */ | |
31de1948 | 685 | static void s626_preload(struct comedi_device *dev, |
b13db6bf | 686 | unsigned int chan, u32 value) |
e3eb08d0 | 687 | { |
0c9a057c HS |
688 | s626_debi_write(dev, S626_LP_CNTR(chan), value); |
689 | s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16); | |
e3eb08d0 HS |
690 | } |
691 | ||
010be96f IA |
692 | /* ****** PRIVATE COUNTER FUNCTIONS ****** */ |
693 | ||
694 | /* | |
695 | * Reset a counter's index and overflow event capture flags. | |
696 | */ | |
26499b8b | 697 | static void s626_reset_cap_flags(struct comedi_device *dev, |
0c9a057c | 698 | unsigned int chan) |
010be96f | 699 | { |
0bc45380 | 700 | u16 set; |
010be96f | 701 | |
26499b8b | 702 | set = S626_SET_CRB_INTRESETCMD(1); |
0c9a057c | 703 | if (chan < 3) |
26499b8b HS |
704 | set |= S626_SET_CRB_INTRESET_A(1); |
705 | else | |
706 | set |= S626_SET_CRB_INTRESET_B(1); | |
707 | ||
0c9a057c | 708 | s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set); |
010be96f IA |
709 | } |
710 | ||
17afeac2 IA |
711 | /* |
712 | * Set the operating mode for the specified counter. The setup | |
713 | * parameter is treated as a COUNTER_SETUP data type. The following | |
714 | * parameters are programmable (all other parms are ignored): ClkMult, | |
715 | * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc. | |
716 | */ | |
31de1948 | 717 | static void s626_set_mode_a(struct comedi_device *dev, |
0bc45380 SR |
718 | unsigned int chan, u16 setup, |
719 | u16 disable_int_src) | |
17afeac2 IA |
720 | { |
721 | struct s626_private *devpriv = dev->private; | |
0bc45380 SR |
722 | u16 cra; |
723 | u16 crb; | |
f7ede00d | 724 | unsigned int cntsrc, clkmult, clkpol; |
17afeac2 IA |
725 | |
726 | /* Initialize CRA and CRB images. */ | |
727 | /* Preload trigger is passed through. */ | |
0830ada5 | 728 | cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup)); |
2cea19fa IA |
729 | /* IndexSrc is passed through. */ |
730 | cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup)); | |
17afeac2 IA |
731 | |
732 | /* Reset any pending CounterA event captures. */ | |
0830ada5 | 733 | crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1); |
17afeac2 | 734 | /* Clock enable is passed through. */ |
0830ada5 | 735 | crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup)); |
17afeac2 IA |
736 | |
737 | /* Force IntSrc to Disabled if disable_int_src is asserted. */ | |
738 | if (!disable_int_src) | |
0830ada5 | 739 | cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup)); |
17afeac2 IA |
740 | |
741 | /* Populate all mode-dependent attributes of CRA & CRB images. */ | |
0830ada5 IA |
742 | clkpol = S626_GET_STD_CLKPOL(setup); |
743 | switch (S626_GET_STD_ENCMODE(setup)) { | |
622ec01a | 744 | case S626_ENCMODE_EXTENDER: /* Extender Mode: */ |
d8515652 | 745 | /* Force to Timer mode (Extender valid only for B counters). */ |
622ec01a IA |
746 | /* Fall through to case S626_ENCMODE_TIMER: */ |
747 | case S626_ENCMODE_TIMER: /* Timer Mode: */ | |
748 | /* CntSrcA<1> selects system clock */ | |
0830ada5 | 749 | cntsrc = S626_CNTSRC_SYSCLK; |
622ec01a | 750 | /* Count direction (CntSrcA<0>) obtained from ClkPol. */ |
0830ada5 | 751 | cntsrc |= clkpol; |
17afeac2 | 752 | /* ClkPolA behaves as always-on clock enable. */ |
0830ada5 | 753 | clkpol = 1; |
17afeac2 | 754 | /* ClkMult must be 1x. */ |
7a1046e5 | 755 | clkmult = S626_CLKMULT_1X; |
17afeac2 IA |
756 | break; |
757 | default: /* Counter Mode: */ | |
758 | /* Select ENC_C and ENC_D as clock/direction inputs. */ | |
0830ada5 | 759 | cntsrc = S626_CNTSRC_ENCODER; |
17afeac2 | 760 | /* Clock polarity is passed through. */ |
17afeac2 | 761 | /* Force multiplier to x1 if not legal, else pass through. */ |
0830ada5 | 762 | clkmult = S626_GET_STD_CLKMULT(setup); |
7a1046e5 IA |
763 | if (clkmult == S626_CLKMULT_SPECIAL) |
764 | clkmult = S626_CLKMULT_1X; | |
17afeac2 IA |
765 | break; |
766 | } | |
0830ada5 IA |
767 | cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) | |
768 | S626_SET_CRA_CLKMULT_A(clkmult); | |
17afeac2 IA |
769 | |
770 | /* | |
771 | * Force positive index polarity if IndxSrc is software-driven only, | |
772 | * otherwise pass it through. | |
773 | */ | |
2cea19fa | 774 | if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT) |
0830ada5 | 775 | cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup)); |
17afeac2 IA |
776 | |
777 | /* | |
778 | * If IntSrc has been forced to Disabled, update the MISC2 interrupt | |
779 | * enable mask to indicate the counter interrupt is disabled. | |
780 | */ | |
781 | if (disable_int_src) | |
0c9a057c HS |
782 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
783 | S626_INDXMASK(chan)); | |
17afeac2 IA |
784 | |
785 | /* | |
786 | * While retaining CounterB and LatchSrc configurations, program the | |
787 | * new counter operating mode. | |
788 | */ | |
0c9a057c | 789 | s626_debi_replace(dev, S626_LP_CRA(chan), |
622ec01a | 790 | S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra); |
0c9a057c | 791 | s626_debi_replace(dev, S626_LP_CRB(chan), |
d8515652 | 792 | ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb); |
17afeac2 IA |
793 | } |
794 | ||
31de1948 | 795 | static void s626_set_mode_b(struct comedi_device *dev, |
0bc45380 SR |
796 | unsigned int chan, u16 setup, |
797 | u16 disable_int_src) | |
17afeac2 IA |
798 | { |
799 | struct s626_private *devpriv = dev->private; | |
0bc45380 SR |
800 | u16 cra; |
801 | u16 crb; | |
f7ede00d | 802 | unsigned int cntsrc, clkmult, clkpol; |
17afeac2 IA |
803 | |
804 | /* Initialize CRA and CRB images. */ | |
2cea19fa IA |
805 | /* IndexSrc is passed through. */ |
806 | cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup)); | |
17afeac2 IA |
807 | |
808 | /* Reset event captures and disable interrupts. */ | |
0830ada5 | 809 | crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1); |
17afeac2 | 810 | /* Clock enable is passed through. */ |
0830ada5 | 811 | crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup)); |
17afeac2 | 812 | /* Preload trigger source is passed through. */ |
0830ada5 | 813 | crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup)); |
17afeac2 IA |
814 | |
815 | /* Force IntSrc to Disabled if disable_int_src is asserted. */ | |
816 | if (!disable_int_src) | |
0830ada5 | 817 | crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup)); |
17afeac2 IA |
818 | |
819 | /* Populate all mode-dependent attributes of CRA & CRB images. */ | |
0830ada5 IA |
820 | clkpol = S626_GET_STD_CLKPOL(setup); |
821 | switch (S626_GET_STD_ENCMODE(setup)) { | |
622ec01a IA |
822 | case S626_ENCMODE_TIMER: /* Timer Mode: */ |
823 | /* CntSrcB<1> selects system clock */ | |
0830ada5 | 824 | cntsrc = S626_CNTSRC_SYSCLK; |
622ec01a | 825 | /* with direction (CntSrcB<0>) obtained from ClkPol. */ |
0830ada5 | 826 | cntsrc |= clkpol; |
17afeac2 | 827 | /* ClkPolB behaves as always-on clock enable. */ |
0830ada5 | 828 | clkpol = 1; |
17afeac2 | 829 | /* ClkMultB must be 1x. */ |
7a1046e5 | 830 | clkmult = S626_CLKMULT_1X; |
17afeac2 | 831 | break; |
622ec01a IA |
832 | case S626_ENCMODE_EXTENDER: /* Extender Mode: */ |
833 | /* CntSrcB source is OverflowA (same as "timer") */ | |
0830ada5 | 834 | cntsrc = S626_CNTSRC_SYSCLK; |
17afeac2 | 835 | /* with direction obtained from ClkPol. */ |
0830ada5 | 836 | cntsrc |= clkpol; |
17afeac2 | 837 | /* ClkPolB controls IndexB -- always set to active. */ |
0830ada5 | 838 | clkpol = 1; |
17afeac2 | 839 | /* ClkMultB selects OverflowA as the clock source. */ |
7a1046e5 | 840 | clkmult = S626_CLKMULT_SPECIAL; |
17afeac2 IA |
841 | break; |
842 | default: /* Counter Mode: */ | |
843 | /* Select ENC_C and ENC_D as clock/direction inputs. */ | |
0830ada5 | 844 | cntsrc = S626_CNTSRC_ENCODER; |
17afeac2 | 845 | /* ClkPol is passed through. */ |
17afeac2 | 846 | /* Force ClkMult to x1 if not legal, otherwise pass through. */ |
0830ada5 | 847 | clkmult = S626_GET_STD_CLKMULT(setup); |
7a1046e5 IA |
848 | if (clkmult == S626_CLKMULT_SPECIAL) |
849 | clkmult = S626_CLKMULT_1X; | |
17afeac2 IA |
850 | break; |
851 | } | |
0830ada5 IA |
852 | cra |= S626_SET_CRA_CNTSRC_B(cntsrc); |
853 | crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult); | |
17afeac2 IA |
854 | |
855 | /* | |
856 | * Force positive index polarity if IndxSrc is software-driven only, | |
857 | * otherwise pass it through. | |
858 | */ | |
2cea19fa | 859 | if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT) |
0830ada5 | 860 | crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup)); |
17afeac2 IA |
861 | |
862 | /* | |
863 | * If IntSrc has been forced to Disabled, update the MISC2 interrupt | |
864 | * enable mask to indicate the counter interrupt is disabled. | |
865 | */ | |
866 | if (disable_int_src) | |
0c9a057c HS |
867 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
868 | S626_INDXMASK(chan)); | |
17afeac2 IA |
869 | |
870 | /* | |
871 | * While retaining CounterA and LatchSrc configurations, program the | |
872 | * new counter operating mode. | |
873 | */ | |
0c9a057c | 874 | s626_debi_replace(dev, S626_LP_CRA(chan), |
622ec01a | 875 | ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra); |
0c9a057c | 876 | s626_debi_replace(dev, S626_LP_CRB(chan), |
d8515652 | 877 | S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb); |
17afeac2 IA |
878 | } |
879 | ||
b35d6a38 | 880 | static void s626_set_mode(struct comedi_device *dev, |
0c9a057c | 881 | unsigned int chan, |
0bc45380 | 882 | u16 setup, u16 disable_int_src) |
b35d6a38 | 883 | { |
0c9a057c HS |
884 | if (chan < 3) |
885 | s626_set_mode_a(dev, chan, setup, disable_int_src); | |
b35d6a38 | 886 | else |
0c9a057c | 887 | s626_set_mode_b(dev, chan, setup, disable_int_src); |
b35d6a38 HS |
888 | } |
889 | ||
17afeac2 IA |
890 | /* |
891 | * Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. | |
892 | */ | |
c718f4a1 | 893 | static void s626_set_enable(struct comedi_device *dev, |
0bc45380 | 894 | unsigned int chan, u16 enab) |
17afeac2 | 895 | { |
c718f4a1 HS |
896 | unsigned int mask = S626_CRBMSK_INTCTRL; |
897 | unsigned int set; | |
17afeac2 | 898 | |
0c9a057c | 899 | if (chan < 3) { |
c718f4a1 HS |
900 | mask |= S626_CRBMSK_CLKENAB_A; |
901 | set = S626_SET_CRB_CLKENAB_A(enab); | |
902 | } else { | |
903 | mask |= S626_CRBMSK_CLKENAB_B; | |
904 | set = S626_SET_CRB_CLKENAB_B(enab); | |
905 | } | |
0c9a057c | 906 | s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set); |
17afeac2 IA |
907 | } |
908 | ||
17afeac2 IA |
909 | /* |
910 | * Return/set the event that will trigger transfer of the preload | |
911 | * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow, | |
912 | * 2=OverflowA (B counters only), 3=disabled. | |
913 | */ | |
7f03b749 | 914 | static void s626_set_load_trig(struct comedi_device *dev, |
0bc45380 | 915 | unsigned int chan, u16 trig) |
17afeac2 | 916 | { |
0bc45380 SR |
917 | u16 reg; |
918 | u16 mask; | |
919 | u16 set; | |
17afeac2 | 920 | |
0c9a057c HS |
921 | if (chan < 3) { |
922 | reg = S626_LP_CRA(chan); | |
7f03b749 HS |
923 | mask = S626_CRAMSK_LOADSRC_A; |
924 | set = S626_SET_CRA_LOADSRC_A(trig); | |
925 | } else { | |
0c9a057c | 926 | reg = S626_LP_CRB(chan); |
7f03b749 HS |
927 | mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL; |
928 | set = S626_SET_CRB_LOADSRC_B(trig); | |
929 | } | |
930 | s626_debi_replace(dev, reg, ~mask, set); | |
17afeac2 IA |
931 | } |
932 | ||
bc284a2a IA |
933 | /* |
934 | * Return/set counter interrupt source and clear any captured | |
935 | * index/overflow events. int_source: 0=Disabled, 1=OverflowOnly, | |
936 | * 2=IndexOnly, 3=IndexAndOverflow. | |
937 | */ | |
253e2ee4 | 938 | static void s626_set_int_src(struct comedi_device *dev, |
0bc45380 | 939 | unsigned int chan, u16 int_source) |
bc284a2a IA |
940 | { |
941 | struct s626_private *devpriv = dev->private; | |
0bc45380 SR |
942 | u16 cra_reg = S626_LP_CRA(chan); |
943 | u16 crb_reg = S626_LP_CRB(chan); | |
bc284a2a | 944 | |
0c9a057c | 945 | if (chan < 3) { |
253e2ee4 HS |
946 | /* Reset any pending counter overflow or index captures */ |
947 | s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL, | |
948 | S626_SET_CRB_INTRESETCMD(1) | | |
949 | S626_SET_CRB_INTRESET_A(1)); | |
950 | ||
951 | /* Program counter interrupt source */ | |
952 | s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A, | |
953 | S626_SET_CRA_INTSRC_A(int_source)); | |
954 | } else { | |
0bc45380 | 955 | u16 crb; |
bc284a2a | 956 | |
253e2ee4 HS |
957 | /* Cache writeable CRB register image */ |
958 | crb = s626_debi_read(dev, crb_reg); | |
959 | crb &= ~S626_CRBMSK_INTCTRL; | |
bc284a2a | 960 | |
253e2ee4 HS |
961 | /* Reset any pending counter overflow or index captures */ |
962 | s626_debi_write(dev, crb_reg, | |
963 | crb | S626_SET_CRB_INTRESETCMD(1) | | |
964 | S626_SET_CRB_INTRESET_B(1)); | |
bc284a2a | 965 | |
253e2ee4 HS |
966 | /* Program counter interrupt source */ |
967 | s626_debi_write(dev, crb_reg, | |
968 | (crb & ~S626_CRBMSK_INTSRC_B) | | |
969 | S626_SET_CRB_INTSRC_B(int_source)); | |
970 | } | |
bc284a2a IA |
971 | |
972 | /* Update MISC2 interrupt enable mask. */ | |
0c9a057c HS |
973 | devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) | |
974 | S626_INDXMASK(chan)); | |
f76d02f8 HS |
975 | switch (int_source) { |
976 | case 0: | |
977 | default: | |
978 | break; | |
979 | case 1: | |
0c9a057c | 980 | devpriv->counter_int_enabs |= S626_OVERMASK(chan); |
f76d02f8 HS |
981 | break; |
982 | case 2: | |
0c9a057c | 983 | devpriv->counter_int_enabs |= S626_INDXMASK(chan); |
f76d02f8 HS |
984 | break; |
985 | case 3: | |
0c9a057c HS |
986 | devpriv->counter_int_enabs |= (S626_OVERMASK(chan) | |
987 | S626_INDXMASK(chan)); | |
f76d02f8 HS |
988 | break; |
989 | } | |
bc284a2a IA |
990 | } |
991 | ||
bc284a2a IA |
992 | /* |
993 | * Generate an index pulse. | |
994 | */ | |
92249e1f | 995 | static void s626_pulse_index(struct comedi_device *dev, |
0c9a057c | 996 | unsigned int chan) |
bc284a2a | 997 | { |
0c9a057c | 998 | if (chan < 3) { |
0bc45380 | 999 | u16 cra; |
bc284a2a | 1000 | |
0c9a057c | 1001 | cra = s626_debi_read(dev, S626_LP_CRA(chan)); |
bc284a2a | 1002 | |
92249e1f | 1003 | /* Pulse index */ |
0c9a057c | 1004 | s626_debi_write(dev, S626_LP_CRA(chan), |
92249e1f | 1005 | (cra ^ S626_CRAMSK_INDXPOL_A)); |
0c9a057c | 1006 | s626_debi_write(dev, S626_LP_CRA(chan), cra); |
92249e1f | 1007 | } else { |
0bc45380 | 1008 | u16 crb; |
bc284a2a | 1009 | |
0c9a057c | 1010 | crb = s626_debi_read(dev, S626_LP_CRB(chan)); |
92249e1f HS |
1011 | crb &= ~S626_CRBMSK_INTCTRL; |
1012 | ||
1013 | /* Pulse index */ | |
0c9a057c | 1014 | s626_debi_write(dev, S626_LP_CRB(chan), |
92249e1f | 1015 | (crb ^ S626_CRBMSK_INDXPOL_B)); |
0c9a057c | 1016 | s626_debi_write(dev, S626_LP_CRB(chan), crb); |
92249e1f | 1017 | } |
bc284a2a IA |
1018 | } |
1019 | ||
5fd4b711 | 1020 | static unsigned int s626_ai_reg_to_uint(unsigned int data) |
11e865c1 | 1021 | { |
5fd4b711 | 1022 | return ((data >> 18) & 0x3fff) ^ 0x2000; |
020c44f3 | 1023 | } |
8231eb56 | 1024 | |
6baffbc2 HS |
1025 | static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan) |
1026 | { | |
100b4edc HS |
1027 | unsigned int group = chan / 16; |
1028 | unsigned int mask = 1 << (chan - (16 * group)); | |
6baffbc2 HS |
1029 | unsigned int status; |
1030 | ||
6baffbc2 | 1031 | /* set channel to capture positive edge */ |
d8515652 IA |
1032 | status = s626_debi_read(dev, S626_LP_RDEDGSEL(group)); |
1033 | s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status); | |
6baffbc2 HS |
1034 | |
1035 | /* enable interrupt on selected channel */ | |
d8515652 IA |
1036 | status = s626_debi_read(dev, S626_LP_RDINTSEL(group)); |
1037 | s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status); | |
6baffbc2 HS |
1038 | |
1039 | /* enable edge capture write command */ | |
d8515652 | 1040 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP); |
6baffbc2 HS |
1041 | |
1042 | /* enable edge capture on selected channel */ | |
d8515652 IA |
1043 | status = s626_debi_read(dev, S626_LP_RDCAPSEL(group)); |
1044 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status); | |
6baffbc2 HS |
1045 | |
1046 | return 0; | |
1047 | } | |
1048 | ||
1049 | static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group, | |
1050 | unsigned int mask) | |
1051 | { | |
6baffbc2 | 1052 | /* disable edge capture write command */ |
d8515652 | 1053 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
6baffbc2 HS |
1054 | |
1055 | /* enable edge capture on selected channel */ | |
d8515652 | 1056 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask); |
6baffbc2 HS |
1057 | |
1058 | return 0; | |
1059 | } | |
1060 | ||
1061 | static int s626_dio_clear_irq(struct comedi_device *dev) | |
1062 | { | |
1063 | unsigned int group; | |
1064 | ||
1065 | /* disable edge capture write command */ | |
d8515652 | 1066 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
6baffbc2 | 1067 | |
100b4edc HS |
1068 | /* clear all dio pending events and interrupt */ |
1069 | for (group = 0; group < S626_DIO_BANKS; group++) | |
d8515652 | 1070 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff); |
6baffbc2 HS |
1071 | |
1072 | return 0; | |
1073 | } | |
1074 | ||
31de1948 | 1075 | static void s626_handle_dio_interrupt(struct comedi_device *dev, |
0bc45380 | 1076 | u16 irqbit, u8 group) |
65a17c29 HS |
1077 | { |
1078 | struct s626_private *devpriv = dev->private; | |
1079 | struct comedi_subdevice *s = dev->read_subdev; | |
1080 | struct comedi_cmd *cmd = &s->async->cmd; | |
1081 | ||
1082 | s626_dio_reset_irq(dev, group, irqbit); | |
1083 | ||
1084 | if (devpriv->ai_cmd_running) { | |
1085 | /* check if interrupt is an ai acquisition start trigger */ | |
1086 | if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 && | |
1087 | cmd->start_src == TRIG_EXT) { | |
1088 | /* Start executing the RPS program */ | |
d8515652 | 1089 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
65a17c29 HS |
1090 | |
1091 | if (cmd->scan_begin_src == TRIG_EXT) | |
1092 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
1093 | } | |
1094 | if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 && | |
1095 | cmd->scan_begin_src == TRIG_EXT) { | |
ddd9813e | 1096 | /* Trigger ADC scan loop start */ |
d8515652 | 1097 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
65a17c29 HS |
1098 | |
1099 | if (cmd->convert_src == TRIG_EXT) { | |
1100 | devpriv->ai_convert_count = cmd->chanlist_len; | |
1101 | ||
1102 | s626_dio_set_irq(dev, cmd->convert_arg); | |
1103 | } | |
1104 | ||
1105 | if (cmd->convert_src == TRIG_TIMER) { | |
65a17c29 | 1106 | devpriv->ai_convert_count = cmd->chanlist_len; |
0c9a057c | 1107 | s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS); |
65a17c29 HS |
1108 | } |
1109 | } | |
1110 | if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 && | |
1111 | cmd->convert_src == TRIG_EXT) { | |
ddd9813e | 1112 | /* Trigger ADC scan loop start */ |
d8515652 | 1113 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
65a17c29 HS |
1114 | |
1115 | devpriv->ai_convert_count--; | |
1116 | if (devpriv->ai_convert_count > 0) | |
1117 | s626_dio_set_irq(dev, cmd->convert_arg); | |
1118 | } | |
1119 | } | |
1120 | } | |
1121 | ||
31de1948 | 1122 | static void s626_check_dio_interrupts(struct comedi_device *dev) |
65a17c29 | 1123 | { |
0bc45380 | 1124 | u16 irqbit; |
d9f9600b | 1125 | u8 group; |
65a17c29 HS |
1126 | |
1127 | for (group = 0; group < S626_DIO_BANKS; group++) { | |
65a17c29 | 1128 | /* read interrupt type */ |
d8515652 | 1129 | irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group)); |
65a17c29 HS |
1130 | |
1131 | /* check if interrupt is generated from dio channels */ | |
1132 | if (irqbit) { | |
31de1948 | 1133 | s626_handle_dio_interrupt(dev, irqbit, group); |
65a17c29 HS |
1134 | return; |
1135 | } | |
1136 | } | |
1137 | } | |
1138 | ||
31de1948 | 1139 | static void s626_check_counter_interrupts(struct comedi_device *dev) |
0b9675d5 HS |
1140 | { |
1141 | struct s626_private *devpriv = dev->private; | |
1142 | struct comedi_subdevice *s = dev->read_subdev; | |
1143 | struct comedi_async *async = s->async; | |
1144 | struct comedi_cmd *cmd = &async->cmd; | |
0bc45380 | 1145 | u16 irqbit; |
0b9675d5 HS |
1146 | |
1147 | /* read interrupt type */ | |
d8515652 | 1148 | irqbit = s626_debi_read(dev, S626_LP_RDMISC2); |
0b9675d5 HS |
1149 | |
1150 | /* check interrupt on counters */ | |
d8515652 | 1151 | if (irqbit & S626_IRQ_COINT1A) { |
0b9675d5 | 1152 | /* clear interrupt capture flag */ |
0c9a057c | 1153 | s626_reset_cap_flags(dev, 0); |
0b9675d5 | 1154 | } |
d8515652 | 1155 | if (irqbit & S626_IRQ_COINT2A) { |
0b9675d5 | 1156 | /* clear interrupt capture flag */ |
0c9a057c | 1157 | s626_reset_cap_flags(dev, 1); |
0b9675d5 | 1158 | } |
d8515652 | 1159 | if (irqbit & S626_IRQ_COINT3A) { |
0b9675d5 | 1160 | /* clear interrupt capture flag */ |
0c9a057c | 1161 | s626_reset_cap_flags(dev, 2); |
0b9675d5 | 1162 | } |
d8515652 | 1163 | if (irqbit & S626_IRQ_COINT1B) { |
0b9675d5 | 1164 | /* clear interrupt capture flag */ |
0c9a057c | 1165 | s626_reset_cap_flags(dev, 3); |
0b9675d5 | 1166 | } |
d8515652 | 1167 | if (irqbit & S626_IRQ_COINT2B) { |
0b9675d5 | 1168 | /* clear interrupt capture flag */ |
0c9a057c | 1169 | s626_reset_cap_flags(dev, 4); |
0b9675d5 HS |
1170 | |
1171 | if (devpriv->ai_convert_count > 0) { | |
1172 | devpriv->ai_convert_count--; | |
1173 | if (devpriv->ai_convert_count == 0) | |
0c9a057c | 1174 | s626_set_enable(dev, 4, S626_CLKENAB_INDEX); |
0b9675d5 HS |
1175 | |
1176 | if (cmd->convert_src == TRIG_TIMER) { | |
ddd9813e | 1177 | /* Trigger ADC scan loop start */ |
d8515652 IA |
1178 | s626_mc_enable(dev, S626_MC2_ADC_RPS, |
1179 | S626_P_MC2); | |
0b9675d5 HS |
1180 | } |
1181 | } | |
1182 | } | |
d8515652 | 1183 | if (irqbit & S626_IRQ_COINT3B) { |
0b9675d5 | 1184 | /* clear interrupt capture flag */ |
0c9a057c | 1185 | s626_reset_cap_flags(dev, 5); |
0b9675d5 HS |
1186 | |
1187 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
ddd9813e | 1188 | /* Trigger ADC scan loop start */ |
d8515652 | 1189 | s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); |
0b9675d5 HS |
1190 | } |
1191 | ||
1192 | if (cmd->convert_src == TRIG_TIMER) { | |
0b9675d5 | 1193 | devpriv->ai_convert_count = cmd->chanlist_len; |
0c9a057c | 1194 | s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS); |
0b9675d5 HS |
1195 | } |
1196 | } | |
1197 | } | |
1198 | ||
31de1948 | 1199 | static bool s626_handle_eos_interrupt(struct comedi_device *dev) |
4c2d13e0 HS |
1200 | { |
1201 | struct s626_private *devpriv = dev->private; | |
1202 | struct comedi_subdevice *s = dev->read_subdev; | |
1203 | struct comedi_async *async = s->async; | |
1204 | struct comedi_cmd *cmd = &async->cmd; | |
1205 | /* | |
1206 | * Init ptr to DMA buffer that holds new ADC data. We skip the | |
1207 | * first uint16_t in the buffer because it contains junk data | |
1208 | * from the final ADC of the previous poll list scan. | |
1209 | */ | |
b13db6bf | 1210 | u32 *readaddr = (u32 *)devpriv->ana_buf.logical_base + 1; |
4c2d13e0 HS |
1211 | int i; |
1212 | ||
1213 | /* get the data and hand it over to comedi */ | |
1214 | for (i = 0; i < cmd->chanlist_len; i++) { | |
5fd4b711 | 1215 | unsigned short tempdata; |
4c2d13e0 HS |
1216 | |
1217 | /* | |
1218 | * Convert ADC data to 16-bit integer values and copy | |
1219 | * to application buffer. | |
1220 | */ | |
5fd4b711 | 1221 | tempdata = s626_ai_reg_to_uint(*readaddr); |
4c2d13e0 HS |
1222 | readaddr++; |
1223 | ||
0e017a4b | 1224 | comedi_buf_write_samples(s, &tempdata, 1); |
4c2d13e0 HS |
1225 | } |
1226 | ||
aee15aea HS |
1227 | if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg) |
1228 | async->events |= COMEDI_CB_EOA; | |
4c2d13e0 | 1229 | |
aee15aea HS |
1230 | if (async->events & COMEDI_CB_CANCEL_MASK) |
1231 | devpriv->ai_cmd_running = 0; | |
4c2d13e0 HS |
1232 | |
1233 | if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) | |
1234 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
1235 | ||
365dae93 | 1236 | comedi_handle_events(dev, s); |
4c2d13e0 | 1237 | |
365dae93 | 1238 | return !devpriv->ai_cmd_running; |
4c2d13e0 HS |
1239 | } |
1240 | ||
020c44f3 HS |
1241 | static irqreturn_t s626_irq_handler(int irq, void *d) |
1242 | { | |
1243 | struct comedi_device *dev = d; | |
020c44f3 | 1244 | unsigned long flags; |
b13db6bf | 1245 | u32 irqtype, irqstatus; |
11e865c1 | 1246 | |
a7401cdd | 1247 | if (!dev->attached) |
020c44f3 | 1248 | return IRQ_NONE; |
8ee52611 | 1249 | /* lock to avoid race with comedi_poll */ |
020c44f3 | 1250 | spin_lock_irqsave(&dev->spinlock, flags); |
11e865c1 | 1251 | |
020c44f3 | 1252 | /* save interrupt enable register state */ |
de9cd5ca | 1253 | irqstatus = readl(dev->mmio + S626_P_IER); |
11e865c1 | 1254 | |
020c44f3 | 1255 | /* read interrupt type */ |
de9cd5ca | 1256 | irqtype = readl(dev->mmio + S626_P_ISR); |
11e865c1 | 1257 | |
020c44f3 | 1258 | /* disable master interrupt */ |
de9cd5ca | 1259 | writel(0, dev->mmio + S626_P_IER); |
11e865c1 | 1260 | |
020c44f3 | 1261 | /* clear interrupt */ |
de9cd5ca | 1262 | writel(irqtype, dev->mmio + S626_P_ISR); |
11e865c1 | 1263 | |
020c44f3 | 1264 | switch (irqtype) { |
d8515652 | 1265 | case S626_IRQ_RPS1: /* end_of_scan occurs */ |
31de1948 | 1266 | if (s626_handle_eos_interrupt(dev)) |
020c44f3 | 1267 | irqstatus = 0; |
020c44f3 | 1268 | break; |
d8515652 | 1269 | case S626_IRQ_GPIO3: /* check dio and counter interrupt */ |
020c44f3 | 1270 | /* s626_dio_clear_irq(dev); */ |
31de1948 IA |
1271 | s626_check_dio_interrupts(dev); |
1272 | s626_check_counter_interrupts(dev); | |
0b9675d5 | 1273 | break; |
020c44f3 | 1274 | } |
11e865c1 | 1275 | |
020c44f3 | 1276 | /* enable interrupt */ |
de9cd5ca | 1277 | writel(irqstatus, dev->mmio + S626_P_IER); |
b6c77757 | 1278 | |
020c44f3 HS |
1279 | spin_unlock_irqrestore(&dev->spinlock, flags); |
1280 | return IRQ_HANDLED; | |
1281 | } | |
b6c77757 | 1282 | |
020c44f3 | 1283 | /* |
8ee52611 | 1284 | * This function builds the RPS program for hardware driven acquisition. |
020c44f3 | 1285 | */ |
d9f9600b | 1286 | static void s626_reset_adc(struct comedi_device *dev, u8 *ppl) |
020c44f3 | 1287 | { |
7f2f7e05 | 1288 | struct s626_private *devpriv = dev->private; |
9c9ab3c1 HS |
1289 | struct comedi_subdevice *s = dev->read_subdev; |
1290 | struct comedi_cmd *cmd = &s->async->cmd; | |
b13db6bf SR |
1291 | u32 *rps; |
1292 | u32 jmp_adrs; | |
0bc45380 SR |
1293 | u16 i; |
1294 | u16 n; | |
b13db6bf | 1295 | u32 local_ppl; |
11e865c1 | 1296 | |
c5cf4606 | 1297 | /* Stop RPS program in case it is currently running */ |
d8515652 | 1298 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 1299 | |
8ee52611 | 1300 | /* Set starting logical address to write RPS commands. */ |
b13db6bf | 1301 | rps = (u32 *)devpriv->rps_buf.logical_base; |
11e865c1 | 1302 | |
25f8fd5e | 1303 | /* Initialize RPS instruction pointer */ |
b13db6bf | 1304 | writel((u32)devpriv->rps_buf.physical_base, |
de9cd5ca | 1305 | dev->mmio + S626_P_RPSADDR1); |
11e865c1 | 1306 | |
07a36d66 | 1307 | /* Construct RPS program in rps_buf DMA buffer */ |
857ced45 | 1308 | if (cmd->scan_begin_src != TRIG_FOLLOW) { |
8ee52611 | 1309 | /* Wait for Start trigger. */ |
d8515652 IA |
1310 | *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; |
1311 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; | |
020c44f3 | 1312 | } |
11e865c1 | 1313 | |
8ee52611 IA |
1314 | /* |
1315 | * SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary | |
020c44f3 HS |
1316 | * because the first RPS DEBI Write following a non-RPS DEBI write |
1317 | * seems to always fail. If we don't do this dummy write, the ADC | |
1318 | * gain might not be set to the value required for the first slot in | |
1319 | * the poll list; the ADC gain would instead remain unchanged from | |
1320 | * the previously programmed value. | |
1321 | */ | |
020c44f3 | 1322 | /* Write DEBI Write command and address to shadow RAM. */ |
d8515652 IA |
1323 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1324 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; | |
1325 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); | |
8ee52611 | 1326 | /* Write DEBI immediate data to shadow RAM: */ |
d8515652 IA |
1327 | *rps++ = S626_GSEL_BIPOLAR5V; /* arbitrary immediate data value. */ |
1328 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; | |
8ee52611 | 1329 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 IA |
1330 | /* Invoke shadow RAM upload. */ |
1331 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; | |
1332 | /* Wait for shadow upload to finish. */ | |
1333 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; | |
11e865c1 | 1334 | |
8ee52611 IA |
1335 | /* |
1336 | * Digitize all slots in the poll list. This is implemented as a | |
020c44f3 | 1337 | * for loop to limit the slot count to 16 in case the application |
d8515652 | 1338 | * forgot to set the S626_EOPL flag in the final slot. |
020c44f3 | 1339 | */ |
07a36d66 IA |
1340 | for (devpriv->adc_items = 0; devpriv->adc_items < 16; |
1341 | devpriv->adc_items++) { | |
8ee52611 IA |
1342 | /* |
1343 | * Convert application's poll list item to private board class | |
020c44f3 HS |
1344 | * format. Each app poll list item is an uint8_t with form |
1345 | * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 = | |
1346 | * +-10V, 1 = +-5V, and EOPL = End of Poll List marker. | |
b6c77757 | 1347 | */ |
d8515652 IA |
1348 | local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V : |
1349 | S626_GSEL_BIPOLAR10V); | |
8ee52611 IA |
1350 | |
1351 | /* Switch ADC analog gain. */ | |
1352 | /* Write DEBI command and address to shadow RAM. */ | |
d8515652 IA |
1353 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
1354 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL; | |
8ee52611 | 1355 | /* Write DEBI immediate data to shadow RAM. */ |
d8515652 | 1356 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); |
f1f7efce | 1357 | *rps++ = local_ppl; |
8ee52611 | 1358 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 | 1359 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
8ee52611 | 1360 | /* Invoke shadow RAM upload. */ |
d8515652 | 1361 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
8ee52611 | 1362 | /* Wait for shadow upload to finish. */ |
d8515652 | 1363 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
8ee52611 | 1364 | /* Select ADC analog input channel. */ |
d8515652 | 1365 | *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2); |
8ee52611 | 1366 | /* Write DEBI command and address to shadow RAM. */ |
d8515652 IA |
1367 | *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL; |
1368 | *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2); | |
8ee52611 | 1369 | /* Write DEBI immediate data to shadow RAM. */ |
f1f7efce | 1370 | *rps++ = local_ppl; |
8ee52611 | 1371 | /* Reset "shadow RAM uploaded" flag. */ |
d8515652 | 1372 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI; |
8ee52611 | 1373 | /* Invoke shadow RAM upload. */ |
d8515652 | 1374 | *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI; |
8ee52611 | 1375 | /* Wait for shadow upload to finish. */ |
d8515652 | 1376 | *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI; |
11e865c1 | 1377 | |
8ee52611 IA |
1378 | /* |
1379 | * Delay at least 10 microseconds for analog input settling. | |
d8515652 IA |
1380 | * Instead of padding with NOPs, we use S626_RPS_JUMP |
1381 | * instructions here; this allows us to produce a longer delay | |
1382 | * than is possible with NOPs because each S626_RPS_JUMP | |
1383 | * flushes the RPS' instruction prefetch pipeline. | |
020c44f3 | 1384 | */ |
f1f7efce | 1385 | jmp_adrs = |
b13db6bf SR |
1386 | (u32)devpriv->rps_buf.physical_base + |
1387 | (u32)((unsigned long)rps - | |
07a36d66 IA |
1388 | (unsigned long)devpriv-> |
1389 | rps_buf.logical_base); | |
d8515652 | 1390 | for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) { |
f1f7efce | 1391 | jmp_adrs += 8; /* Repeat to implement time delay: */ |
d8515652 IA |
1392 | /* Jump to next RPS instruction. */ |
1393 | *rps++ = S626_RPS_JUMP; | |
f1f7efce | 1394 | *rps++ = jmp_adrs; |
020c44f3 | 1395 | } |
11e865c1 | 1396 | |
857ced45 | 1397 | if (cmd->convert_src != TRIG_NOW) { |
8ee52611 | 1398 | /* Wait for Start trigger. */ |
d8515652 IA |
1399 | *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC; |
1400 | *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; | |
020c44f3 | 1401 | } |
8ee52611 IA |
1402 | /* Start ADC by pulsing GPIO1. */ |
1403 | /* Begin ADC Start pulse. */ | |
d8515652 IA |
1404 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1405 | *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; | |
1406 | *rps++ = S626_RPS_NOP; | |
8ee52611 IA |
1407 | /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ |
1408 | /* End ADC Start pulse. */ | |
d8515652 IA |
1409 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); |
1410 | *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; | |
8ee52611 IA |
1411 | /* |
1412 | * Wait for ADC to complete (GPIO2 is asserted high when ADC not | |
020c44f3 HS |
1413 | * busy) and for data from previous conversion to shift into FB |
1414 | * BUFFER 1 register. | |
1415 | */ | |
d8515652 IA |
1416 | /* Wait for ADC done. */ |
1417 | *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; | |
11e865c1 | 1418 | |
8ee52611 | 1419 | /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */ |
d8515652 IA |
1420 | *rps++ = S626_RPS_STREG | |
1421 | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); | |
b13db6bf | 1422 | *rps++ = (u32)devpriv->ana_buf.physical_base + |
f1f7efce | 1423 | (devpriv->adc_items << 2); |
11e865c1 | 1424 | |
8ee52611 IA |
1425 | /* |
1426 | * If this slot's EndOfPollList flag is set, all channels have | |
1427 | * now been processed. | |
1428 | */ | |
d8515652 | 1429 | if (*ppl++ & S626_EOPL) { |
07a36d66 | 1430 | devpriv->adc_items++; /* Adjust poll list item count. */ |
8ee52611 | 1431 | break; /* Exit poll list processing loop. */ |
020c44f3 HS |
1432 | } |
1433 | } | |
11e865c1 | 1434 | |
8ee52611 IA |
1435 | /* |
1436 | * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the | |
020c44f3 HS |
1437 | * ADC to stabilize for 2 microseconds before starting the final |
1438 | * (dummy) conversion. This delay is necessary to allow sufficient | |
1439 | * time between last conversion finished and the start of the dummy | |
1440 | * conversion. Without this delay, the last conversion's data value | |
1441 | * is sometimes set to the previous conversion's data value. | |
1442 | */ | |
d8515652 IA |
1443 | for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++) |
1444 | *rps++ = S626_RPS_NOP; | |
11e865c1 | 1445 | |
8ee52611 IA |
1446 | /* |
1447 | * Start a dummy conversion to cause the data from the last | |
020c44f3 HS |
1448 | * conversion of interest to be shifted in. |
1449 | */ | |
d8515652 IA |
1450 | /* Begin ADC Start pulse. */ |
1451 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); | |
1452 | *rps++ = S626_GPIO_BASE | S626_GPIO1_LO; | |
1453 | *rps++ = S626_RPS_NOP; | |
020c44f3 | 1454 | /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */ |
d8515652 IA |
1455 | *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */ |
1456 | *rps++ = S626_GPIO_BASE | S626_GPIO1_HI; | |
11e865c1 | 1457 | |
8ee52611 IA |
1458 | /* |
1459 | * Wait for the data from the last conversion of interest to arrive | |
020c44f3 HS |
1460 | * in FB BUFFER 1 register. |
1461 | */ | |
d8515652 | 1462 | *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2; /* Wait for ADC done. */ |
11e865c1 | 1463 | |
8ee52611 | 1464 | /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */ |
d8515652 | 1465 | *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2); |
b13db6bf | 1466 | *rps++ = (u32)devpriv->ana_buf.physical_base + |
f1f7efce | 1467 | (devpriv->adc_items << 2); |
11e865c1 | 1468 | |
8ee52611 IA |
1469 | /* Indicate ADC scan loop is finished. */ |
1470 | /* Signal ReadADC() that scan is done. */ | |
d8515652 | 1471 | /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */ |
11e865c1 | 1472 | |
020c44f3 | 1473 | /* invoke interrupt */ |
8ee52611 | 1474 | if (devpriv->ai_cmd_running == 1) |
d8515652 | 1475 | *rps++ = S626_RPS_IRQ; |
11e865c1 | 1476 | |
8ee52611 | 1477 | /* Restart RPS program at its beginning. */ |
d8515652 | 1478 | *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */ |
b13db6bf | 1479 | *rps++ = (u32)devpriv->rps_buf.physical_base; |
8ee52611 IA |
1480 | |
1481 | /* End of RPS program build */ | |
020c44f3 | 1482 | } |
11e865c1 | 1483 | |
45b281e4 HS |
1484 | static int s626_ai_eoc(struct comedi_device *dev, |
1485 | struct comedi_subdevice *s, | |
1486 | struct comedi_insn *insn, | |
1487 | unsigned long context) | |
1488 | { | |
45b281e4 HS |
1489 | unsigned int status; |
1490 | ||
de9cd5ca | 1491 | status = readl(dev->mmio + S626_P_PSR); |
45b281e4 HS |
1492 | if (status & S626_PSR_GPIO2) |
1493 | return 0; | |
1494 | return -EBUSY; | |
1495 | } | |
1496 | ||
020c44f3 HS |
1497 | static int s626_ai_insn_read(struct comedi_device *dev, |
1498 | struct comedi_subdevice *s, | |
de9cd5ca HS |
1499 | struct comedi_insn *insn, |
1500 | unsigned int *data) | |
020c44f3 | 1501 | { |
0bc45380 SR |
1502 | u16 chan = CR_CHAN(insn->chanspec); |
1503 | u16 range = CR_RANGE(insn->chanspec); | |
1504 | u16 adc_spec = 0; | |
b13db6bf SR |
1505 | u32 gpio_image; |
1506 | u32 tmp; | |
45b281e4 | 1507 | int ret; |
020c44f3 | 1508 | int n; |
11e865c1 | 1509 | |
8ee52611 IA |
1510 | /* |
1511 | * Convert application's ADC specification into form | |
020c44f3 HS |
1512 | * appropriate for register programming. |
1513 | */ | |
1514 | if (range == 0) | |
d8515652 | 1515 | adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V); |
020c44f3 | 1516 | else |
d8515652 | 1517 | adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V); |
11e865c1 | 1518 | |
8ee52611 | 1519 | /* Switch ADC analog gain. */ |
d8515652 | 1520 | s626_debi_write(dev, S626_LP_GSEL, adc_spec); /* Set gain. */ |
11e865c1 | 1521 | |
8ee52611 | 1522 | /* Select ADC analog input channel. */ |
d8515652 | 1523 | s626_debi_write(dev, S626_LP_ISEL, adc_spec); /* Select channel. */ |
11e865c1 | 1524 | |
020c44f3 | 1525 | for (n = 0; n < insn->n; n++) { |
8ee52611 | 1526 | /* Delay 10 microseconds for analog input settling. */ |
df6ff8a1 | 1527 | usleep_range(10, 20); |
11e865c1 | 1528 | |
be008602 | 1529 | /* Start ADC by pulsing GPIO1 low */ |
de9cd5ca | 1530 | gpio_image = readl(dev->mmio + S626_P_GPIO); |
25f8fd5e | 1531 | /* Assert ADC Start command */ |
de9cd5ca | 1532 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
25f8fd5e | 1533 | /* and stretch it out */ |
de9cd5ca HS |
1534 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
1535 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); | |
25f8fd5e | 1536 | /* Negate ADC Start command */ |
de9cd5ca | 1537 | writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
11e865c1 | 1538 | |
8ee52611 IA |
1539 | /* |
1540 | * Wait for ADC to complete (GPIO2 is asserted high when | |
1541 | * ADC not busy) and for data from previous conversion to | |
1542 | * shift into FB BUFFER 1 register. | |
1543 | */ | |
11e865c1 | 1544 | |
be008602 | 1545 | /* Wait for ADC done */ |
45b281e4 HS |
1546 | ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0); |
1547 | if (ret) | |
1548 | return ret; | |
11e865c1 | 1549 | |
be008602 HS |
1550 | /* Fetch ADC data */ |
1551 | if (n != 0) { | |
de9cd5ca | 1552 | tmp = readl(dev->mmio + S626_P_FB_BUFFER1); |
be008602 HS |
1553 | data[n - 1] = s626_ai_reg_to_uint(tmp); |
1554 | } | |
11e865c1 | 1555 | |
8ee52611 IA |
1556 | /* |
1557 | * Allow the ADC to stabilize for 4 microseconds before | |
020c44f3 HS |
1558 | * starting the next (final) conversion. This delay is |
1559 | * necessary to allow sufficient time between last | |
1560 | * conversion finished and the start of the next | |
1561 | * conversion. Without this delay, the last conversion's | |
1562 | * data value is sometimes set to the previous | |
1563 | * conversion's data value. | |
1564 | */ | |
1565 | udelay(4); | |
1566 | } | |
11e865c1 | 1567 | |
8ee52611 IA |
1568 | /* |
1569 | * Start a dummy conversion to cause the data from the | |
1570 | * previous conversion to be shifted in. | |
1571 | */ | |
de9cd5ca | 1572 | gpio_image = readl(dev->mmio + S626_P_GPIO); |
020c44f3 | 1573 | /* Assert ADC Start command */ |
de9cd5ca | 1574 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
25f8fd5e | 1575 | /* and stretch it out */ |
de9cd5ca HS |
1576 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
1577 | writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO); | |
25f8fd5e | 1578 | /* Negate ADC Start command */ |
de9cd5ca | 1579 | writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
11e865c1 | 1580 | |
8ee52611 | 1581 | /* Wait for the data to arrive in FB BUFFER 1 register. */ |
11e865c1 | 1582 | |
be008602 | 1583 | /* Wait for ADC done */ |
571845c6 CS |
1584 | ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0); |
1585 | if (ret) | |
1586 | return ret; | |
11e865c1 | 1587 | |
8ee52611 | 1588 | /* Fetch ADC data from audio interface's input shift register. */ |
11e865c1 | 1589 | |
be008602 HS |
1590 | /* Fetch ADC data */ |
1591 | if (n != 0) { | |
de9cd5ca | 1592 | tmp = readl(dev->mmio + S626_P_FB_BUFFER1); |
be008602 HS |
1593 | data[n - 1] = s626_ai_reg_to_uint(tmp); |
1594 | } | |
11e865c1 | 1595 | |
020c44f3 HS |
1596 | return n; |
1597 | } | |
11e865c1 | 1598 | |
d9f9600b | 1599 | static int s626_ai_load_polllist(u8 *ppl, struct comedi_cmd *cmd) |
020c44f3 | 1600 | { |
020c44f3 | 1601 | int n; |
11e865c1 | 1602 | |
020c44f3 | 1603 | for (n = 0; n < cmd->chanlist_len; n++) { |
8ee52611 | 1604 | if (CR_RANGE(cmd->chanlist[n]) == 0) |
d8515652 | 1605 | ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V; |
020c44f3 | 1606 | else |
d8515652 | 1607 | ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V; |
020c44f3 HS |
1608 | } |
1609 | if (n != 0) | |
d8515652 | 1610 | ppl[n - 1] |= S626_EOPL; |
11e865c1 | 1611 | |
020c44f3 HS |
1612 | return n; |
1613 | } | |
11e865c1 | 1614 | |
020c44f3 | 1615 | static int s626_ai_inttrig(struct comedi_device *dev, |
478da5c9 HS |
1616 | struct comedi_subdevice *s, |
1617 | unsigned int trig_num) | |
020c44f3 | 1618 | { |
478da5c9 HS |
1619 | struct comedi_cmd *cmd = &s->async->cmd; |
1620 | ||
1621 | if (trig_num != cmd->start_arg) | |
020c44f3 | 1622 | return -EINVAL; |
11e865c1 | 1623 | |
ddd9813e | 1624 | /* Start executing the RPS program */ |
d8515652 | 1625 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 1626 | |
020c44f3 | 1627 | s->async->inttrig = NULL; |
11e865c1 | 1628 | |
020c44f3 HS |
1629 | return 1; |
1630 | } | |
11e865c1 | 1631 | |
8ee52611 IA |
1632 | /* |
1633 | * This function doesn't require a particular form, this is just what | |
6baffbc2 HS |
1634 | * happens to be used in some of the drivers. It should convert ns |
1635 | * nanoseconds to a counter value suitable for programming the device. | |
1636 | * Also, it should adjust ns so that it cooresponds to the actual time | |
8ee52611 IA |
1637 | * that the device will use. |
1638 | */ | |
a207c12f | 1639 | static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags) |
6baffbc2 HS |
1640 | { |
1641 | int divider, base; | |
1642 | ||
1643 | base = 500; /* 2MHz internal clock */ | |
1644 | ||
889277b9 IA |
1645 | switch (flags & CMDF_ROUND_MASK) { |
1646 | case CMDF_ROUND_NEAREST: | |
6baffbc2 | 1647 | default: |
d9798aa6 | 1648 | divider = DIV_ROUND_CLOSEST(*nanosec, base); |
6baffbc2 | 1649 | break; |
889277b9 | 1650 | case CMDF_ROUND_DOWN: |
6baffbc2 HS |
1651 | divider = (*nanosec) / base; |
1652 | break; | |
889277b9 | 1653 | case CMDF_ROUND_UP: |
97996da1 | 1654 | divider = DIV_ROUND_UP(*nanosec, base); |
6baffbc2 HS |
1655 | break; |
1656 | } | |
1657 | ||
1658 | *nanosec = base * divider; | |
1659 | return divider - 1; | |
1660 | } | |
1661 | ||
3a305a66 | 1662 | static void s626_timer_load(struct comedi_device *dev, |
0c9a057c | 1663 | unsigned int chan, int tick) |
e3eb08d0 | 1664 | { |
0bc45380 | 1665 | u16 setup = |
d8515652 | 1666 | /* Preload upon index. */ |
0830ada5 | 1667 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 1668 | /* Disable hardware index. */ |
0830ada5 | 1669 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 1670 | /* Operating mode is Timer. */ |
0830ada5 | 1671 | S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) | |
d8515652 | 1672 | /* Count direction is Down. */ |
0830ada5 | 1673 | S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) | |
d8515652 | 1674 | /* Clock multiplier is 1x. */ |
0830ada5 IA |
1675 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
1676 | /* Enabled by index */ | |
1677 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); | |
0bc45380 | 1678 | u16 value_latchsrc = S626_LATCHSRC_A_INDXA; |
d8515652 | 1679 | /* uint16_t enab = S626_CLKENAB_ALWAYS; */ |
e3eb08d0 | 1680 | |
0c9a057c | 1681 | s626_set_mode(dev, chan, setup, false); |
e3eb08d0 | 1682 | |
8ee52611 | 1683 | /* Set the preload register */ |
0c9a057c | 1684 | s626_preload(dev, chan, tick); |
e3eb08d0 | 1685 | |
8ee52611 IA |
1686 | /* |
1687 | * Software index pulse forces the preload register to load | |
1688 | * into the counter | |
1689 | */ | |
0c9a057c HS |
1690 | s626_set_load_trig(dev, chan, 0); |
1691 | s626_pulse_index(dev, chan); | |
e3eb08d0 HS |
1692 | |
1693 | /* set reload on counter overflow */ | |
0c9a057c | 1694 | s626_set_load_trig(dev, chan, 1); |
e3eb08d0 HS |
1695 | |
1696 | /* set interrupt on overflow */ | |
0c9a057c | 1697 | s626_set_int_src(dev, chan, S626_INTSRC_OVER); |
e3eb08d0 | 1698 | |
0c9a057c HS |
1699 | s626_set_latch_source(dev, chan, value_latchsrc); |
1700 | /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */ | |
e3eb08d0 HS |
1701 | } |
1702 | ||
8ee52611 | 1703 | /* TO COMPLETE */ |
020c44f3 HS |
1704 | static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
1705 | { | |
7f2f7e05 | 1706 | struct s626_private *devpriv = dev->private; |
d9f9600b | 1707 | u8 ppl[16]; |
020c44f3 | 1708 | struct comedi_cmd *cmd = &s->async->cmd; |
020c44f3 | 1709 | int tick; |
11e865c1 | 1710 | |
020c44f3 | 1711 | if (devpriv->ai_cmd_running) { |
730b8e15 IA |
1712 | dev_err(dev->class_dev, |
1713 | "s626_ai_cmd: Another ai_cmd is running\n"); | |
020c44f3 HS |
1714 | return -EBUSY; |
1715 | } | |
1716 | /* disable interrupt */ | |
de9cd5ca | 1717 | writel(0, dev->mmio + S626_P_IER); |
11e865c1 | 1718 | |
020c44f3 | 1719 | /* clear interrupt request */ |
de9cd5ca | 1720 | writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR); |
11e865c1 | 1721 | |
020c44f3 HS |
1722 | /* clear any pending interrupt */ |
1723 | s626_dio_clear_irq(dev); | |
8ee52611 | 1724 | /* s626_enc_clear_irq(dev); */ |
11e865c1 | 1725 | |
020c44f3 HS |
1726 | /* reset ai_cmd_running flag */ |
1727 | devpriv->ai_cmd_running = 0; | |
11e865c1 | 1728 | |
020c44f3 HS |
1729 | s626_ai_load_polllist(ppl, cmd); |
1730 | devpriv->ai_cmd_running = 1; | |
1731 | devpriv->ai_convert_count = 0; | |
11e865c1 | 1732 | |
020c44f3 HS |
1733 | switch (cmd->scan_begin_src) { |
1734 | case TRIG_FOLLOW: | |
1735 | break; | |
1736 | case TRIG_TIMER: | |
8ee52611 IA |
1737 | /* |
1738 | * set a counter to generate adc trigger at scan_begin_arg | |
1739 | * interval | |
1740 | */ | |
a207c12f | 1741 | tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags); |
11e865c1 | 1742 | |
020c44f3 | 1743 | /* load timer value and enable interrupt */ |
0c9a057c HS |
1744 | s626_timer_load(dev, 5, tick); |
1745 | s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS); | |
020c44f3 HS |
1746 | break; |
1747 | case TRIG_EXT: | |
8ee52611 | 1748 | /* set the digital line and interrupt for scan trigger */ |
020c44f3 HS |
1749 | if (cmd->start_src != TRIG_EXT) |
1750 | s626_dio_set_irq(dev, cmd->scan_begin_arg); | |
020c44f3 HS |
1751 | break; |
1752 | } | |
11e865c1 | 1753 | |
020c44f3 HS |
1754 | switch (cmd->convert_src) { |
1755 | case TRIG_NOW: | |
1756 | break; | |
1757 | case TRIG_TIMER: | |
8ee52611 IA |
1758 | /* |
1759 | * set a counter to generate adc trigger at convert_arg | |
1760 | * interval | |
1761 | */ | |
a207c12f | 1762 | tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags); |
11e865c1 | 1763 | |
020c44f3 | 1764 | /* load timer value and enable interrupt */ |
0c9a057c HS |
1765 | s626_timer_load(dev, 4, tick); |
1766 | s626_set_enable(dev, 4, S626_CLKENAB_INDEX); | |
020c44f3 HS |
1767 | break; |
1768 | case TRIG_EXT: | |
8ee52611 IA |
1769 | /* set the digital line and interrupt for convert trigger */ |
1770 | if (cmd->scan_begin_src != TRIG_EXT && | |
1771 | cmd->start_src == TRIG_EXT) | |
020c44f3 | 1772 | s626_dio_set_irq(dev, cmd->convert_arg); |
020c44f3 HS |
1773 | break; |
1774 | } | |
11e865c1 | 1775 | |
31de1948 | 1776 | s626_reset_adc(dev, ppl); |
11e865c1 | 1777 | |
020c44f3 HS |
1778 | switch (cmd->start_src) { |
1779 | case TRIG_NOW: | |
ddd9813e | 1780 | /* Trigger ADC scan loop start */ |
d8515652 | 1781 | /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */ |
11e865c1 | 1782 | |
ddd9813e | 1783 | /* Start executing the RPS program */ |
d8515652 | 1784 | s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1); |
020c44f3 HS |
1785 | s->async->inttrig = NULL; |
1786 | break; | |
1787 | case TRIG_EXT: | |
1788 | /* configure DIO channel for acquisition trigger */ | |
1789 | s626_dio_set_irq(dev, cmd->start_arg); | |
020c44f3 HS |
1790 | s->async->inttrig = NULL; |
1791 | break; | |
1792 | case TRIG_INT: | |
1793 | s->async->inttrig = s626_ai_inttrig; | |
1794 | break; | |
11e865c1 | 1795 | } |
b6c77757 | 1796 | |
020c44f3 | 1797 | /* enable interrupt */ |
de9cd5ca | 1798 | writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER); |
b6c77757 | 1799 | |
020c44f3 HS |
1800 | return 0; |
1801 | } | |
b6c77757 | 1802 | |
020c44f3 HS |
1803 | static int s626_ai_cmdtest(struct comedi_device *dev, |
1804 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
1805 | { | |
1806 | int err = 0; | |
c646efe1 | 1807 | unsigned int arg; |
b6c77757 | 1808 | |
27020ffe | 1809 | /* Step 1 : check if triggers are trivially valid */ |
b6c77757 | 1810 | |
d044e28f IA |
1811 | err |= comedi_check_trigger_src(&cmd->start_src, |
1812 | TRIG_NOW | TRIG_INT | TRIG_EXT); | |
1813 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, | |
1814 | TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW); | |
1815 | err |= comedi_check_trigger_src(&cmd->convert_src, | |
1816 | TRIG_TIMER | TRIG_EXT | TRIG_NOW); | |
1817 | err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
1818 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); | |
11e865c1 | 1819 | |
020c44f3 HS |
1820 | if (err) |
1821 | return 1; | |
11e865c1 | 1822 | |
27020ffe | 1823 | /* Step 2a : make sure trigger sources are unique */ |
11e865c1 | 1824 | |
d044e28f IA |
1825 | err |= comedi_check_trigger_is_unique(cmd->start_src); |
1826 | err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); | |
1827 | err |= comedi_check_trigger_is_unique(cmd->convert_src); | |
1828 | err |= comedi_check_trigger_is_unique(cmd->stop_src); | |
27020ffe HS |
1829 | |
1830 | /* Step 2b : and mutually compatible */ | |
020c44f3 HS |
1831 | |
1832 | if (err) | |
1833 | return 2; | |
1834 | ||
478da5c9 | 1835 | /* Step 3: check if arguments are trivially valid */ |
020c44f3 | 1836 | |
478da5c9 HS |
1837 | switch (cmd->start_src) { |
1838 | case TRIG_NOW: | |
1839 | case TRIG_INT: | |
d044e28f | 1840 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
478da5c9 HS |
1841 | break; |
1842 | case TRIG_EXT: | |
d044e28f | 1843 | err |= comedi_check_trigger_arg_max(&cmd->start_arg, 39); |
478da5c9 HS |
1844 | break; |
1845 | } | |
1846 | ||
53a254b9 | 1847 | if (cmd->scan_begin_src == TRIG_EXT) |
d044e28f | 1848 | err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 39); |
53a254b9 | 1849 | if (cmd->convert_src == TRIG_EXT) |
d044e28f | 1850 | err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 39); |
11e865c1 | 1851 | |
676921c9 IA |
1852 | #define S626_MAX_SPEED 200000 /* in nanoseconds */ |
1853 | #define S626_MIN_SPEED 2000000000 /* in nanoseconds */ | |
11e865c1 | 1854 | |
020c44f3 | 1855 | if (cmd->scan_begin_src == TRIG_TIMER) { |
d044e28f IA |
1856 | err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, |
1857 | S626_MAX_SPEED); | |
1858 | err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, | |
1859 | S626_MIN_SPEED); | |
020c44f3 | 1860 | } else { |
d044e28f IA |
1861 | /* |
1862 | * external trigger | |
1863 | * should be level/edge, hi/lo specification here | |
1864 | * should specify multiple external triggers | |
1865 | * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9); | |
1866 | */ | |
020c44f3 HS |
1867 | } |
1868 | if (cmd->convert_src == TRIG_TIMER) { | |
d044e28f IA |
1869 | err |= comedi_check_trigger_arg_min(&cmd->convert_arg, |
1870 | S626_MAX_SPEED); | |
1871 | err |= comedi_check_trigger_arg_max(&cmd->convert_arg, | |
1872 | S626_MIN_SPEED); | |
020c44f3 | 1873 | } else { |
d044e28f IA |
1874 | /* |
1875 | * external trigger - see above | |
1876 | * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9); | |
1877 | */ | |
020c44f3 | 1878 | } |
11e865c1 | 1879 | |
d044e28f IA |
1880 | err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, |
1881 | cmd->chanlist_len); | |
53a254b9 HS |
1882 | |
1883 | if (cmd->stop_src == TRIG_COUNT) | |
d044e28f | 1884 | err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); |
53a254b9 | 1885 | else /* TRIG_NONE */ |
d044e28f | 1886 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
11e865c1 | 1887 | |
020c44f3 HS |
1888 | if (err) |
1889 | return 3; | |
1890 | ||
1891 | /* step 4: fix up any arguments */ | |
1892 | ||
1893 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
c646efe1 | 1894 | arg = cmd->scan_begin_arg; |
a207c12f | 1895 | s626_ns_to_timer(&arg, cmd->flags); |
d044e28f | 1896 | err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg); |
020c44f3 | 1897 | } |
c646efe1 | 1898 | |
020c44f3 | 1899 | if (cmd->convert_src == TRIG_TIMER) { |
c646efe1 | 1900 | arg = cmd->convert_arg; |
a207c12f | 1901 | s626_ns_to_timer(&arg, cmd->flags); |
d044e28f | 1902 | err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg); |
c646efe1 HS |
1903 | |
1904 | if (cmd->scan_begin_src == TRIG_TIMER) { | |
1905 | arg = cmd->convert_arg * cmd->scan_end_arg; | |
d044e28f IA |
1906 | err |= comedi_check_trigger_arg_min(&cmd-> |
1907 | scan_begin_arg, | |
1908 | arg); | |
020c44f3 | 1909 | } |
11e865c1 | 1910 | } |
11e865c1 | 1911 | |
020c44f3 HS |
1912 | if (err) |
1913 | return 4; | |
1914 | ||
1915 | return 0; | |
11e865c1 GP |
1916 | } |
1917 | ||
020c44f3 | 1918 | static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
11e865c1 | 1919 | { |
7f2f7e05 HS |
1920 | struct s626_private *devpriv = dev->private; |
1921 | ||
c5cf4606 | 1922 | /* Stop RPS program in case it is currently running */ |
d8515652 | 1923 | s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1); |
11e865c1 | 1924 | |
020c44f3 | 1925 | /* disable master interrupt */ |
de9cd5ca | 1926 | writel(0, dev->mmio + S626_P_IER); |
11e865c1 | 1927 | |
020c44f3 | 1928 | devpriv->ai_cmd_running = 0; |
11e865c1 | 1929 | |
020c44f3 HS |
1930 | return 0; |
1931 | } | |
11e865c1 | 1932 | |
18259ffc HS |
1933 | static int s626_ao_insn_write(struct comedi_device *dev, |
1934 | struct comedi_subdevice *s, | |
1935 | struct comedi_insn *insn, | |
1936 | unsigned int *data) | |
11e865c1 | 1937 | { |
18259ffc | 1938 | unsigned int chan = CR_CHAN(insn->chanspec); |
020c44f3 | 1939 | int i; |
11e865c1 | 1940 | |
020c44f3 | 1941 | for (i = 0; i < insn->n; i++) { |
e45c2379 | 1942 | s16 dacdata = (s16)data[i]; |
18259ffc HS |
1943 | int ret; |
1944 | ||
020c44f3 | 1945 | dacdata -= (0x1fff); |
11e865c1 | 1946 | |
a7aa94ce CS |
1947 | ret = s626_set_dac(dev, chan, dacdata); |
1948 | if (ret) | |
1949 | return ret; | |
11e865c1 | 1950 | |
18259ffc HS |
1951 | s->readback[chan] = data[i]; |
1952 | } | |
11e865c1 | 1953 | |
18259ffc | 1954 | return insn->n; |
020c44f3 | 1955 | } |
11e865c1 | 1956 | |
8ee52611 IA |
1957 | /* *************** DIGITAL I/O FUNCTIONS *************** */ |
1958 | ||
1959 | /* | |
020c44f3 HS |
1960 | * All DIO functions address a group of DIO channels by means of |
1961 | * "group" argument. group may be 0, 1 or 2, which correspond to DIO | |
1962 | * ports A, B and C, respectively. | |
1963 | */ | |
11e865c1 | 1964 | |
020c44f3 HS |
1965 | static void s626_dio_init(struct comedi_device *dev) |
1966 | { | |
0bc45380 | 1967 | u16 group; |
11e865c1 | 1968 | |
8ee52611 | 1969 | /* Prepare to treat writes to WRCapSel as capture disables. */ |
d8515652 | 1970 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP); |
11e865c1 | 1971 | |
8ee52611 | 1972 | /* For each group of sixteen channels ... */ |
020c44f3 | 1973 | for (group = 0; group < S626_DIO_BANKS; group++) { |
100b4edc | 1974 | /* Disable all interrupts */ |
d8515652 | 1975 | s626_debi_write(dev, S626_LP_WRINTSEL(group), 0); |
100b4edc | 1976 | /* Disable all event captures */ |
d8515652 | 1977 | s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff); |
100b4edc | 1978 | /* Init all DIOs to default edge polarity */ |
d8515652 | 1979 | s626_debi_write(dev, S626_LP_WREDGSEL(group), 0); |
100b4edc | 1980 | /* Program all outputs to inactive state */ |
d8515652 | 1981 | s626_debi_write(dev, S626_LP_WRDOUT(group), 0); |
11e865c1 | 1982 | } |
020c44f3 | 1983 | } |
11e865c1 | 1984 | |
020c44f3 HS |
1985 | static int s626_dio_insn_bits(struct comedi_device *dev, |
1986 | struct comedi_subdevice *s, | |
1515e522 HS |
1987 | struct comedi_insn *insn, |
1988 | unsigned int *data) | |
020c44f3 | 1989 | { |
100b4edc | 1990 | unsigned long group = (unsigned long)s->private; |
11e865c1 | 1991 | |
6ea79c1d | 1992 | if (comedi_dio_update_state(s, data)) |
d8515652 | 1993 | s626_debi_write(dev, S626_LP_WRDOUT(group), s->state); |
6ea79c1d | 1994 | |
d8515652 | 1995 | data[1] = s626_debi_read(dev, S626_LP_RDDIN(group)); |
11e865c1 | 1996 | |
020c44f3 | 1997 | return insn->n; |
11e865c1 GP |
1998 | } |
1999 | ||
020c44f3 HS |
2000 | static int s626_dio_insn_config(struct comedi_device *dev, |
2001 | struct comedi_subdevice *s, | |
e920fad2 HS |
2002 | struct comedi_insn *insn, |
2003 | unsigned int *data) | |
11e865c1 | 2004 | { |
100b4edc | 2005 | unsigned long group = (unsigned long)s->private; |
ddf62f2c HS |
2006 | int ret; |
2007 | ||
2008 | ret = comedi_dio_insn_config(dev, s, insn, data, 0); | |
2009 | if (ret) | |
2010 | return ret; | |
11e865c1 | 2011 | |
d8515652 | 2012 | s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits); |
11e865c1 | 2013 | |
e920fad2 | 2014 | return insn->n; |
11e865c1 GP |
2015 | } |
2016 | ||
8ee52611 IA |
2017 | /* |
2018 | * Now this function initializes the value of the counter (data[0]) | |
2019 | * and set the subdevice. To complete with trigger and interrupt | |
2020 | * configuration. | |
2021 | * | |
2022 | * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating | |
affdc230 | 2023 | * what is being configured, but this function appears to be using data[0] |
8ee52611 IA |
2024 | * as a variable. |
2025 | */ | |
020c44f3 HS |
2026 | static int s626_enc_insn_config(struct comedi_device *dev, |
2027 | struct comedi_subdevice *s, | |
2028 | struct comedi_insn *insn, unsigned int *data) | |
2029 | { | |
0c9a057c | 2030 | unsigned int chan = CR_CHAN(insn->chanspec); |
0bc45380 | 2031 | u16 setup = |
d8515652 | 2032 | /* Preload upon index. */ |
0830ada5 | 2033 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 2034 | /* Disable hardware index. */ |
0830ada5 | 2035 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 2036 | /* Operating mode is Counter. */ |
0830ada5 | 2037 | S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) | |
d8515652 | 2038 | /* Active high clock. */ |
0830ada5 | 2039 | S626_SET_STD_CLKPOL(S626_CLKPOL_POS) | |
d8515652 | 2040 | /* Clock multiplier is 1x. */ |
0830ada5 IA |
2041 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
2042 | /* Enabled by index */ | |
2043 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); | |
c3e3a56d | 2044 | /* uint16_t disable_int_src = true; */ |
8ee52611 | 2045 | /* uint32_t Preloadvalue; //Counter initial value */ |
0bc45380 SR |
2046 | u16 value_latchsrc = S626_LATCHSRC_AB_READ; |
2047 | u16 enab = S626_CLKENAB_ALWAYS; | |
11e865c1 | 2048 | |
8ee52611 | 2049 | /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */ |
11e865c1 | 2050 | |
0c9a057c HS |
2051 | s626_set_mode(dev, chan, setup, true); |
2052 | s626_preload(dev, chan, data[0]); | |
2053 | s626_pulse_index(dev, chan); | |
2054 | s626_set_latch_source(dev, chan, value_latchsrc); | |
2055 | s626_set_enable(dev, chan, (enab != 0)); | |
11e865c1 | 2056 | |
020c44f3 HS |
2057 | return insn->n; |
2058 | } | |
11e865c1 | 2059 | |
020c44f3 HS |
2060 | static int s626_enc_insn_read(struct comedi_device *dev, |
2061 | struct comedi_subdevice *s, | |
81202ecf HS |
2062 | struct comedi_insn *insn, |
2063 | unsigned int *data) | |
020c44f3 | 2064 | { |
81202ecf | 2065 | unsigned int chan = CR_CHAN(insn->chanspec); |
0bc45380 | 2066 | u16 cntr_latch_reg = S626_LP_CNTR(chan); |
81202ecf | 2067 | int i; |
11e865c1 | 2068 | |
81202ecf HS |
2069 | for (i = 0; i < insn->n; i++) { |
2070 | unsigned int val; | |
11e865c1 | 2071 | |
81202ecf HS |
2072 | /* |
2073 | * Read the counter's output latch LSW/MSW. | |
2074 | * Latches on LSW read. | |
2075 | */ | |
2076 | val = s626_debi_read(dev, cntr_latch_reg); | |
2077 | val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16); | |
2078 | data[i] = val; | |
2079 | } | |
2080 | ||
2081 | return insn->n; | |
020c44f3 | 2082 | } |
11e865c1 | 2083 | |
020c44f3 HS |
2084 | static int s626_enc_insn_write(struct comedi_device *dev, |
2085 | struct comedi_subdevice *s, | |
2086 | struct comedi_insn *insn, unsigned int *data) | |
2087 | { | |
0c9a057c | 2088 | unsigned int chan = CR_CHAN(insn->chanspec); |
11e865c1 | 2089 | |
8ee52611 | 2090 | /* Set the preload register */ |
0c9a057c | 2091 | s626_preload(dev, chan, data[0]); |
11e865c1 | 2092 | |
8ee52611 IA |
2093 | /* |
2094 | * Software index pulse forces the preload register to load | |
2095 | * into the counter | |
2096 | */ | |
0c9a057c HS |
2097 | s626_set_load_trig(dev, chan, 0); |
2098 | s626_pulse_index(dev, chan); | |
2099 | s626_set_load_trig(dev, chan, 2); | |
11e865c1 | 2100 | |
020c44f3 | 2101 | return 1; |
11e865c1 GP |
2102 | } |
2103 | ||
0bc45380 | 2104 | static void s626_write_misc2(struct comedi_device *dev, u16 new_image) |
11e865c1 | 2105 | { |
d8515652 IA |
2106 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE); |
2107 | s626_debi_write(dev, S626_LP_WRMISC2, new_image); | |
2108 | s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE); | |
020c44f3 | 2109 | } |
11e865c1 | 2110 | |
31de1948 | 2111 | static void s626_counters_init(struct comedi_device *dev) |
11e865c1 | 2112 | { |
020c44f3 | 2113 | int chan; |
0bc45380 | 2114 | u16 setup = |
d8515652 | 2115 | /* Preload upon index. */ |
0830ada5 | 2116 | S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) | |
d8515652 | 2117 | /* Disable hardware index. */ |
0830ada5 | 2118 | S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) | |
d8515652 | 2119 | /* Operating mode is counter. */ |
0830ada5 | 2120 | S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) | |
d8515652 | 2121 | /* Active high clock. */ |
0830ada5 | 2122 | S626_SET_STD_CLKPOL(S626_CLKPOL_POS) | |
d8515652 | 2123 | /* Clock multiplier is 1x. */ |
0830ada5 | 2124 | S626_SET_STD_CLKMULT(S626_CLKMULT_1X) | |
d8515652 | 2125 | /* Enabled by index */ |
0830ada5 | 2126 | S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX); |
8ee52611 IA |
2127 | |
2128 | /* | |
2129 | * Disable all counter interrupts and clear any captured counter events. | |
2130 | */ | |
020c44f3 | 2131 | for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) { |
0c9a057c HS |
2132 | s626_set_mode(dev, chan, setup, true); |
2133 | s626_set_int_src(dev, chan, 0); | |
2134 | s626_reset_cap_flags(dev, chan); | |
2135 | s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS); | |
020c44f3 | 2136 | } |
020c44f3 | 2137 | } |
11e865c1 | 2138 | |
b7047895 HS |
2139 | static int s626_allocate_dma_buffers(struct comedi_device *dev) |
2140 | { | |
2141 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); | |
7f2f7e05 | 2142 | struct s626_private *devpriv = dev->private; |
b7047895 HS |
2143 | void *addr; |
2144 | dma_addr_t appdma; | |
2145 | ||
d8515652 | 2146 | addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma); |
b7047895 HS |
2147 | if (!addr) |
2148 | return -ENOMEM; | |
07a36d66 IA |
2149 | devpriv->ana_buf.logical_base = addr; |
2150 | devpriv->ana_buf.physical_base = appdma; | |
b7047895 | 2151 | |
d8515652 | 2152 | addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma); |
b7047895 HS |
2153 | if (!addr) |
2154 | return -ENOMEM; | |
07a36d66 IA |
2155 | devpriv->rps_buf.logical_base = addr; |
2156 | devpriv->rps_buf.physical_base = appdma; | |
b7047895 | 2157 | |
b7047895 HS |
2158 | return 0; |
2159 | } | |
2160 | ||
3757e795 HS |
2161 | static void s626_free_dma_buffers(struct comedi_device *dev) |
2162 | { | |
2163 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); | |
2164 | struct s626_private *devpriv = dev->private; | |
2165 | ||
2166 | if (!devpriv) | |
2167 | return; | |
2168 | ||
2169 | if (devpriv->rps_buf.logical_base) | |
2170 | pci_free_consistent(pcidev, S626_DMABUF_SIZE, | |
2171 | devpriv->rps_buf.logical_base, | |
2172 | devpriv->rps_buf.physical_base); | |
2173 | if (devpriv->ana_buf.logical_base) | |
2174 | pci_free_consistent(pcidev, S626_DMABUF_SIZE, | |
2175 | devpriv->ana_buf.logical_base, | |
2176 | devpriv->ana_buf.physical_base); | |
2177 | } | |
2178 | ||
a7aa94ce | 2179 | static int s626_initialize(struct comedi_device *dev) |
020c44f3 | 2180 | { |
7f2f7e05 | 2181 | struct s626_private *devpriv = dev->private; |
f1f7efce | 2182 | dma_addr_t phys_buf; |
0bc45380 | 2183 | u16 chan; |
020c44f3 | 2184 | int i; |
a7aa94ce | 2185 | int ret; |
11e865c1 | 2186 | |
54a2a02e | 2187 | /* Enable DEBI and audio pins, enable I2C interface */ |
d8515652 IA |
2188 | s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C, |
2189 | S626_P_MC1); | |
54a2a02e HS |
2190 | |
2191 | /* | |
8ee52611 | 2192 | * Configure DEBI operating mode |
54a2a02e | 2193 | * |
8ee52611 IA |
2194 | * Local bus is 16 bits wide |
2195 | * Declare DEBI transfer timeout interval | |
2196 | * Set up byte lane steering | |
2197 | * Intel-compatible local bus (DEBI never times out) | |
54a2a02e | 2198 | */ |
d8515652 IA |
2199 | writel(S626_DEBI_CFG_SLAVE16 | |
2200 | (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP | | |
de9cd5ca | 2201 | S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG); |
54a2a02e HS |
2202 | |
2203 | /* Disable MMU paging */ | |
de9cd5ca | 2204 | writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE); |
54a2a02e HS |
2205 | |
2206 | /* Init GPIO so that ADC Start* is negated */ | |
de9cd5ca | 2207 | writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO); |
68ad0ae0 | 2208 | |
17553c88 | 2209 | /* I2C device address for onboard eeprom (revb) */ |
07a36d66 | 2210 | devpriv->i2c_adrs = 0xA0; |
11e865c1 | 2211 | |
54a2a02e HS |
2212 | /* |
2213 | * Issue an I2C ABORT command to halt any I2C | |
2214 | * operation in progress and reset BUSY flag. | |
2215 | */ | |
d8515652 | 2216 | writel(S626_I2C_CLKSEL | S626_I2C_ABORT, |
de9cd5ca | 2217 | dev->mmio + S626_P_I2CSTAT); |
d8515652 | 2218 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
571845c6 CS |
2219 | ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0); |
2220 | if (ret) | |
2221 | return ret; | |
68ad0ae0 | 2222 | |
54a2a02e HS |
2223 | /* |
2224 | * Per SAA7146 data sheet, write to STATUS | |
2225 | * reg twice to reset all I2C error flags. | |
2226 | */ | |
68ad0ae0 | 2227 | for (i = 0; i < 2; i++) { |
de9cd5ca | 2228 | writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT); |
d8515652 | 2229 | s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2); |
2061d410 RKM |
2230 | ret = comedi_timeout(dev, NULL, |
2231 | NULL, s626_i2c_handshake_eoc, 0); | |
571845c6 CS |
2232 | if (ret) |
2233 | return ret; | |
68ad0ae0 | 2234 | } |
11e865c1 | 2235 | |
54a2a02e HS |
2236 | /* |
2237 | * Init audio interface functional attributes: set DAC/ADC | |
68ad0ae0 HS |
2238 | * serial clock rates, invert DAC serial clock so that |
2239 | * DAC data setup times are satisfied, enable DAC serial | |
2240 | * clock out. | |
2241 | */ | |
de9cd5ca | 2242 | writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2); |
11e865c1 | 2243 | |
54a2a02e HS |
2244 | /* |
2245 | * Set up TSL1 slot list, which is used to control the | |
d8515652 IA |
2246 | * accumulation of ADC data: S626_RSD1 = shift data in on SD1. |
2247 | * S626_SIB_A1 = store data uint8_t at next available location | |
54a2a02e HS |
2248 | * in FB BUFFER1 register. |
2249 | */ | |
de9cd5ca | 2250 | writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1); |
d8515652 | 2251 | writel(S626_RSD1 | S626_SIB_A1 | S626_EOS, |
de9cd5ca | 2252 | dev->mmio + S626_P_TSL1 + 4); |
11e865c1 | 2253 | |
54a2a02e | 2254 | /* Enable TSL1 slot list so that it executes all the time */ |
de9cd5ca | 2255 | writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1); |
11e865c1 | 2256 | |
54a2a02e HS |
2257 | /* |
2258 | * Initialize RPS registers used for ADC | |
2259 | */ | |
11e865c1 | 2260 | |
54a2a02e | 2261 | /* Physical start of RPS program */ |
b13db6bf | 2262 | writel((u32)devpriv->rps_buf.physical_base, |
de9cd5ca | 2263 | dev->mmio + S626_P_RPSADDR1); |
54a2a02e | 2264 | /* RPS program performs no explicit mem writes */ |
de9cd5ca | 2265 | writel(0, dev->mmio + S626_P_RPSPAGE1); |
54a2a02e | 2266 | /* Disable RPS timeouts */ |
de9cd5ca | 2267 | writel(0, dev->mmio + S626_P_RPS1_TOUT); |
11e865c1 | 2268 | |
59747847 HS |
2269 | #if 0 |
2270 | /* | |
2271 | * SAA7146 BUG WORKAROUND | |
2272 | * | |
2273 | * Initialize SAA7146 ADC interface to a known state by | |
2274 | * invoking ADCs until FB BUFFER 1 register shows that it | |
2275 | * is correctly receiving ADC data. This is necessary | |
2276 | * because the SAA7146 ADC interface does not start up in | |
2277 | * a defined state after a PCI reset. | |
68ad0ae0 | 2278 | */ |
59747847 | 2279 | { |
9c9ab3c1 | 2280 | struct comedi_subdevice *s = dev->read_subdev; |
f1f7efce IA |
2281 | uint8_t poll_list; |
2282 | uint16_t adc_data; | |
2283 | uint16_t start_val; | |
8ee52611 IA |
2284 | uint16_t index; |
2285 | unsigned int data[16]; | |
59747847 | 2286 | |
8ee52611 | 2287 | /* Create a simple polling list for analog input channel 0 */ |
d8515652 | 2288 | poll_list = S626_EOPL; |
31de1948 | 2289 | s626_reset_adc(dev, &poll_list); |
59747847 | 2290 | |
8ee52611 | 2291 | /* Get initial ADC value */ |
9c9ab3c1 | 2292 | s626_ai_rinsn(dev, s, NULL, data); |
f1f7efce | 2293 | start_val = data[0]; |
59747847 | 2294 | |
8ee52611 IA |
2295 | /* |
2296 | * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED | |
2297 | * EXECUTION. | |
2298 | * | |
2299 | * Invoke ADCs until the new ADC value differs from the initial | |
2300 | * value or a timeout occurs. The timeout protects against the | |
2301 | * possibility that the driver is restarting and the ADC data is | |
2302 | * a fixed value resulting from the applied ADC analog input | |
2303 | * being unusually quiet or at the rail. | |
2304 | */ | |
2305 | for (index = 0; index < 500; index++) { | |
9c9ab3c1 | 2306 | s626_ai_rinsn(dev, s, NULL, data); |
f1f7efce IA |
2307 | adc_data = data[0]; |
2308 | if (adc_data != start_val) | |
8ee52611 IA |
2309 | break; |
2310 | } | |
59747847 HS |
2311 | } |
2312 | #endif /* SAA7146 BUG WORKAROUND */ | |
11e865c1 | 2313 | |
54a2a02e HS |
2314 | /* |
2315 | * Initialize the DAC interface | |
2316 | */ | |
11e865c1 | 2317 | |
54a2a02e HS |
2318 | /* |
2319 | * Init Audio2's output DMAC attributes: | |
2320 | * burst length = 1 DWORD | |
2321 | * threshold = 1 DWORD. | |
68ad0ae0 | 2322 | */ |
de9cd5ca | 2323 | writel(0, dev->mmio + S626_P_PCI_BT_A); |
68ad0ae0 | 2324 | |
54a2a02e HS |
2325 | /* |
2326 | * Init Audio2's output DMA physical addresses. The protection | |
68ad0ae0 HS |
2327 | * address is set to 1 DWORD past the base address so that a |
2328 | * single DWORD will be transferred each time a DMA transfer is | |
54a2a02e HS |
2329 | * enabled. |
2330 | */ | |
f1f7efce | 2331 | phys_buf = devpriv->ana_buf.physical_base + |
b13db6bf SR |
2332 | (S626_DAC_WDMABUF_OS * sizeof(u32)); |
2333 | writel((u32)phys_buf, dev->mmio + S626_P_BASEA2_OUT); | |
2334 | writel((u32)(phys_buf + sizeof(u32)), | |
de9cd5ca | 2335 | dev->mmio + S626_P_PROTA2_OUT); |
68ad0ae0 | 2336 | |
54a2a02e HS |
2337 | /* |
2338 | * Cache Audio2's output DMA buffer logical address. This is | |
2339 | * where DAC data is buffered for A2 output DMA transfers. | |
2340 | */ | |
b13db6bf | 2341 | devpriv->dac_wbuf = (u32 *)devpriv->ana_buf.logical_base + |
d8515652 | 2342 | S626_DAC_WDMABUF_OS; |
68ad0ae0 | 2343 | |
54a2a02e HS |
2344 | /* |
2345 | * Audio2's output channels does not use paging. The | |
2346 | * protection violation handling bit is set so that the | |
2347 | * DMAC will automatically halt and its PCI address pointer | |
2348 | * will be reset when the protection address is reached. | |
2349 | */ | |
de9cd5ca | 2350 | writel(8, dev->mmio + S626_P_PAGEA2_OUT); |
68ad0ae0 | 2351 | |
54a2a02e HS |
2352 | /* |
2353 | * Initialize time slot list 2 (TSL2), which is used to control | |
68ad0ae0 HS |
2354 | * the clock generation for and serialization of data to be sent |
2355 | * to the DAC devices. Slot 0 is a NOP that is used to trap TSL | |
2356 | * execution; this permits other slots to be safely modified | |
2357 | * without first turning off the TSL sequencer (which is | |
2358 | * apparently impossible to do). Also, SD3 (which is driven by a | |
2359 | * pull-up resistor) is shifted in and stored to the MSB of | |
2360 | * FB_BUFFER2 to be used as evidence that the slot sequence has | |
2361 | * not yet finished executing. | |
2362 | */ | |
11e865c1 | 2363 | |
54a2a02e | 2364 | /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */ |
d8515652 | 2365 | writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS, |
de9cd5ca | 2366 | dev->mmio + S626_VECTPORT(0)); |
11e865c1 | 2367 | |
54a2a02e HS |
2368 | /* |
2369 | * Initialize slot 1, which is constant. Slot 1 causes a | |
68ad0ae0 HS |
2370 | * DWORD to be transferred from audio channel 2's output FIFO |
2371 | * to the FIFO's output buffer so that it can be serialized | |
2372 | * and sent to the DAC during subsequent slots. All remaining | |
2373 | * slots are dynamically populated as required by the target | |
2374 | * DAC device. | |
2375 | */ | |
54a2a02e HS |
2376 | |
2377 | /* Slot 1: Fetch DWORD from Audio2's output FIFO */ | |
de9cd5ca | 2378 | writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1)); |
11e865c1 | 2379 | |
54a2a02e | 2380 | /* Start DAC's audio interface (TSL2) running */ |
de9cd5ca | 2381 | writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1); |
11e865c1 | 2382 | |
54a2a02e HS |
2383 | /* |
2384 | * Init Trim DACs to calibrated values. Do it twice because the | |
68ad0ae0 HS |
2385 | * SAA7146 audio channel does not always reset properly and |
2386 | * sometimes causes the first few TrimDAC writes to malfunction. | |
2387 | */ | |
31de1948 | 2388 | s626_load_trim_dacs(dev); |
a7aa94ce CS |
2389 | ret = s626_load_trim_dacs(dev); |
2390 | if (ret) | |
2391 | return ret; | |
11e865c1 | 2392 | |
54a2a02e HS |
2393 | /* |
2394 | * Manually init all gate array hardware in case this is a soft | |
68ad0ae0 HS |
2395 | * reset (we have no way of determining whether this is a warm |
2396 | * or cold start). This is necessary because the gate array will | |
2397 | * reset only in response to a PCI hard reset; there is no soft | |
54a2a02e HS |
2398 | * reset function. |
2399 | */ | |
11e865c1 | 2400 | |
54a2a02e HS |
2401 | /* |
2402 | * Init all DAC outputs to 0V and init all DAC setpoint and | |
68ad0ae0 HS |
2403 | * polarity images. |
2404 | */ | |
a7aa94ce CS |
2405 | for (chan = 0; chan < S626_DAC_CHANNELS; chan++) { |
2406 | ret = s626_set_dac(dev, chan, 0); | |
2407 | if (ret) | |
2408 | return ret; | |
2409 | } | |
11e865c1 | 2410 | |
54a2a02e | 2411 | /* Init counters */ |
31de1948 | 2412 | s626_counters_init(dev); |
11e865c1 | 2413 | |
54a2a02e HS |
2414 | /* |
2415 | * Without modifying the state of the Battery Backup enab, disable | |
68ad0ae0 HS |
2416 | * the watchdog timer, set DIO channels 0-5 to operate in the |
2417 | * standard DIO (vs. counter overflow) mode, disable the battery | |
2418 | * charger, and reset the watchdog interval selector to zero. | |
2419 | */ | |
d8515652 IA |
2420 | s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) & |
2421 | S626_MISC2_BATT_ENABLE)); | |
11e865c1 | 2422 | |
54a2a02e | 2423 | /* Initialize the digital I/O subsystem */ |
68ad0ae0 | 2424 | s626_dio_init(dev); |
a7aa94ce CS |
2425 | |
2426 | return 0; | |
80ec9510 HS |
2427 | } |
2428 | ||
a690b7e5 | 2429 | static int s626_auto_attach(struct comedi_device *dev, |
6c7d2c8b | 2430 | unsigned long context_unused) |
80ec9510 | 2431 | { |
750af5e5 | 2432 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
7f2f7e05 | 2433 | struct s626_private *devpriv; |
80ec9510 HS |
2434 | struct comedi_subdevice *s; |
2435 | int ret; | |
2436 | ||
0bdab509 | 2437 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
c34fa261 HS |
2438 | if (!devpriv) |
2439 | return -ENOMEM; | |
80ec9510 | 2440 | |
818f569f | 2441 | ret = comedi_pci_enable(dev); |
80ec9510 HS |
2442 | if (ret) |
2443 | return ret; | |
80ec9510 | 2444 | |
de9cd5ca HS |
2445 | dev->mmio = pci_ioremap_bar(pcidev, 0); |
2446 | if (!dev->mmio) | |
80ec9510 HS |
2447 | return -ENOMEM; |
2448 | ||
2449 | /* disable master interrupt */ | |
de9cd5ca | 2450 | writel(0, dev->mmio + S626_P_IER); |
80ec9510 HS |
2451 | |
2452 | /* soft reset */ | |
de9cd5ca | 2453 | writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1); |
80ec9510 HS |
2454 | |
2455 | /* DMA FIXME DMA// */ | |
2456 | ||
2457 | ret = s626_allocate_dma_buffers(dev); | |
2458 | if (ret) | |
2459 | return ret; | |
2460 | ||
2461 | if (pcidev->irq) { | |
2462 | ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED, | |
2463 | dev->board_name, dev); | |
2464 | ||
2465 | if (ret == 0) | |
2466 | dev->irq = pcidev->irq; | |
2467 | } | |
2468 | ||
2469 | ret = comedi_alloc_subdevices(dev, 6); | |
2470 | if (ret) | |
2471 | return ret; | |
2472 | ||
f0717f5d | 2473 | s = &dev->subdevices[0]; |
80ec9510 | 2474 | /* analog input subdevice */ |
ca2f1091 | 2475 | s->type = COMEDI_SUBD_AI; |
f95321f3 | 2476 | s->subdev_flags = SDF_READABLE | SDF_DIFF; |
ca2f1091 HS |
2477 | s->n_chan = S626_ADC_CHANNELS; |
2478 | s->maxdata = 0x3fff; | |
2479 | s->range_table = &s626_range_table; | |
2480 | s->len_chanlist = S626_ADC_CHANNELS; | |
ca2f1091 | 2481 | s->insn_read = s626_ai_insn_read; |
2281befd HS |
2482 | if (dev->irq) { |
2483 | dev->read_subdev = s; | |
f95321f3 | 2484 | s->subdev_flags |= SDF_CMD_READ; |
2281befd HS |
2485 | s->do_cmd = s626_ai_cmd; |
2486 | s->do_cmdtest = s626_ai_cmdtest; | |
2487 | s->cancel = s626_ai_cancel; | |
2488 | } | |
80ec9510 | 2489 | |
f0717f5d | 2490 | s = &dev->subdevices[1]; |
80ec9510 | 2491 | /* analog output subdevice */ |
ca2f1091 HS |
2492 | s->type = COMEDI_SUBD_AO; |
2493 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2494 | s->n_chan = S626_DAC_CHANNELS; | |
2495 | s->maxdata = 0x3fff; | |
2496 | s->range_table = &range_bipolar10; | |
18259ffc | 2497 | s->insn_write = s626_ao_insn_write; |
18259ffc HS |
2498 | |
2499 | ret = comedi_alloc_subdev_readback(s); | |
2500 | if (ret) | |
2501 | return ret; | |
80ec9510 | 2502 | |
f0717f5d | 2503 | s = &dev->subdevices[2]; |
80ec9510 | 2504 | /* digital I/O subdevice */ |
ca2f1091 HS |
2505 | s->type = COMEDI_SUBD_DIO; |
2506 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2507 | s->n_chan = 16; | |
2508 | s->maxdata = 1; | |
2509 | s->io_bits = 0xffff; | |
2510 | s->private = (void *)0; /* DIO group 0 */ | |
2511 | s->range_table = &range_digital; | |
2512 | s->insn_config = s626_dio_insn_config; | |
2513 | s->insn_bits = s626_dio_insn_bits; | |
80ec9510 | 2514 | |
f0717f5d | 2515 | s = &dev->subdevices[3]; |
80ec9510 | 2516 | /* digital I/O subdevice */ |
ca2f1091 HS |
2517 | s->type = COMEDI_SUBD_DIO; |
2518 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2519 | s->n_chan = 16; | |
2520 | s->maxdata = 1; | |
2521 | s->io_bits = 0xffff; | |
2522 | s->private = (void *)1; /* DIO group 1 */ | |
2523 | s->range_table = &range_digital; | |
2524 | s->insn_config = s626_dio_insn_config; | |
2525 | s->insn_bits = s626_dio_insn_bits; | |
80ec9510 | 2526 | |
f0717f5d | 2527 | s = &dev->subdevices[4]; |
80ec9510 | 2528 | /* digital I/O subdevice */ |
ca2f1091 HS |
2529 | s->type = COMEDI_SUBD_DIO; |
2530 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE; | |
2531 | s->n_chan = 16; | |
2532 | s->maxdata = 1; | |
2533 | s->io_bits = 0xffff; | |
2534 | s->private = (void *)2; /* DIO group 2 */ | |
2535 | s->range_table = &range_digital; | |
8ee52611 | 2536 | s->insn_config = s626_dio_insn_config; |
ca2f1091 | 2537 | s->insn_bits = s626_dio_insn_bits; |
80ec9510 | 2538 | |
f0717f5d | 2539 | s = &dev->subdevices[5]; |
80ec9510 | 2540 | /* encoder (counter) subdevice */ |
ca2f1091 HS |
2541 | s->type = COMEDI_SUBD_COUNTER; |
2542 | s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL; | |
2543 | s->n_chan = S626_ENCODER_CHANNELS; | |
2544 | s->maxdata = 0xffffff; | |
ca2f1091 HS |
2545 | s->range_table = &range_unknown; |
2546 | s->insn_config = s626_enc_insn_config; | |
2547 | s->insn_read = s626_enc_insn_read; | |
2548 | s->insn_write = s626_enc_insn_write; | |
80ec9510 | 2549 | |
71b9f42e | 2550 | return s626_initialize(dev); |
11e865c1 GP |
2551 | } |
2552 | ||
020c44f3 | 2553 | static void s626_detach(struct comedi_device *dev) |
11e865c1 | 2554 | { |
7f2f7e05 | 2555 | struct s626_private *devpriv = dev->private; |
f574af6d | 2556 | |
020c44f3 HS |
2557 | if (devpriv) { |
2558 | /* stop ai_command */ | |
2559 | devpriv->ai_cmd_running = 0; | |
11e865c1 | 2560 | |
de9cd5ca | 2561 | if (dev->mmio) { |
020c44f3 | 2562 | /* interrupt mask */ |
25f8fd5e | 2563 | /* Disable master interrupt */ |
de9cd5ca | 2564 | writel(0, dev->mmio + S626_P_IER); |
25f8fd5e | 2565 | /* Clear board's IRQ status flag */ |
d8515652 | 2566 | writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, |
de9cd5ca | 2567 | dev->mmio + S626_P_ISR); |
11e865c1 | 2568 | |
8ee52611 | 2569 | /* Disable the watchdog timer and battery charger. */ |
31de1948 | 2570 | s626_write_misc2(dev, 0); |
11e865c1 | 2571 | |
25f8fd5e | 2572 | /* Close all interfaces on 7146 device */ |
de9cd5ca HS |
2573 | writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1); |
2574 | writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1); | |
020c44f3 | 2575 | } |
f574af6d | 2576 | } |
8075bfb6 | 2577 | comedi_pci_detach(dev); |
3757e795 | 2578 | s626_free_dma_buffers(dev); |
11e865c1 | 2579 | } |
7122b76d | 2580 | |
75e6301b | 2581 | static struct comedi_driver s626_driver = { |
7122b76d HS |
2582 | .driver_name = "s626", |
2583 | .module = THIS_MODULE, | |
750af5e5 | 2584 | .auto_attach = s626_auto_attach, |
7122b76d HS |
2585 | .detach = s626_detach, |
2586 | }; | |
2587 | ||
a690b7e5 | 2588 | static int s626_pci_probe(struct pci_dev *dev, |
b8f4ac23 | 2589 | const struct pci_device_id *id) |
7122b76d | 2590 | { |
b8f4ac23 | 2591 | return comedi_pci_auto_config(dev, &s626_driver, id->driver_data); |
7122b76d HS |
2592 | } |
2593 | ||
7122b76d HS |
2594 | /* |
2595 | * For devices with vendor:device id == 0x1131:0x7146 you must specify | |
2596 | * also subvendor:subdevice ids, because otherwise it will conflict with | |
2597 | * Philips SAA7146 media/dvb based cards. | |
2598 | */ | |
41e043fc | 2599 | static const struct pci_device_id s626_pci_table[] = { |
498c5070 IA |
2600 | { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146, |
2601 | 0x6000, 0x0272) }, | |
7122b76d HS |
2602 | { 0 } |
2603 | }; | |
2604 | MODULE_DEVICE_TABLE(pci, s626_pci_table); | |
2605 | ||
75e6301b HS |
2606 | static struct pci_driver s626_pci_driver = { |
2607 | .name = "s626", | |
7122b76d | 2608 | .id_table = s626_pci_table, |
75e6301b | 2609 | .probe = s626_pci_probe, |
9901a4d7 | 2610 | .remove = comedi_pci_auto_unconfig, |
7122b76d | 2611 | }; |
75e6301b | 2612 | module_comedi_pci_driver(s626_driver, s626_pci_driver); |
7122b76d HS |
2613 | |
2614 | MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>"); | |
2615 | MODULE_DESCRIPTION("Sensoray 626 Comedi driver module"); | |
2616 | MODULE_LICENSE("GPL"); |