]>
Commit | Line | Data |
---|---|---|
7963eb43 JW |
1 | /*************************************************************************** |
2 | * Copyright (c) 2005-2009, Broadcom Corporation. | |
3 | * | |
4 | * Name: crystalhd_misc . h | |
5 | * | |
6 | * Description: | |
7 | * BCM70012 Linux driver general purpose routines. | |
8 | * Includes reg/mem read and write routines. | |
9 | * | |
10 | * HISTORY: | |
11 | * | |
12 | ********************************************************************** | |
13 | * This file is part of the crystalhd device driver. | |
14 | * | |
15 | * This driver is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License as published by | |
17 | * the Free Software Foundation, version 2 of the License. | |
18 | * | |
19 | * This driver is distributed in the hope that it will be useful, | |
20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | * GNU General Public License for more details. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License | |
25 | * along with this driver. If not, see <http://www.gnu.org/licenses/>. | |
26 | **********************************************************************/ | |
27 | ||
28 | #ifndef _CRYSTALHD_MISC_H_ | |
29 | #define _CRYSTALHD_MISC_H_ | |
30 | ||
01c32070 JV |
31 | #include "crystalhd.h" |
32 | ||
7963eb43 JW |
33 | #include <linux/module.h> |
34 | #include <linux/kernel.h> | |
35 | #include <linux/errno.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/ioctl.h> | |
38 | #include <linux/dma-mapping.h> | |
7963eb43 | 39 | #include <linux/sched.h> |
9ffc93f2 | 40 | #include "bc_dts_glob_lnx.h" |
7963eb43 JW |
41 | |
42 | /* Global log level variable defined in crystal_misc.c file */ | |
43 | extern uint32_t g_linklog_level; | |
44 | ||
45 | /* Global element pool for all Queue management. | |
46 | * TX: Active = BC_TX_LIST_CNT, Free = BC_TX_LIST_CNT. | |
47 | * RX: Free = BC_RX_LIST_CNT, Active = 2 | |
48 | * FW-CMD: 4 | |
49 | */ | |
50 | #define BC_LINK_ELEM_POOL_SZ ((BC_TX_LIST_CNT * 2) + BC_RX_LIST_CNT + 2 + 4) | |
51 | ||
52 | /* Driver's IODATA pool count */ | |
53 | #define CHD_IODATA_POOL_SZ (BC_IOCTL_DATA_POOL_SIZE * BC_LINK_MAX_OPENS) | |
54 | ||
55 | /* Scatter Gather memory pool size for Tx and Rx */ | |
56 | #define BC_LINK_SG_POOL_SZ (BC_TX_LIST_CNT + BC_RX_LIST_CNT) | |
57 | ||
abfc768d | 58 | enum crystalhd_dio_sig { |
7963eb43 JW |
59 | crystalhd_dio_inv = 0, |
60 | crystalhd_dio_locked, | |
61 | crystalhd_dio_sg_mapped, | |
62 | }; | |
63 | ||
64 | struct crystalhd_dio_user_info { | |
65 | void *xfr_buff; | |
66 | uint32_t xfr_len; | |
67 | uint32_t uv_offset; | |
68 | bool dir_tx; | |
69 | ||
70 | uint32_t uv_sg_ix; | |
71 | uint32_t uv_sg_off; | |
72 | int comp_sts; | |
73 | int ev_sts; | |
74 | uint32_t y_done_sz; | |
75 | uint32_t uv_done_sz; | |
76 | uint32_t comp_flags; | |
77 | bool b422mode; | |
78 | }; | |
79 | ||
abfc768d | 80 | struct crystalhd_dio_req { |
7963eb43 JW |
81 | uint32_t sig; |
82 | uint32_t max_pages; | |
83 | struct page **pages; | |
84 | struct scatterlist *sg; | |
85 | int sg_cnt; | |
86 | int page_cnt; | |
87 | int direction; | |
88 | struct crystalhd_dio_user_info uinfo; | |
89 | void *fb_va; | |
90 | uint32_t fb_size; | |
91 | dma_addr_t fb_pa; | |
abfc768d LD |
92 | struct crystalhd_dio_req *next; |
93 | }; | |
7963eb43 JW |
94 | |
95 | #define BC_LINK_DIOQ_SIG (0x09223280) | |
96 | ||
abfc768d LD |
97 | struct crystalhd_elem { |
98 | struct crystalhd_elem *flink; | |
99 | struct crystalhd_elem *blink; | |
7963eb43 JW |
100 | void *data; |
101 | uint32_t tag; | |
abfc768d | 102 | }; |
7963eb43 JW |
103 | |
104 | typedef void (*crystalhd_data_free_cb)(void *context, void *data); | |
105 | ||
abfc768d | 106 | struct crystalhd_dioq { |
7963eb43 JW |
107 | uint32_t sig; |
108 | struct crystalhd_adp *adp; | |
abfc768d LD |
109 | struct crystalhd_elem *head; |
110 | struct crystalhd_elem *tail; | |
7963eb43 JW |
111 | uint32_t count; |
112 | spinlock_t lock; | |
113 | wait_queue_head_t event; | |
114 | crystalhd_data_free_cb data_rel_cb; | |
115 | void *cb_context; | |
abfc768d | 116 | }; |
7963eb43 | 117 | |
abfc768d LD |
118 | typedef void (*hw_comp_callback)(struct crystalhd_dio_req *, |
119 | wait_queue_head_t *event, enum BC_STATUS sts); | |
7963eb43 JW |
120 | |
121 | /*========= Decoder (7412) register access routines.================= */ | |
122 | uint32_t bc_dec_reg_rd(struct crystalhd_adp *, uint32_t); | |
123 | void bc_dec_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); | |
124 | ||
125 | /*========= Link (70012) register access routines.. =================*/ | |
126 | uint32_t crystalhd_reg_rd(struct crystalhd_adp *, uint32_t); | |
127 | void crystalhd_reg_wr(struct crystalhd_adp *, uint32_t, uint32_t); | |
128 | ||
129 | /*========= Decoder (7412) memory access routines..=================*/ | |
d7c9455a AG |
130 | enum BC_STATUS crystalhd_mem_rd(struct crystalhd_adp *, |
131 | uint32_t, uint32_t, uint32_t *); | |
132 | enum BC_STATUS crystalhd_mem_wr(struct crystalhd_adp *, | |
133 | uint32_t, uint32_t, uint32_t *); | |
7963eb43 JW |
134 | |
135 | /*==========Link (70012) PCIe Config access routines.================*/ | |
d7c9455a AG |
136 | enum BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, |
137 | uint32_t, uint32_t, uint32_t *); | |
138 | enum BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, | |
139 | uint32_t, uint32_t, uint32_t); | |
7963eb43 JW |
140 | |
141 | /*========= Linux Kernel Interface routines. ======================= */ | |
142 | void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *); | |
143 | void bc_kern_dma_free(struct crystalhd_adp *, uint32_t, | |
144 | void *, dma_addr_t); | |
145 | #define crystalhd_create_event(_ev) init_waitqueue_head(_ev) | |
146 | #define crystalhd_set_event(_ev) wake_up_interruptible(_ev) | |
147 | #define crystalhd_wait_on_event(ev, condition, timeout, ret, nosig) \ | |
148 | do { \ | |
149 | DECLARE_WAITQUEUE(entry, current); \ | |
150 | unsigned long end = jiffies + ((timeout * HZ) / 1000); \ | |
151 | ret = 0; \ | |
152 | add_wait_queue(ev, &entry); \ | |
153 | for (;;) { \ | |
154 | __set_current_state(TASK_INTERRUPTIBLE); \ | |
155 | if (condition) { \ | |
156 | break; \ | |
157 | } \ | |
158 | if (time_after_eq(jiffies, end)) { \ | |
159 | ret = -EBUSY; \ | |
160 | break; \ | |
161 | } \ | |
162 | schedule_timeout((HZ / 100 > 1) ? HZ / 100 : 1); \ | |
163 | if (!nosig && signal_pending(current)) { \ | |
164 | ret = -EINTR; \ | |
165 | break; \ | |
166 | } \ | |
167 | } \ | |
168 | __set_current_state(TASK_RUNNING); \ | |
169 | remove_wait_queue(ev, &entry); \ | |
170 | } while (0) | |
171 | ||
172 | /*================ Direct IO mapping routines ==================*/ | |
173 | extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t); | |
174 | extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *); | |
d7c9455a AG |
175 | extern enum BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, |
176 | uint32_t, uint32_t, bool, bool, struct crystalhd_dio_req**); | |
7963eb43 | 177 | |
d7c9455a AG |
178 | extern enum BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, |
179 | struct crystalhd_dio_req*); | |
df23983c SL |
180 | #define crystalhd_get_sgle_paddr(_dio, _ix) (sg_dma_address(&_dio->sg[_ix])) |
181 | #define crystalhd_get_sgle_len(_dio, _ix) (sg_dma_len(&_dio->sg[_ix])) | |
7963eb43 JW |
182 | |
183 | /*================ General Purpose Queues ==================*/ | |
d7c9455a AG |
184 | extern enum BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, |
185 | struct crystalhd_dioq **, crystalhd_data_free_cb , void *); | |
186 | extern void crystalhd_delete_dioq(struct crystalhd_adp *, | |
187 | struct crystalhd_dioq *); | |
188 | extern enum BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, | |
189 | void *data, bool wake, uint32_t tag); | |
abfc768d | 190 | extern void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq); |
d7c9455a AG |
191 | extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, |
192 | uint32_t tag); | |
193 | extern void *crystalhd_dioq_fetch_wait(struct crystalhd_dioq *ioq, | |
194 | uint32_t to_secs, uint32_t *sig_pend); | |
7963eb43 JW |
195 | |
196 | #define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0) | |
197 | ||
198 | extern int crystalhd_create_elem_pool(struct crystalhd_adp *, uint32_t); | |
199 | extern void crystalhd_delete_elem_pool(struct crystalhd_adp *); | |
200 | ||
201 | ||
202 | /*================ Debug routines/macros .. ================================*/ | |
d7c9455a AG |
203 | extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, |
204 | uint32_t dwcount); | |
7963eb43 JW |
205 | |
206 | enum _chd_log_levels { | |
207 | BCMLOG_ERROR = 0x80000000, /* Don't disable this option */ | |
208 | BCMLOG_DATA = 0x40000000, /* Data, enable by default */ | |
cc922722 | 209 | BCMLOG_SPINLOCK = 0x20000000, /* Special case for Spin locks*/ |
7963eb43 JW |
210 | |
211 | /* Following are allowed only in debug mode */ | |
212 | BCMLOG_INFO = 0x00000001, /* Generic informational */ | |
213 | BCMLOG_DBG = 0x00000002, /* First level Debug info */ | |
214 | BCMLOG_SSTEP = 0x00000004, /* Stepping information */ | |
7963eb43 JW |
215 | }; |
216 | ||
413db8c1 JV |
217 | |
218 | #define BCMLOG(trace, fmt, args...) \ | |
219 | do { \ | |
220 | if (g_linklog_level & trace) \ | |
221 | printk(fmt, ##args); \ | |
222 | } while (0) | |
223 | ||
224 | ||
225 | #define BCMLOG_ERR(fmt, args...) \ | |
226 | do { \ | |
227 | if (g_linklog_level & BCMLOG_ERROR) \ | |
228 | printk(KERN_ERR "*ERR*:%s:%d: "fmt, \ | |
229 | __FILE__, __LINE__, ##args); \ | |
230 | } while (0) | |
7963eb43 JW |
231 | |
232 | #endif |