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Merge tag 'xfs-for-linus-3.20-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-artful-kernel.git] / drivers / staging / dgnc / dgnc_neo.c
CommitLineData
0b99d589
LL		 1/*
2 * Copyright 2003 Digi International (www.digi.com)
3 * Scott H Kilau <Scott_Kilau at digi dot com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
5ba5b89a 9 *
0b99d589 10 * This program is distributed in the hope that it will be useful,
5ba5b89a
LL		 11 * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
12 * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
0b99d589 13 * PURPOSE. See the GNU General Public License for more details.
5ba5b89a 14 *
0b99d589
LL		 15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 *
20 * NOTE TO LINUX KERNEL HACKERS: DO NOT REFORMAT THIS CODE!
21 *
22 * This is shared code between Digi's CVS archive and the
23 * Linux Kernel sources.
24 * Changing the source just for reformatting needlessly breaks
25 * our CVS diff history.
26 *
27 * Send any bug fixes/changes to: Eng.Linux at digi dot com.
28 * Thank you.
29 *
0b99d589
LL		 30 */
31
32
33#include <linux/kernel.h>
0b99d589
LL		 34#include <linux/sched.h> /* For jiffies, task states */
35#include <linux/interrupt.h> /* For tasklet and interrupt structs/defines */
36#include <linux/delay.h> /* For udelay */
9dfe5670 37#include <linux/io.h> /* For read[bwl]/write[bwl] */
0b99d589
LL		 38#include <linux/serial.h> /* For struct async_serial */
39#include <linux/serial_reg.h> /* For the various UART offsets */
40
41#include "dgnc_driver.h" /* Driver main header file */
42#include "dgnc_neo.h" /* Our header file */
43#include "dgnc_tty.h"
0b99d589 44
03425f55
LL		 45static inline void neo_parse_lsr(struct dgnc_board *brd, uint port);
46static inline void neo_parse_isr(struct dgnc_board *brd, uint port);
0b99d589
LL		 47static void neo_copy_data_from_uart_to_queue(struct channel_t *ch);
48static inline void neo_clear_break(struct channel_t *ch, int force);
49static inline void neo_set_cts_flow_control(struct channel_t *ch);
50static inline void neo_set_rts_flow_control(struct channel_t *ch);
51static inline void neo_set_ixon_flow_control(struct channel_t *ch);
52static inline void neo_set_ixoff_flow_control(struct channel_t *ch);
53static inline void neo_set_no_output_flow_control(struct channel_t *ch);
54static inline void neo_set_no_input_flow_control(struct channel_t *ch);
55static inline void neo_set_new_start_stop_chars(struct channel_t *ch);
446393e9 56static void neo_parse_modem(struct channel_t *ch, unsigned char signals);
0b99d589 57static void neo_tasklet(unsigned long data);
03425f55 58static void neo_vpd(struct dgnc_board *brd);
0b99d589
LL		 59static void neo_uart_init(struct channel_t *ch);
60static void neo_uart_off(struct channel_t *ch);
61static int neo_drain(struct tty_struct *tty, uint seconds);
62static void neo_param(struct tty_struct *tty);
63static void neo_assert_modem_signals(struct channel_t *ch);
64static void neo_flush_uart_write(struct channel_t *ch);
65static void neo_flush_uart_read(struct channel_t *ch);
66static void neo_disable_receiver(struct channel_t *ch);
67static void neo_enable_receiver(struct channel_t *ch);
68static void neo_send_break(struct channel_t *ch, int msecs);
69static void neo_send_start_character(struct channel_t *ch);
70static void neo_send_stop_character(struct channel_t *ch);
71static void neo_copy_data_from_queue_to_uart(struct channel_t *ch);
72static uint neo_get_uart_bytes_left(struct channel_t *ch);
73static void neo_send_immediate_char(struct channel_t *ch, unsigned char c);
74static irqreturn_t neo_intr(int irq, void *voidbrd);
75
76
77struct board_ops dgnc_neo_ops = {
78 .tasklet = neo_tasklet,
79 .intr = neo_intr,
80 .uart_init = neo_uart_init,
81 .uart_off = neo_uart_off,
82 .drain = neo_drain,
83 .param = neo_param,
84 .vpd = neo_vpd,
85 .assert_modem_signals = neo_assert_modem_signals,
86 .flush_uart_write = neo_flush_uart_write,
87 .flush_uart_read = neo_flush_uart_read,
88 .disable_receiver = neo_disable_receiver,
89 .enable_receiver = neo_enable_receiver,
90 .send_break = neo_send_break,
91 .send_start_character = neo_send_start_character,
92 .send_stop_character = neo_send_stop_character,
93 .copy_data_from_queue_to_uart = neo_copy_data_from_queue_to_uart,
94 .get_uart_bytes_left = neo_get_uart_bytes_left,
95 .send_immediate_char = neo_send_immediate_char
96};
5ba5b89a 97
0b99d589
LL		 98static uint dgnc_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
99
100
101/*
102 * This function allows calls to ensure that all outstanding
103 * PCI writes have been completed, by doing a PCI read against
104 * a non-destructive, read-only location on the Neo card.
105 *
106 * In this case, we are reading the DVID (Read-only Device Identification)
107 * value of the Neo card.
108 */
03425f55 109static inline void neo_pci_posting_flush(struct dgnc_board *bd)
0b99d589
LL		 110{
111 readb(bd->re_map_membase + 0x8D);
112}
113
114static inline void neo_set_cts_flow_control(struct channel_t *ch)
115{
446393e9
EA		 116 unsigned char ier = readb(&ch->ch_neo_uart->ier);
117 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589
LL		 118
119
0b99d589
LL		 120 /* Turn on auto CTS flow control */
121#if 1
122 ier |= (UART_17158_IER_CTSDSR);
123#else
124 ier &= ~(UART_17158_IER_CTSDSR);
125#endif
126
127 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
128
5ba5b89a 129 /* Turn off auto Xon flow control */
0b99d589
LL		 130 efr &= ~(UART_17158_EFR_IXON);
131
132 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
133 writeb(0, &ch->ch_neo_uart->efr);
134
135 /* Turn on UART enhanced bits */
136 writeb(efr, &ch->ch_neo_uart->efr);
137
138 /* Turn on table D, with 8 char hi/low watermarks */
139 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
140
141 /* Feed the UART our trigger levels */
142 writeb(8, &ch->ch_neo_uart->tfifo);
143 ch->ch_t_tlevel = 8;
144
145 writeb(ier, &ch->ch_neo_uart->ier);
146
147 neo_pci_posting_flush(ch->ch_bd);
148}
149
150
151static inline void neo_set_rts_flow_control(struct channel_t *ch)
152{
446393e9
EA		 153 unsigned char ier = readb(&ch->ch_neo_uart->ier);
154 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 155
0b99d589
LL		 156 /* Turn on auto RTS flow control */
157#if 1
158 ier |= (UART_17158_IER_RTSDTR);
159#else
160 ier &= ~(UART_17158_IER_RTSDTR);
161#endif
162 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
163
164 /* Turn off auto Xoff flow control */
165 ier &= ~(UART_17158_IER_XOFF);
166 efr &= ~(UART_17158_EFR_IXOFF);
167
168 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
169 writeb(0, &ch->ch_neo_uart->efr);
170
171 /* Turn on UART enhanced bits */
172 writeb(efr, &ch->ch_neo_uart->efr);
173
174 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
175 ch->ch_r_watermark = 4;
176
177 writeb(32, &ch->ch_neo_uart->rfifo);
178 ch->ch_r_tlevel = 32;
179
180 writeb(ier, &ch->ch_neo_uart->ier);
181
182 /*
183 * From the Neo UART spec sheet:
184 * The auto RTS/DTR function must be started by asserting
185 * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
186 * it is enabled.
187 */
188 ch->ch_mostat |= (UART_MCR_RTS);
189
190 neo_pci_posting_flush(ch->ch_bd);
191}
192
193
194static inline void neo_set_ixon_flow_control(struct channel_t *ch)
195{
446393e9
EA		 196 unsigned char ier = readb(&ch->ch_neo_uart->ier);
197 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 198
0b99d589
LL		 199 /* Turn off auto CTS flow control */
200 ier &= ~(UART_17158_IER_CTSDSR);
201 efr &= ~(UART_17158_EFR_CTSDSR);
202
203 /* Turn on auto Xon flow control */
204 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
205
206 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
207 writeb(0, &ch->ch_neo_uart->efr);
208
209 /* Turn on UART enhanced bits */
210 writeb(efr, &ch->ch_neo_uart->efr);
211
212 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
213 ch->ch_r_watermark = 4;
214
215 writeb(32, &ch->ch_neo_uart->rfifo);
216 ch->ch_r_tlevel = 32;
217
218 /* Tell UART what start/stop chars it should be looking for */
219 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
220 writeb(0, &ch->ch_neo_uart->xonchar2);
221
222 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
223 writeb(0, &ch->ch_neo_uart->xoffchar2);
224
225 writeb(ier, &ch->ch_neo_uart->ier);
226
227 neo_pci_posting_flush(ch->ch_bd);
228}
229
230
231static inline void neo_set_ixoff_flow_control(struct channel_t *ch)
232{
446393e9
EA		 233 unsigned char ier = readb(&ch->ch_neo_uart->ier);
234 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 235
0b99d589
LL		 236 /* Turn off auto RTS flow control */
237 ier &= ~(UART_17158_IER_RTSDTR);
238 efr &= ~(UART_17158_EFR_RTSDTR);
239
240 /* Turn on auto Xoff flow control */
241 ier |= (UART_17158_IER_XOFF);
242 efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
243
244 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
245 writeb(0, &ch->ch_neo_uart->efr);
246
247 /* Turn on UART enhanced bits */
248 writeb(efr, &ch->ch_neo_uart->efr);
249
250 /* Turn on table D, with 8 char hi/low watermarks */
251 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
252
253 writeb(8, &ch->ch_neo_uart->tfifo);
00804f77 254 ch->ch_t_tlevel = 8;
0b99d589
LL		 255
256 /* Tell UART what start/stop chars it should be looking for */
257 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
258 writeb(0, &ch->ch_neo_uart->xonchar2);
259
260 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
261 writeb(0, &ch->ch_neo_uart->xoffchar2);
262
263 writeb(ier, &ch->ch_neo_uart->ier);
264
265 neo_pci_posting_flush(ch->ch_bd);
266}
267
268
269static inline void neo_set_no_input_flow_control(struct channel_t *ch)
270{
446393e9
EA		 271 unsigned char ier = readb(&ch->ch_neo_uart->ier);
272 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 273
0b99d589
LL		 274 /* Turn off auto RTS flow control */
275 ier &= ~(UART_17158_IER_RTSDTR);
276 efr &= ~(UART_17158_EFR_RTSDTR);
277
278 /* Turn off auto Xoff flow control */
279 ier &= ~(UART_17158_IER_XOFF);
280 if (ch->ch_c_iflag & IXON)
281 efr &= ~(UART_17158_EFR_IXOFF);
282 else
283 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
284
285
286 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
287 writeb(0, &ch->ch_neo_uart->efr);
288
289 /* Turn on UART enhanced bits */
290 writeb(efr, &ch->ch_neo_uart->efr);
291
292 /* Turn on table D, with 8 char hi/low watermarks */
293 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
294
295 ch->ch_r_watermark = 0;
296
297 writeb(16, &ch->ch_neo_uart->tfifo);
00804f77 298 ch->ch_t_tlevel = 16;
0b99d589
LL		 299
300 writeb(16, &ch->ch_neo_uart->rfifo);
00804f77 301 ch->ch_r_tlevel = 16;
0b99d589
LL		 302
303 writeb(ier, &ch->ch_neo_uart->ier);
304
305 neo_pci_posting_flush(ch->ch_bd);
306}
307
308
309static inline void neo_set_no_output_flow_control(struct channel_t *ch)
310{
446393e9
EA		 311 unsigned char ier = readb(&ch->ch_neo_uart->ier);
312 unsigned char efr = readb(&ch->ch_neo_uart->efr);
0b99d589 313
0b99d589
LL		 314 /* Turn off auto CTS flow control */
315 ier &= ~(UART_17158_IER_CTSDSR);
316 efr &= ~(UART_17158_EFR_CTSDSR);
317
318 /* Turn off auto Xon flow control */
319 if (ch->ch_c_iflag & IXOFF)
320 efr &= ~(UART_17158_EFR_IXON);
321 else
322 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
323
324 /* Why? Becuz Exar's spec says we have to zero it out before setting it */
325 writeb(0, &ch->ch_neo_uart->efr);
326
327 /* Turn on UART enhanced bits */
328 writeb(efr, &ch->ch_neo_uart->efr);
329
330 /* Turn on table D, with 8 char hi/low watermarks */
331 writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
332
333 ch->ch_r_watermark = 0;
334
335 writeb(16, &ch->ch_neo_uart->tfifo);
00804f77 336 ch->ch_t_tlevel = 16;
0b99d589
LL		 337
338 writeb(16, &ch->ch_neo_uart->rfifo);
00804f77 339 ch->ch_r_tlevel = 16;
0b99d589
LL		 340
341 writeb(ier, &ch->ch_neo_uart->ier);
342
343 neo_pci_posting_flush(ch->ch_bd);
344}
345
346
347/* change UARTs start/stop chars */
348static inline void neo_set_new_start_stop_chars(struct channel_t *ch)
349{
350
351 /* if hardware flow control is set, then skip this whole thing */
352 if (ch->ch_digi.digi_flags & (CTSPACE | RTSPACE) || ch->ch_c_cflag & CRTSCTS)
353 return;
354
0b99d589
LL		 355 /* Tell UART what start/stop chars it should be looking for */
356 writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
357 writeb(0, &ch->ch_neo_uart->xonchar2);
358
359 writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
360 writeb(0, &ch->ch_neo_uart->xoffchar2);
361
362 neo_pci_posting_flush(ch->ch_bd);
363}
364
365
366/*
367 * No locks are assumed to be held when calling this function.
368 */
369static inline void neo_clear_break(struct channel_t *ch, int force)
370{
7be869b0 371 unsigned long flags;
0b99d589 372
7be869b0 373 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589
LL		 374
375 /* Bail if we aren't currently sending a break. */
376 if (!ch->ch_stop_sending_break) {
7be869b0 377 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 378 return;
379 }
380
381 /* Turn break off, and unset some variables */
382 if (ch->ch_flags & CH_BREAK_SENDING) {
7879be81
MS		 383 if (time_after_eq(jiffies, ch->ch_stop_sending_break)
384 || force) {
446393e9 385 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1eba3dba 386
00804f77 387 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
0b99d589
LL		 388 neo_pci_posting_flush(ch->ch_bd);
389 ch->ch_flags &= ~(CH_BREAK_SENDING);
390 ch->ch_stop_sending_break = 0;
00804f77
LL		 391 }
392 }
7be869b0 393 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 394}
395
396
397/*
398 * Parse the ISR register.
399 */
03425f55 400static inline void neo_parse_isr(struct dgnc_board *brd, uint port)
0b99d589
LL		 401{
402 struct channel_t *ch;
446393e9
EA		 403 unsigned char isr;
404 unsigned char cause;
7be869b0 405 unsigned long flags;
0b99d589
LL		 406
407 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
408 return;
409
410 if (port > brd->maxports)
411 return;
412
413 ch = brd->channels[port];
414 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
415 return;
416
417 /* Here we try to figure out what caused the interrupt to happen */
418 while (1) {
419
420 isr = readb(&ch->ch_neo_uart->isr_fcr);
421
422 /* Bail if no pending interrupt */
50667c67 423 if (isr & UART_IIR_NO_INT)
0b99d589 424 break;
0b99d589
LL		 425
426 /*
427 * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
428 */
429 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
430
0b99d589
LL		 431 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
432 /* Read data from uart -> queue */
433 brd->intr_rx++;
434 ch->ch_intr_rx++;
435 neo_copy_data_from_uart_to_queue(ch);
436
437 /* Call our tty layer to enforce queue flow control if needed. */
7be869b0 438 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 439 dgnc_check_queue_flow_control(ch);
7be869b0 440 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 441 }
442
443 if (isr & UART_IIR_THRI) {
444 brd->intr_tx++;
445 ch->ch_intr_tx++;
446 /* Transfer data (if any) from Write Queue -> UART. */
7be869b0 447 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 448 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
7be869b0 449 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 450 neo_copy_data_from_queue_to_uart(ch);
451 }
452
453 if (isr & UART_17158_IIR_XONXOFF) {
454 cause = readb(&ch->ch_neo_uart->xoffchar1);
455
0b99d589
LL		 456 /*
457 * Since the UART detected either an XON or
458 * XOFF match, we need to figure out which
459 * one it was, so we can suspend or resume data flow.
460 */
461 if (cause == UART_17158_XON_DETECT) {
462 /* Is output stopped right now, if so, resume it */
463 if (brd->channels[port]->ch_flags & CH_STOP) {
7be869b0
RD		 464 spin_lock_irqsave(&ch->ch_lock,
465 flags);
0b99d589 466 ch->ch_flags &= ~(CH_STOP);
7be869b0
RD		 467 spin_unlock_irqrestore(&ch->ch_lock,
468 flags);
0b99d589 469 }
2000c581 470 } else if (cause == UART_17158_XOFF_DETECT) {
0b99d589 471 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
7be869b0
RD		 472 spin_lock_irqsave(&ch->ch_lock,
473 flags);
0b99d589 474 ch->ch_flags |= CH_STOP;
7be869b0
RD		 475 spin_unlock_irqrestore(&ch->ch_lock,
476 flags);
0b99d589 477 }
0b99d589
LL		 478 }
479 }
480
481 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
482 /*
483 * If we get here, this means the hardware is doing auto flow control.
484 * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
485 */
486 brd->intr_modem++;
487 ch->ch_intr_modem++;
488 cause = readb(&ch->ch_neo_uart->mcr);
489 /* Which pin is doing auto flow? RTS or DTR? */
490 if ((cause & 0x4) == 0) {
491 if (cause & UART_MCR_RTS) {
7be869b0
RD		 492 spin_lock_irqsave(&ch->ch_lock,
493 flags);
0b99d589 494 ch->ch_mostat |= UART_MCR_RTS;
7be869b0
RD		 495 spin_unlock_irqrestore(&ch->ch_lock,
496 flags);
2000c581 497 } else {
7be869b0
RD		 498 spin_lock_irqsave(&ch->ch_lock,
499 flags);
0b99d589 500 ch->ch_mostat &= ~(UART_MCR_RTS);
7be869b0
RD		 501 spin_unlock_irqrestore(&ch->ch_lock,
502 flags);
0b99d589
LL		 503 }
504 } else {
505 if (cause & UART_MCR_DTR) {
7be869b0
RD		 506 spin_lock_irqsave(&ch->ch_lock,
507 flags);
0b99d589 508 ch->ch_mostat |= UART_MCR_DTR;
7be869b0
RD		 509 spin_unlock_irqrestore(&ch->ch_lock,
510 flags);
2000c581 511 } else {
7be869b0
RD		 512 spin_lock_irqsave(&ch->ch_lock,
513 flags);
0b99d589 514 ch->ch_mostat &= ~(UART_MCR_DTR);
7be869b0
RD		 515 spin_unlock_irqrestore(&ch->ch_lock,
516 flags);
0b99d589
LL		 517 }
518 }
519 }
520
521 /* Parse any modem signal changes */
0b99d589
LL		 522 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
523 }
524}
525
526
03425f55 527static inline void neo_parse_lsr(struct dgnc_board *brd, uint port)
0b99d589
LL		 528{
529 struct channel_t *ch;
530 int linestatus;
7be869b0 531 unsigned long flags;
0b99d589 532
1f26adc9
RD		 533 /*
534 * Check to make sure it didn't receive interrupt with a null board
535 * associated or a board pointer that wasn't ours.
536 */
537 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
0b99d589
LL		 538 return;
539
540 if (port > brd->maxports)
541 return;
542
543 ch = brd->channels[port];
544 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
545 return;
546
547 linestatus = readb(&ch->ch_neo_uart->lsr);
548
0b99d589
LL		 549 ch->ch_cached_lsr |= linestatus;
550
551 if (ch->ch_cached_lsr & UART_LSR_DR) {
552 brd->intr_rx++;
553 ch->ch_intr_rx++;
554 /* Read data from uart -> queue */
555 neo_copy_data_from_uart_to_queue(ch);
7be869b0 556 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 557 dgnc_check_queue_flow_control(ch);
7be869b0 558 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 559 }
560
0b99d589
LL		 561 /*
562 * The next 3 tests should *NOT* happen, as the above test
563 * should encapsulate all 3... At least, thats what Exar says.
564 */
565
f1e51745 566 if (linestatus & UART_LSR_PE)
0b99d589 567 ch->ch_err_parity++;
0b99d589 568
f1e51745 569 if (linestatus & UART_LSR_FE)
0b99d589 570 ch->ch_err_frame++;
0b99d589 571
f1e51745 572 if (linestatus & UART_LSR_BI)
0b99d589 573 ch->ch_err_break++;
0b99d589
LL		 574
575 if (linestatus & UART_LSR_OE) {
576 /*
577 * Rx Oruns. Exar says that an orun will NOT corrupt
578 * the FIFO. It will just replace the holding register
579 * with this new data byte. So basically just ignore this.
580 * Probably we should eventually have an orun stat in our driver...
581 */
582 ch->ch_err_overrun++;
0b99d589
LL		 583 }
584
585 if (linestatus & UART_LSR_THRE) {
586 brd->intr_tx++;
587 ch->ch_intr_tx++;
7be869b0 588 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 589 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
7be869b0 590 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 591
592 /* Transfer data (if any) from Write Queue -> UART. */
593 neo_copy_data_from_queue_to_uart(ch);
2000c581 594 } else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
0b99d589
LL		 595 brd->intr_tx++;
596 ch->ch_intr_tx++;
7be869b0 597 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 598 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
7be869b0 599 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 600
601 /* Transfer data (if any) from Write Queue -> UART. */
602 neo_copy_data_from_queue_to_uart(ch);
603 }
604}
605
606
607/*
608 * neo_param()
609 * Send any/all changes to the line to the UART.
610 */
611static void neo_param(struct tty_struct *tty)
612{
446393e9
EA		 613 unsigned char lcr = 0;
614 unsigned char uart_lcr = 0;
615 unsigned char ier = 0;
616 unsigned char uart_ier = 0;
00804f77 617 uint baud = 9600;
0b99d589 618 int quot = 0;
03425f55 619 struct dgnc_board *bd;
0b99d589 620 struct channel_t *ch;
00804f77 621 struct un_t *un;
0b99d589 622
50667c67 623 if (!tty || tty->magic != TTY_MAGIC)
0b99d589 624 return;
0b99d589
LL		 625
626 un = (struct un_t *) tty->driver_data;
50667c67 627 if (!un || un->magic != DGNC_UNIT_MAGIC)
0b99d589 628 return;
0b99d589 629
5ba5b89a 630 ch = un->un_ch;
50667c67 631 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
0b99d589 632 return;
0b99d589
LL		 633
634 bd = ch->ch_bd;
50667c67 635 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
0b99d589 636 return;
0b99d589 637
0b99d589
LL		 638 /*
639 * If baud rate is zero, flush queues, and set mval to drop DTR.
640 */
641 if ((ch->ch_c_cflag & (CBAUD)) == 0) {
587abd7b
SL		 642 ch->ch_r_head = 0;
643 ch->ch_r_tail = 0;
644 ch->ch_e_head = 0;
645 ch->ch_e_tail = 0;
646 ch->ch_w_head = 0;
647 ch->ch_w_tail = 0;
0b99d589
LL		 648
649 neo_flush_uart_write(ch);
650 neo_flush_uart_read(ch);
651
652 /* The baudrate is B0 so all modem lines are to be dropped. */
653 ch->ch_flags |= (CH_BAUD0);
654 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
655 neo_assert_modem_signals(ch);
656 ch->ch_old_baud = 0;
657 return;
658
659 } else if (ch->ch_custom_speed) {
660
661 baud = ch->ch_custom_speed;
662 /* Handle transition from B0 */
663 if (ch->ch_flags & CH_BAUD0) {
664 ch->ch_flags &= ~(CH_BAUD0);
665
666 /*
667 * Bring back up RTS and DTR...
668 * Also handle RTS or DTR toggle if set.
669 */
670 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
671 ch->ch_mostat |= (UART_MCR_RTS);
672 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
673 ch->ch_mostat |= (UART_MCR_DTR);
674 }
675 } else {
676 int iindex = 0;
677 int jindex = 0;
678
679 ulong bauds[4][16] = {
680 { /* slowbaud */
681 0, 50, 75, 110,
682 134, 150, 200, 300,
683 600, 1200, 1800, 2400,
684 4800, 9600, 19200, 38400 },
685 { /* slowbaud & CBAUDEX */
686 0, 57600, 115200, 230400,
687 460800, 150, 200, 921600,
688 600, 1200, 1800, 2400,
689 4800, 9600, 19200, 38400 },
690 { /* fastbaud */
691 0, 57600, 76800, 115200,
692 131657, 153600, 230400, 460800,
693 921600, 1200, 1800, 2400,
694 4800, 9600, 19200, 38400 },
695 { /* fastbaud & CBAUDEX */
696 0, 57600, 115200, 230400,
697 460800, 150, 200, 921600,
698 600, 1200, 1800, 2400,
699 4800, 9600, 19200, 38400 }
700 };
701
702 /* Only use the TXPrint baud rate if the terminal unit is NOT open */
703 if (!(ch->ch_tun.un_flags & UN_ISOPEN) && (un->un_type == DGNC_PRINT))
704 baud = C_BAUD(ch->ch_pun.un_tty) & 0xff;
705 else
706 baud = C_BAUD(ch->ch_tun.un_tty) & 0xff;
707
708 if (ch->ch_c_cflag & CBAUDEX)
709 iindex = 1;
710
711 if (ch->ch_digi.digi_flags & DIGI_FAST)
712 iindex += 2;
713
714 jindex = baud;
715
f1e51745 716 if ((iindex >= 0) && (iindex < 4) && (jindex >= 0) && (jindex < 16))
5ba5b89a 717 baud = bauds[iindex][jindex];
f1e51745 718 else
0b99d589 719 baud = 0;
0b99d589
LL		 720
721 if (baud == 0)
722 baud = 9600;
723
724 /* Handle transition from B0 */
725 if (ch->ch_flags & CH_BAUD0) {
726 ch->ch_flags &= ~(CH_BAUD0);
727
728 /*
729 * Bring back up RTS and DTR...
730 * Also handle RTS or DTR toggle if set.
731 */
732 if (!(ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE))
733 ch->ch_mostat |= (UART_MCR_RTS);
734 if (!(ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE))
735 ch->ch_mostat |= (UART_MCR_DTR);
736 }
737 }
738
50667c67 739 if (ch->ch_c_cflag & PARENB)
0b99d589 740 lcr |= UART_LCR_PARITY;
0b99d589 741
50667c67 742 if (!(ch->ch_c_cflag & PARODD))
0b99d589 743 lcr |= UART_LCR_EPAR;
0b99d589 744
5ba5b89a 745 /*
0b99d589
LL		 746 * Not all platforms support mark/space parity,
747 * so this will hide behind an ifdef.
748 */
749#ifdef CMSPAR
5ba5b89a 750 if (ch->ch_c_cflag & CMSPAR)
0b99d589
LL		 751 lcr |= UART_LCR_SPAR;
752#endif
753
754 if (ch->ch_c_cflag & CSTOPB)
755 lcr |= UART_LCR_STOP;
756
757 switch (ch->ch_c_cflag & CSIZE) {
758 case CS5:
759 lcr |= UART_LCR_WLEN5;
760 break;
761 case CS6:
762 lcr |= UART_LCR_WLEN6;
763 break;
764 case CS7:
765 lcr |= UART_LCR_WLEN7;
766 break;
767 case CS8:
768 default:
769 lcr |= UART_LCR_WLEN8;
770 break;
771 }
772
587abd7b
SL		 773 uart_ier = readb(&ch->ch_neo_uart->ier);
774 ier = uart_ier;
775
0b99d589
LL		 776 uart_lcr = readb(&ch->ch_neo_uart->lcr);
777
778 if (baud == 0)
779 baud = 9600;
780
781 quot = ch->ch_bd->bd_dividend / baud;
782
783 if (quot != 0 && ch->ch_old_baud != baud) {
784 ch->ch_old_baud = baud;
785 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
786 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
787 writeb((quot >> 8), &ch->ch_neo_uart->ier);
788 writeb(lcr, &ch->ch_neo_uart->lcr);
00804f77 789 }
0b99d589
LL		 790
791 if (uart_lcr != lcr)
792 writeb(lcr, &ch->ch_neo_uart->lcr);
793
50667c67 794 if (ch->ch_c_cflag & CREAD)
0b99d589 795 ier |= (UART_IER_RDI | UART_IER_RLSI);
50667c67 796 else
0b99d589 797 ier &= ~(UART_IER_RDI | UART_IER_RLSI);
0b99d589
LL		 798
799 /*
800 * Have the UART interrupt on modem signal changes ONLY when
801 * we are in hardware flow control mode, or CLOCAL/FORCEDCD is not set.
802 */
33cfbaf5
MN		 803 if ((ch->ch_digi.digi_flags & CTSPACE) ||
804 (ch->ch_digi.digi_flags & RTSPACE) ||
805 (ch->ch_c_cflag & CRTSCTS) ||
806 !(ch->ch_digi.digi_flags & DIGI_FORCEDCD) ||
807 !(ch->ch_c_cflag & CLOCAL))
0b99d589 808 ier |= UART_IER_MSI;
33cfbaf5 809 else
0b99d589 810 ier &= ~UART_IER_MSI;
0b99d589
LL		 811
812 ier |= UART_IER_THRI;
813
814 if (ier != uart_ier)
815 writeb(ier, &ch->ch_neo_uart->ier);
816
817 /* Set new start/stop chars */
818 neo_set_new_start_stop_chars(ch);
819
820 if (ch->ch_digi.digi_flags & CTSPACE || ch->ch_c_cflag & CRTSCTS) {
821 neo_set_cts_flow_control(ch);
2000c581 822 } else if (ch->ch_c_iflag & IXON) {
0b99d589
LL		 823 /* If start/stop is set to disable, then we should disable flow control */
824 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
825 neo_set_no_output_flow_control(ch);
826 else
827 neo_set_ixon_flow_control(ch);
2000c581 828 } else {
0b99d589
LL		 829 neo_set_no_output_flow_control(ch);
830 }
831
832 if (ch->ch_digi.digi_flags & RTSPACE || ch->ch_c_cflag & CRTSCTS) {
833 neo_set_rts_flow_control(ch);
2000c581 834 } else if (ch->ch_c_iflag & IXOFF) {
0b99d589
LL		 835 /* If start/stop is set to disable, then we should disable flow control */
836 if ((ch->ch_startc == _POSIX_VDISABLE) || (ch->ch_stopc == _POSIX_VDISABLE))
837 neo_set_no_input_flow_control(ch);
838 else
839 neo_set_ixoff_flow_control(ch);
2000c581 840 } else {
0b99d589
LL		 841 neo_set_no_input_flow_control(ch);
842 }
843
844 /*
845 * Adjust the RX FIFO Trigger level if baud is less than 9600.
846 * Not exactly elegant, but this is needed because of the Exar chip's
847 * delay on firing off the RX FIFO interrupt on slower baud rates.
848 */
849 if (baud < 9600) {
850 writeb(1, &ch->ch_neo_uart->rfifo);
851 ch->ch_r_tlevel = 1;
852 }
853
854 neo_assert_modem_signals(ch);
855
856 /* Get current status of the modem signals now */
857 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
858}
859
860
861/*
862 * Our board poller function.
863 */
864static void neo_tasklet(unsigned long data)
865{
03425f55 866 struct dgnc_board *bd = (struct dgnc_board *) data;
0b99d589 867 struct channel_t *ch;
7be869b0 868 unsigned long flags;
0b99d589
LL		 869 int i;
870 int state = 0;
871 int ports = 0;
872
1f26adc9 873 if (!bd || bd->magic != DGNC_BOARD_MAGIC)
0b99d589 874 return;
0b99d589
LL		 875
876 /* Cache a couple board values */
7be869b0 877 spin_lock_irqsave(&bd->bd_lock, flags);
0b99d589
LL		 878 state = bd->state;
879 ports = bd->nasync;
7be869b0 880 spin_unlock_irqrestore(&bd->bd_lock, flags);
0b99d589
LL		 881
882 /*
883 * Do NOT allow the interrupt routine to read the intr registers
884 * Until we release this lock.
885 */
7be869b0 886 spin_lock_irqsave(&bd->bd_intr_lock, flags);
0b99d589
LL		 887
888 /*
889 * If board is ready, parse deeper to see if there is anything to do.
890 */
891 if ((state == BOARD_READY) && (ports > 0)) {
892 /* Loop on each port */
893 for (i = 0; i < ports; i++) {
894 ch = bd->channels[i];
895
896 /* Just being careful... */
897 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
898 continue;
899
900 /*
901 * NOTE: Remember you CANNOT hold any channel
902 * locks when calling the input routine.
903 *
904 * During input processing, its possible we
905 * will call the Linux ld, which might in turn,
906 * do a callback right back into us, resulting
907 * in us trying to grab the channel lock twice!
908 */
909 dgnc_input(ch);
910
911 /*
912 * Channel lock is grabbed and then released
913 * inside both of these routines, but neither
914 * call anything else that could call back into us.
915 */
916 neo_copy_data_from_queue_to_uart(ch);
917 dgnc_wakeup_writes(ch);
918
919 /*
920 * Call carrier carrier function, in case something
921 * has changed.
922 */
923 dgnc_carrier(ch);
924
925 /*
926 * Check to see if we need to turn off a sending break.
927 * The timing check is done inside clear_break()
928 */
929 if (ch->ch_stop_sending_break)
930 neo_clear_break(ch, 0);
931 }
932 }
933
934 /* Allow interrupt routine to access the interrupt register again */
7be869b0 935 spin_unlock_irqrestore(&bd->bd_intr_lock, flags);
0b99d589
LL		 936
937}
938
939
940/*
941 * dgnc_neo_intr()
942 *
943 * Neo specific interrupt handler.
944 */
945static irqreturn_t neo_intr(int irq, void *voidbrd)
946{
fc33bd29 947 struct dgnc_board *brd = voidbrd;
0b99d589
LL		 948 struct channel_t *ch;
949 int port = 0;
950 int type = 0;
951 int current_port;
952 u32 tmp;
953 u32 uart_poll;
7be869b0
RD		 954 unsigned long flags;
955 unsigned long flags2;
0b99d589 956
0b99d589 957 /*
1f26adc9
RD		 958 * Check to make sure it didn't receive interrupt with a null board
959 * associated or a board pointer that wasn't ours.
0b99d589 960 */
1f26adc9 961 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
0b99d589 962 return IRQ_NONE;
0b99d589
LL		 963
964 brd->intr_count++;
965
966 /* Lock out the slow poller from running on this board. */
7be869b0 967 spin_lock_irqsave(&brd->bd_intr_lock, flags);
0b99d589
LL		 968
969 /*
970 * Read in "extended" IRQ information from the 32bit Neo register.
971 * Bits 0-7: What port triggered the interrupt.
972 * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
973 */
974 uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
975
0b99d589
LL		 976 /*
977 * If 0, no interrupts pending.
978 * This can happen if the IRQ is shared among a couple Neo/Classic boards.
979 */
980 if (!uart_poll) {
7be869b0 981 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
0b99d589
LL		 982 return IRQ_NONE;
983 }
984
985 /* At this point, we have at least SOMETHING to service, dig further... */
986
987 current_port = 0;
988
989 /* Loop on each port */
990 while ((uart_poll & 0xff) != 0) {
991
992 tmp = uart_poll;
993
994 /* Check current port to see if it has interrupt pending */
995 if ((tmp & dgnc_offset_table[current_port]) != 0) {
996 port = current_port;
997 type = tmp >> (8 + (port * 3));
998 type &= 0x7;
999 } else {
1000 current_port++;
1001 continue;
1002 }
1003
0b99d589
LL		 1004 /* Remove this port + type from uart_poll */
1005 uart_poll &= ~(dgnc_offset_table[port]);
1006
1007 if (!type) {
1008 /* If no type, just ignore it, and move onto next port */
0b99d589
LL		 1009 continue;
1010 }
1011
1012 /* Switch on type of interrupt we have */
1013 switch (type) {
1014
1015 case UART_17158_RXRDY_TIMEOUT:
1016 /*
1017 * RXRDY Time-out is cleared by reading data in the
00804f77 1018 * RX FIFO until it falls below the trigger level.
0b99d589
LL		 1019 */
1020
1021 /* Verify the port is in range. */
1022 if (port > brd->nasync)
1023 continue;
1024
1025 ch = brd->channels[port];
1026 neo_copy_data_from_uart_to_queue(ch);
1027
1028 /* Call our tty layer to enforce queue flow control if needed. */
7be869b0 1029 spin_lock_irqsave(&ch->ch_lock, flags2);
0b99d589 1030 dgnc_check_queue_flow_control(ch);
7be869b0 1031 spin_unlock_irqrestore(&ch->ch_lock, flags2);
0b99d589
LL		 1032
1033 continue;
1034
1035 case UART_17158_RX_LINE_STATUS:
1036 /*
1037 * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1038 */
1039 neo_parse_lsr(brd, port);
1040 continue;
1041
1042 case UART_17158_TXRDY:
1043 /*
1044 * TXRDY interrupt clears after reading ISR register for the UART channel.
1045 */
1046
1047 /*
1048 * Yes, this is odd...
1049 * Why would I check EVERY possibility of type of
1050 * interrupt, when we know its TXRDY???
1051 * Becuz for some reason, even tho we got triggered for TXRDY,
79e30af2 1052 * it seems to be occasionally wrong. Instead of TX, which
0b99d589
LL		 1053 * it should be, I was getting things like RXDY too. Weird.
1054 */
1055 neo_parse_isr(brd, port);
1056 continue;
1057
1058 case UART_17158_MSR:
1059 /*
1060 * MSR or flow control was seen.
1061 */
1062 neo_parse_isr(brd, port);
1063 continue;
5ba5b89a 1064
0b99d589
LL		 1065 default:
1066 /*
1067 * The UART triggered us with a bogus interrupt type.
1068 * It appears the Exar chip, when REALLY bogged down, will throw
1069 * these once and awhile.
1070 * Its harmless, just ignore it and move on.
1071 */
0b99d589
LL		 1072 continue;
1073 }
1074 }
1075
1076 /*
1077 * Schedule tasklet to more in-depth servicing at a better time.
1078 */
1079 tasklet_schedule(&brd->helper_tasklet);
1080
7be869b0 1081 spin_unlock_irqrestore(&brd->bd_intr_lock, flags);
0b99d589 1082
0b99d589
LL		 1083 return IRQ_HANDLED;
1084}
1085
1086
1087/*
1088 * Neo specific way of turning off the receiver.
1089 * Used as a way to enforce queue flow control when in
1090 * hardware flow control mode.
1091 */
1092static void neo_disable_receiver(struct channel_t *ch)
1093{
446393e9 1094 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1eba3dba 1095
0b99d589
LL		 1096 tmp &= ~(UART_IER_RDI);
1097 writeb(tmp, &ch->ch_neo_uart->ier);
1098 neo_pci_posting_flush(ch->ch_bd);
1099}
1100
1101
1102/*
1103 * Neo specific way of turning on the receiver.
1104 * Used as a way to un-enforce queue flow control when in
1105 * hardware flow control mode.
1106 */
1107static void neo_enable_receiver(struct channel_t *ch)
1108{
446393e9 1109 unsigned char tmp = readb(&ch->ch_neo_uart->ier);
1eba3dba 1110
0b99d589
LL		 1111 tmp |= (UART_IER_RDI);
1112 writeb(tmp, &ch->ch_neo_uart->ier);
1113 neo_pci_posting_flush(ch->ch_bd);
1114}
1115
1116
1117static void neo_copy_data_from_uart_to_queue(struct channel_t *ch)
1118{
00804f77 1119 int qleft = 0;
446393e9
EA		 1120 unsigned char linestatus = 0;
1121 unsigned char error_mask = 0;
00804f77
LL		 1122 int n = 0;
1123 int total = 0;
0b99d589
LL		 1124 ushort head;
1125 ushort tail;
7be869b0 1126 unsigned long flags;
0b99d589
LL		 1127
1128 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1129 return;
1130
7be869b0 1131 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589
LL		 1132
1133 /* cache head and tail of queue */
1134 head = ch->ch_r_head & RQUEUEMASK;
1135 tail = ch->ch_r_tail & RQUEUEMASK;
1136
1137 /* Get our cached LSR */
1138 linestatus = ch->ch_cached_lsr;
1139 ch->ch_cached_lsr = 0;
1140
1141 /* Store how much space we have left in the queue */
f7c851d4
CP		 1142 qleft = tail - head - 1;
1143 if (qleft < 0)
0b99d589
LL		 1144 qleft += RQUEUEMASK + 1;
1145
1146 /*
1147 * If the UART is not in FIFO mode, force the FIFO copy to
1148 * NOT be run, by setting total to 0.
1149 *
1150 * On the other hand, if the UART IS in FIFO mode, then ask
1151 * the UART to give us an approximation of data it has RX'ed.
1152 */
1153 if (!(ch->ch_flags & CH_FIFO_ENABLED))
1154 total = 0;
1155 else {
1156 total = readb(&ch->ch_neo_uart->rfifo);
1157
1158 /*
1159 * EXAR chip bug - RX FIFO COUNT - Fudge factor.
1160 *
1161 * This resolves a problem/bug with the Exar chip that sometimes
1162 * returns a bogus value in the rfifo register.
1163 * The count can be any where from 0-3 bytes "off".
1164 * Bizarre, but true.
1165 */
50667c67 1166 if ((ch->ch_bd->dvid & 0xf0) >= UART_XR17E158_DVID)
0b99d589 1167 total -= 1;
50667c67 1168 else
0b99d589 1169 total -= 3;
0b99d589
LL		 1170 }
1171
1172
1173 /*
1174 * Finally, bound the copy to make sure we don't overflow
1175 * our own queue...
1176 * The byte by byte copy loop below this loop this will
1177 * deal with the queue overflow possibility.
1178 */
1179 total = min(total, qleft);
1180
5ba5b89a 1181 while (total > 0) {
0b99d589
LL		 1182
1183 /*
1184 * Grab the linestatus register, we need to check
1185 * to see if there are any errors in the FIFO.
1186 */
1187 linestatus = readb(&ch->ch_neo_uart->lsr);
1188
1189 /*
1190 * Break out if there is a FIFO error somewhere.
1191 * This will allow us to go byte by byte down below,
1192 * finding the exact location of the error.
1193 */
1194 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
1195 break;
1196
1197 /* Make sure we don't go over the end of our queue */
1198 n = min(((uint) total), (RQUEUESIZE - (uint) head));
1199
1200 /*
1201 * Cut down n even further if needed, this is to fix
1202 * a problem with memcpy_fromio() with the Neo on the
1203 * IBM pSeries platform.
1204 * 15 bytes max appears to be the magic number.
1205 */
1206 n = min((uint) n, (uint) 12);
1207
1208 /*
1209 * Since we are grabbing the linestatus register, which
1210 * will reset some bits after our read, we need to ensure
1211 * we don't miss our TX FIFO emptys.
1212 */
50667c67 1213 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
0b99d589 1214 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
0b99d589
LL		 1215
1216 linestatus = 0;
1217
1218 /* Copy data from uart to the queue */
1219 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
0b99d589
LL		 1220
1221 /*
1222 * Since RX_FIFO_DATA_ERROR was 0, we are guarenteed
1223 * that all the data currently in the FIFO is free of
1224 * breaks and parity/frame/orun errors.
1225 */
1226 memset(ch->ch_equeue + head, 0, n);
1227
1228 /* Add to and flip head if needed */
1229 head = (head + n) & RQUEUEMASK;
1230 total -= n;
1231 qleft -= n;
1232 ch->ch_rxcount += n;
1233 }
1234
1235 /*
1236 * Create a mask to determine whether we should
1237 * insert the character (if any) into our queue.
1238 */
1239 if (ch->ch_c_iflag & IGNBRK)
1240 error_mask |= UART_LSR_BI;
1241
1242 /*
1243 * Now cleanup any leftover bytes still in the UART.
1244 * Also deal with any possible queue overflow here as well.
1245 */
1246 while (1) {
1247
1248 /*
1249 * Its possible we have a linestatus from the loop above
1250 * this, so we "OR" on any extra bits.
1251 */
1252 linestatus |= readb(&ch->ch_neo_uart->lsr);
1253
1254 /*
1255 * If the chip tells us there is no more data pending to
1256 * be read, we can then leave.
1257 * But before we do, cache the linestatus, just in case.
1258 */
1259 if (!(linestatus & UART_LSR_DR)) {
1260 ch->ch_cached_lsr = linestatus;
1261 break;
1262 }
1263
1264 /* No need to store this bit */
1265 linestatus &= ~UART_LSR_DR;
1266
1267 /*
1268 * Since we are grabbing the linestatus register, which
1269 * will reset some bits after our read, we need to ensure
1270 * we don't miss our TX FIFO emptys.
1271 */
1272 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
1273 linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
1274 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1275 }
1276
1277 /*
1278 * Discard character if we are ignoring the error mask.
1279 */
1280 if (linestatus & error_mask) {
446393e9 1281 unsigned char discard;
1eba3dba 1282
0b99d589
LL		 1283 linestatus = 0;
1284 memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
1285 continue;
1286 }
1287
1288 /*
1289 * If our queue is full, we have no choice but to drop some data.
1290 * The assumption is that HWFLOW or SWFLOW should have stopped
1291 * things way way before we got to this point.
1292 *
1293 * I decided that I wanted to ditch the oldest data first,
1294 * I hope thats okay with everyone? Yes? Good.
1295 */
1296 while (qleft < 1) {
587abd7b
SL		 1297 tail = (tail + 1) & RQUEUEMASK;
1298 ch->ch_r_tail = tail;
0b99d589
LL		 1299 ch->ch_err_overrun++;
1300 qleft++;
1301 }
1302
1303 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
446393e9 1304 ch->ch_equeue[head] = (unsigned char) linestatus;
0b99d589 1305
0b99d589
LL		 1306 /* Ditch any remaining linestatus value. */
1307 linestatus = 0;
1308
1309 /* Add to and flip head if needed */
1310 head = (head + 1) & RQUEUEMASK;
1311
1312 qleft--;
1313 ch->ch_rxcount++;
1314 }
1315
1316 /*
1317 * Write new final heads to channel structure.
1318 */
1319 ch->ch_r_head = head & RQUEUEMASK;
1320 ch->ch_e_head = head & EQUEUEMASK;
1321
7be869b0 1322 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1323}
1324
1325
1326/*
1327 * This function basically goes to sleep for secs, or until
1328 * it gets signalled that the port has fully drained.
1329 */
1330static int neo_drain(struct tty_struct *tty, uint seconds)
1331{
7be869b0 1332 unsigned long flags;
0b99d589 1333 struct channel_t *ch;
00804f77 1334 struct un_t *un;
0b99d589
LL		 1335 int rc = 0;
1336
50667c67 1337 if (!tty || tty->magic != TTY_MAGIC)
8f90ef80 1338 return -ENXIO;
0b99d589
LL		 1339
1340 un = (struct un_t *) tty->driver_data;
50667c67 1341 if (!un || un->magic != DGNC_UNIT_MAGIC)
8f90ef80 1342 return -ENXIO;
0b99d589 1343
5ba5b89a 1344 ch = un->un_ch;
50667c67 1345 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
8f90ef80 1346 return -ENXIO;
0b99d589 1347
7be869b0 1348 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589 1349 un->un_flags |= UN_EMPTY;
7be869b0 1350 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1351
1352 /*
1353 * Go to sleep waiting for the tty layer to wake me back up when
1354 * the empty flag goes away.
1355 *
1356 * NOTE: TODO: Do something with time passed in.
1357 */
1358 rc = wait_event_interruptible(un->un_flags_wait, ((un->un_flags & UN_EMPTY) == 0));
1359
1360 /* If ret is non-zero, user ctrl-c'ed us */
8f90ef80 1361 return rc;
0b99d589 1362}
5ba5b89a 1363
0b99d589
LL		 1364
1365/*
1366 * Flush the WRITE FIFO on the Neo.
1367 *
1368 * NOTE: Channel lock MUST be held before calling this function!
1369 */
1370static void neo_flush_uart_write(struct channel_t *ch)
1371{
446393e9 1372 unsigned char tmp = 0;
0b99d589
LL		 1373 int i = 0;
1374
50667c67 1375 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
0b99d589 1376 return;
0b99d589
LL		 1377
1378 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1379 neo_pci_posting_flush(ch->ch_bd);
1380
1381 for (i = 0; i < 10; i++) {
1382
1383 /* Check to see if the UART feels it completely flushed the FIFO. */
1384 tmp = readb(&ch->ch_neo_uart->isr_fcr);
f1e51745 1385 if (tmp & 4)
0b99d589 1386 udelay(10);
f1e51745 1387 else
0b99d589
LL		 1388 break;
1389 }
1390
1391 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1392}
1393
1394
1395/*
1396 * Flush the READ FIFO on the Neo.
1397 *
1398 * NOTE: Channel lock MUST be held before calling this function!
1399 */
1400static void neo_flush_uart_read(struct channel_t *ch)
1401{
446393e9 1402 unsigned char tmp = 0;
0b99d589
LL		 1403 int i = 0;
1404
50667c67 1405 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
0b99d589 1406 return;
0b99d589
LL		 1407
1408 writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
1409 neo_pci_posting_flush(ch->ch_bd);
1410
1411 for (i = 0; i < 10; i++) {
1412
1413 /* Check to see if the UART feels it completely flushed the FIFO. */
1414 tmp = readb(&ch->ch_neo_uart->isr_fcr);
f1e51745 1415 if (tmp & 2)
0b99d589 1416 udelay(10);
f1e51745 1417 else
0b99d589
LL		 1418 break;
1419 }
1420}
1421
1422
1423static void neo_copy_data_from_queue_to_uart(struct channel_t *ch)
1424{
1425 ushort head;
1426 ushort tail;
1427 int n;
1428 int s;
1429 int qlen;
1430 uint len_written = 0;
7be869b0 1431 unsigned long flags;
0b99d589
LL		 1432
1433 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1434 return;
1435
7be869b0 1436 spin_lock_irqsave(&ch->ch_lock, flags);
0b99d589
LL		 1437
1438 /* No data to write to the UART */
1439 if (ch->ch_w_tail == ch->ch_w_head) {
7be869b0 1440 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1441 return;
1442 }
1443
1444 /* If port is "stopped", don't send any data to the UART */
1445 if ((ch->ch_flags & CH_FORCED_STOP) || (ch->ch_flags & CH_BREAK_SENDING)) {
7be869b0 1446 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1447 return;
1448 }
1449
1450 /*
1451 * If FIFOs are disabled. Send data directly to txrx register
1452 */
1453 if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
446393e9 1454 unsigned char lsrbits = readb(&ch->ch_neo_uart->lsr);
0b99d589
LL		 1455
1456 /* Cache the LSR bits for later parsing */
1457 ch->ch_cached_lsr |= lsrbits;
1458 if (ch->ch_cached_lsr & UART_LSR_THRE) {
1459 ch->ch_cached_lsr &= ~(UART_LSR_THRE);
1460
1461 /*
1462 * If RTS Toggle mode is on, turn on RTS now if not already set,
1463 * and make sure we get an event when the data transfer has completed.
1464 */
1465 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1466 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1467 ch->ch_mostat |= (UART_MCR_RTS);
1468 neo_assert_modem_signals(ch);
1469 }
1470 ch->ch_tun.un_flags |= (UN_EMPTY);
1471 }
1472 /*
1473 * If DTR Toggle mode is on, turn on DTR now if not already set,
1474 * and make sure we get an event when the data transfer has completed.
1475 */
1476 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1477 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1478 ch->ch_mostat |= (UART_MCR_DTR);
1479 neo_assert_modem_signals(ch);
1480 }
1481 ch->ch_tun.un_flags |= (UN_EMPTY);
1482 }
1483
1484 writeb(ch->ch_wqueue[ch->ch_w_tail], &ch->ch_neo_uart->txrx);
0b99d589
LL		 1485 ch->ch_w_tail++;
1486 ch->ch_w_tail &= WQUEUEMASK;
1487 ch->ch_txcount++;
1488 }
7be869b0 1489 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1490 return;
1491 }
1492
1493 /*
1494 * We have to do it this way, because of the EXAR TXFIFO count bug.
1495 */
1496 if ((ch->ch_bd->dvid & 0xf0) < UART_XR17E158_DVID) {
1497 if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM))) {
7be869b0 1498 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1499 return;
1500 }
1501
1502 len_written = 0;
1503
1504 n = readb(&ch->ch_neo_uart->tfifo);
1505
1506 if ((unsigned int) n > ch->ch_t_tlevel) {
7be869b0 1507 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1508 return;
1509 }
1510
1511 n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
2000c581 1512 } else {
0b99d589
LL		 1513 n = UART_17158_TX_FIFOSIZE - readb(&ch->ch_neo_uart->tfifo);
1514 }
1515
1516 /* cache head and tail of queue */
1517 head = ch->ch_w_head & WQUEUEMASK;
1518 tail = ch->ch_w_tail & WQUEUEMASK;
1519 qlen = (head - tail) & WQUEUEMASK;
1520
1521 /* Find minimum of the FIFO space, versus queue length */
1522 n = min(n, qlen);
1523
1524 while (n > 0) {
1525
1526 s = ((head >= tail) ? head : WQUEUESIZE) - tail;
1527 s = min(s, n);
1528
1529 if (s <= 0)
1530 break;
1531
1532 /*
1533 * If RTS Toggle mode is on, turn on RTS now if not already set,
1534 * and make sure we get an event when the data transfer has completed.
1535 */
1536 if (ch->ch_digi.digi_flags & DIGI_RTS_TOGGLE) {
1537 if (!(ch->ch_mostat & UART_MCR_RTS)) {
1538 ch->ch_mostat |= (UART_MCR_RTS);
1539 neo_assert_modem_signals(ch);
1540 }
1541 ch->ch_tun.un_flags |= (UN_EMPTY);
1542 }
1543
1544 /*
1545 * If DTR Toggle mode is on, turn on DTR now if not already set,
1546 * and make sure we get an event when the data transfer has completed.
1547 */
1548 if (ch->ch_digi.digi_flags & DIGI_DTR_TOGGLE) {
1549 if (!(ch->ch_mostat & UART_MCR_DTR)) {
1550 ch->ch_mostat |= (UART_MCR_DTR);
1551 neo_assert_modem_signals(ch);
1552 }
1553 ch->ch_tun.un_flags |= (UN_EMPTY);
1554 }
1555
1556 memcpy_toio(&ch->ch_neo_uart->txrxburst, ch->ch_wqueue + tail, s);
0b99d589
LL		 1557
1558 /* Add and flip queue if needed */
1559 tail = (tail + s) & WQUEUEMASK;
1560 n -= s;
1561 ch->ch_txcount += s;
1562 len_written += s;
1563 }
1564
1565 /* Update the final tail */
1566 ch->ch_w_tail = tail & WQUEUEMASK;
1567
1568 if (len_written > 0) {
1569 neo_pci_posting_flush(ch->ch_bd);
1570 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1571 }
1572
7be869b0 1573 spin_unlock_irqrestore(&ch->ch_lock, flags);
0b99d589
LL		 1574}
1575
1576
446393e9 1577static void neo_parse_modem(struct channel_t *ch, unsigned char signals)
0b99d589 1578{
446393e9 1579 unsigned char msignals = signals;
0b99d589
LL		 1580
1581 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1582 return;
1583
0b99d589
LL		 1584 /*
1585 * Do altpin switching. Altpin switches DCD and DSR.
1586 * This prolly breaks DSRPACE, so we should be more clever here.
1587 */
1588 if (ch->ch_digi.digi_flags & DIGI_ALTPIN) {
446393e9 1589 unsigned char mswap = msignals;
0b99d589
LL		 1590
1591 if (mswap & UART_MSR_DDCD) {
1592 msignals &= ~UART_MSR_DDCD;
1593 msignals |= UART_MSR_DDSR;
1594 }
1595 if (mswap & UART_MSR_DDSR) {
1596 msignals &= ~UART_MSR_DDSR;
1597 msignals |= UART_MSR_DDCD;
1598 }
1599 if (mswap & UART_MSR_DCD) {
1600 msignals &= ~UART_MSR_DCD;
1601 msignals |= UART_MSR_DSR;
1602 }
1603 if (mswap & UART_MSR_DSR) {
1604 msignals &= ~UART_MSR_DSR;
1605 msignals |= UART_MSR_DCD;
1606 }
1607 }
1608
1609 /* Scrub off lower bits. They signify delta's, which I don't care about */
1610 msignals &= 0xf0;
1611
1612 if (msignals & UART_MSR_DCD)
1613 ch->ch_mistat |= UART_MSR_DCD;
1614 else
1615 ch->ch_mistat &= ~UART_MSR_DCD;
1616
1617 if (msignals & UART_MSR_DSR)
1618 ch->ch_mistat |= UART_MSR_DSR;
1619 else
1620 ch->ch_mistat &= ~UART_MSR_DSR;
1621
1622 if (msignals & UART_MSR_RI)
1623 ch->ch_mistat |= UART_MSR_RI;
1624 else
1625 ch->ch_mistat &= ~UART_MSR_RI;
1626
1627 if (msignals & UART_MSR_CTS)
1628 ch->ch_mistat |= UART_MSR_CTS;
1629 else
1630 ch->ch_mistat &= ~UART_MSR_CTS;
0b99d589
LL		 1631}
1632
1633
1634/* Make the UART raise any of the output signals we want up */
1635static void neo_assert_modem_signals(struct channel_t *ch)
1636{
446393e9 1637 unsigned char out;
0b99d589
LL		 1638
1639 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1640 return;
1641
1642 out = ch->ch_mostat;
1643
1644 if (ch->ch_flags & CH_LOOPBACK)
1645 out |= UART_MCR_LOOP;
1646
1647 writeb(out, &ch->ch_neo_uart->mcr);
1648 neo_pci_posting_flush(ch->ch_bd);
1649
1650 /* Give time for the UART to actually raise/drop the signals */
1651 udelay(10);
1652}
1653
1654
1655static void neo_send_start_character(struct channel_t *ch)
1656{
1657 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1658 return;
1659
1660 if (ch->ch_startc != _POSIX_VDISABLE) {
1661 ch->ch_xon_sends++;
1662 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1663 neo_pci_posting_flush(ch->ch_bd);
1664 udelay(10);
1665 }
1666}
1667
1668
1669static void neo_send_stop_character(struct channel_t *ch)
1670{
1671 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1672 return;
1673
1674 if (ch->ch_stopc != _POSIX_VDISABLE) {
1675 ch->ch_xoff_sends++;
1676 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1677 neo_pci_posting_flush(ch->ch_bd);
1678 udelay(10);
1679 }
1680}
1681
1682
1683/*
1684 * neo_uart_init
1685 */
1686static void neo_uart_init(struct channel_t *ch)
1687{
1688
1689 writeb(0, &ch->ch_neo_uart->ier);
1690 writeb(0, &ch->ch_neo_uart->efr);
1691 writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
5ba5b89a 1692
0b99d589 1693
00804f77 1694 /* Clear out UART and FIFO */
0b99d589
LL		 1695 readb(&ch->ch_neo_uart->txrx);
1696 writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1697 readb(&ch->ch_neo_uart->lsr);
1698 readb(&ch->ch_neo_uart->msr);
1699
1700 ch->ch_flags |= CH_FIFO_ENABLED;
1701
1702 /* Assert any signals we want up */
1703 writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1704 neo_pci_posting_flush(ch->ch_bd);
1705}
1706
1707
1708/*
1709 * Make the UART completely turn off.
1710 */
1711static void neo_uart_off(struct channel_t *ch)
1712{
1713 /* Turn off UART enhanced bits */
1714 writeb(0, &ch->ch_neo_uart->efr);
1715
1716 /* Stop all interrupts from occurring. */
1717 writeb(0, &ch->ch_neo_uart->ier);
1718 neo_pci_posting_flush(ch->ch_bd);
1719}
1720
1721
1722static uint neo_get_uart_bytes_left(struct channel_t *ch)
1723{
446393e9
EA		 1724 unsigned char left = 0;
1725 unsigned char lsr = readb(&ch->ch_neo_uart->lsr);
0b99d589
LL		 1726
1727 /* We must cache the LSR as some of the bits get reset once read... */
1728 ch->ch_cached_lsr |= lsr;
5ba5b89a 1729
0b99d589
LL		 1730 /* Determine whether the Transmitter is empty or not */
1731 if (!(lsr & UART_LSR_TEMT)) {
13d1773a 1732 if (ch->ch_flags & CH_TX_FIFO_EMPTY)
00804f77 1733 tasklet_schedule(&ch->ch_bd->helper_tasklet);
0b99d589
LL		 1734 left = 1;
1735 } else {
1736 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1737 left = 0;
1738 }
1739
1740 return left;
1741}
1742
1743
1744/* Channel lock MUST be held by the calling function! */
1745static void neo_send_break(struct channel_t *ch, int msecs)
1746{
1747 /*
1748 * If we receive a time of 0, this means turn off the break.
1749 */
1750 if (msecs == 0) {
1751 if (ch->ch_flags & CH_BREAK_SENDING) {
446393e9 1752 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
1eba3dba 1753
0b99d589
LL		 1754 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1755 neo_pci_posting_flush(ch->ch_bd);
1756 ch->ch_flags &= ~(CH_BREAK_SENDING);
1757 ch->ch_stop_sending_break = 0;
0b99d589
LL		 1758 }
1759 return;
1760 }
1761
1762 /*
1763 * Set the time we should stop sending the break.
1764 * If we are already sending a break, toss away the existing
1765 * time to stop, and use this new value instead.
1766 */
1767 ch->ch_stop_sending_break = jiffies + dgnc_jiffies_from_ms(msecs);
1768
1769 /* Tell the UART to start sending the break */
1770 if (!(ch->ch_flags & CH_BREAK_SENDING)) {
446393e9 1771 unsigned char temp = readb(&ch->ch_neo_uart->lcr);
5ef33f38 1772
00804f77 1773 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
0b99d589
LL		 1774 neo_pci_posting_flush(ch->ch_bd);
1775 ch->ch_flags |= (CH_BREAK_SENDING);
00804f77 1776 }
0b99d589
LL		 1777}
1778
1779
1780/*
1781 * neo_send_immediate_char.
1782 *
5ba5b89a 1783 * Sends a specific character as soon as possible to the UART,
0b99d589
LL		 1784 * jumping over any bytes that might be in the write queue.
1785 *
1786 * The channel lock MUST be held by the calling function.
1787 */
1788static void neo_send_immediate_char(struct channel_t *ch, unsigned char c)
1789{
1790 if (!ch || ch->magic != DGNC_CHANNEL_MAGIC)
1791 return;
1792
1793 writeb(c, &ch->ch_neo_uart->txrx);
1794 neo_pci_posting_flush(ch->ch_bd);
1795}
1796
1797
c2ac546e 1798static unsigned int neo_read_eeprom(unsigned char __iomem *base, unsigned int address)
0b99d589
LL		 1799{
1800 unsigned int enable;
1801 unsigned int bits;
1802 unsigned int databit;
1803 unsigned int val;
1804
1805 /* enable chip select */
1806 writeb(NEO_EECS, base + NEO_EEREG);
1807 /* READ */
1808 enable = (address | 0x180);
1809
1810 for (bits = 9; bits--; ) {
1811 databit = (enable & (1 << bits)) ? NEO_EEDI : 0;
1812 /* Set read address */
1813 writeb(databit | NEO_EECS, base + NEO_EEREG);
1814 writeb(databit | NEO_EECS | NEO_EECK, base + NEO_EEREG);
1815 }
1816
1817 val = 0;
1818
1819 for (bits = 17; bits--; ) {
1820 /* clock to EEPROM */
1821 writeb(NEO_EECS, base + NEO_EEREG);
1822 writeb(NEO_EECS | NEO_EECK, base + NEO_EEREG);
1823 val <<= 1;
1824 /* read EEPROM */
1825 if (readb(base + NEO_EEREG) & NEO_EEDO)
1826 val |= 1;
1827 }
1828
1829 /* clock falling edge */
1830 writeb(NEO_EECS, base + NEO_EEREG);
1831
1832 /* drop chip select */
1833 writeb(0x00, base + NEO_EEREG);
1834
1835 return val;
1836}
1837
1838
03425f55 1839static void neo_vpd(struct dgnc_board *brd)
0b99d589
LL		 1840{
1841 unsigned int i = 0;
1842 unsigned int a;
1843
1844 if (!brd || brd->magic != DGNC_BOARD_MAGIC)
1845 return;
1846
1847 if (!brd->re_map_membase)
1848 return;
1849
1850 /* Store the VPD into our buffer */
1851 for (i = 0; i < NEO_VPD_IMAGESIZE; i++) {
1852 a = neo_read_eeprom(brd->re_map_membase, i);
1853 brd->vpd[i*2] = a & 0xff;
1854 brd->vpd[(i*2)+1] = (a >> 8) & 0xff;
1855 }
1856
1857 if (((brd->vpd[0x08] != 0x82) /* long resource name tag */
1858 && (brd->vpd[0x10] != 0x82)) /* long resource name tag (PCI-66 files)*/
5ef33f38
KZ		 1859 || (brd->vpd[0x7F] != 0x78)) { /* small resource end tag */
1860
0b99d589 1861 memset(brd->vpd, '\0', NEO_VPD_IMAGESIZE);
2000c581 1862 } else {
0b99d589 1863 /* Search for the serial number */
50667c67
MN		 1864 for (i = 0; i < NEO_VPD_IMAGEBYTES - 3; i++)
1865 if (brd->vpd[i] == 'S' && brd->vpd[i + 1] == 'N')
0b99d589 1866 strncpy(brd->serial_num, &(brd->vpd[i + 3]), 9);
0b99d589
LL		 1867 }
1868}
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