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staging: dwc2: interpret all hwcfg and related register at init time
[mirror_ubuntu-zesty-kernel.git] / drivers / staging / dwc2 / core.h
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56f5b1cf
PZ		 1/*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef __DWC2_CORE_H__
38#define __DWC2_CORE_H__
39
40#include <linux/usb/phy.h>
41#include "hw.h"
42
43#ifdef DWC2_LOG_WRITES
44static inline void do_write(u32 value, void *addr)
45{
46 writel(value, addr);
47 pr_info("INFO:: wrote %08x to %p\n", value, addr);
48}
49
50#undef writel
51#define writel(v, a) do_write(v, a)
52#endif
53
54/* Maximum number of Endpoints/HostChannels */
55#define MAX_EPS_CHANNELS 16
56
57struct dwc2_hsotg;
58struct dwc2_host_chan;
59
60/* Device States */
61enum dwc2_lx_state {
62 DWC2_L0, /* On state */
63 DWC2_L1, /* LPM sleep state */
64 DWC2_L2, /* USB suspend state */
65 DWC2_L3, /* Off state */
66};
67
68/**
69 * struct dwc2_core_params - Parameters for configuring the core
70 *
71 * @otg_cap: Specifies the OTG capabilities. The driver will
72 * automatically detect the value for this parameter if
73 * none is specified.
74 * 0 - HNP and SRP capable (default)
75 * 1 - SRP Only capable
76 * 2 - No HNP/SRP capable
725acc86
PZ		 77 * @otg_ver: OTG version supported
78 * 0 - 1.3
79 * 1 - 2.0
56f5b1cf
PZ		 80 * @dma_enable: Specifies whether to use slave or DMA mode for accessing
81 * the data FIFOs. The driver will automatically detect the
82 * value for this parameter if none is specified.
83 * 0 - Slave
84 * 1 - DMA (default, if available)
85 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
86 * address DMA mode or descriptor DMA mode for accessing
87 * the data FIFOs. The driver will automatically detect the
88 * value for this if none is specified.
89 * 0 - Address DMA
90 * 1 - Descriptor DMA (default, if available)
91 * @speed: Specifies the maximum speed of operation in host and
92 * device mode. The actual speed depends on the speed of
93 * the attached device and the value of phy_type.
94 * 0 - High Speed (default)
95 * 1 - Full Speed
56f5b1cf
PZ		 96 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
97 * 1 - Allow dynamic FIFO sizing (default)
725acc86
PZ		 98 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
99 * are enabled
56f5b1cf
PZ		 100 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
101 * dynamic FIFO sizing is enabled
102 * 16 to 32768 (default 1024)
103 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
104 * in host mode when dynamic FIFO sizing is enabled
105 * 16 to 32768 (default 1024)
106 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
107 * host mode when dynamic FIFO sizing is enabled
108 * 16 to 32768 (default 1024)
109 * @max_transfer_size: The maximum transfer size supported, in bytes
110 * 2047 to 65,535 (default 65,535)
111 * @max_packet_count: The maximum number of packets in a transfer
112 * 15 to 511 (default 511)
113 * @host_channels: The number of host channel registers to use
114 * 1 to 16 (default 12)
115 * @phy_type: Specifies the type of PHY interface to use. By default,
116 * the driver will automatically detect the phy_type.
117 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
118 * is applicable for a phy_type of UTMI+ or ULPI. (For a
119 * ULPI phy_type, this parameter indicates the data width
120 * between the MAC and the ULPI Wrapper.) Also, this
121 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
122 * parameter was set to "8 and 16 bits", meaning that the
123 * core has been configured to work at either data path
124 * width.
125 * 8 or 16 (default 16)
126 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
127 * data rate. This parameter is only applicable if phy_type
128 * is ULPI.
129 * 0 - single data rate ULPI interface with 8 bit wide
130 * data bus (default)
131 * 1 - double data rate ULPI interface with 4 bit wide
132 * data bus
133 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
134 * external supply to drive the VBus
135 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
136 * speed PHY. This parameter is only applicable if phy_type
137 * is FS.
138 * 0 - No (default)
139 * 1 - Yes
140 * @ulpi_fs_ls: True to make ULPI phy operate in FS/LS mode only
725acc86
PZ		 141 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
142 * when attached to a Full Speed or Low Speed device in
143 * host mode.
144 * 0 - Don't support low power mode (default)
145 * 1 - Support low power mode
146 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
147 * when connected to a Low Speed device in host mode. This
148 * parameter is applicable only if
149 * host_support_fs_ls_low_power is enabled. If phy_type is
150 * set to FS then defaults to 6 MHZ otherwise 48 MHZ.
151 * 0 - 48 MHz
152 * 1 - 6 MHz
56f5b1cf 153 * @ts_dline: True to enable Term Select Dline pulsing
56f5b1cf
PZ		 154 * @reload_ctl: True to allow dynamic reloading of HFIR register during
155 * runtime
4d3190e1
PZ		 156 * @ahbcfg: This field allows the default value of the GAHBCFG
157 * register to be overridden
158 * -1 - GAHBCFG value will not be overridden
159 * all others - GAHBCFG value will be overridden with
160 * this value
56f5b1cf
PZ		 161 *
162 * The following parameters may be specified when starting the module. These
163 * parameters define how the DWC_otg controller should be configured.
164 */
165struct dwc2_core_params {
8284f93b
MK		 166 /*
167 * Don't add any non-int members here, this will break
168 * dwc2_set_all_params!
169 */
56f5b1cf
PZ		 170 int otg_cap;
171 int otg_ver;
172 int dma_enable;
173 int dma_desc_enable;
174 int speed;
175 int enable_dynamic_fifo;
176 int en_multiple_tx_fifo;
177 int host_rx_fifo_size;
178 int host_nperio_tx_fifo_size;
179 int host_perio_tx_fifo_size;
180 int max_transfer_size;
181 int max_packet_count;
182 int host_channels;
183 int phy_type;
184 int phy_utmi_width;
185 int phy_ulpi_ddr;
186 int phy_ulpi_ext_vbus;
187 int i2c_enable;
188 int ulpi_fs_ls;
189 int host_support_fs_ls_low_power;
190 int host_ls_low_power_phy_clk;
191 int ts_dline;
192 int reload_ctl;
4d3190e1 193 int ahbcfg;
56f5b1cf
PZ		 194};
195
9badec2f
MK		 196/**
197 * struct dwc2_hw_params - Autodetected parameters.
198 *
199 * These parameters are the various parameters read from hardware
200 * registers during initialization. They typically contain the best
201 * supported or maximum value that can be configured in the
202 * corresponding dwc2_core_params value.
203 *
204 * The values that are not in dwc2_core_params are documented below.
205 *
206 * @op_mode Mode of Operation
207 * 0 - HNP- and SRP-Capable OTG (Host & Device)
208 * 1 - SRP-Capable OTG (Host & Device)
209 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
210 * 3 - SRP-Capable Device
211 * 4 - Non-OTG Device
212 * 5 - SRP-Capable Host
213 * 6 - Non-OTG Host
214 * @arch Architecture
215 * 0 - Slave only
216 * 1 - External DMA
217 * 2 - Internal DMA
218 * @power_optimized Are power optimizations enabled?
219 * @num_dev_ep Number of device endpoints available
220 * @num_dev_perio_in_ep Number of device periodic IN endpoints
221 * avaialable
222 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
223 * Depth
224 * 0 to 30
225 * @host_perio_tx_q_depth
226 * Host Mode Periodic Request Queue Depth
227 * 2, 4 or 8
228 * @nperio_tx_q_depth
229 * Non-Periodic Request Queue Depth
230 * 2, 4 or 8
231 * @hs_phy_type High-speed PHY interface type
232 * 0 - High-speed interface not supported
233 * 1 - UTMI+
234 * 2 - ULPI
235 * 3 - UTMI+ and ULPI
236 * @fs_phy_type Full-speed PHY interface type
237 * 0 - Full speed interface not supported
238 * 1 - Dedicated full speed interface
239 * 2 - FS pins shared with UTMI+ pins
240 * 3 - FS pins shared with ULPI pins
241 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
242 * @snpsid: Value from SNPSID register
243 */
244struct dwc2_hw_params {
245 unsigned op_mode:3;
246 unsigned arch:2;
247 unsigned dma_desc_enable:1;
248 unsigned enable_dynamic_fifo:1;
249 unsigned en_multiple_tx_fifo:1;
250 unsigned host_rx_fifo_size:16;
251 unsigned host_nperio_tx_fifo_size:16;
252 unsigned host_perio_tx_fifo_size:16;
253 unsigned nperio_tx_q_depth:3;
254 unsigned host_perio_tx_q_depth:3;
255 unsigned dev_token_q_depth:5;
256 unsigned max_transfer_size:26;
257 unsigned max_packet_count:11;
258 unsigned host_channels:4;
259 unsigned hs_phy_type:2;
260 unsigned fs_phy_type:2;
261 unsigned i2c_enable:1;
262 unsigned num_dev_ep:4;
263 unsigned num_dev_perio_in_ep:4;
264 unsigned total_fifo_size:16;
265 unsigned power_optimized:1;
266 u32 snpsid;
267};
268
56f5b1cf
PZ		 269/**
270 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
271 * and periodic schedules
272 *
273 * @dev: The struct device pointer
274 * @regs: Pointer to controller regs
275 * @core_params: Parameters that define how the core should be configured
9badec2f
MK		 276 * @hw_params: Parameters that were autodetected from the
277 * hardware registers
56f5b1cf
PZ		 278 * @op_state: The operational State, during transitions (a_host=>
279 * a_peripheral and b_device=>b_host) this may not match
280 * the core, but allows the software to determine
281 * transitions
282 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
283 * transfer are in process of being queued
284 * @srp_success: Stores status of SRP request in the case of a FS PHY
285 * with an I2C interface
286 * @wq_otg: Workqueue object used for handling of some interrupts
287 * @wf_otg: Work object for handling Connector ID Status Change
288 * interrupt
289 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
290 * @lx_state: Lx state of connected device
291 * @flags: Flags for handling root port state changes
292 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
293 * Transfers associated with these QHs are not currently
294 * assigned to a host channel.
295 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
296 * Transfers associated with these QHs are currently
297 * assigned to a host channel.
298 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
299 * non-periodic schedule
300 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
301 * list of QHs for periodic transfers that are _not_
302 * scheduled for the next frame. Each QH in the list has an
303 * interval counter that determines when it needs to be
304 * scheduled for execution. This scheduling mechanism
305 * allows only a simple calculation for periodic bandwidth
306 * used (i.e. must assume that all periodic transfers may
307 * need to execute in the same frame). However, it greatly
308 * simplifies scheduling and should be sufficient for the
309 * vast majority of OTG hosts, which need to connect to a
310 * small number of peripherals at one time. Items move from
311 * this list to periodic_sched_ready when the QH interval
312 * counter is 0 at SOF.
313 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
314 * the next frame, but have not yet been assigned to host
315 * channels. Items move from this list to
316 * periodic_sched_assigned as host channels become
317 * available during the current frame.
318 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
319 * frame that are assigned to host channels. Items move
320 * from this list to periodic_sched_queued as the
321 * transactions for the QH are queued to the DWC_otg
322 * controller.
323 * @periodic_sched_queued: List of periodic QHs that have been queued for
324 * execution. Items move from this list to either
325 * periodic_sched_inactive or periodic_sched_ready when the
326 * channel associated with the transfer is released. If the
327 * interval for the QH is 1, the item moves to
328 * periodic_sched_ready because it must be rescheduled for
329 * the next frame. Otherwise, the item moves to
330 * periodic_sched_inactive.
331 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
332 * This value is in microseconds per (micro)frame. The
333 * assumption is that all periodic transfers may occur in
334 * the same (micro)frame.
335 * @frame_number: Frame number read from the core at SOF. The value ranges
336 * from 0 to HFNUM_MAX_FRNUM.
337 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
338 * SOF enable/disable.
339 * @free_hc_list: Free host channels in the controller. This is a list of
340 * struct dwc2_host_chan items.
341 * @periodic_channels: Number of host channels assigned to periodic transfers.
342 * Currently assuming that there is a dedicated host
343 * channel for each periodic transaction and at least one
344 * host channel is available for non-periodic transactions.
345 * @non_periodic_channels: Number of host channels assigned to non-periodic
346 * transfers
347 * @hc_ptr_array: Array of pointers to the host channel descriptors.
348 * Allows accessing a host channel descriptor given the
349 * host channel number. This is useful in interrupt
350 * handlers.
351 * @status_buf: Buffer used for data received during the status phase of
352 * a control transfer.
353 * @status_buf_dma: DMA address for status_buf
354 * @start_work: Delayed work for handling host A-cable connection
355 * @reset_work: Delayed work for handling a port reset
356 * @lock: Spinlock that protects all the driver data structures
357 * @priv: Stores a pointer to the struct usb_hcd
358 * @otg_port: OTG port number
359 * @frame_list: Frame list
360 * @frame_list_dma: Frame list DMA address
361 */
362struct dwc2_hsotg {
363 struct device *dev;
364 void __iomem *regs;
9badec2f
MK		 365 /** Params detected from hardware */
366 struct dwc2_hw_params hw_params;
367 /** Params to actually use */
56f5b1cf 368 struct dwc2_core_params *core_params;
56f5b1cf
PZ		 369 enum usb_otg_state op_state;
370
371 unsigned int queuing_high_bandwidth:1;
372 unsigned int srp_success:1;
373
374 struct workqueue_struct *wq_otg;
375 struct work_struct wf_otg;
376 struct timer_list wkp_timer;
377 enum dwc2_lx_state lx_state;
378
379 union dwc2_hcd_internal_flags {
380 u32 d32;
381 struct {
382 unsigned port_connect_status_change:1;
383 unsigned port_connect_status:1;
384 unsigned port_reset_change:1;
385 unsigned port_enable_change:1;
386 unsigned port_suspend_change:1;
387 unsigned port_over_current_change:1;
388 unsigned port_l1_change:1;
389 unsigned reserved:26;
390 } b;
391 } flags;
392
393 struct list_head non_periodic_sched_inactive;
394 struct list_head non_periodic_sched_active;
395 struct list_head *non_periodic_qh_ptr;
396 struct list_head periodic_sched_inactive;
397 struct list_head periodic_sched_ready;
398 struct list_head periodic_sched_assigned;
399 struct list_head periodic_sched_queued;
400 u16 periodic_usecs;
401 u16 frame_number;
402 u16 periodic_qh_count;
403
404#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
405#define FRAME_NUM_ARRAY_SIZE 1000
406 u16 last_frame_num;
407 u16 *frame_num_array;
408 u16 *last_frame_num_array;
409 int frame_num_idx;
410 int dumped_frame_num_array;
411#endif
412
413 struct list_head free_hc_list;
414 int periodic_channels;
415 int non_periodic_channels;
416 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
417 u8 *status_buf;
418 dma_addr_t status_buf_dma;
419#define DWC2_HCD_STATUS_BUF_SIZE 64
420
421 struct delayed_work start_work;
422 struct delayed_work reset_work;
423 spinlock_t lock;
424 void *priv;
425 u8 otg_port;
426 u32 *frame_list;
427 dma_addr_t frame_list_dma;
428
429 /* DWC OTG HW Release versions */
430#define DWC2_CORE_REV_2_71a 0x4f54271a
431#define DWC2_CORE_REV_2_90a 0x4f54290a
432#define DWC2_CORE_REV_2_92a 0x4f54292a
433#define DWC2_CORE_REV_2_94a 0x4f54294a
434#define DWC2_CORE_REV_3_00a 0x4f54300a
435
436#ifdef DEBUG
437 u32 frrem_samples;
438 u64 frrem_accum;
439
440 u32 hfnum_7_samples_a;
441 u64 hfnum_7_frrem_accum_a;
442 u32 hfnum_0_samples_a;
443 u64 hfnum_0_frrem_accum_a;
444 u32 hfnum_other_samples_a;
445 u64 hfnum_other_frrem_accum_a;
446
447 u32 hfnum_7_samples_b;
448 u64 hfnum_7_frrem_accum_b;
449 u32 hfnum_0_samples_b;
450 u64 hfnum_0_frrem_accum_b;
451 u32 hfnum_other_samples_b;
452 u64 hfnum_other_frrem_accum_b;
453#endif
454};
455
456/* Reasons for halting a host channel */
457enum dwc2_halt_status {
458 DWC2_HC_XFER_NO_HALT_STATUS,
459 DWC2_HC_XFER_COMPLETE,
460 DWC2_HC_XFER_URB_COMPLETE,
461 DWC2_HC_XFER_ACK,
462 DWC2_HC_XFER_NAK,
463 DWC2_HC_XFER_NYET,
464 DWC2_HC_XFER_STALL,
465 DWC2_HC_XFER_XACT_ERR,
466 DWC2_HC_XFER_FRAME_OVERRUN,
467 DWC2_HC_XFER_BABBLE_ERR,
468 DWC2_HC_XFER_DATA_TOGGLE_ERR,
469 DWC2_HC_XFER_AHB_ERR,
470 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
471 DWC2_HC_XFER_URB_DEQUEUE,
472};
473
474/*
475 * The following functions support initialization of the core driver component
476 * and the DWC_otg controller
477 */
478extern void dwc2_core_host_init(struct dwc2_hsotg *hsotg);
479
480/*
481 * Host core Functions.
482 * The following functions support managing the DWC_otg controller in host
483 * mode.
484 */
485extern void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan);
486extern void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
487 enum dwc2_halt_status halt_status);
488extern void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg,
489 struct dwc2_host_chan *chan);
490extern void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
491 struct dwc2_host_chan *chan);
492extern void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
493 struct dwc2_host_chan *chan);
494extern int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
495 struct dwc2_host_chan *chan);
496extern void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
497 struct dwc2_host_chan *chan);
498extern void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg);
499extern void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg);
500
501extern u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg);
502extern int dwc2_check_core_status(struct dwc2_hsotg *hsotg);
503
504/*
505 * Common core Functions.
506 * The following functions support managing the DWC_otg controller in either
507 * device or host mode.
508 */
509extern void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
510extern void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
511extern void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
512
6706c721 513extern int dwc2_core_init(struct dwc2_hsotg *hsotg, bool select_phy, int irq);
56f5b1cf
PZ		 514extern void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
515extern void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
516
517/* This function should be called on every hardware interrupt. */
518extern irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
519
520/* OTG Core Parameters */
521
522/*
523 * Specifies the OTG capabilities. The driver will automatically
524 * detect the value for this parameter if none is specified.
525 * 0 - HNP and SRP capable (default)
526 * 1 - SRP Only capable
527 * 2 - No HNP/SRP capable
528 */
529extern int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val);
530#define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
531#define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
532#define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
533
534/*
535 * Specifies whether to use slave or DMA mode for accessing the data
536 * FIFOs. The driver will automatically detect the value for this
537 * parameter if none is specified.
538 * 0 - Slave
539 * 1 - DMA (default, if available)
540 */
541extern int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val);
542
543/*
544 * When DMA mode is enabled specifies whether to use
545 * address DMA or DMA Descritor mode for accessing the data
546 * FIFOs in device mode. The driver will automatically detect
547 * the value for this parameter if none is specified.
548 * 0 - address DMA
549 * 1 - DMA Descriptor(default, if available)
550 */
551extern int dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val);
552
553/*
554 * Specifies the maximum speed of operation in host and device mode.
555 * The actual speed depends on the speed of the attached device and
556 * the value of phy_type. The actual speed depends on the speed of the
557 * attached device.
558 * 0 - High Speed (default)
559 * 1 - Full Speed
560 */
561extern int dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val);
562#define DWC2_SPEED_PARAM_HIGH 0
563#define DWC2_SPEED_PARAM_FULL 1
564
565/*
566 * Specifies whether low power mode is supported when attached
567 * to a Full Speed or Low Speed device in host mode.
568 *
569 * 0 - Don't support low power mode (default)
570 * 1 - Support low power mode
571 */
572extern int dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
573 int val);
574
575/*
576 * Specifies the PHY clock rate in low power mode when connected to a
577 * Low Speed device in host mode. This parameter is applicable only if
578 * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS
579 * then defaults to 6 MHZ otherwise 48 MHZ.
580 *
581 * 0 - 48 MHz
582 * 1 - 6 MHz
583 */
584extern int dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg,
585 int val);
586#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
587#define DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
588
589/*
590 * 0 - Use cC FIFO size parameters
591 * 1 - Allow dynamic FIFO sizing (default)
592 */
593extern int dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg,
594 int val);
595
596/*
597 * Number of 4-byte words in the Rx FIFO in host mode when dynamic
598 * FIFO sizing is enabled.
599 * 16 to 32768 (default 1024)
600 */
601extern int dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val);
602
603/*
604 * Number of 4-byte words in the non-periodic Tx FIFO in host mode
605 * when Dynamic FIFO sizing is enabled in the core.
606 * 16 to 32768 (default 256)
607 */
608extern int dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg,
609 int val);
610
611/*
612 * Number of 4-byte words in the host periodic Tx FIFO when dynamic
613 * FIFO sizing is enabled.
614 * 16 to 32768 (default 256)
615 */
616extern int dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg,
617 int val);
618
619/*
620 * The maximum transfer size supported in bytes.
621 * 2047 to 65,535 (default 65,535)
622 */
623extern int dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val);
624
625/*
626 * The maximum number of packets in a transfer.
627 * 15 to 511 (default 511)
628 */
629extern int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val);
630
631/*
632 * The number of host channel registers to use.
633 * 1 to 16 (default 11)
634 * Note: The FPGA configuration supports a maximum of 11 host channels.
635 */
636extern int dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val);
637
638/*
639 * Specifies the type of PHY interface to use. By default, the driver
640 * will automatically detect the phy_type.
641 *
642 * 0 - Full Speed PHY
643 * 1 - UTMI+ (default)
644 * 2 - ULPI
645 */
646extern int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val);
647#define DWC2_PHY_TYPE_PARAM_FS 0
648#define DWC2_PHY_TYPE_PARAM_UTMI 1
649#define DWC2_PHY_TYPE_PARAM_ULPI 2
650
651/*
652 * Specifies the UTMI+ Data Width. This parameter is
653 * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI
654 * PHY_TYPE, this parameter indicates the data width between
655 * the MAC and the ULPI Wrapper.) Also, this parameter is
656 * applicable only if the OTG_HSPHY_WIDTH cC parameter was set
657 * to "8 and 16 bits", meaning that the core has been
658 * configured to work at either data path width.
659 *
660 * 8 or 16 bits (default 16)
661 */
662extern int dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val);
663
664/*
665 * Specifies whether the ULPI operates at double or single
666 * data rate. This parameter is only applicable if PHY_TYPE is
667 * ULPI.
668 *
669 * 0 - single data rate ULPI interface with 8 bit wide data
670 * bus (default)
671 * 1 - double data rate ULPI interface with 4 bit wide data
672 * bus
673 */
674extern int dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val);
675
676/*
677 * Specifies whether to use the internal or external supply to
678 * drive the vbus with a ULPI phy.
679 */
680extern int dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val);
681#define DWC2_PHY_ULPI_INTERNAL_VBUS 0
682#define DWC2_PHY_ULPI_EXTERNAL_VBUS 1
683
684/*
685 * Specifies whether to use the I2Cinterface for full speed PHY. This
686 * parameter is only applicable if PHY_TYPE is FS.
687 * 0 - No (default)
688 * 1 - Yes
689 */
690extern int dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val);
691
692extern int dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val);
693
694extern int dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val);
695
696/*
697 * Specifies whether dedicated transmit FIFOs are
698 * enabled for non periodic IN endpoints in device mode
699 * 0 - No
700 * 1 - Yes
701 */
702extern int dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg,
703 int val);
704
705extern int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val);
706
4d3190e1 707extern int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val);
56f5b1cf
PZ		 708
709extern int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val);
710
711/*
712 * Dump core registers and SPRAM
713 */
714extern void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
715extern void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
716extern void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
717
718/*
719 * Return OTG version - either 1.3 or 2.0
720 */
721extern u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg);
722
723#endif /* __DWC2_CORE_H__ */
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