]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/staging/dwc2/hcd.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
staging: dwc2: refactor dwc2_host_complete()
[mirror_ubuntu-bionic-kernel.git] / drivers / staging / dwc2 / hcd.c
CommitLineData
7359d482
PZ		 1/*
2 * hcd.c - DesignWare HS OTG Controller host-mode routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the core HCD code, and implements the Linux hc_driver
39 * API
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/spinlock.h>
44#include <linux/interrupt.h>
45#include <linux/dma-mapping.h>
46#include <linux/delay.h>
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/usb.h>
50
51#include <linux/usb/hcd.h>
52#include <linux/usb/ch11.h>
53
54#include "core.h"
55#include "hcd.h"
56
57/**
58 * dwc2_dump_channel_info() - Prints the state of a host channel
59 *
60 * @hsotg: Programming view of DWC_otg controller
61 * @chan: Pointer to the channel to dump
62 *
63 * Must be called with interrupt disabled and spinlock held
64 *
65 * NOTE: This function will be removed once the peripheral controller code
66 * is integrated and the driver is stable
67 */
68static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
69 struct dwc2_host_chan *chan)
70{
71#ifdef VERBOSE_DEBUG
72 int num_channels = hsotg->core_params->host_channels;
73 struct dwc2_qh *qh;
74 u32 hcchar;
75 u32 hcsplt;
76 u32 hctsiz;
77 u32 hc_dma;
78 int i;
79
80 if (chan == NULL)
81 return;
82
83 hcchar = readl(hsotg->regs + HCCHAR(chan->hc_num));
84 hcsplt = readl(hsotg->regs + HCSPLT(chan->hc_num));
85 hctsiz = readl(hsotg->regs + HCTSIZ(chan->hc_num));
86 hc_dma = readl(hsotg->regs + HCDMA(chan->hc_num));
87
88 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
89 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
90 hcchar, hcsplt);
91 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
92 hctsiz, hc_dma);
93 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
94 chan->dev_addr, chan->ep_num, chan->ep_is_in);
95 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
96 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
97 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
98 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
99 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
100 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
101 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
102 (unsigned long)chan->xfer_dma);
103 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
104 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
105 dev_dbg(hsotg->dev, " NP inactive sched:\n");
106 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
107 qh_list_entry)
108 dev_dbg(hsotg->dev, " %p\n", qh);
109 dev_dbg(hsotg->dev, " NP active sched:\n");
110 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
111 qh_list_entry)
112 dev_dbg(hsotg->dev, " %p\n", qh);
113 dev_dbg(hsotg->dev, " Channels:\n");
114 for (i = 0; i < num_channels; i++) {
115 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
116
117 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
118 }
119#endif /* VERBOSE_DEBUG */
120}
121
122/*
123 * Processes all the URBs in a single list of QHs. Completes them with
124 * -ETIMEDOUT and frees the QTD.
125 *
126 * Must be called with interrupt disabled and spinlock held
127 */
128static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
129 struct list_head *qh_list)
130{
131 struct dwc2_qh *qh, *qh_tmp;
132 struct dwc2_qtd *qtd, *qtd_tmp;
133
134 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
135 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
136 qtd_list_entry) {
0d012b98
PZ		 137 dwc2_host_complete(hsotg, qtd, -ETIMEDOUT);
138 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
7359d482
PZ		 139 }
140 }
141}
142
143static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
144 struct list_head *qh_list)
145{
146 struct dwc2_qtd *qtd, *qtd_tmp;
147 struct dwc2_qh *qh, *qh_tmp;
148 unsigned long flags;
149
150 if (!qh_list->next)
151 /* The list hasn't been initialized yet */
152 return;
153
154 spin_lock_irqsave(&hsotg->lock, flags);
155
156 /* Ensure there are no QTDs or URBs left */
157 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
158
159 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
160 dwc2_hcd_qh_unlink(hsotg, qh);
161
162 /* Free each QTD in the QH's QTD list */
163 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
164 qtd_list_entry)
165 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
166
167 spin_unlock_irqrestore(&hsotg->lock, flags);
168 dwc2_hcd_qh_free(hsotg, qh);
169 spin_lock_irqsave(&hsotg->lock, flags);
170 }
171
172 spin_unlock_irqrestore(&hsotg->lock, flags);
173}
174
175/*
176 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
177 * and periodic schedules. The QTD associated with each URB is removed from
178 * the schedule and freed. This function may be called when a disconnect is
179 * detected or when the HCD is being stopped.
180 *
181 * Must be called with interrupt disabled and spinlock held
182 */
183static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
184{
185 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
186 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
187 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
188 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
189 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
190 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
191}
192
193/**
194 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
195 *
196 * @hsotg: Pointer to struct dwc2_hsotg
197 */
198void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
199{
200 u32 hprt0;
201
202 if (hsotg->op_state == OTG_STATE_B_HOST) {
203 /*
204 * Reset the port. During a HNP mode switch the reset
205 * needs to occur within 1ms and have a duration of at
206 * least 50ms.
207 */
208 hprt0 = dwc2_read_hprt0(hsotg);
209 hprt0 |= HPRT0_RST;
210 writel(hprt0, hsotg->regs + HPRT0);
211 }
212
213 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
214 msecs_to_jiffies(50));
215}
216
217/* Must be called with interrupt disabled and spinlock held */
218static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
219{
220 int num_channels = hsotg->core_params->host_channels;
221 struct dwc2_host_chan *channel;
222 u32 hcchar;
223 int i;
224
225 if (hsotg->core_params->dma_enable <= 0) {
226 /* Flush out any channel requests in slave mode */
227 for (i = 0; i < num_channels; i++) {
228 channel = hsotg->hc_ptr_array[i];
229 if (!list_empty(&channel->hc_list_entry))
230 continue;
231 hcchar = readl(hsotg->regs + HCCHAR(i));
232 if (hcchar & HCCHAR_CHENA) {
233 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
234 hcchar |= HCCHAR_CHDIS;
235 writel(hcchar, hsotg->regs + HCCHAR(i));
236 }
237 }
238 }
239
240 for (i = 0; i < num_channels; i++) {
241 channel = hsotg->hc_ptr_array[i];
242 if (!list_empty(&channel->hc_list_entry))
243 continue;
244 hcchar = readl(hsotg->regs + HCCHAR(i));
245 if (hcchar & HCCHAR_CHENA) {
246 /* Halt the channel */
247 hcchar |= HCCHAR_CHDIS;
248 writel(hcchar, hsotg->regs + HCCHAR(i));
249 }
250
251 dwc2_hc_cleanup(hsotg, channel);
252 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
253 /*
254 * Added for Descriptor DMA to prevent channel double cleanup in
255 * release_channel_ddma(), which is called from ep_disable when
256 * device disconnects
257 */
258 channel->qh = NULL;
259 }
260}
261
262/**
263 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
264 *
265 * @hsotg: Pointer to struct dwc2_hsotg
266 *
267 * Must be called with interrupt disabled and spinlock held
268 */
269void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
270{
271 u32 intr;
272
273 /* Set status flags for the hub driver */
274 hsotg->flags.b.port_connect_status_change = 1;
275 hsotg->flags.b.port_connect_status = 0;
276
277 /*
278 * Shutdown any transfers in process by clearing the Tx FIFO Empty
279 * interrupt mask and status bits and disabling subsequent host
280 * channel interrupts.
281 */
282 intr = readl(hsotg->regs + GINTMSK);
283 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
284 writel(intr, hsotg->regs + GINTMSK);
285 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
286 writel(intr, hsotg->regs + GINTSTS);
287
288 /*
289 * Turn off the vbus power only if the core has transitioned to device
290 * mode. If still in host mode, need to keep power on to detect a
291 * reconnection.
292 */
293 if (dwc2_is_device_mode(hsotg)) {
294 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
295 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
296 writel(0, hsotg->regs + HPRT0);
297 }
298
299 dwc2_disable_host_interrupts(hsotg);
300 }
301
302 /* Respond with an error status to all URBs in the schedule */
303 dwc2_kill_all_urbs(hsotg);
304
305 if (dwc2_is_host_mode(hsotg))
306 /* Clean up any host channels that were in use */
307 dwc2_hcd_cleanup_channels(hsotg);
308
309 dwc2_host_disconnect(hsotg);
310}
311
312/**
313 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
314 *
315 * @hsotg: Pointer to struct dwc2_hsotg
316 */
317static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
318{
319 if (hsotg->lx_state == DWC2_L2)
320 hsotg->flags.b.port_suspend_change = 1;
321 else
322 hsotg->flags.b.port_l1_change = 1;
323}
324
325/**
326 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
327 *
328 * @hsotg: Pointer to struct dwc2_hsotg
329 *
330 * Must be called with interrupt disabled and spinlock held
331 */
332void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
333{
334 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
335
336 /*
337 * The root hub should be disconnected before this function is called.
338 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
339 * and the QH lists (via ..._hcd_endpoint_disable).
340 */
341
342 /* Turn off all host-specific interrupts */
343 dwc2_disable_host_interrupts(hsotg);
344
345 /* Turn off the vbus power */
346 dev_dbg(hsotg->dev, "PortPower off\n");
347 writel(0, hsotg->regs + HPRT0);
348}
349
350static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
351 struct dwc2_hcd_urb *urb, void **ep_handle,
352 gfp_t mem_flags)
353{
354 struct dwc2_qtd *qtd;
355 unsigned long flags;
356 u32 intr_mask;
357 int retval;
358
359 if (!hsotg->flags.b.port_connect_status) {
360 /* No longer connected */
361 dev_err(hsotg->dev, "Not connected\n");
362 return -ENODEV;
363 }
364
365 qtd = kzalloc(sizeof(*qtd), mem_flags);
366 if (!qtd)
367 return -ENOMEM;
368
369 dwc2_hcd_qtd_init(qtd, urb);
370 retval = dwc2_hcd_qtd_add(hsotg, qtd, (struct dwc2_qh **)ep_handle,
371 mem_flags);
372 if (retval < 0) {
373 dev_err(hsotg->dev,
374 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
375 retval);
376 kfree(qtd);
377 return retval;
378 }
379
380 intr_mask = readl(hsotg->regs + GINTMSK);
381 if (!(intr_mask & GINTSTS_SOF) && retval == 0) {
382 enum dwc2_transaction_type tr_type;
383
384 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
385 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
386 /*
387 * Do not schedule SG transactions until qtd has
388 * URB_GIVEBACK_ASAP set
389 */
390 return 0;
391
392 spin_lock_irqsave(&hsotg->lock, flags);
393 tr_type = dwc2_hcd_select_transactions(hsotg);
394 if (tr_type != DWC2_TRANSACTION_NONE)
395 dwc2_hcd_queue_transactions(hsotg, tr_type);
396 spin_unlock_irqrestore(&hsotg->lock, flags);
397 }
398
399 return retval;
400}
401
402/* Must be called with interrupt disabled and spinlock held */
403static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
404 struct dwc2_hcd_urb *urb)
405{
406 struct dwc2_qh *qh;
407 struct dwc2_qtd *urb_qtd;
408
409 urb_qtd = urb->qtd;
410 if (!urb_qtd) {
411 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
412 return -EINVAL;
413 }
414
415 qh = urb_qtd->qh;
416 if (!qh) {
417 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
418 return -EINVAL;
419 }
420
0d012b98
PZ		 421 urb->priv = NULL;
422
7359d482
PZ		 423 if (urb_qtd->in_process && qh->channel) {
424 dwc2_dump_channel_info(hsotg, qh->channel);
425
426 /* The QTD is in process (it has been assigned to a channel) */
427 if (hsotg->flags.b.port_connect_status)
428 /*
429 * If still connected (i.e. in host mode), halt the
430 * channel so it can be used for other transfers. If
431 * no longer connected, the host registers can't be
432 * written to halt the channel since the core is in
433 * device mode.
434 */
435 dwc2_hc_halt(hsotg, qh->channel,
436 DWC2_HC_XFER_URB_DEQUEUE);
437 }
438
439 /*
440 * Free the QTD and clean up the associated QH. Leave the QH in the
441 * schedule if it has any remaining QTDs.
442 */
443 if (hsotg->core_params->dma_desc_enable <= 0) {
444 u8 in_process = urb_qtd->in_process;
445
446 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
447 if (in_process) {
448 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
449 qh->channel = NULL;
450 } else if (list_empty(&qh->qtd_list)) {
451 dwc2_hcd_qh_unlink(hsotg, qh);
452 }
453 } else {
454 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
455 }
456
457 return 0;
458}
459
460/* Must NOT be called with interrupt disabled or spinlock held */
461static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
462 struct usb_host_endpoint *ep, int retry)
463{
464 struct dwc2_qtd *qtd, *qtd_tmp;
465 struct dwc2_qh *qh;
466 unsigned long flags;
467 int rc;
468
469 spin_lock_irqsave(&hsotg->lock, flags);
470
471 qh = ep->hcpriv;
472 if (!qh) {
473 rc = -EINVAL;
474 goto err;
475 }
476
477 while (!list_empty(&qh->qtd_list) && retry--) {
478 if (retry == 0) {
479 dev_err(hsotg->dev,
480 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
481 rc = -EBUSY;
482 goto err;
483 }
484
485 spin_unlock_irqrestore(&hsotg->lock, flags);
486 usleep_range(20000, 40000);
487 spin_lock_irqsave(&hsotg->lock, flags);
488 qh = ep->hcpriv;
489 if (!qh) {
490 rc = -EINVAL;
491 goto err;
492 }
493 }
494
495 dwc2_hcd_qh_unlink(hsotg, qh);
496
497 /* Free each QTD in the QH's QTD list */
498 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
499 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
500
501 ep->hcpriv = NULL;
502 spin_unlock_irqrestore(&hsotg->lock, flags);
503 dwc2_hcd_qh_free(hsotg, qh);
504
505 return 0;
506
507err:
508 ep->hcpriv = NULL;
509 spin_unlock_irqrestore(&hsotg->lock, flags);
510
511 return rc;
512}
513
514/* Must be called with interrupt disabled and spinlock held */
515static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
516 struct usb_host_endpoint *ep)
517{
518 struct dwc2_qh *qh = ep->hcpriv;
519
520 if (!qh)
521 return -EINVAL;
522
523 qh->data_toggle = DWC2_HC_PID_DATA0;
524
525 return 0;
526}
527
528/*
529 * Initializes dynamic portions of the DWC_otg HCD state
530 *
531 * Must be called with interrupt disabled and spinlock held
532 */
533static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
534{
535 struct dwc2_host_chan *chan, *chan_tmp;
536 int num_channels;
537 int i;
538
539 hsotg->flags.d32 = 0;
540
541 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
542 hsotg->non_periodic_channels = 0;
543 hsotg->periodic_channels = 0;
544
545 /*
546 * Put all channels in the free channel list and clean up channel
547 * states
548 */
549 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
550 hc_list_entry)
551 list_del_init(&chan->hc_list_entry);
552
553 num_channels = hsotg->core_params->host_channels;
554 for (i = 0; i < num_channels; i++) {
555 chan = hsotg->hc_ptr_array[i];
556 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
557 dwc2_hc_cleanup(hsotg, chan);
558 }
559
560 /* Initialize the DWC core for host mode operation */
561 dwc2_core_host_init(hsotg);
562}
563
564static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
565 struct dwc2_host_chan *chan,
566 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
567{
568 int hub_addr, hub_port;
569
570 chan->do_split = 1;
571 chan->xact_pos = qtd->isoc_split_pos;
572 chan->complete_split = qtd->complete_split;
573 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
574 chan->hub_addr = (u8)hub_addr;
575 chan->hub_port = (u8)hub_port;
576}
577
578static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
579 struct dwc2_host_chan *chan,
580 struct dwc2_qtd *qtd, void *bufptr)
581{
582 struct dwc2_hcd_urb *urb = qtd->urb;
583 struct dwc2_hcd_iso_packet_desc *frame_desc;
584
585 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
586 case USB_ENDPOINT_XFER_CONTROL:
587 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
588
589 switch (qtd->control_phase) {
590 case DWC2_CONTROL_SETUP:
591 dev_vdbg(hsotg->dev, " Control setup transaction\n");
592 chan->do_ping = 0;
593 chan->ep_is_in = 0;
594 chan->data_pid_start = DWC2_HC_PID_SETUP;
595 if (hsotg->core_params->dma_enable > 0)
596 chan->xfer_dma = urb->setup_dma;
597 else
598 chan->xfer_buf = urb->setup_packet;
599 chan->xfer_len = 8;
600 bufptr = NULL;
601 break;
602
603 case DWC2_CONTROL_DATA:
604 dev_vdbg(hsotg->dev, " Control data transaction\n");
605 chan->data_pid_start = qtd->data_toggle;
606 break;
607
608 case DWC2_CONTROL_STATUS:
609 /*
610 * Direction is opposite of data direction or IN if no
611 * data
612 */
613 dev_vdbg(hsotg->dev, " Control status transaction\n");
614 if (urb->length == 0)
615 chan->ep_is_in = 1;
616 else
617 chan->ep_is_in =
618 dwc2_hcd_is_pipe_out(&urb->pipe_info);
619 if (chan->ep_is_in)
620 chan->do_ping = 0;
621 chan->data_pid_start = DWC2_HC_PID_DATA1;
622 chan->xfer_len = 0;
623 if (hsotg->core_params->dma_enable > 0)
624 chan->xfer_dma = hsotg->status_buf_dma;
625 else
626 chan->xfer_buf = hsotg->status_buf;
627 bufptr = NULL;
628 break;
629 }
630 break;
631
632 case USB_ENDPOINT_XFER_BULK:
633 chan->ep_type = USB_ENDPOINT_XFER_BULK;
634 break;
635
636 case USB_ENDPOINT_XFER_INT:
637 chan->ep_type = USB_ENDPOINT_XFER_INT;
638 break;
639
640 case USB_ENDPOINT_XFER_ISOC:
641 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
642 if (hsotg->core_params->dma_desc_enable > 0)
643 break;
644
645 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
646 frame_desc->status = 0;
647
648 if (hsotg->core_params->dma_enable > 0) {
649 chan->xfer_dma = urb->dma;
650 chan->xfer_dma += frame_desc->offset +
651 qtd->isoc_split_offset;
652 } else {
653 chan->xfer_buf = urb->buf;
654 chan->xfer_buf += frame_desc->offset +
655 qtd->isoc_split_offset;
656 }
657
658 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
659
660 /* For non-dword aligned buffers */
661 if (hsotg->core_params->dma_enable > 0 &&
662 (chan->xfer_dma & 0x3))
663 bufptr = (u8 *)urb->buf + frame_desc->offset +
664 qtd->isoc_split_offset;
665 else
666 bufptr = NULL;
667
668 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
669 if (chan->xfer_len <= 188)
670 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
671 else
672 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
673 }
674 break;
675 }
676
677 return bufptr;
678}
679
680static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
681 struct dwc2_host_chan *chan, void *bufptr)
682{
683 u32 buf_size;
684
685 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
686 buf_size = hsotg->core_params->max_transfer_size;
687 else
688 buf_size = 4096;
689
690 if (!qh->dw_align_buf) {
691 qh->dw_align_buf = dma_alloc_coherent(hsotg->dev, buf_size,
692 &qh->dw_align_buf_dma,
693 GFP_ATOMIC);
694 if (!qh->dw_align_buf)
695 return -ENOMEM;
696 }
697
698 if (!chan->ep_is_in && chan->xfer_len) {
699 dma_sync_single_for_cpu(hsotg->dev, chan->xfer_dma, buf_size,
700 DMA_TO_DEVICE);
701 memcpy(qh->dw_align_buf, bufptr, chan->xfer_len);
702 dma_sync_single_for_device(hsotg->dev, chan->xfer_dma, buf_size,
703 DMA_TO_DEVICE);
704 }
705
706 chan->align_buf = qh->dw_align_buf_dma;
707 return 0;
708}
709
710/**
711 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
712 * channel and initializes the host channel to perform the transactions. The
713 * host channel is removed from the free list.
714 *
715 * @hsotg: The HCD state structure
716 * @qh: Transactions from the first QTD for this QH are selected and assigned
717 * to a free host channel
718 */
719static void dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg,
720 struct dwc2_qh *qh)
721{
722 struct dwc2_host_chan *chan;
723 struct dwc2_hcd_urb *urb;
724 struct dwc2_qtd *qtd;
725 void *bufptr = NULL;
726
b49977a6
MK		 727 if (dbg_qh(qh))
728 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
7359d482
PZ		 729
730 if (list_empty(&qh->qtd_list)) {
731 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
732 return;
733 }
734
735 if (list_empty(&hsotg->free_hc_list)) {
736 dev_dbg(hsotg->dev, "No free channel to assign\n");
737 return;
738 }
739
740 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
741 hc_list_entry);
742
743 /* Remove the host channel from the free list */
744 list_del_init(&chan->hc_list_entry);
745
746 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
747 urb = qtd->urb;
748 qh->channel = chan;
749 qtd->in_process = 1;
750
751 /*
752 * Use usb_pipedevice to determine device address. This address is
753 * 0 before the SET_ADDRESS command and the correct address afterward.
754 */
755 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
756 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
757 chan->speed = qh->dev_speed;
758 chan->max_packet = dwc2_max_packet(qh->maxp);
759
760 chan->xfer_started = 0;
761 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
762 chan->error_state = (qtd->error_count > 0);
763 chan->halt_on_queue = 0;
764 chan->halt_pending = 0;
765 chan->requests = 0;
766
767 /*
768 * The following values may be modified in the transfer type section
769 * below. The xfer_len value may be reduced when the transfer is
770 * started to accommodate the max widths of the XferSize and PktCnt
771 * fields in the HCTSIZn register.
772 */
773
774 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
775 if (chan->ep_is_in)
776 chan->do_ping = 0;
777 else
778 chan->do_ping = qh->ping_state;
779
780 chan->data_pid_start = qh->data_toggle;
781 chan->multi_count = 1;
782
783 if (hsotg->core_params->dma_enable > 0) {
784 chan->xfer_dma = urb->dma + urb->actual_length;
785
786 /* For non-dword aligned case */
787 if (hsotg->core_params->dma_desc_enable <= 0 &&
788 (chan->xfer_dma & 0x3))
789 bufptr = (u8 *)urb->buf + urb->actual_length;
790 } else {
791 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
792 }
793
794 chan->xfer_len = urb->length - urb->actual_length;
795 chan->xfer_count = 0;
796
797 /* Set the split attributes if required */
798 if (qh->do_split)
799 dwc2_hc_init_split(hsotg, chan, qtd, urb);
800 else
801 chan->do_split = 0;
802
803 /* Set the transfer attributes */
804 bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
805
806 /* Non DWORD-aligned buffer case */
807 if (bufptr) {
808 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
809 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, bufptr)) {
810 dev_err(hsotg->dev,
811 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
812 __func__);
813 /* Add channel back to free list */
814 chan->align_buf = 0;
815 chan->multi_count = 0;
816 list_add_tail(&chan->hc_list_entry,
817 &hsotg->free_hc_list);
818 qtd->in_process = 0;
819 qh->channel = NULL;
820 return;
821 }
822 } else {
823 chan->align_buf = 0;
824 }
825
826 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
827 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
828 /*
829 * This value may be modified when the transfer is started
830 * to reflect the actual transfer length
831 */
832 chan->multi_count = dwc2_hb_mult(qh->maxp);
833
834 if (hsotg->core_params->dma_desc_enable > 0)
835 chan->desc_list_addr = qh->desc_list_dma;
836
837 dwc2_hc_init(hsotg, chan);
838 chan->qh = qh;
839}
840
841/**
842 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
843 * schedule and assigns them to available host channels. Called from the HCD
844 * interrupt handler functions.
845 *
846 * @hsotg: The HCD state structure
847 *
848 * Return: The types of new transactions that were assigned to host channels
849 */
850enum dwc2_transaction_type dwc2_hcd_select_transactions(
851 struct dwc2_hsotg *hsotg)
852{
853 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
854 struct list_head *qh_ptr;
855 struct dwc2_qh *qh;
856 int num_channels;
857
858#ifdef DWC2_DEBUG_SOF
859 dev_vdbg(hsotg->dev, " Select Transactions\n");
860#endif
861
862 /* Process entries in the periodic ready list */
863 qh_ptr = hsotg->periodic_sched_ready.next;
864 while (qh_ptr != &hsotg->periodic_sched_ready) {
865 if (list_empty(&hsotg->free_hc_list))
866 break;
867 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
868 dwc2_assign_and_init_hc(hsotg, qh);
869
870 /*
871 * Move the QH from the periodic ready schedule to the
872 * periodic assigned schedule
873 */
874 qh_ptr = qh_ptr->next;
875 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
876 ret_val = DWC2_TRANSACTION_PERIODIC;
877 }
878
879 /*
880 * Process entries in the inactive portion of the non-periodic
881 * schedule. Some free host channels may not be used if they are
882 * reserved for periodic transfers.
883 */
884 num_channels = hsotg->core_params->host_channels;
885 qh_ptr = hsotg->non_periodic_sched_inactive.next;
886 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
887 if (hsotg->non_periodic_channels >= num_channels -
888 hsotg->periodic_channels)
889 break;
890 if (list_empty(&hsotg->free_hc_list))
891 break;
892 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
893 dwc2_assign_and_init_hc(hsotg, qh);
894
895 /*
896 * Move the QH from the non-periodic inactive schedule to the
897 * non-periodic active schedule
898 */
899 qh_ptr = qh_ptr->next;
900 list_move(&qh->qh_list_entry,
901 &hsotg->non_periodic_sched_active);
902
903 if (ret_val == DWC2_TRANSACTION_NONE)
904 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
905 else
906 ret_val = DWC2_TRANSACTION_ALL;
907
908 hsotg->non_periodic_channels++;
909 }
910
911 return ret_val;
912}
913
914/**
915 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
916 * a host channel associated with either a periodic or non-periodic transfer
917 *
918 * @hsotg: The HCD state structure
919 * @chan: Host channel descriptor associated with either a periodic or
920 * non-periodic transfer
921 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
922 * for periodic transfers or the non-periodic Tx FIFO
923 * for non-periodic transfers
924 *
925 * Return: 1 if a request is queued and more requests may be needed to
926 * complete the transfer, 0 if no more requests are required for this
927 * transfer, -1 if there is insufficient space in the Tx FIFO
928 *
929 * This function assumes that there is space available in the appropriate
930 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
931 * it checks whether space is available in the appropriate Tx FIFO.
932 *
933 * Must be called with interrupt disabled and spinlock held
934 */
935static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
936 struct dwc2_host_chan *chan,
937 u16 fifo_dwords_avail)
938{
939 int retval = 0;
940
941 if (hsotg->core_params->dma_enable > 0) {
942 if (hsotg->core_params->dma_desc_enable > 0) {
943 if (!chan->xfer_started ||
944 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
945 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
946 chan->qh->ping_state = 0;
947 }
948 } else if (!chan->xfer_started) {
949 dwc2_hc_start_transfer(hsotg, chan);
950 chan->qh->ping_state = 0;
951 }
952 } else if (chan->halt_pending) {
953 /* Don't queue a request if the channel has been halted */
954 } else if (chan->halt_on_queue) {
955 dwc2_hc_halt(hsotg, chan, chan->halt_status);
956 } else if (chan->do_ping) {
957 if (!chan->xfer_started)
958 dwc2_hc_start_transfer(hsotg, chan);
959 } else if (!chan->ep_is_in ||
960 chan->data_pid_start == DWC2_HC_PID_SETUP) {
961 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
962 if (!chan->xfer_started) {
963 dwc2_hc_start_transfer(hsotg, chan);
964 retval = 1;
965 } else {
966 retval = dwc2_hc_continue_transfer(hsotg, chan);
967 }
968 } else {
969 retval = -1;
970 }
971 } else {
972 if (!chan->xfer_started) {
973 dwc2_hc_start_transfer(hsotg, chan);
974 retval = 1;
975 } else {
976 retval = dwc2_hc_continue_transfer(hsotg, chan);
977 }
978 }
979
980 return retval;
981}
982
983/*
984 * Processes periodic channels for the next frame and queues transactions for
985 * these channels to the DWC_otg controller. After queueing transactions, the
986 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
987 * to queue as Periodic Tx FIFO or request queue space becomes available.
988 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
989 *
990 * Must be called with interrupt disabled and spinlock held
991 */
992static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
993{
994 struct list_head *qh_ptr;
995 struct dwc2_qh *qh;
996 u32 tx_status;
997 u32 fspcavail;
998 u32 gintmsk;
999 int status;
1000 int no_queue_space = 0;
1001 int no_fifo_space = 0;
1002 u32 qspcavail;
1003
b49977a6
MK		 1004 if (dbg_perio())
1005 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
7359d482
PZ		 1006
1007 tx_status = readl(hsotg->regs + HPTXSTS);
1008 qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1009 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1010 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1011 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1012
1013 if (dbg_perio()) {
1014 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
1015 qspcavail);
1016 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
1017 fspcavail);
1018 }
7359d482
PZ		 1019
1020 qh_ptr = hsotg->periodic_sched_assigned.next;
1021 while (qh_ptr != &hsotg->periodic_sched_assigned) {
1022 tx_status = readl(hsotg->regs + HPTXSTS);
1023 if ((tx_status & TXSTS_QSPCAVAIL_MASK) == 0) {
1024 no_queue_space = 1;
1025 break;
1026 }
1027
1028 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1029 if (!qh->channel) {
1030 qh_ptr = qh_ptr->next;
1031 continue;
1032 }
1033
1034 /* Make sure EP's TT buffer is clean before queueing qtds */
1035 if (qh->tt_buffer_dirty) {
1036 qh_ptr = qh_ptr->next;
1037 continue;
1038 }
1039
1040 /*
1041 * Set a flag if we're queuing high-bandwidth in slave mode.
1042 * The flag prevents any halts to get into the request queue in
1043 * the middle of multiple high-bandwidth packets getting queued.
1044 */
1045 if (hsotg->core_params->dma_enable <= 0 &&
1046 qh->channel->multi_count > 1)
1047 hsotg->queuing_high_bandwidth = 1;
1048
1049 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1050 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1051 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1052 if (status < 0) {
1053 no_fifo_space = 1;
1054 break;
1055 }
1056
1057 /*
1058 * In Slave mode, stay on the current transfer until there is
1059 * nothing more to do or the high-bandwidth request count is
1060 * reached. In DMA mode, only need to queue one request. The
1061 * controller automatically handles multiple packets for
1062 * high-bandwidth transfers.
1063 */
1064 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1065 qh->channel->requests == qh->channel->multi_count) {
1066 qh_ptr = qh_ptr->next;
1067 /*
1068 * Move the QH from the periodic assigned schedule to
1069 * the periodic queued schedule
1070 */
1071 list_move(&qh->qh_list_entry,
1072 &hsotg->periodic_sched_queued);
1073
1074 /* done queuing high bandwidth */
1075 hsotg->queuing_high_bandwidth = 0;
1076 }
1077 }
1078
1079 if (hsotg->core_params->dma_enable <= 0) {
1080 tx_status = readl(hsotg->regs + HPTXSTS);
1081 qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1082 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1083 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1084 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
b49977a6
MK		 1085 if (dbg_perio()) {
1086 dev_vdbg(hsotg->dev,
1087 " P Tx Req Queue Space Avail (after queue): %d\n",
1088 qspcavail);
1089 dev_vdbg(hsotg->dev,
1090 " P Tx FIFO Space Avail (after queue): %d\n",
1091 fspcavail);
1092 }
7359d482
PZ		 1093
1094 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1095 no_queue_space || no_fifo_space) {
1096 /*
1097 * May need to queue more transactions as the request
1098 * queue or Tx FIFO empties. Enable the periodic Tx
1099 * FIFO empty interrupt. (Always use the half-empty
1100 * level to ensure that new requests are loaded as
1101 * soon as possible.)
1102 */
1103 gintmsk = readl(hsotg->regs + GINTMSK);
1104 gintmsk |= GINTSTS_PTXFEMP;
1105 writel(gintmsk, hsotg->regs + GINTMSK);
1106 } else {
1107 /*
1108 * Disable the Tx FIFO empty interrupt since there are
1109 * no more transactions that need to be queued right
1110 * now. This function is called from interrupt
1111 * handlers to queue more transactions as transfer
1112 * states change.
1113 */
1114 gintmsk = readl(hsotg->regs + GINTMSK);
1115 gintmsk &= ~GINTSTS_PTXFEMP;
1116 writel(gintmsk, hsotg->regs + GINTMSK);
1117 }
1118 }
1119}
1120
1121/*
1122 * Processes active non-periodic channels and queues transactions for these
1123 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1124 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1125 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1126 * FIFO Empty interrupt is disabled.
1127 *
1128 * Must be called with interrupt disabled and spinlock held
1129 */
1130static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1131{
1132 struct list_head *orig_qh_ptr;
1133 struct dwc2_qh *qh;
1134 u32 tx_status;
1135 u32 qspcavail;
1136 u32 fspcavail;
1137 u32 gintmsk;
1138 int status;
1139 int no_queue_space = 0;
1140 int no_fifo_space = 0;
1141 int more_to_do = 0;
1142
1143 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1144
1145 tx_status = readl(hsotg->regs + GNPTXSTS);
1146 qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1147 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1148 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1149 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1150 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
1151 qspcavail);
1152 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
1153 fspcavail);
1154
1155 /*
1156 * Keep track of the starting point. Skip over the start-of-list
1157 * entry.
1158 */
1159 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1160 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1161 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1162
1163 /*
1164 * Process once through the active list or until no more space is
1165 * available in the request queue or the Tx FIFO
1166 */
1167 do {
1168 tx_status = readl(hsotg->regs + GNPTXSTS);
1169 qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1170 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1171 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1172 no_queue_space = 1;
1173 break;
1174 }
1175
1176 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1177 qh_list_entry);
1178 if (!qh->channel)
1179 goto next;
1180
1181 /* Make sure EP's TT buffer is clean before queueing qtds */
1182 if (qh->tt_buffer_dirty)
1183 goto next;
1184
1185 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1186 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1187 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1188
1189 if (status > 0) {
1190 more_to_do = 1;
1191 } else if (status < 0) {
1192 no_fifo_space = 1;
1193 break;
1194 }
1195next:
1196 /* Advance to next QH, skipping start-of-list entry */
1197 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1198 if (hsotg->non_periodic_qh_ptr ==
1199 &hsotg->non_periodic_sched_active)
1200 hsotg->non_periodic_qh_ptr =
1201 hsotg->non_periodic_qh_ptr->next;
1202 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1203
1204 if (hsotg->core_params->dma_enable <= 0) {
1205 tx_status = readl(hsotg->regs + GNPTXSTS);
1206 qspcavail = tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1207 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT;
1208 fspcavail = tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1209 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT;
1210 dev_vdbg(hsotg->dev,
1211 " NP Tx Req Queue Space Avail (after queue): %d\n",
1212 qspcavail);
1213 dev_vdbg(hsotg->dev,
1214 " NP Tx FIFO Space Avail (after queue): %d\n",
1215 fspcavail);
1216
1217 if (more_to_do || no_queue_space || no_fifo_space) {
1218 /*
1219 * May need to queue more transactions as the request
1220 * queue or Tx FIFO empties. Enable the non-periodic
1221 * Tx FIFO empty interrupt. (Always use the half-empty
1222 * level to ensure that new requests are loaded as
1223 * soon as possible.)
1224 */
1225 gintmsk = readl(hsotg->regs + GINTMSK);
1226 gintmsk |= GINTSTS_NPTXFEMP;
1227 writel(gintmsk, hsotg->regs + GINTMSK);
1228 } else {
1229 /*
1230 * Disable the Tx FIFO empty interrupt since there are
1231 * no more transactions that need to be queued right
1232 * now. This function is called from interrupt
1233 * handlers to queue more transactions as transfer
1234 * states change.
1235 */
1236 gintmsk = readl(hsotg->regs + GINTMSK);
1237 gintmsk &= ~GINTSTS_NPTXFEMP;
1238 writel(gintmsk, hsotg->regs + GINTMSK);
1239 }
1240 }
1241}
1242
1243/**
1244 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1245 * and queues transactions for these channels to the DWC_otg controller. Called
1246 * from the HCD interrupt handler functions.
1247 *
1248 * @hsotg: The HCD state structure
1249 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1250 * or both)
1251 *
1252 * Must be called with interrupt disabled and spinlock held
1253 */
1254void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1255 enum dwc2_transaction_type tr_type)
1256{
1257#ifdef DWC2_DEBUG_SOF
1258 dev_vdbg(hsotg->dev, "Queue Transactions\n");
1259#endif
1260 /* Process host channels associated with periodic transfers */
1261 if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1262 tr_type == DWC2_TRANSACTION_ALL) &&
1263 !list_empty(&hsotg->periodic_sched_assigned))
1264 dwc2_process_periodic_channels(hsotg);
1265
1266 /* Process host channels associated with non-periodic transfers */
1267 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1268 tr_type == DWC2_TRANSACTION_ALL) {
1269 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1270 dwc2_process_non_periodic_channels(hsotg);
1271 } else {
1272 /*
1273 * Ensure NP Tx FIFO empty interrupt is disabled when
1274 * there are no non-periodic transfers to process
1275 */
1276 u32 gintmsk = readl(hsotg->regs + GINTMSK);
1277
1278 gintmsk &= ~GINTSTS_NPTXFEMP;
1279 writel(gintmsk, hsotg->regs + GINTMSK);
1280 }
1281 }
1282}
1283
1284static void dwc2_conn_id_status_change(struct work_struct *work)
1285{
1286 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1287 wf_otg);
1288 u32 count = 0;
1289 u32 gotgctl;
1290
1291 dev_dbg(hsotg->dev, "%s()\n", __func__);
1292
1293 gotgctl = readl(hsotg->regs + GOTGCTL);
1294 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1295 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1296 !!(gotgctl & GOTGCTL_CONID_B));
1297
1298 /* B-Device connector (Device Mode) */
1299 if (gotgctl & GOTGCTL_CONID_B) {
1300 /* Wait for switch to device mode */
1301 dev_dbg(hsotg->dev, "connId B\n");
1302 while (!dwc2_is_device_mode(hsotg)) {
1303 dev_info(hsotg->dev,
1304 "Waiting for Peripheral Mode, Mode=%s\n",
1305 dwc2_is_host_mode(hsotg) ? "Host" :
1306 "Peripheral");
1307 usleep_range(20000, 40000);
1308 if (++count > 250)
1309 break;
1310 }
1311 if (count > 250)
1312 dev_err(hsotg->dev,
de9169a1 1313 "Connection id status change timed out\n");
7359d482 1314 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
6706c721 1315 dwc2_core_init(hsotg, false, -1);
7359d482
PZ		 1316 dwc2_enable_global_interrupts(hsotg);
1317 } else {
1318 /* A-Device connector (Host Mode) */
1319 dev_dbg(hsotg->dev, "connId A\n");
1320 while (!dwc2_is_host_mode(hsotg)) {
1321 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1322 dwc2_is_host_mode(hsotg) ?
1323 "Host" : "Peripheral");
1324 usleep_range(20000, 40000);
1325 if (++count > 250)
1326 break;
1327 }
1328 if (count > 250)
1329 dev_err(hsotg->dev,
de9169a1 1330 "Connection id status change timed out\n");
7359d482
PZ		 1331 hsotg->op_state = OTG_STATE_A_HOST;
1332
1333 /* Initialize the Core for Host mode */
6706c721 1334 dwc2_core_init(hsotg, false, -1);
7359d482
PZ		 1335 dwc2_enable_global_interrupts(hsotg);
1336 dwc2_hcd_start(hsotg);
1337 }
1338}
1339
1340static void dwc2_wakeup_detected(unsigned long data)
1341{
1342 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1343 u32 hprt0;
1344
1345 dev_dbg(hsotg->dev, "%s()\n", __func__);
1346
1347 /*
1348 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1349 * so that OPT tests pass with all PHYs.)
1350 */
1351 hprt0 = dwc2_read_hprt0(hsotg);
1352 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1353 hprt0 &= ~HPRT0_RES;
1354 writel(hprt0, hsotg->regs + HPRT0);
1355 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1356 readl(hsotg->regs + HPRT0));
1357
1358 dwc2_hcd_rem_wakeup(hsotg);
1359
1360 /* Change to L0 state */
1361 hsotg->lx_state = DWC2_L0;
1362}
1363
1364static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1365{
1366 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1367
1368 return hcd->self.b_hnp_enable;
1369}
1370
1371/* Must NOT be called with interrupt disabled or spinlock held */
1372static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1373{
1374 unsigned long flags;
1375 u32 hprt0;
1376 u32 pcgctl;
1377 u32 gotgctl;
1378
1379 dev_dbg(hsotg->dev, "%s()\n", __func__);
1380
1381 spin_lock_irqsave(&hsotg->lock, flags);
1382
1383 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1384 gotgctl = readl(hsotg->regs + GOTGCTL);
1385 gotgctl |= GOTGCTL_HSTSETHNPEN;
1386 writel(gotgctl, hsotg->regs + GOTGCTL);
1387 hsotg->op_state = OTG_STATE_A_SUSPEND;
1388 }
1389
1390 hprt0 = dwc2_read_hprt0(hsotg);
1391 hprt0 |= HPRT0_SUSP;
1392 writel(hprt0, hsotg->regs + HPRT0);
1393
1394 /* Update lx_state */
1395 hsotg->lx_state = DWC2_L2;
1396
1397 /* Suspend the Phy Clock */
1398 pcgctl = readl(hsotg->regs + PCGCTL);
1399 pcgctl |= PCGCTL_STOPPCLK;
1400 writel(pcgctl, hsotg->regs + PCGCTL);
1401 udelay(10);
1402
1403 /* For HNP the bus must be suspended for at least 200ms */
1404 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1405 pcgctl = readl(hsotg->regs + PCGCTL);
1406 pcgctl &= ~PCGCTL_STOPPCLK;
1407 writel(pcgctl, hsotg->regs + PCGCTL);
1408
1409 spin_unlock_irqrestore(&hsotg->lock, flags);
1410
1411 usleep_range(200000, 250000);
1412 } else {
1413 spin_unlock_irqrestore(&hsotg->lock, flags);
1414 }
1415}
1416
1417/* Handles hub class-specific requests */
1418static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1419 u16 wvalue, u16 windex, char *buf, u16 wlength)
1420{
1421 struct usb_hub_descriptor *hub_desc;
1422 int retval = 0;
1423 u32 hprt0;
1424 u32 port_status;
1425 u32 speed;
1426 u32 pcgctl;
1427
1428 switch (typereq) {
1429 case ClearHubFeature:
1430 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1431
1432 switch (wvalue) {
1433 case C_HUB_LOCAL_POWER:
1434 case C_HUB_OVER_CURRENT:
1435 /* Nothing required here */
1436 break;
1437
1438 default:
1439 retval = -EINVAL;
1440 dev_err(hsotg->dev,
1441 "ClearHubFeature request %1xh unknown\n",
1442 wvalue);
1443 }
1444 break;
1445
1446 case ClearPortFeature:
1447 if (wvalue != USB_PORT_FEAT_L1)
1448 if (!windex || windex > 1)
1449 goto error;
1450 switch (wvalue) {
1451 case USB_PORT_FEAT_ENABLE:
1452 dev_dbg(hsotg->dev,
1453 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1454 hprt0 = dwc2_read_hprt0(hsotg);
1455 hprt0 |= HPRT0_ENA;
1456 writel(hprt0, hsotg->regs + HPRT0);
1457 break;
1458
1459 case USB_PORT_FEAT_SUSPEND:
1460 dev_dbg(hsotg->dev,
1461 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1462 writel(0, hsotg->regs + PCGCTL);
1463 usleep_range(20000, 40000);
1464
1465 hprt0 = dwc2_read_hprt0(hsotg);
1466 hprt0 |= HPRT0_RES;
1467 writel(hprt0, hsotg->regs + HPRT0);
1468 hprt0 &= ~HPRT0_SUSP;
1469 usleep_range(100000, 150000);
1470
1471 hprt0 &= ~HPRT0_RES;
1472 writel(hprt0, hsotg->regs + HPRT0);
1473 break;
1474
1475 case USB_PORT_FEAT_POWER:
1476 dev_dbg(hsotg->dev,
1477 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1478 hprt0 = dwc2_read_hprt0(hsotg);
1479 hprt0 &= ~HPRT0_PWR;
1480 writel(hprt0, hsotg->regs + HPRT0);
1481 break;
1482
1483 case USB_PORT_FEAT_INDICATOR:
1484 dev_dbg(hsotg->dev,
1485 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1486 /* Port indicator not supported */
1487 break;
1488
1489 case USB_PORT_FEAT_C_CONNECTION:
1490 /*
1491 * Clears driver's internal Connect Status Change flag
1492 */
1493 dev_dbg(hsotg->dev,
1494 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1495 hsotg->flags.b.port_connect_status_change = 0;
1496 break;
1497
1498 case USB_PORT_FEAT_C_RESET:
1499 /* Clears driver's internal Port Reset Change flag */
1500 dev_dbg(hsotg->dev,
1501 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1502 hsotg->flags.b.port_reset_change = 0;
1503 break;
1504
1505 case USB_PORT_FEAT_C_ENABLE:
1506 /*
1507 * Clears the driver's internal Port Enable/Disable
1508 * Change flag
1509 */
1510 dev_dbg(hsotg->dev,
1511 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1512 hsotg->flags.b.port_enable_change = 0;
1513 break;
1514
1515 case USB_PORT_FEAT_C_SUSPEND:
1516 /*
1517 * Clears the driver's internal Port Suspend Change
1518 * flag, which is set when resume signaling on the host
1519 * port is complete
1520 */
1521 dev_dbg(hsotg->dev,
1522 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1523 hsotg->flags.b.port_suspend_change = 0;
1524 break;
1525
1526 case USB_PORT_FEAT_C_PORT_L1:
1527 dev_dbg(hsotg->dev,
1528 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1529 hsotg->flags.b.port_l1_change = 0;
1530 break;
1531
1532 case USB_PORT_FEAT_C_OVER_CURRENT:
1533 dev_dbg(hsotg->dev,
1534 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1535 hsotg->flags.b.port_over_current_change = 0;
1536 break;
1537
1538 default:
1539 retval = -EINVAL;
1540 dev_err(hsotg->dev,
1541 "ClearPortFeature request %1xh unknown or unsupported\n",
1542 wvalue);
1543 }
1544 break;
1545
1546 case GetHubDescriptor:
1547 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1548 hub_desc = (struct usb_hub_descriptor *)buf;
1549 hub_desc->bDescLength = 9;
1550 hub_desc->bDescriptorType = 0x29;
1551 hub_desc->bNbrPorts = 1;
1552 hub_desc->wHubCharacteristics = cpu_to_le16(0x08);
1553 hub_desc->bPwrOn2PwrGood = 1;
1554 hub_desc->bHubContrCurrent = 0;
1555 hub_desc->u.hs.DeviceRemovable[0] = 0;
1556 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1557 break;
1558
1559 case GetHubStatus:
1560 dev_dbg(hsotg->dev, "GetHubStatus\n");
1561 memset(buf, 0, 4);
1562 break;
1563
1564 case GetPortStatus:
b8313417
PZ		 1565 dev_vdbg(hsotg->dev,
1566 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1567 hsotg->flags.d32);
7359d482
PZ		 1568 if (!windex || windex > 1)
1569 goto error;
1570
1571 port_status = 0;
1572 if (hsotg->flags.b.port_connect_status_change)
1573 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1574 if (hsotg->flags.b.port_enable_change)
1575 port_status |= USB_PORT_STAT_C_ENABLE << 16;
1576 if (hsotg->flags.b.port_suspend_change)
1577 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1578 if (hsotg->flags.b.port_l1_change)
1579 port_status |= USB_PORT_STAT_C_L1 << 16;
1580 if (hsotg->flags.b.port_reset_change)
1581 port_status |= USB_PORT_STAT_C_RESET << 16;
1582 if (hsotg->flags.b.port_over_current_change) {
1583 dev_warn(hsotg->dev, "Overcurrent change detected\n");
1584 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1585 }
1586
1587 if (!hsotg->flags.b.port_connect_status) {
1588 /*
1589 * The port is disconnected, which means the core is
1590 * either in device mode or it soon will be. Just
1591 * return 0's for the remainder of the port status
1592 * since the port register can't be read if the core
1593 * is in device mode.
1594 */
1595 *(__le32 *)buf = cpu_to_le32(port_status);
1596 break;
1597 }
1598
1599 hprt0 = readl(hsotg->regs + HPRT0);
b8313417 1600 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
7359d482
PZ		 1601
1602 if (hprt0 & HPRT0_CONNSTS)
1603 port_status |= USB_PORT_STAT_CONNECTION;
1604 if (hprt0 & HPRT0_ENA)
1605 port_status |= USB_PORT_STAT_ENABLE;
1606 if (hprt0 & HPRT0_SUSP)
1607 port_status |= USB_PORT_STAT_SUSPEND;
1608 if (hprt0 & HPRT0_OVRCURRACT)
1609 port_status |= USB_PORT_STAT_OVERCURRENT;
1610 if (hprt0 & HPRT0_RST)
1611 port_status |= USB_PORT_STAT_RESET;
1612 if (hprt0 & HPRT0_PWR)
1613 port_status |= USB_PORT_STAT_POWER;
1614
1615 speed = hprt0 & HPRT0_SPD_MASK;
1616 if (speed == HPRT0_SPD_HIGH_SPEED)
1617 port_status |= USB_PORT_STAT_HIGH_SPEED;
1618 else if (speed == HPRT0_SPD_LOW_SPEED)
1619 port_status |= USB_PORT_STAT_LOW_SPEED;
1620
1621 if (hprt0 & HPRT0_TSTCTL_MASK)
1622 port_status |= USB_PORT_STAT_TEST;
1623 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1624
b8313417 1625 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
7359d482
PZ		 1626 *(__le32 *)buf = cpu_to_le32(port_status);
1627 break;
1628
1629 case SetHubFeature:
1630 dev_dbg(hsotg->dev, "SetHubFeature\n");
1631 /* No HUB features supported */
1632 break;
1633
1634 case SetPortFeature:
1635 dev_dbg(hsotg->dev, "SetPortFeature\n");
1636 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1637 goto error;
1638
1639 if (!hsotg->flags.b.port_connect_status) {
1640 /*
1641 * The port is disconnected, which means the core is
1642 * either in device mode or it soon will be. Just
1643 * return without doing anything since the port
1644 * register can't be written if the core is in device
1645 * mode.
1646 */
1647 break;
1648 }
1649
1650 switch (wvalue) {
1651 case USB_PORT_FEAT_SUSPEND:
1652 dev_dbg(hsotg->dev,
1653 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1654 if (windex != hsotg->otg_port)
1655 goto error;
1656 dwc2_port_suspend(hsotg, windex);
1657 break;
1658
1659 case USB_PORT_FEAT_POWER:
1660 dev_dbg(hsotg->dev,
1661 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1662 hprt0 = dwc2_read_hprt0(hsotg);
1663 hprt0 |= HPRT0_PWR;
1664 writel(hprt0, hsotg->regs + HPRT0);
1665 break;
1666
1667 case USB_PORT_FEAT_RESET:
1668 hprt0 = dwc2_read_hprt0(hsotg);
1669 dev_dbg(hsotg->dev,
1670 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1671 pcgctl = readl(hsotg->regs + PCGCTL);
1672 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1673 writel(pcgctl, hsotg->regs + PCGCTL);
1674 /* ??? Original driver does this */
1675 writel(0, hsotg->regs + PCGCTL);
1676
1677 hprt0 = dwc2_read_hprt0(hsotg);
1678 /* Clear suspend bit if resetting from suspend state */
1679 hprt0 &= ~HPRT0_SUSP;
1680
1681 /*
1682 * When B-Host the Port reset bit is set in the Start
1683 * HCD Callback function, so that the reset is started
1684 * within 1ms of the HNP success interrupt
1685 */
1686 if (!dwc2_hcd_is_b_host(hsotg)) {
1687 hprt0 |= HPRT0_PWR | HPRT0_RST;
1688 dev_dbg(hsotg->dev,
1689 "In host mode, hprt0=%08x\n", hprt0);
1690 writel(hprt0, hsotg->regs + HPRT0);
1691 }
1692
1693 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1694 usleep_range(50000, 70000);
1695 hprt0 &= ~HPRT0_RST;
1696 writel(hprt0, hsotg->regs + HPRT0);
1697 hsotg->lx_state = DWC2_L0; /* Now back to On state */
1698 break;
1699
1700 case USB_PORT_FEAT_INDICATOR:
1701 dev_dbg(hsotg->dev,
1702 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1703 /* Not supported */
1704 break;
1705
1706 default:
1707 retval = -EINVAL;
1708 dev_err(hsotg->dev,
1709 "SetPortFeature %1xh unknown or unsupported\n",
1710 wvalue);
1711 break;
1712 }
1713 break;
1714
1715 default:
1716error:
1717 retval = -EINVAL;
1718 dev_dbg(hsotg->dev,
1719 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1720 typereq, windex, wvalue);
1721 break;
1722 }
1723
1724 return retval;
1725}
1726
1727static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1728{
1729 int retval;
1730
7359d482
PZ		 1731 if (port != 1)
1732 return -EINVAL;
1733
1734 retval = (hsotg->flags.b.port_connect_status_change ||
1735 hsotg->flags.b.port_reset_change ||
1736 hsotg->flags.b.port_enable_change ||
1737 hsotg->flags.b.port_suspend_change ||
1738 hsotg->flags.b.port_over_current_change);
1739
1740 if (retval) {
1741 dev_dbg(hsotg->dev,
1742 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1743 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
1744 hsotg->flags.b.port_connect_status_change);
1745 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
1746 hsotg->flags.b.port_reset_change);
1747 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
1748 hsotg->flags.b.port_enable_change);
1749 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
1750 hsotg->flags.b.port_suspend_change);
1751 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
1752 hsotg->flags.b.port_over_current_change);
1753 }
1754
1755 return retval;
1756}
1757
1758int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1759{
1760 u32 hfnum = readl(hsotg->regs + HFNUM);
1761
1762#ifdef DWC2_DEBUG_SOF
1763 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1764 hfnum >> HFNUM_FRNUM_SHIFT &
1765 HFNUM_FRNUM_MASK >> HFNUM_FRNUM_SHIFT);
1766#endif
1767 return hfnum >> HFNUM_FRNUM_SHIFT &
1768 HFNUM_FRNUM_MASK >> HFNUM_FRNUM_SHIFT;
1769}
1770
1771int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1772{
1773 return (hsotg->op_state == OTG_STATE_B_HOST);
1774}
1775
1776static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1777 int iso_desc_count,
1778 gfp_t mem_flags)
1779{
1780 struct dwc2_hcd_urb *urb;
1781 u32 size = sizeof(*urb) + iso_desc_count *
1782 sizeof(struct dwc2_hcd_iso_packet_desc);
1783
1784 urb = kzalloc(size, mem_flags);
1785 if (urb)
1786 urb->packet_count = iso_desc_count;
1787 return urb;
1788}
1789
1790static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1791 struct dwc2_hcd_urb *urb, u8 dev_addr,
1792 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1793{
b49977a6
MK		 1794 if (dbg_perio() ||
1795 ep_type == USB_ENDPOINT_XFER_BULK ||
1796 ep_type == USB_ENDPOINT_XFER_CONTROL)
1797 dev_vdbg(hsotg->dev,
1798 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1799 dev_addr, ep_num, ep_dir, ep_type, mps);
7359d482
PZ		 1800 urb->pipe_info.dev_addr = dev_addr;
1801 urb->pipe_info.ep_num = ep_num;
1802 urb->pipe_info.pipe_type = ep_type;
1803 urb->pipe_info.pipe_dir = ep_dir;
1804 urb->pipe_info.mps = mps;
1805}
1806
1807/*
1808 * NOTE: This function will be removed once the peripheral controller code
1809 * is integrated and the driver is stable
1810 */
1811void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1812{
1813#ifdef DEBUG
1814 struct dwc2_host_chan *chan;
1815 struct dwc2_hcd_urb *urb;
1816 struct dwc2_qtd *qtd;
1817 int num_channels;
1818 u32 np_tx_status;
1819 u32 p_tx_status;
1820 int i;
1821
1822 num_channels = hsotg->core_params->host_channels;
1823 dev_dbg(hsotg->dev, "\n");
1824 dev_dbg(hsotg->dev,
1825 "************************************************************\n");
1826 dev_dbg(hsotg->dev, "HCD State:\n");
1827 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
1828
1829 for (i = 0; i < num_channels; i++) {
1830 chan = hsotg->hc_ptr_array[i];
1831 dev_dbg(hsotg->dev, " Channel %d:\n", i);
1832 dev_dbg(hsotg->dev,
1833 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1834 chan->dev_addr, chan->ep_num, chan->ep_is_in);
1835 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
1836 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
1837 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
1838 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
1839 chan->data_pid_start);
1840 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
1841 dev_dbg(hsotg->dev, " xfer_started: %d\n",
1842 chan->xfer_started);
1843 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
1844 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
1845 (unsigned long)chan->xfer_dma);
1846 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
1847 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
1848 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
1849 chan->halt_on_queue);
1850 dev_dbg(hsotg->dev, " halt_pending: %d\n",
1851 chan->halt_pending);
1852 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
1853 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
1854 dev_dbg(hsotg->dev, " complete_split: %d\n",
1855 chan->complete_split);
1856 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
1857 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
1858 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
1859 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
1860 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
1861
1862 if (chan->xfer_started) {
1863 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1864
1865 hfnum = readl(hsotg->regs + HFNUM);
1866 hcchar = readl(hsotg->regs + HCCHAR(i));
1867 hctsiz = readl(hsotg->regs + HCTSIZ(i));
1868 hcint = readl(hsotg->regs + HCINT(i));
1869 hcintmsk = readl(hsotg->regs + HCINTMSK(i));
1870 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
1871 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
1872 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
1873 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
1874 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
1875 }
1876
1877 if (!(chan->xfer_started && chan->qh))
1878 continue;
1879
1880 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
1881 if (!qtd->in_process)
1882 break;
1883 urb = qtd->urb;
1884 dev_dbg(hsotg->dev, " URB Info:\n");
1885 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
1886 qtd, urb);
1887 if (urb) {
1888 dev_dbg(hsotg->dev,
1889 " Dev: %d, EP: %d %s\n",
1890 dwc2_hcd_get_dev_addr(&urb->pipe_info),
1891 dwc2_hcd_get_ep_num(&urb->pipe_info),
1892 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
1893 "IN" : "OUT");
1894 dev_dbg(hsotg->dev,
1895 " Max packet size: %d\n",
1896 dwc2_hcd_get_mps(&urb->pipe_info));
1897 dev_dbg(hsotg->dev,
1898 " transfer_buffer: %p\n",
1899 urb->buf);
157dfaac
PZ		 1900 dev_dbg(hsotg->dev,
1901 " transfer_dma: %08lx\n",
1902 (unsigned long)urb->dma);
7359d482
PZ		 1903 dev_dbg(hsotg->dev,
1904 " transfer_buffer_length: %d\n",
1905 urb->length);
1906 dev_dbg(hsotg->dev, " actual_length: %d\n",
1907 urb->actual_length);
1908 }
1909 }
1910 }
1911
1912 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
1913 hsotg->non_periodic_channels);
1914 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
1915 hsotg->periodic_channels);
1916 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
1917 np_tx_status = readl(hsotg->regs + GNPTXSTS);
1918 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
1919 np_tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1920 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT);
1921 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
1922 np_tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1923 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT);
1924 p_tx_status = readl(hsotg->regs + HPTXSTS);
1925 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
1926 p_tx_status >> TXSTS_QSPCAVAIL_SHIFT &
1927 TXSTS_QSPCAVAIL_MASK >> TXSTS_QSPCAVAIL_SHIFT);
1928 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
1929 p_tx_status >> TXSTS_FSPCAVAIL_SHIFT &
1930 TXSTS_FSPCAVAIL_MASK >> TXSTS_FSPCAVAIL_SHIFT);
1931 dwc2_hcd_dump_frrem(hsotg);
1932 dwc2_dump_global_registers(hsotg);
1933 dwc2_dump_host_registers(hsotg);
1934 dev_dbg(hsotg->dev,
1935 "************************************************************\n");
1936 dev_dbg(hsotg->dev, "\n");
1937#endif
1938}
1939
1940/*
1941 * NOTE: This function will be removed once the peripheral controller code
1942 * is integrated and the driver is stable
1943 */
1944void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
1945{
1946#ifdef DWC2_DUMP_FRREM
1947 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
1948 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1949 hsotg->frrem_samples, hsotg->frrem_accum,
1950 hsotg->frrem_samples > 0 ?
1951 hsotg->frrem_accum / hsotg->frrem_samples : 0);
1952 dev_dbg(hsotg->dev, "\n");
1953 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
1954 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1955 hsotg->hfnum_7_samples,
1956 hsotg->hfnum_7_frrem_accum,
1957 hsotg->hfnum_7_samples > 0 ?
1958 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
1959 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
1960 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1961 hsotg->hfnum_0_samples,
1962 hsotg->hfnum_0_frrem_accum,
1963 hsotg->hfnum_0_samples > 0 ?
1964 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
1965 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
1966 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1967 hsotg->hfnum_other_samples,
1968 hsotg->hfnum_other_frrem_accum,
1969 hsotg->hfnum_other_samples > 0 ?
1970 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
1971 0);
1972 dev_dbg(hsotg->dev, "\n");
1973 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
1974 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1975 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
1976 hsotg->hfnum_7_samples_a > 0 ?
1977 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
1978 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
1979 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1980 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
1981 hsotg->hfnum_0_samples_a > 0 ?
1982 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
1983 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
1984 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1985 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
1986 hsotg->hfnum_other_samples_a > 0 ?
1987 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
1988 : 0);
1989 dev_dbg(hsotg->dev, "\n");
1990 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
1991 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1992 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
1993 hsotg->hfnum_7_samples_b > 0 ?
1994 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
1995 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
1996 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
1997 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
1998 (hsotg->hfnum_0_samples_b > 0) ?
1999 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2000 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2001 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
2002 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2003 (hsotg->hfnum_other_samples_b > 0) ?
2004 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2005 : 0);
2006#endif
2007}
2008
2009struct wrapper_priv_data {
2010 struct dwc2_hsotg *hsotg;
2011};
2012
2013/* Gets the dwc2_hsotg from a usb_hcd */
2014static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2015{
2016 struct wrapper_priv_data *p;
2017
2018 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2019 return p->hsotg;
2020}
2021
2022static int _dwc2_hcd_start(struct usb_hcd *hcd);
2023
2024void dwc2_host_start(struct dwc2_hsotg *hsotg)
2025{
2026 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2027
2028 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2029 _dwc2_hcd_start(hcd);
2030}
2031
2032void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2033{
2034 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2035
2036 hcd->self.is_b_host = 0;
2037}
2038
2039void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2040 int *hub_port)
2041{
2042 struct urb *urb = context;
2043
2044 if (urb->dev->tt)
2045 *hub_addr = urb->dev->tt->hub->devnum;
2046 else
2047 *hub_addr = 0;
2048 *hub_port = urb->dev->ttport;
2049}
2050
2051int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2052{
2053 struct urb *urb = context;
2054
2055 return urb->dev->speed;
2056}
2057
2058static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2059 struct urb *urb)
2060{
2061 struct usb_bus *bus = hcd_to_bus(hcd);
2062
2063 if (urb->interval)
2064 bus->bandwidth_allocated += bw / urb->interval;
2065 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2066 bus->bandwidth_isoc_reqs++;
2067 else
2068 bus->bandwidth_int_reqs++;
2069}
2070
2071static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2072 struct urb *urb)
2073{
2074 struct usb_bus *bus = hcd_to_bus(hcd);
2075
2076 if (urb->interval)
2077 bus->bandwidth_allocated -= bw / urb->interval;
2078 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2079 bus->bandwidth_isoc_reqs--;
2080 else
2081 bus->bandwidth_int_reqs--;
2082}
2083
2084/*
2085 * Sets the final status of an URB and returns it to the upper layer. Any
2086 * required cleanup of the URB is performed.
2087 *
2088 * Must be called with interrupt disabled and spinlock held
2089 */
0d012b98
PZ		 2090void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2091 int status)
7359d482 2092{
0d012b98 2093 struct urb *urb;
7359d482
PZ		 2094 int i;
2095
0d012b98
PZ		 2096 if (!qtd) {
2097 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
7359d482
PZ		 2098 return;
2099 }
2100
0d012b98
PZ		 2101 if (!qtd->urb) {
2102 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
7359d482
PZ		 2103 return;
2104 }
2105
0d012b98
PZ		 2106 urb = qtd->urb->priv;
2107 if (!urb) {
2108 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2109 return;
2110 }
2111
2112 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
7359d482 2113
b49977a6
MK		 2114 if (dbg_urb(urb))
2115 dev_vdbg(hsotg->dev,
2116 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2117 __func__, urb, usb_pipedevice(urb->pipe),
2118 usb_pipeendpoint(urb->pipe),
2119 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2120 urb->actual_length);
7359d482 2121
b49977a6 2122 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
7359d482
PZ		 2123 for (i = 0; i < urb->number_of_packets; i++)
2124 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2125 i, urb->iso_frame_desc[i].status);
2126 }
2127
2128 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
0d012b98 2129 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
7359d482
PZ		 2130 for (i = 0; i < urb->number_of_packets; ++i) {
2131 urb->iso_frame_desc[i].actual_length =
2132 dwc2_hcd_urb_get_iso_desc_actual_length(
0d012b98 2133 qtd->urb, i);
7359d482 2134 urb->iso_frame_desc[i].status =
0d012b98 2135 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
7359d482
PZ		 2136 }
2137 }
2138
2139 urb->status = status;
7359d482
PZ		 2140 if (!status) {
2141 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2142 urb->actual_length < urb->transfer_buffer_length)
2143 urb->status = -EREMOTEIO;
2144 }
2145
2146 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2147 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2148 struct usb_host_endpoint *ep = urb->ep;
2149
2150 if (ep)
2151 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2152 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2153 urb);
2154 }
2155
0d012b98
PZ		 2156 urb->hcpriv = NULL;
2157 kfree(qtd->urb);
2158 qtd->urb = NULL;
7359d482
PZ		 2159
2160 spin_unlock(&hsotg->lock);
2161 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2162 spin_lock(&hsotg->lock);
2163}
2164
2165/*
2166 * Work queue function for starting the HCD when A-Cable is connected
2167 */
2168static void dwc2_hcd_start_func(struct work_struct *work)
2169{
2170 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2171 start_work.work);
2172
2173 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2174 dwc2_host_start(hsotg);
2175}
2176
2177/*
2178 * Reset work queue function
2179 */
2180static void dwc2_hcd_reset_func(struct work_struct *work)
2181{
2182 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2183 reset_work.work);
2184 u32 hprt0;
2185
2186 dev_dbg(hsotg->dev, "USB RESET function called\n");
2187 hprt0 = dwc2_read_hprt0(hsotg);
2188 hprt0 &= ~HPRT0_RST;
2189 writel(hprt0, hsotg->regs + HPRT0);
2190 hsotg->flags.b.port_reset_change = 1;
2191}
2192
2193/*
2194 * =========================================================================
2195 * Linux HC Driver Functions
2196 * =========================================================================
2197 */
2198
2199/*
2200 * Initializes the DWC_otg controller and its root hub and prepares it for host
2201 * mode operation. Activates the root port. Returns 0 on success and a negative
2202 * error code on failure.
2203 */
2204static int _dwc2_hcd_start(struct usb_hcd *hcd)
2205{
2206 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2207 struct usb_bus *bus = hcd_to_bus(hcd);
2208 unsigned long flags;
2209
2210 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2211
2212 spin_lock_irqsave(&hsotg->lock, flags);
2213
2214 hcd->state = HC_STATE_RUNNING;
2215
2216 if (dwc2_is_device_mode(hsotg)) {
2217 spin_unlock_irqrestore(&hsotg->lock, flags);
2218 return 0; /* why 0 ?? */
2219 }
2220
2221 dwc2_hcd_reinit(hsotg);
2222
2223 /* Initialize and connect root hub if one is not already attached */
2224 if (bus->root_hub) {
2225 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2226 /* Inform the HUB driver to resume */
2227 usb_hcd_resume_root_hub(hcd);
2228 }
2229
2230 spin_unlock_irqrestore(&hsotg->lock, flags);
2231 return 0;
2232}
2233
2234/*
2235 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2236 * stopped.
2237 */
2238static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2239{
2240 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2241 unsigned long flags;
2242
2243 spin_lock_irqsave(&hsotg->lock, flags);
2244 dwc2_hcd_stop(hsotg);
2245 spin_unlock_irqrestore(&hsotg->lock, flags);
2246
2247 usleep_range(1000, 3000);
2248}
2249
2250/* Returns the current frame number */
2251static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2252{
2253 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2254
2255 return dwc2_hcd_get_frame_number(hsotg);
2256}
2257
2258static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2259 char *fn_name)
2260{
2261#ifdef VERBOSE_DEBUG
2262 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2263 char *pipetype;
2264 char *speed;
2265
2266 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2267 dev_vdbg(hsotg->dev, " Device address: %d\n",
2268 usb_pipedevice(urb->pipe));
2269 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
2270 usb_pipeendpoint(urb->pipe),
2271 usb_pipein(urb->pipe) ? "IN" : "OUT");
2272
2273 switch (usb_pipetype(urb->pipe)) {
2274 case PIPE_CONTROL:
2275 pipetype = "CONTROL";
2276 break;
2277 case PIPE_BULK:
2278 pipetype = "BULK";
2279 break;
2280 case PIPE_INTERRUPT:
2281 pipetype = "INTERRUPT";
2282 break;
2283 case PIPE_ISOCHRONOUS:
2284 pipetype = "ISOCHRONOUS";
2285 break;
2286 default:
2287 pipetype = "UNKNOWN";
2288 break;
2289 }
2290
2291 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
2292 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2293 "IN" : "OUT");
2294
2295 switch (urb->dev->speed) {
2296 case USB_SPEED_HIGH:
2297 speed = "HIGH";
2298 break;
2299 case USB_SPEED_FULL:
2300 speed = "FULL";
2301 break;
2302 case USB_SPEED_LOW:
2303 speed = "LOW";
2304 break;
2305 default:
2306 speed = "UNKNOWN";
2307 break;
2308 }
2309
2310 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
2311 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
2312 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2313 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
2314 urb->transfer_buffer_length);
157dfaac
PZ		 2315 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
2316 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2317 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
2318 urb->setup_packet, (unsigned long)urb->setup_dma);
7359d482
PZ		 2319 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
2320
2321 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2322 int i;
2323
2324 for (i = 0; i < urb->number_of_packets; i++) {
2325 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
2326 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
2327 urb->iso_frame_desc[i].offset,
2328 urb->iso_frame_desc[i].length);
2329 }
2330 }
2331#endif
2332}
2333
2334/*
2335 * Starts processing a USB transfer request specified by a USB Request Block
2336 * (URB). mem_flags indicates the type of memory allocation to use while
2337 * processing this URB.
2338 */
2339static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2340 gfp_t mem_flags)
2341{
2342 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2343 struct usb_host_endpoint *ep = urb->ep;
2344 struct dwc2_hcd_urb *dwc2_urb;
2345 int i;
2346 int alloc_bandwidth = 0;
2347 int retval = 0;
2348 u8 ep_type = 0;
2349 u32 tflags = 0;
2350 void *buf;
2351 unsigned long flags;
2352
b49977a6
MK		 2353 if (dbg_urb(urb)) {
2354 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2355 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2356 }
7359d482
PZ		 2357
2358 if (ep == NULL)
2359 return -EINVAL;
2360
2361 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2362 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2363 spin_lock_irqsave(&hsotg->lock, flags);
2364 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2365 alloc_bandwidth = 1;
2366 spin_unlock_irqrestore(&hsotg->lock, flags);
2367 }
2368
2369 switch (usb_pipetype(urb->pipe)) {
2370 case PIPE_CONTROL:
2371 ep_type = USB_ENDPOINT_XFER_CONTROL;
2372 break;
2373 case PIPE_ISOCHRONOUS:
2374 ep_type = USB_ENDPOINT_XFER_ISOC;
2375 break;
2376 case PIPE_BULK:
2377 ep_type = USB_ENDPOINT_XFER_BULK;
2378 break;
2379 case PIPE_INTERRUPT:
2380 ep_type = USB_ENDPOINT_XFER_INT;
2381 break;
2382 default:
2383 dev_warn(hsotg->dev, "Wrong ep type\n");
2384 }
2385
2386 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2387 mem_flags);
2388 if (!dwc2_urb)
2389 return -ENOMEM;
2390
2391 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2392 usb_pipeendpoint(urb->pipe), ep_type,
2393 usb_pipein(urb->pipe),
2394 usb_maxpacket(urb->dev, urb->pipe,
2395 !(usb_pipein(urb->pipe))));
2396
2397 buf = urb->transfer_buffer;
2398 if (hcd->self.uses_dma) {
2399 /*
2400 * Calculate virtual address from physical address, because
2401 * some class driver may not fill transfer_buffer.
2402 * In Buffer DMA mode virtual address is used, when handling
2403 * non-DWORD aligned buffers.
2404 */
2405 buf = bus_to_virt(urb->transfer_dma);
2406 }
2407
2408 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2409 tflags |= URB_GIVEBACK_ASAP;
2410 if (urb->transfer_flags & URB_ZERO_PACKET)
2411 tflags |= URB_SEND_ZERO_PACKET;
2412
2413 dwc2_urb->priv = urb;
2414 dwc2_urb->buf = buf;
2415 dwc2_urb->dma = urb->transfer_dma;
2416 dwc2_urb->length = urb->transfer_buffer_length;
2417 dwc2_urb->setup_packet = urb->setup_packet;
2418 dwc2_urb->setup_dma = urb->setup_dma;
2419 dwc2_urb->flags = tflags;
2420 dwc2_urb->interval = urb->interval;
2421 dwc2_urb->status = -EINPROGRESS;
2422
2423 for (i = 0; i < urb->number_of_packets; ++i)
2424 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2425 urb->iso_frame_desc[i].offset,
2426 urb->iso_frame_desc[i].length);
2427
2428 urb->hcpriv = dwc2_urb;
2429 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, &ep->hcpriv,
2430 mem_flags);
2431 if (retval) {
2432 urb->hcpriv = NULL;
2433 kfree(dwc2_urb);
2434 } else {
2435 if (alloc_bandwidth) {
2436 spin_lock_irqsave(&hsotg->lock, flags);
2437 dwc2_allocate_bus_bandwidth(hcd,
2438 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2439 urb);
2440 spin_unlock_irqrestore(&hsotg->lock, flags);
2441 }
2442 }
2443
2444 return retval;
2445}
2446
2447/*
2448 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2449 */
2450static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2451 int status)
2452{
2453 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2454 int rc = 0;
2455 unsigned long flags;
2456
2457 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2458 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2459
2460 spin_lock_irqsave(&hsotg->lock, flags);
2461
2462 if (!urb->hcpriv) {
2463 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2464 goto out;
2465 }
2466
2467 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2468
2469 kfree(urb->hcpriv);
2470 urb->hcpriv = NULL;
2471
2472 /* Higher layer software sets URB status */
2473 spin_unlock(&hsotg->lock);
2474 usb_hcd_giveback_urb(hcd, urb, status);
2475 spin_lock(&hsotg->lock);
2476
2477 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2478 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
2479out:
2480 spin_unlock_irqrestore(&hsotg->lock, flags);
2481
2482 return rc;
2483}
2484
2485/*
2486 * Frees resources in the DWC_otg controller related to a given endpoint. Also
2487 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2488 * must already be dequeued.
2489 */
2490static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2491 struct usb_host_endpoint *ep)
2492{
2493 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2494
2495 dev_dbg(hsotg->dev,
2496 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2497 ep->desc.bEndpointAddress, ep->hcpriv);
2498 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2499}
2500
2501/*
2502 * Resets endpoint specific parameter values, in current version used to reset
2503 * the data toggle (as a WA). This function can be called from usb_clear_halt
2504 * routine.
2505 */
2506static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2507 struct usb_host_endpoint *ep)
2508{
2509 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2510 int is_control = usb_endpoint_xfer_control(&ep->desc);
2511 int is_out = usb_endpoint_dir_out(&ep->desc);
2512 int epnum = usb_endpoint_num(&ep->desc);
2513 struct usb_device *udev;
2514 unsigned long flags;
2515
2516 dev_dbg(hsotg->dev,
2517 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2518 ep->desc.bEndpointAddress);
2519
2520 udev = to_usb_device(hsotg->dev);
2521
2522 spin_lock_irqsave(&hsotg->lock, flags);
2523
2524 usb_settoggle(udev, epnum, is_out, 0);
2525 if (is_control)
2526 usb_settoggle(udev, epnum, !is_out, 0);
2527 dwc2_hcd_endpoint_reset(hsotg, ep);
2528
2529 spin_unlock_irqrestore(&hsotg->lock, flags);
2530}
2531
2532/*
2533 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2534 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2535 * interrupt.
2536 *
2537 * This function is called by the USB core when an interrupt occurs
2538 */
2539static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2540{
2541 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
7359d482 2542
ca18f4a6 2543 return dwc2_handle_hcd_intr(hsotg);
7359d482
PZ		 2544}
2545
2546/*
2547 * Creates Status Change bitmap for the root hub and root port. The bitmap is
2548 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2549 * is the status change indicator for the single root port. Returns 1 if either
2550 * change indicator is 1, otherwise returns 0.
2551 */
2552static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2553{
2554 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2555
2556 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2557 return buf[0] != 0;
2558}
2559
2560/* Handles hub class-specific requests */
2561static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2562 u16 windex, char *buf, u16 wlength)
2563{
2564 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2565 wvalue, windex, buf, wlength);
2566 return retval;
2567}
2568
2569/* Handles hub TT buffer clear completions */
2570static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2571 struct usb_host_endpoint *ep)
2572{
2573 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2574 struct dwc2_qh *qh;
2575 unsigned long flags;
2576
2577 qh = ep->hcpriv;
2578 if (!qh)
2579 return;
2580
2581 spin_lock_irqsave(&hsotg->lock, flags);
2582 qh->tt_buffer_dirty = 0;
2583
2584 if (hsotg->flags.b.port_connect_status)
2585 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2586
2587 spin_unlock_irqrestore(&hsotg->lock, flags);
2588}
2589
2590static struct hc_driver dwc2_hc_driver = {
2591 .description = "dwc2_hsotg",
2592 .product_desc = "DWC OTG Controller",
2593 .hcd_priv_size = sizeof(struct wrapper_priv_data),
2594
2595 .irq = _dwc2_hcd_irq,
2596 .flags = HCD_MEMORY | HCD_USB2,
2597
2598 .start = _dwc2_hcd_start,
2599 .stop = _dwc2_hcd_stop,
2600 .urb_enqueue = _dwc2_hcd_urb_enqueue,
2601 .urb_dequeue = _dwc2_hcd_urb_dequeue,
2602 .endpoint_disable = _dwc2_hcd_endpoint_disable,
2603 .endpoint_reset = _dwc2_hcd_endpoint_reset,
2604 .get_frame_number = _dwc2_hcd_get_frame_number,
2605
2606 .hub_status_data = _dwc2_hcd_hub_status_data,
2607 .hub_control = _dwc2_hcd_hub_control,
2608 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2609};
2610
2611/*
2612 * Frees secondary storage associated with the dwc2_hsotg structure contained
2613 * in the struct usb_hcd field
2614 */
2615static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2616{
2617 u32 ahbcfg;
2618 u32 dctl;
2619 int i;
2620
2621 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2622
2623 /* Free memory for QH/QTD lists */
2624 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2625 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2626 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2627 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2628 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2629 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2630
2631 /* Free memory for the host channels */
2632 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2633 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2634
2635 if (chan != NULL) {
2636 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2637 i, chan);
2638 hsotg->hc_ptr_array[i] = NULL;
2639 kfree(chan);
2640 }
2641 }
2642
2643 if (hsotg->core_params->dma_enable > 0) {
2644 if (hsotg->status_buf) {
2645 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2646 hsotg->status_buf,
2647 hsotg->status_buf_dma);
2648 hsotg->status_buf = NULL;
2649 }
2650 } else {
2651 kfree(hsotg->status_buf);
2652 hsotg->status_buf = NULL;
2653 }
2654
2655 ahbcfg = readl(hsotg->regs + GAHBCFG);
2656
2657 /* Disable all interrupts */
2658 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2659 writel(ahbcfg, hsotg->regs + GAHBCFG);
2660 writel(0, hsotg->regs + GINTMSK);
2661
2662 if (hsotg->snpsid >= DWC2_CORE_REV_3_00a) {
2663 dctl = readl(hsotg->regs + DCTL);
2664 dctl |= DCTL_SFTDISCON;
2665 writel(dctl, hsotg->regs + DCTL);
2666 }
2667
2668 if (hsotg->wq_otg) {
2669 if (!cancel_work_sync(&hsotg->wf_otg))
2670 flush_workqueue(hsotg->wq_otg);
2671 destroy_workqueue(hsotg->wq_otg);
2672 }
2673
2674 kfree(hsotg->core_params);
2675 hsotg->core_params = NULL;
2676 del_timer(&hsotg->wkp_timer);
2677}
2678
2679static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2680{
2681 /* Turn off all host-specific interrupts */
2682 dwc2_disable_host_interrupts(hsotg);
2683
2684 dwc2_hcd_free(hsotg);
2685}
2686
8284f93b
MK		 2687/*
2688 * Sets all parameters to the given value.
2689 *
2690 * Assumes that the dwc2_core_params struct contains only integers.
2691 */
2692void dwc2_set_all_params(struct dwc2_core_params *params, int value)
7359d482 2693{
8284f93b
MK		 2694 int *p = (int *)params;
2695 size_t size = sizeof(*params) / sizeof(*p);
7359d482
PZ		 2696 int i;
2697
2698 for (i = 0; i < size; i++)
2699 p[i] = -1;
2700}
5b9974b1 2701EXPORT_SYMBOL_GPL(dwc2_set_all_params);
7359d482
PZ		 2702
2703/*
2704 * Initializes the HCD. This function allocates memory for and initializes the
2705 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2706 * USB bus with the core and calls the hc_driver->start() function. It returns
2707 * a negative error on failure.
2708 */
e62662c7 2709int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
90dbceaf 2710 const struct dwc2_core_params *params)
7359d482
PZ		 2711{
2712 struct usb_hcd *hcd;
2713 struct dwc2_host_chan *channel;
2714 u32 snpsid, gusbcfg, hcfg;
2715 int i, num_channels;
2716 int retval = -ENOMEM;
2717
e62662c7 2718 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
7359d482
PZ		 2719
2720 /*
2721 * Attempt to ensure this device is really a DWC_otg Controller.
2722 * Read and verify the GSNPSID register contents. The value should be
2723 * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
2724 * as in "OTG version 2.xx" or "OTG version 3.xx".
2725 */
2726 snpsid = readl(hsotg->regs + GSNPSID);
2727 if ((snpsid & 0xfffff000) != 0x4f542000 &&
2728 (snpsid & 0xfffff000) != 0x4f543000) {
e62662c7 2729 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n", snpsid);
7359d482
PZ		 2730 retval = -ENODEV;
2731 goto error1;
2732 }
2733
7359d482
PZ		 2734 /*
2735 * Store the contents of the hardware configuration registers here for
2736 * easy access later
2737 */
2738 hsotg->hwcfg1 = readl(hsotg->regs + GHWCFG1);
2739 hsotg->hwcfg2 = readl(hsotg->regs + GHWCFG2);
2740 hsotg->hwcfg3 = readl(hsotg->regs + GHWCFG3);
2741 hsotg->hwcfg4 = readl(hsotg->regs + GHWCFG4);
2742
2743 dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hsotg->hwcfg1);
2744 dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hsotg->hwcfg2);
2745 dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hsotg->hwcfg3);
2746 dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hsotg->hwcfg4);
2747
2748 /* Force host mode to get HPTXFSIZ exact power on value */
2749 gusbcfg = readl(hsotg->regs + GUSBCFG);
2750 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
2751 writel(gusbcfg, hsotg->regs + GUSBCFG);
2752 usleep_range(100000, 150000);
2753
2754 hsotg->hptxfsiz = readl(hsotg->regs + HPTXFSIZ);
2755 dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hsotg->hptxfsiz);
2756 gusbcfg = readl(hsotg->regs + GUSBCFG);
2757 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
2758 writel(gusbcfg, hsotg->regs + GUSBCFG);
2759 usleep_range(100000, 150000);
2760
2761 hcfg = readl(hsotg->regs + HCFG);
2762 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
2763 dev_dbg(hsotg->dev, "op_mode=%0x\n",
2764 hsotg->hwcfg2 >> GHWCFG2_OP_MODE_SHIFT &
2765 GHWCFG2_OP_MODE_MASK >> GHWCFG2_OP_MODE_SHIFT);
2766 dev_dbg(hsotg->dev, "arch=%0x\n",
2767 hsotg->hwcfg2 >> GHWCFG2_ARCHITECTURE_SHIFT &
2768 GHWCFG2_ARCHITECTURE_MASK >> GHWCFG2_ARCHITECTURE_SHIFT);
2769 dev_dbg(hsotg->dev, "num_dev_ep=%d\n",
2770 hsotg->hwcfg2 >> GHWCFG2_NUM_DEV_EP_SHIFT &
2771 GHWCFG2_NUM_DEV_EP_MASK >> GHWCFG2_NUM_DEV_EP_SHIFT);
2772 dev_dbg(hsotg->dev, "max_host_chan=%d\n",
2773 hsotg->hwcfg2 >> GHWCFG2_NUM_HOST_CHAN_SHIFT &
2774 GHWCFG2_NUM_HOST_CHAN_MASK >> GHWCFG2_NUM_HOST_CHAN_SHIFT);
2775 dev_dbg(hsotg->dev, "nonperio_tx_q_depth=0x%0x\n",
2776 hsotg->hwcfg2 >> GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT &
2777 GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK >>
2778 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT);
2779 dev_dbg(hsotg->dev, "host_perio_tx_q_depth=0x%0x\n",
2780 hsotg->hwcfg2 >> GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT &
2781 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK >>
2782 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT);
2783 dev_dbg(hsotg->dev, "dev_token_q_depth=0x%0x\n",
2784 hsotg->hwcfg2 >> GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT &
2785 GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK >>
2786 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT);
2787
2788#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2789 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
2790 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2791 if (!hsotg->frame_num_array)
ba0e60d1 2792 goto error1;
7359d482
PZ		 2793 hsotg->last_frame_num_array = kzalloc(
2794 sizeof(*hsotg->last_frame_num_array) *
2795 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
2796 if (!hsotg->last_frame_num_array)
ba0e60d1 2797 goto error1;
7359d482
PZ		 2798 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
2799#endif
2800
2801 hsotg->core_params = kzalloc(sizeof(*hsotg->core_params), GFP_KERNEL);
2802 if (!hsotg->core_params)
ba0e60d1 2803 goto error1;
7359d482 2804
8284f93b 2805 dwc2_set_all_params(hsotg->core_params, -1);
7359d482
PZ		 2806
2807 /* Validate parameter values */
2808 dwc2_set_parameters(hsotg, params);
2809
ba0e60d1
PZ		 2810 /* Set device flags indicating whether the HCD supports DMA */
2811 if (hsotg->core_params->dma_enable > 0) {
30885313
PZ		 2812 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
2813 dev_warn(hsotg->dev, "can't set DMA mask\n");
ba0e60d1
PZ		 2814 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)
2815 dev_warn(hsotg->dev,
2816 "can't enable workaround for >2GB RAM\n");
2817 } else {
2818 dma_set_mask(hsotg->dev, 0);
2819 dma_set_coherent_mask(hsotg->dev, 0);
2820 }
2821
2822 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
2823 if (!hcd)
2824 goto error1;
2825
2826 hcd->has_tt = 1;
2827
2828 spin_lock_init(&hsotg->lock);
2829 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
2830 hsotg->priv = hcd;
2831
7359d482
PZ		 2832 /*
2833 * Disable the global interrupt until all the interrupt handlers are
2834 * installed
2835 */
2836 dwc2_disable_global_interrupts(hsotg);
2837
6706c721
MK		 2838 /* Initialize the DWC_otg core, and select the Phy type */
2839 retval = dwc2_core_init(hsotg, true, irq);
2840 if (retval)
2841 goto error2;
2842
7359d482 2843 /* Create new workqueue and init work */
53510352 2844 retval = -ENOMEM;
050232a7 2845 hsotg->wq_otg = create_singlethread_workqueue("dwc2");
7359d482
PZ		 2846 if (!hsotg->wq_otg) {
2847 dev_err(hsotg->dev, "Failed to create workqueue\n");
2848 goto error2;
2849 }
2850 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
2851
2852 hsotg->snpsid = readl(hsotg->regs + GSNPSID);
2853 dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x\n",
2854 hsotg->snpsid >> 12 & 0xf, hsotg->snpsid >> 8 & 0xf,
2855 hsotg->snpsid >> 4 & 0xf, hsotg->snpsid & 0xf);
2856
2857 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
2858 (unsigned long)hsotg);
2859
2860 /* Initialize the non-periodic schedule */
2861 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
2862 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
2863
2864 /* Initialize the periodic schedule */
2865 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
2866 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
2867 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
2868 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
2869
2870 /*
2871 * Create a host channel descriptor for each host channel implemented
2872 * in the controller. Initialize the channel descriptor array.
2873 */
2874 INIT_LIST_HEAD(&hsotg->free_hc_list);
2875 num_channels = hsotg->core_params->host_channels;
2876 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
2877
2878 for (i = 0; i < num_channels; i++) {
2879 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
2880 if (channel == NULL)
2881 goto error3;
2882 channel->hc_num = i;
2883 hsotg->hc_ptr_array[i] = channel;
2884 }
2885
2886 /* Initialize hsotg start work */
2887 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
2888
2889 /* Initialize port reset work */
2890 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
2891
2892 /*
2893 * Allocate space for storing data on status transactions. Normally no
2894 * data is sent, but this space acts as a bit bucket. This must be
2895 * done after usb_add_hcd since that function allocates the DMA buffer
2896 * pool.
2897 */
2898 if (hsotg->core_params->dma_enable > 0)
2899 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
2900 DWC2_HCD_STATUS_BUF_SIZE,
2901 &hsotg->status_buf_dma, GFP_KERNEL);
2902 else
2903 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
2904 GFP_KERNEL);
2905
2906 if (!hsotg->status_buf)
2907 goto error3;
2908
2909 hsotg->otg_port = 1;
2910 hsotg->frame_list = NULL;
2911 hsotg->frame_list_dma = 0;
2912 hsotg->periodic_qh_count = 0;
2913
2914 /* Initiate lx_state to L3 disconnected state */
2915 hsotg->lx_state = DWC2_L3;
2916
2917 hcd->self.otg_port = hsotg->otg_port;
2918
2919 /* Don't support SG list at this point */
2920 hcd->self.sg_tablesize = 0;
2921
2922 /*
2923 * Finish generic HCD initialization and start the HCD. This function
2924 * allocates the DMA buffer pool, registers the USB bus, requests the
2925 * IRQ line, and calls hcd_start method.
2926 */
66513f49 2927 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
7359d482
PZ		 2928 if (retval < 0)
2929 goto error3;
2930
2931 dwc2_dump_global_registers(hsotg);
2932 dwc2_dump_host_registers(hsotg);
2933 dwc2_hcd_dump_state(hsotg);
2934
2935 dwc2_enable_global_interrupts(hsotg);
2936
2937 return 0;
2938
2939error3:
2940 dwc2_hcd_release(hsotg);
2941error2:
ba0e60d1
PZ		 2942 usb_put_hcd(hcd);
2943error1:
7359d482
PZ		 2944 kfree(hsotg->core_params);
2945
2946#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2947 kfree(hsotg->last_frame_num_array);
2948 kfree(hsotg->frame_num_array);
2949#endif
2950
e62662c7 2951 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
7359d482
PZ		 2952 return retval;
2953}
2954EXPORT_SYMBOL_GPL(dwc2_hcd_init);
2955
2956/*
2957 * Removes the HCD.
2958 * Frees memory and resources associated with the HCD and deregisters the bus.
2959 */
e62662c7 2960void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
7359d482
PZ		 2961{
2962 struct usb_hcd *hcd;
2963
e62662c7 2964 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
7359d482
PZ		 2965
2966 hcd = dwc2_hsotg_to_hcd(hsotg);
e62662c7 2967 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
7359d482
PZ		 2968
2969 if (!hcd) {
e62662c7 2970 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
7359d482
PZ		 2971 __func__);
2972 return;
2973 }
2974
2975 usb_remove_hcd(hcd);
2976 hsotg->priv = NULL;
2977 dwc2_hcd_release(hsotg);
ba0e60d1 2978 usb_put_hcd(hcd);
7359d482
PZ		 2979
2980#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
2981 kfree(hsotg->last_frame_num_array);
2982 kfree(hsotg->frame_num_array);
2983#endif
7359d482
PZ		 2984}
2985EXPORT_SYMBOL_GPL(dwc2_hcd_remove);
ubuntu-bionic-kernel mirror